A real-time calculation SVPWM method capable of eliminating PWM one-beat delay

Abstract

The application provides a real-time calculation SVPWM method capable of eliminating PWM one-beat delay. According to the characteristics of SVPWM vector output, a vector with long enough duration is selected to be output at the starting moment of each beat, so as to ensure that no vector switching occurs within the calculation time, and to ensure that the system can complete calculation and update PWM instruction within the calculation time, so that the delay update of the PWM instruction is equivalent to the update at the sampling point. The application also provides a proper vector switching sequence and a duty cycle calculation method, so that the PWM strategy can reliably operate, and according to the voltage output law of the controller, a hysteresis loop and a lookup table are designed to determine the output vector at the starting moment of each beat. The application can ensure that the one-beat delay of the system is eliminated, and the modulation range is not lost, so that ideal three-phase system non-delay PWM is achieved.

Description

Technical Field

[0001] This invention belongs to the field of PWM modulation technology, specifically relating to a real-time SVPWM calculation method that can eliminate PWM one-beat delay. Background Technology

[0002] The pulse-width modulation (PWM) command updates implemented by digital controllers have a one-beat lag. This lag can lead to adverse effects such as limited system bandwidth and reduced stability. To avoid the impact of this one-beat delay, a common method is to use predictive control or an observer to compensate for the delay. However, due to factors such as noise interference in current sampling and the asymptotic convergence process of the observer, these compensation-based methods offer limited improvements in system performance.

[0003] Another method for handling delays is to update the PWM command immediately after calculation; this is called real-time calculation. Real-time calculation does not include controller sampling feedback, therefore it does not suffer from the drawbacks of compensation-based methods. A common real-time calculation method is to continuously change the trigger time of the system interrupt according to the system's duty cycle characteristics (i.e., selecting whether the system interrupt is triggered at the carrier peak or trough), thus making the delayed PWM command update equivalent to its update at the sampling point. This approach is relatively perfect for single-phase systems. However, due to the inter-phase coupling in three-phase systems, the voltage vector output characteristics of three-phase systems are different from those of single-phase systems. This means that when this method is extended to three-phase systems, it can only be based on sinusoidal pulse-width modulation (SPWM). For example, the literature "Lin Z, Ruan X, Zhang H, et al. A Generalized Real-Time Computation Method With Dual-Sampling Mode to Eliminate the Computation Delay in Digitally Controlled Inverters[J]. IEEE Transactions on Power Electronics, 2022, 37(5): 5186-5195" utilizes the three-phase decoupling characteristics of SPWM to complete the real-time calculation of the three-phase system. However, due to the low voltage utilization of the SPWM method, this method has an inherent modulation loss in the three-phase system. In addition, this method also has inherent defects of the SPWM method, such as high harmonic content. The Space Vector Pulse Width Modulation (SVPWM) method does not have the problems of the SPWM method. Therefore, in order to address the problems of the one-step delay elimination strategy based on the SPWM method in the above three-phase system, this invention introduces a strategy based on the SVPWM method to complete the PWM delay elimination. Summary of the Invention

[0004] To address the performance degradation caused by a single-step delay in PWM strategies for digital systems, this invention provides a real-time SVPWM calculation method that eliminates this delay. Based on the characteristics of SVPWM vector output, a vector with a sufficiently long duration is selected for output at the beginning of each step, ensuring no vector switching occurs during the calculation time and guaranteeing that the system can complete the calculation and update the PWM command within that time. This makes the delayed update of the PWM command equivalent to its update at the sampling point. The invention also provides appropriate vector switching sequences and duty cycle calculation methods to ensure reliable PWM strategy operation. Furthermore, hysteresis loops and lookup tables are designed according to the controller's voltage output characteristics to determine the output vector at the beginning of each step. This invention guarantees the elimination of the single-step delay without loss of modulation range, achieving ideal three-phase system delay-free PWM.

[0005] A real-time SVPWM calculation method capable of eliminating PWM one-beat delay is characterized by the following steps:

[0006] Step 1: Enter the k-th interrupt time of the controller system and obtain the given voltage of the controller at this time.

[0007] Step 2: Based on the voltage vector V output at the start of this cycle origin To configure a three-phase EPWM comparator, specifically including:

[0008] If V origin =V0, Located in sectors I to VI, a three-phase EPWM comparator is configured according to the seven-segment SVPWM method;

[0009] If V origin =V1, when When located in sector I, the three-phase EPWM comparator is configured according to the following formula:

[0010]

[0011] when When located in sector VI, the three-phase EPWM comparator is configured according to the following formula:

[0012]

[0013] If V origin =V2, when When located in sector I, the three-phase EPWM comparator is configured according to the following formula:

[0014]

[0015] when When located in sector II, the three-phase EPWM comparator is configured according to the following formula:

[0016]

[0017] If V origin =V3, when When located in sector II, the three-phase EPWM comparator is configured according to the following formula:

[0018]

[0019] when When located in sector III, the three-phase EPWM comparator is configured according to the following formula:

[0020]

[0021] If V origin =V4, when When located in sector III, the three-phase EPWM comparator is configured according to the following formula:

[0022]

[0023] when When located in sector IV, the three-phase EPWM comparator is configured according to the following formula:

[0024]

[0025] If V origin =V5, when When located in sector IV, the three-phase EPWM comparator is configured according to the following formula:

[0026]

[0027] when When located in sector V, the three-phase EPWM comparator is configured according to the following formula:

[0028]

[0029] If V origin =V6, when When located in sector V, the three-phase EPWM comparator is configured according to the following formula:

[0030]

[0031] when When located in sector VI, the three-phase EPWM comparator is configured according to the following formula:

[0032]

[0033] Wherein, V0 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 000, V1 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 100, V2 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 110, V3 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 010, V4 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 011, V5 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 001, and V6 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 101; sector I is the triangular region formed by vectors V1 and V2 as sides in the voltage vector hexagon; sector II is the triangular region formed by vectors V2 and V3 as sides in the voltage vector hexagon. Sector 3 is a triangular region formed by sides; Sector III is a triangular region formed by sides of the voltage vector hexagon with vectors V3 and V4 as sides; Sector IV is a triangular region formed by sides of the voltage vector hexagon with vectors V4 and V5 as sides; Sector V is a triangular region formed by sides of the voltage vector hexagon with vectors V5 and V6 as sides; Sector VI is a triangular region formed by sides of the voltage vector hexagon with vectors V6 and V1 as sides; EPWMA, EPWMB, and EPWMC all represent the EPWM modules of the DSP, corresponding to the three phases respectively; CMPA and CMPB represent the per-unit results of the comparison register values ​​in the EPWM module of the DSP; DutyA represents the duty cycle of phase A obtained by the minimum value zero-sequence injection method, DutyB represents the duty cycle of phase B obtained by the minimum value zero-sequence injection method, and DutyC represents the duty cycle of phase C obtained by the minimum value zero-sequence injection method.

[0034] When the EPWM comparator and the carrier intersect, the operation of the EPWM module is set to be the inversion of the above switching state;

[0035] Step 3: Wait for the idle time in the middle of the current interruption, then sample the current at the end of the current interruption, and calculate the three-phase current error criterion Δi according to the following formula. a(k)-judge , Δi b(k)-judge and Δi c(k)-judge :

[0036]

[0037] Among them, U ea U eb and U ec These represent the components of the controller's disturbance rejection section output on axes a, b, and c in the three-phase vector diagram; and These represent the given currents of phases A, B, and C, respectively; i ai b and i c Then, k represents the actual current at the time points A, B, and C respectively; x The gain is fixed and determined by the controller architecture.

[0038] If the current error criteria for phases A, B, and C respectively satisfy the following formula, let the voltage vector V output at the beginning of the next cycle be... origin =V0:

[0039]

[0040]

[0041]

[0042] Where, δi a ,δi b and δi c U represents the feasible range of the three-phase current error criterion for phases A, B, and C, respectively. dc This refers to the bus voltage.

[0043] Otherwise, determine the output voltage vector V at the start time of the next cycle as follows. origin :

[0044] If Δi a(k)-judge >0 and Δi b(k)-judge <0 and Δi c(k)-judge <0, let V origin =V1;

[0045] If Δi a(k)-judge >0 and Δi b(k)-judge >0 and Δi c(k)-judge <0, let V origin =V2;

[0046] If Δi a(k)-judge <0 and Δi b(k)-judge >0 and Δi c(k)-judge <0, let V origin =V3;

[0047] If Δi a(k)-judge <0 and Δi b(k)-judge >0 and Δi c(k)-judge >0, let V origin =V4;

[0048] If Δi a(k)-judge <0 and Δi b(k)-judge <0 and Δi c(k)-judge >0, let V origin =V5;

[0049] If Δia(k)-judge >0 and Δi b(k)-judge <0 and Δi c(k)-judge >0, let V origin =V6.

[0050] The beneficial effects of this invention are as follows: By selecting a vector with a sufficiently long duration for output at the beginning of each cycle based on the characteristics of SVPWM vector output, it is ensured that no vector switching occurs during the calculation time. Since the calculation of this cycle and the update of the PWM command are ensured to be completed before vector switching occurs, the delayed update of the PWM command is equivalent to its update at the sampling point. Because an appropriate vector switching sequence and duty cycle calculation method are designed to address the potential for non-zero vector output at the beginning of the proposed delay elimination method, the PWM strategy can operate reliably. Because a hysteresis loop and lookup formula are designed according to the voltage output law of the controller, and the vector output at the beginning of each cycle is determined by performing an additional sampling and hysteresis judgment in advance, it is ensured that the one-cycle delay of the system is eliminated, and the voltage vector-based output strategy ensures no loss of modulation range. The real-time calculation SVPWM method proposed in this invention can eliminate the one-cycle delay present in digital systems, greatly improving the system's stability margin and bandwidth. Unlike existing real-time calculation methods, it does not suffer from limitations in the modulation of three-phase systems or large current harmonics, thus achieving ideal three-phase system delay-free PWM. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of PWM output;

[0052] In the figure, (a) is a schematic diagram of PWM instruction update with a one-beat delay; (b) is a schematic diagram of PWM instruction update using a real-time calculation method.

[0053] Figure 2 It is the voltage vector V output at the beginning of each cycle. origin A diagram illustrating the division;

[0054] Figure 3 This is a diagram showing the vector switching sequence and time execution order of the present invention;

[0055] Figure 4 This is a schematic diagram of the EPWM comparator configuration;

[0056] Figure 5 This is a schematic diagram of the current error and hysteresis comparator;

[0057] Figure 6 This is a timing diagram of the system execution after adding a hysteresis comparator;

[0058] Figure 7This is a flowchart of a real-time SVPWM calculation method that can eliminate PWM one-beat delay according to the present invention;

[0059] Figure 8 This is a comparison chart of experimental results;

[0060] In the figure, (a)-L s / L s0 Comparison of static and dynamic effects of the system with and without a one-beat delay when = 0.3, (b)-L s / L s0 Comparison of static and dynamic effects of the system with and without a one-beat delay when =1, (c)-L s / L s0 =1.7 - Comparison of dynamic and static effects of the system with and without one-beat delay, (d) - Comparison of dynamic and static effects of the system with and without one-beat delay when all disturbances are ignored. Detailed Implementation

[0061] The present invention will be further described below with reference to the accompanying drawings and embodiments. The present invention includes, but is not limited to, the following embodiments.

[0062] PWM update timing with one-beat delay as follows Figure 1 As shown in (a), current sampling, current loop calculation, and SVPWM calculation are completed in the k-th cycle. The time consumed by these sampling and calculations is collectively referred to as the calculation delay T. sw After the above sampling and calculation process, a given PWM instruction D(k) can be obtained, and D(k) is updated at the beginning of the (k+1)th cycle. This results in a carrier period T. s The delay is called a one-beat delay. In the diagram, the coordinate axes represent time t. (k) Sampling, i (k+1) Sampling, i (k+2) The sampling operations represent the current sampling operations at the k-th, (k+1)-th, and (k+2)-th timeframes, respectively. D(k-1), D(k), and D(k+1) represent the PWM commands at the k-th, (k+1)-th, and (k+2)-th timeframes, respectively. The update timing of the PWM carrier and PWM commands is indicated by arrows in the figure. The PWM waveform is also given in the figure as a square wave signal.

[0063] To eliminate one-beat delay, a common method is a real-time calculation method based on PWM instructions to update the instantaneous displacement, specifically as follows: Figure 1 As shown in (b). At T sw Within the specified range, the PWM instruction is not updated; once the calculation is complete, the PWM instruction is updated immediately. It can be seen that as long as the PWM instruction update can be completed before D(k) intersects with the carrier, the update delay of D(k) (i.e., the calculation delay T) is minimal. swThis will not affect the PWM output. Therefore, the one-beat delay is eliminated. To meet the above conditions, the duty cycle of the PWM instruction needs to be limited to:

[0064] 0 <DutyM<1-2T sw / T s (17)

[0065] Wherein, DutyM represents the duty cycle of any one of the three phases ABC. For simplicity, in this invention, M and m are used to refer to any one of the three phases ABC.

[0066] Clearly, this approach leads to an increase in the loss of modulation in the three-phase system as computational complexity increases.

[0067] To overcome the shortcomings of the aforementioned real-time calculation methods, this invention proposes a real-time SVPWM calculation method based on space voltage vectors. This invention is based on a simple fact: for the SVPWM algorithm, the reference voltage vector is always equivalently synthesized by outputting two adjacent non-zero vectors and one zero vector of different durations (these three vectors are called the nearest three vectors, NTVs). Therefore, in NTVs, the vector with the longest output time will always have a duration greater than T. s If the value is 3, then we can consider completing the sampling calculation and PWM instruction update during the output process of this vector, so that there will be relatively sufficient time to complete the real-time calculation and eliminate the one-beat delay.

[0068] Figure 2 The voltage vector V output at the beginning of each cycle is given. origin A diagram showing the division of space, where V... 0(7) -V6 are eight space voltage vectors formed by eight switching state combinations of the inverter. In the diagram, the numbers in parentheses after V1-V6 represent their corresponding switching state combinations. Since switching state combinations 000 and 111 both represent the 0 vector, they are integrated into a single vector node in the diagram, namely V 0(7) Because of V 0(7) This involves two switching states. In the following text, when it is necessary to distinguish between the two switching states, V0 will represent the voltage vector formed by switching state combination 000, and V7 will represent the voltage vector formed by switching state combination 111. In the diagram, sector I to sector VI represent sectors I to VI, respectively. Each sector triangle is formed by six vectors, that is:

[0069] Sector I is a triangular region formed by vectors V1 and V2 as sides in the voltage vector hexagon;

[0070] Sector II is a triangular region formed by vectors V2 and V3 as sides within the voltage vector hexagon;

[0071] Sector III is a triangular region formed by vectors V3 and V4 as sides in the voltage vector hexagon;

[0072] Sector IV is a triangular region formed by vectors V4 and V5 as sides in the voltage vector hexagon;

[0073] Sector V is a triangular region formed by vectors V5 and V6 as sides in the voltage vector hexagon;

[0074] Sector VI is a triangular region formed by vectors V6 and V1 as sides in the voltage vector hexagon.

[0075] Furthermore, according to the solid lines inside the hexagon, Figure 2 It also gave V origin =V 0(7) To V origin =The division of the applicable regions for V6, and the specific principles of this partitioning will be introduced later.

[0076] In the picture This is the voltage vector given by the controller for this (k-th) beat, based on the volt-second balance principle. It can be obtained according to the following formula:

[0077]

[0078] Among them, T1, T2 and T 0(7) They are V1, V2 and V respectively. 0(7) The duration.

[0079] according to Figure 2 It is obvious that T2>T1>T 0(7) Then we can consider following Figure 3 Design a PWM update strategy. For example... Figure 3 As shown, the voltage vector V output at the beginning of each step in the SVPWM algorithm is... origin The value changes from V0 to V2, and the SVPWM switching sequence is updated immediately after the calculation is complete. Because T sw Since the duration of V2 at the initial time is less than that of V2, updating the switching sequence after the calculation is equivalent to updating the switching sequence at the sampling point, and the one-beat delay is eliminated. Similarly, when T1 is the largest of the three, it is only necessary to set V1 to V origin Then, the switching sequence design can be carried out based on this. 0(7) The situation is similar for the maximum voltage and reference voltage vector in other sectors. Figure 3 In the middle, V origin(k) V represents the value set in the k-th beat. originV origin(k+1) V represents the value set in the (k+1)th beat. origin The horizontal axis t represents time.

[0080] Based on the above analysis, we can determine V origin For V 0(7) ~V6 divides the vector voltage hexagon into seven parts, as shown below. Figure 2 As shown, based on each beat exist Figure 2 By determining the position of the voltage vector at the start of each beat, the switching sequence design can be carried out.

[0081] Depend on Figure 3 As can be seen, the switching sequence designed in the figure is not a typical seven-segment SVPWM. For this atypical SVPWM method, V origin The duration of the output at the initial time should be at least T. sw In the diagram, V origin The duration of the output at the initial moment is always its total output time T. origin 1 / 4. The following explains how to implement this atypical SVPWM algorithm, namely the special vector switching sequence and SVPWM algorithm of this invention:

[0082] With V origin =V1, Taking sector I as an example. When V origin When V1, to achieve a total of 6 three-phase switches and 7 vector switching operations, the recommended switching sequence is V1→V2→V1→V0→V1→V2→V1, and the corresponding three-phase switch states are as follows: Figure 4 As shown. By Figure 4 It can be seen that under this switching sequence, phase C is clamped, and the switching states of phases A and B are switched twice and four times, respectively. Therefore, this switching sequence completes seven vector switching operations, and the sum of the number of three-phase switching operations is 6. Figure 4 The duration of the vector is evenly divided according to the number of times it appears in a carrier cycle (that is, T1 is divided into 4 parts according to the switching sequence, and T2 is divided into 2 parts). Meanwhile... Figure 4 The document also provides a comparator configuration method for the EPWM module implemented using a typical DSP (TMS320F28335). Since phase B requires four switching operations, both comparators are enabled. Phase A uses EPWMA-CMPA. The other three comparators are not used in this configuration. When the EPWM comparator intersects with the carrier wave, the EPWM module's operation is configured to invert the switching state.

[0083] The three-phase duty cycles DutyA, DutyB, and DutyC are obtained using the minimum value zero-sequence injection method (Note: minimum value zero-sequence injection will result in one phase duty cycle being 0, for...). Figure 4 In the case of DutyC = 0, the vector duration can be obtained as follows:

[0084]

[0085] According to the set switching sequence and Figure 4 If we assume the peak value of the carrier wave is 1 and the trough value is 0, then the comparator's setting value can be derived as follows:

[0086]

[0087] In this context, EPWMA, EPWMB, and EPWMC all represent the EPWM modules of the DSP. It should be noted that a typical DSP has several EPWM modules, but this invention targets a three-phase system; therefore, only three EPWM modules are needed, named EPWMA, EPWMB, and EPWMC. CMPA and CMPB represent the per-unit values ​​of the two compare registers within a single EPWM module of the DSP, respectively.

[0088] For different V origin and For other sectors, the designed switching sequence is shown in Table 1.

[0089] Table 1

[0090]

[0091] As can be seen from Table 1, V origin It will always appear 4 times in the switching sequence, therefore, as mentioned before, T sw It should be less than T origin / 4.

[0092] With V origin =V1、 Similar to sector I, the EPWM comparator settings for other cases can be derived as shown in Table 2. Since all switching sequences in this invention only require the use of three EPWM comparators, unused EPWM comparators are not listed in Table 2. When the EPWM comparator intersects with the carrier, the set action of the EPWM module is the inversion of the switching state.

[0093] Table 2

[0094]

[0095]

[0096] Although Figure 2 The text provides the basis for... Determine the position of V in the vector diagram. origin This method, however, can only determine V after the SVPWM calculation is completed. origin Therefore V origin The update will have a one-beat lag. To avoid this problem, this invention designs a method based on hysteresis current control strategy to select V. origin The method.

[0097] For most three-phase system current loop controllers, their output voltage satisfies the form shown in the following equation:

[0098] U m = k x Δi m(k) + U em (twenty one)

[0099] Among them, U m The output voltage representing the m-axis, Δi m(k) U is the error between the current sampled on the m-axis at time k and the given current. em It is a voltage quantity that changes very slowly along the m-axis.

[0100] Taking a simple SPMSM drive system as an example, the dq-axis current error of the k-step is assumed to be Δi. dq(k) The output voltage based on the PI controller can then be expressed as:

[0101]

[0102] Among them, U dq k represents the output voltage along the dq axis. p and k i These are the proportional coefficient and the integral coefficient, respectively. idq The output value of the dq-axis digital integrator, taking into account the switching period T. s The impact can be considered as U idq The change is very slow, therefore U idq It's equivalent to U on the dq axis. em Let it be denoted as U edq Obviously, k p Δi dq(k) With k x Δi dq(k) Equivalent. Therefore, k can be considered... x It is a fixed gain, determined by the controller structure.

[0103] For a deadbeat controller, the output voltage is:

[0104]

[0105] Among them, U d U represents the output voltage along the d-axis. q L represents the output voltage along the q-axis. s For SPMSM stator inductance, R s For the stator resistance, ω r Let ψ be the electric angular velocity. f For permanent magnet flux linkage, Δi d(k) Indicates the d-axis current error; Δi q(k) Indicates the q-axis current error; i d Indicates the actual current along the d-axis, i q This represents the actual q-axis current. Since the voltage drop across the resistor is relatively small, it is considered to be U. em A portion of it will not affect U em The characteristics of this. Therefore, the output of the deadbeat controller can also be regarded as k. x Δi dq(k) +U edq Furthermore, the output voltage of PR controllers and similar devices also exhibits this characteristic.

[0106] Furthermore, although the output voltage of the controller described above is obtained under the dq axis, for a typical three-phase symmetrical load, after coordinate transformation, the output voltage can also be expressed in the above form under the abc axis.

[0107] Based on the above analysis, the current error Δi (k) It actually contains some information about the output voltage, so it's worth considering using U. em This is also equivalent to the form of current error. Therefore, the current error along the m-axis can actually be equivalent to... The component on the m-axis. Using the three-phase current errors of a, b, and c to construct a hysteresis judgment and lookup table, the most suitable V can be directly selected. origin .

[0108] Thus, the given voltage U along the m-axis m The calculation formula can be expressed as:

[0109] U m =k x Δi m(k) +U em =k x Δi m(k)-judge (twenty four)

[0110] Where, Δi m(k)-judge This represents the current error criterion for phase m. It can be seen that Δi m(k)-judge Contains U m All information about Δi. Therefore, only Δi needs to be considered. a(k)-judge, Δi b(k)-judge and Δi c(k)-judge With proper processing, the most appropriate V can be obtained. origin .

[0111] Depend on Figure 5 It can be seen that when the most appropriate V origin When V0, the voltages along the abc coordinate axis should satisfy:

[0112] -U dc / 3 em dc / 3 (25)

[0113] Among them, U dc This is the bus voltage.

[0114] According to the above formula, U m Converting this to the form of current error, we have:

[0115]

[0116] Where, δi m This represents the feasible range of the m-phase current error criterion. It can be seen that equation (26) is a standard expression for the hysteresis tolerance range, that is, when Δi a(k)-judge , Δi b(k)-judge and Δi c(k)-judge When all conditions are satisfied, then V origin =V0.

[0117] like Figure 5 medium reference voltage U in em As shown in the figure, Δi (k) This is the vector representation of the three-phase current error. When k x Δi (k) =k x Δi (k1) Time (Δi) (k1) Indicates Δi (k) (An example of the value of k) x Δi (k1) +U e The magnitudes of the components on axes a, b, and c do not exceed the range of the central sub-hexagon; therefore, V0 is chosen as V. origin This is appropriate. It can be seen that if the voltage is equivalent to the current error, then equation (26) is clearly satisfied. And if k x Δi (k) =k x Δi (k2) (Δi (k2) Indicates Δi (k) ​​(An example of the value selection), as shown in the figure, V0 is chosen as V in this case. origin That's not appropriate. This is because... The component on the b-axis extends beyond the range of the central sub-hexagon, meaning there exists |Δi b(k)-judge |>0.5δi b .

[0118] Therefore, when equation (26) is not satisfied, the most appropriate V cannot be directly selected based on the hysteresis judgment. origin This is because there is a possibility that two or three hysteresis boundary conditions may not be satisfied simultaneously. However, Δi m(k)-judge It contains information about the given phase voltage, so it can be directly calculated according to i. a(k)-judge , Δi b(k)-judge and Δi c(k)-judge Choose the most appropriate V based on the size relationship. origin As shown in Table 3.

[0119] Table 3

[0120] <![CDATA[V1]]> <![CDATA[Δi a(k)-judge >0&&Δi b(k)-judge <0&&Δi c(k)-judge <0]]> <![CDATA[V2]]> <![CDATA[Δi a(k)-judge >0&&Δi b(k)-judge >0&&Δi c(k)-judge <0]]> <![CDATA[V3]]> <![CDATA[Δi a(k)-judge <0&&Δi b(k)-judge >0&&Δi c(k)-judge <0]]> <![CDATA[V4]]> <![CDATA[Δi a(k)-judge <0&&Δi b(k)-judge >0&&Δi c(k)-judge >0]]> <![CDATA[V5]]> <![CDATA[Δi a(k)-judge <0&&Δi b(k)-judge <0&&Δi c(k)-judge >0]]> <![CDATA[V6]]> <![CDATA[Δi a(k)-judge >0&&Δi b(k)-judge <0&&Δi c(k)-judge >0]]>

[0121] After the above process, it is assumed that U is between the two beats. e If the current error information is approximately constant, then the reference voltage vector output by the controller can be quickly estimated. The range in which it is located, and thus determine V origin It can be seen that, since the proposed hysteresis comparator only needs to judge Equation (26) and Table 3 after sampling, its structure is much simpler than the method of obtaining the duration of the three vectors using the SVPWM algorithm and then making a judgment. Therefore, it will only bring a small amount of computational delay, thus avoiding V origin There may be a delay in the selection process.

[0122] In summary, by employing the concept of a hysteresis comparator, current sampling is performed in advance to complete hysteresis comparison and lookup table, thereby estimating the reference voltage information on each coordinate axis and thus obtaining an appropriate V. origin Update at the start of the next beat. The timing diagram with the hysteresis comparator is as follows. Figure 6 As shown. A hysteresis comparison is set at the end of each frame. After a brief A / D conversion and hysteresis check, the correct V signal can be obtained. origin This configuration allows for ideal delay elimination in the next clock cycle. Since the hysteresis comparator algorithm is very simple, the computational delay caused by its pre-sampling can be ignored in practical systems. Furthermore, Figure 6 The documentation also specifies an additional computation time for preprocessing hysteresis comparisons. This time is primarily used to obtain Δi. m(k)-judge and Uem Then transform it onto the ABC axis.

[0123] like Figure 7 As shown, the specific steps of the real-time PWM calculation method of the present invention are as follows:

[0124] Step 1: Enter the system interrupt of this step and execute the sampling and control algorithm of this step to obtain the given voltage of the local controller.

[0125] Step 2: Execute the SVPWM algorithm proposed in this invention, that is, according to the voltage vector V determined in the previous step at the beginning of this step. origin To configure the three-phase EPWM comparator, see Table 2.

[0126] Step 3: Wait for the idle time in the middle of this interruption, then sample the current at the end of the interruption and determine the V for the next cycle. origin When all three phases ABC satisfy equation (26), the V of the next pulse... origin =V0, otherwise set V according to Table 3. origin .

[0127] To verify the effectiveness of the method of the present invention, experimental tests were conducted on the proposed method according to the above steps. The experimental test platform consisted of a PMSM motor drive system built with a DSP28335 as the main control chip, an SPMSM, and a load motor. The parameters of the PMSM and the controller are shown in Table 4.

[0128] Table 4

[0129]

[0130]

[0131] The PMSM drive system uses a PI controller for the speed loop and a deadbeat controller for the current loop. d A control strategy with a value of 0 was used. The correctness of the calculation in this invention was verified by comparing the experimental results of traditional PWM and the method of this invention. Real-time calculation-based deadbeat control is abbreviated as RTC in the experimental diagram, while traditional prediction-based deadbeat control is abbreviated as TSP. The experiment compared the performance of RTC and TSP in L... s / L s0 =0.3; L s / L s0 =1; L s / L s0 =1.7(L) s0 To substitute the motor inductance parameters into the controller, where L s0L represents the actual inductance value of the stator. s (representing the inductance value given in the controller), and ignoring all disturbances (i.e., assuming ω in a deadbeat controller). r The phase current waveforms and THD of the motor at 100 r / min and 250 r / min are shown in the figure, with all values ​​being 0. The dynamic process of the speed command stepping from 100 r / min to 250 r / min is also shown in the figure. The experimental results are as follows. Figure 8 As shown in the figure, TSP represents the traditional two-step prediction method for deadbeat control, and RTC represents the real-time calculation method proposed in this invention. The horizontal axis unit of the large image is 50ms / div (div represents one grid), while the horizontal axis unit of the enlarged detailed image is 500us / div; the vertical axis unit is A / div, where A is the unit of current, ampere. a This represents the current in phase A. THD in the diagram represents the total harmonic distortion of the current waveform.

[0132] Depend on Figure 8 It can be seen that the real-time calculation method of this invention can process errors more quickly after they occur in the system. Therefore, it has a relatively smaller THD under both low-frequency control (before a given speed step) and high-frequency control (after a given speed step). The magnified view of the step portion also shows that the current ripple of this invention is relatively small, which is consistent with the comparison results of the THD values. Furthermore, the current rise curve of the real-time calculation method of this invention is significantly steeper when a given speed step occurs, indicating a faster current response speed. Based on the combined experimental results, the real-time calculation method of this invention is effective.

Claims

1. A real-time SVPWM calculation method capable of eliminating PWM one-beat delay, characterized in that... The steps are as follows: Step 1: Enter the k-th interrupt time of the controller system and obtain the given voltage of the controller at this time. Step 2: Based on the voltage vector V output at the start of this cycle origin To configure a three-phase EPWM comparator, specifically including: If V origin =V0, Located in sectors I to VI, a three-phase EPWM comparator is configured according to the seven-segment SVPWM method; If V origin =V1, when When located in sector I, the three-phase EPWM comparator is configured according to the following formula: when When located in sector VI, the three-phase EPWM comparator is configured according to the following formula: If V origin =V2, when When located in sector I, the three-phase EPWM comparator is configured according to the following formula: when When located in sector II, the three-phase EPWM comparator is configured according to the following formula: If V origin =V3, when When located in sector II, the three-phase EPWM comparator is configured according to the following formula: when When located in sector III, the three-phase EPWM comparator is configured according to the following formula: If V origin =V4, when When located in sector III, the three-phase EPWM comparator is configured according to the following formula: when When located in sector IV, the three-phase EPWM comparator is configured according to the following formula: If V origin =V5, when When located in sector IV, the three-phase EPWM comparator is configured according to the following formula: when When located in sector V, the three-phase EPWM comparator is configured according to the following formula: If V origin =V6, when When located in sector V, the three-phase EPWM comparator is configured according to the following formula: when When located in sector VI, the three-phase EPWM comparator is configured according to the following formula: Wherein, V0 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 000, V1 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 100, V2 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 110, V3 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 010, V4 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 011, V5 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 001, and V6 represents the space vector voltage formed when the upper arm switch state combination of the full-bridge inverter is 101; sector I is the triangular region formed by vectors V1 and V2 as sides in the voltage vector hexagon; sector II is the triangular region formed by vectors V2 and V3 as sides in the voltage vector hexagon. Sector 3 is a triangular region formed by sides; Sector III is a triangular region formed by sides of the voltage vector hexagon with vectors V3 and V4 as sides; Sector IV is a triangular region formed by sides of the voltage vector hexagon with vectors V4 and V5 as sides; Sector V is a triangular region formed by sides of the voltage vector hexagon with vectors V5 and V6 as sides; Sector VI is a triangular region formed by sides of the voltage vector hexagon with vectors V6 and V1 as sides; EPWMA, EPWMB, and EPWMC all represent the EPWM modules of the DSP, corresponding to the three phases respectively; CMPA and CMPB represent the per-unit results of the comparison register values ​​in the EPWM module of the DSP; DutyA represents the duty cycle of phase A obtained by the minimum value zero-sequence injection method, DutyB represents the duty cycle of phase B obtained by the minimum value zero-sequence injection method, and DutyC represents the duty cycle of phase C obtained by the minimum value zero-sequence injection method. When the EPWM comparator and the carrier intersect, the operation of the EPWM module is set to be the inversion of the above switching state; Step 3: Wait for the idle time in the middle of the current interruption, then sample the current at the end of the current interruption, and calculate the three-phase current error criterion Δi according to the following formula. a(k)-judge , Δi b(k)-judge and Δi c(k)-judge : Among them, U ea U eb and U ec These represent the components of the controller's disturbance rejection section output on axes a, b, and c in the three-phase vector diagram; and These represent the given currents of phases A, B, and C, respectively; i a i b and i c Then, k represents the actual current at the time points A, B, and C respectively; x The gain is fixed and determined by the controller architecture. If the current error criteria for phases A, B, and C respectively satisfy the following formula, let the voltage vector V output at the beginning of the next cycle be... origin =V0: Where, δi a ,δi b and δi c U represents the feasible range of the three-phase current error criterion for phases A, B, and C, respectively. dc This refers to the bus voltage. Otherwise, determine the output voltage vector V at the start time of the next cycle as follows. origin : If Δi a(k)-judge >0 and Δi b(k)-judge <0 and Δi c(k)-judge <0, let V origin =V1; If Δi a(k)-judge >0 and Δi b(k)-judge >0 and Δi c(k)-judge <0, let V origin =V2; If Δi a(k)-judge <0 and Δi b(k)-judge >0 and Δi c(k)-judge <0, let V origin =V3; If Δi a(k)-judge <0 and Δi b(k)-judge >0 and Δi c(k)-judge >0, let V origin =V4; If Δi a(k)-judge <0 and Δi b(k)-judge <0 and Δi c(k)-judge >0, let V origin =V5; If Δi a(k)-judge >0 and Δi b(k)-judge <0 and Δi c(k)-judge >0, let V origin =V6.

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