Pixel circuit, electronic device, and image acquisition method

Abstract

The application provides a pixel circuit, an electronic device and an image acquisition method. The pixel circuit comprises a photodiode array and at least one voltage detection circuit. M photodiodes in the photodiode array are electrically connected to one voltage detection circuit. The voltage detection circuit is configured to detect a digital voltage value corresponding to an analog voltage of an output of a first photodiode among the m photodiodes, and a ratio of an output analog voltage of m-1 second photodiodes among the m photodiodes to the output analog voltage of the first photodiode, and determine a digital voltage value of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio. The m photodiodes comprise at least one row or at least one column of the photodiodes in the photodiode array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic products, and in particular to a pixel circuit, an electronic device, and an image acquisition method. BACKGROUND

[0002] With the development of electronic products, the photographing and video shooting functions in electronic products are becoming more and more perfect and are widely used. Before each pixel in the camera sensor of an electronic product (such as a terminal device) senses light, the accumulated charge in a photo diode (PD) needs to be emptied first, then the light signal is integrated within a set exposure time, and an electron is generated, which needs to be converted into a voltage and then converted into a digital value through digital-analog conversion to produce an image. At present, an electronic product usually sets one pixel circuit for each column of PDs, and the pixel circuit includes an analog-to-digital converter (ADC) and an integration circuit, so as to obtain the digital voltage value corresponding to the analog voltage output by the PD in the manner of integrating the light signal. Since the digital voltage value of one row of PDs can be obtained at a time, the digital voltage values of all PDs need to be obtained through line-by-line scanning, and finally an image is generated based on the digital voltage values of all PDs, which will result in a large time delay of image generation. SUMMARY

[0003] Embodiments of the present application provide a pixel circuit, an electronic device, and an image acquisition method to solve the problem of a large time delay of image generation.

[0004] In a first aspect, an embodiment of the present application provides a pixel circuit, comprising: a photo diode array and at least one voltage detection circuit, wherein

[0005] m photo diodes in the photo diode array are electrically connected to one voltage detection circuit, and the voltage detection circuit is configured to detect a digital voltage value corresponding to an analog voltage output by a first photo diode among the m photo diodes and a ratio of an output analog voltage of m-1 second photo diodes to the output analog voltage of the first photo diode, and determine digital voltage values of the m-1 second photo diodes according to the digital voltage value of the first photo diode and the ratio.

[0006] The m photo diodes include at least one row or at least one column of photo diodes in the photo diode array.

[0007] In a second aspect, an embodiment of the present application further provides an electronic device comprising the pixel circuit of the first aspect.

[0008] In a second aspect, the embodiments of the present application further provide an image acquisition method, applied to the electronic device of the second aspect, comprising:

[0009] detecting a digital voltage value corresponding to an analog voltage of an output of a first photodiode of the m photodiodes and a ratio of an output analog voltage of the first photodiode to that of m-1 second photodiodes of the m photodiodes;

[0010] determining the digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio;

[0011] generating an image according to the digital voltage value of the first photodiode and the digital voltage values of the m-1 second photodiodes;

[0012] The m photodiodes include at least one row or at least one column of the photodiodes in the photodiode array.

[0013] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0015] Figure 1 is one of the structural schematic diagrams of the pixel circuit provided by the embodiments of the present application;

[0016] Figure 2 is another of the structural schematic diagrams of the pixel circuit provided by the embodiments of the present application;

[0017] Figure 3 is a third of the structural schematic diagrams of the pixel circuit provided by the embodiments of the present application;

[0018] Figure 4 is a structural schematic diagram of a hybrid analog-digital conversion circuit in the pixel circuit provided by the embodiments of the present application;

[0019] Figure 5 is a flow schematic diagram of the image acquisition method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application will be described below in detail with examples shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explanation and are not to be understood as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work under the premise that the present application falls within the scope of protection.

[0021] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in an "or" relationship.

[0022] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0023] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0024] Referring to Figure 1 The embodiments of the present application provide a pixel circuit, as shown in Figure 1 The pixel circuit includes a photodiode array 10 and at least one voltage detection circuit 20, wherein,

[0025] The m photodiodes 101 in the photodiode array 10 are electrically connected with one voltage detection circuit 20, and the voltage detection circuit is configured to detect a digital voltage value corresponding to an analog voltage of an output of a first photodiode among the m photodiodes 101 and a ratio of an output analog voltage of m-1 second photodiodes to the output analog voltage of the first photodiode, and determine the digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio.

[0026] In some embodiments, the m photodiodes include at least one row or at least one column of the photodiodes 101 in the photodiode array.

[0027] In some embodiments, one voltage detection circuit 20 can be connected with at least one row or at least one column of the photodiodes 101. For example, in some embodiments, one voltage detection circuit 20 can be arranged for each row of the photodiodes 101, as shown in FIG. 2A; or one voltage detection circuit 20 can be arranged for every two rows of the photodiodes 101, as shown in FIG. 2B. Figure 1 Figure 2 In some embodiments, when the number of the voltage detection circuits 20 is at least two, the number of the photodiodes 101 connected with each voltage detection circuit 20 can be the same or different.

[0028] It should be noted that in some embodiments, one ADC and one integration circuit can be arranged for each photodiode 101 in each row or each column of the photodiodes 101 without the voltage detection circuit 20, and the digital voltage value of each photodiode 101 can be obtained by scanning. Details can be referred to related technologies and will not be further limited herein.

[0029] It should be understood that after obtaining the digital voltage values of all the photodiodes 101, the digital voltage values can be transmitted to an application processor (AP) through a mobile industry processor interface (MIPI) coding after an in-system programmability (ISP) processing, and converted into JPG for previewing or saving images.

[0030] Optionally, the ratio of the output analog voltage of the m-1 second photodiodes to the output analog voltage of the first photodiode can be understood as the ratio of the output analog voltage of each second photodiode to the output analog voltage of the first photodiode.

[0031] ​In the embodiment of the present application, the pixel circuit comprises a photodiode array 10 and at least one voltage detection circuit 20, wherein m photodiodes 101 in the photodiode array 10 are electrically connected with one voltage detection circuit 20, and the voltage detection circuit is configured to detect a digital voltage value corresponding to an analog voltage of an output of a first photodiode among the m photodiodes 101 and a ratio of an output analog voltage of m-1 second photodiodes to the first photodiode, and determine a digital voltage value of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio. The m photodiodes comprise at least one row or at least one column of the photodiodes 101 in the photodiode array. In this way, since the digital voltage value of the m-1 second photodiodes is determined according to the digital voltage value of the first photodiode and the ratio of the output analog voltage of the m-1 second photodiodes to the first photodiode, the digital voltage values of the m photodiodes 101 can be obtained by integrating the light signal only once, so that the time for obtaining the digital voltage values of the photodiodes 101 can be reduced, and the time delay of image generation is reduced.

[0032] Optionally, in some embodiments, the voltage detection circuit comprises a floating amplifier 201, a reference direct current power supply 202, a first switch tube 203, a second switch tube 204, a reset switch tube 205, a row selection switch tube 206 and a hybrid analog-digital conversion circuit 207, wherein,

[0033] The number of the first switch tubes 203 is m, and the m first switch tubes 203 are connected with the m photodiodes 101 one by one.

[0034] A first end of the floating amplifier 201 is electrically connected with cathodes of the m photodiodes 101 through the m first switch tubes 203, the first end of the floating amplifier 201 is also electrically connected with a high-level end VDD through the reset switch tube 205, and the first end of the floating amplifier 201 is connected with a control end of the second switch tube 204; a second end of the floating amplifier 201 is grounded, and anodes of the m photodiodes 101 are grounded.

[0035] A positive output end of the reference direct current power supply 202 is electrically connected with the high-level end VDD through the row selection switch tube 206 and the second switch tube 204 in sequence, and the positive output end of the reference direct current power supply 202 is also connected with the hybrid analog-digital conversion circuit 207.

[0036] The mixed analog-digital conversion circuit 207 is configured to detect a digital voltage value corresponding to an analog voltage of an output of a first photodiode among the m photodiodes, and a ratio of the analog voltage of the output of the first photodiode to analog voltages of outputs of m-1 second photodiodes among the m photodiodes, and determine the digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio.

[0037] In the embodiments of the present application, the floating amplifier 201 can be referred to as a capacitor, and the first switch tube 203, the second switch tube 204, the reset switch tube 205 and the row selection switch tube 206 can be field effect transistors, or other transistors or logic gate circuits that can realize the function of field effect transistors, which are not limited herein, for example, can be triodes in some embodiments.

[0038] Optionally, in some embodiments, the second switch tube 204 can be understood as a source follower. In operation, the first switch tube 203 and the reset switch tube 205 can be controlled to be turned on at the same time first, so as to empty the floating amplifier 201, and then the first switch tube 203 and the reset switch tube 205 are turned off to start exposure. The electron-hole pairs described in the exposure area will be separated due to the existence of the electric field of the photodiode, and the electrons move to the n region and the holes move to the p region. When the exposure is completed, the second switch tube 204 is activated to reset the floating amplifier 201 to a high level. After the reset is completed, the level of the floating amplifier 201 is read out, and the level of the floating amplifier 201 can obtain an analog voltage of the output of the photodiode at the output end of the reference DC power supply through the second switch tube 204 and the row selection switch tube. By sequentially switching the conduction state of different first switch tubes 203, the analog voltages of the outputs of the m photodiodes can be obtained, and the analog voltages of the outputs of the photodiodes are output to the mixed analog-digital conversion circuit 207.

[0039] It should be noted that in the embodiments of the present application, the analog voltages of the m photodiodes can be input to the mixed analog-digital conversion circuit 207 in series, that is, the analog voltage of one photodiode is obtained at the same time and input to the mixed analog-digital conversion circuit 207. In this way, the complexity and cost of the circuit can be reduced.

[0040] In the embodiments of the present application, the photodiodes 101 in the same row or the same column are connected to the same floating amplifier 201, so that the analog voltages of the photodiodes 101 in the same row or the same column can be output in series. In this way, the difficulty of circuit wiring can be reduced, and industrial production is facilitated.

[0041] In some embodiments, the analog voltage of the m photodiodes can be input to the hybrid analog-digital conversion circuit 207 in parallel, for example, one floating amplifier 201, one reference DC power supply 202, one second switch tube 204, one reset switch tube 205 and one row selection switch tube 206 can be provided for each photodiode.

[0042] For example, one floating amplifier 201, one reference DC power supply 202, one second switch tube 204, one reset switch tube 205 and one row selection switch tube 206 can be provided for the first photodiode in the m photodiodes, while one floating amplifier 201, one reference DC power supply 202, one second switch tube 204, one reset switch tube 205 and one row selection switch tube 206 can be provided for all the second photodiodes in the m photodiodes, that is, the analog voltage of the first photodiode and the second photodiode is input to the hybrid analog-digital conversion circuit 207 in parallel, while the analog voltage of the m-1 second photodiodes is input to the hybrid analog-digital conversion circuit 207 in series. At this time, assuming that the m photodiodes are a row of photodiodes, the second photodiodes in each row of photodiodes 101 are electrically connected to the same floating amplifier 201 through the first switch tube 203, or assuming that the m photodiodes are a column of photodiodes, the second photodiodes in each column of photodiodes 101 are electrically connected to the same floating amplifier 201 through the first switch tube 203.

[0043] It should be noted that since the first switch tube is electrically connected to the floating amplifier for each row or each column, the digital voltage values of all the photodiodes 101 can be read at the same time, thereby achieving the effect of global shutter, solving the jelly effect of photographing tilt or swing during line-by-line scanning, and improving the effect of photographing and recording.

[0044] Optionally, in some embodiments, the array of photodiodes includes m*N photodiodes, wherein,

[0045] N represents the number of rows of photodiodes, and m represents the number of columns of photodiodes, and the m photodiodes are a row of photodiodes;

[0046] Alternatively, m represents the number of rows of photodiodes, and N represents the number of columns of photodiodes, and the m photodiodes are a column of photodiodes.

[0047] In the embodiments of the present application, m represents the number of columns of photodiodes, which can be understood as follows: one hybrid analog-digital conversion circuit 207 can be provided for each row, and the hybrid analog-digital conversion circuit 207 can read out the digital voltage values of a row of photodiodes. For example, Figure 1As shown, the first row of photodiodes can include PD11-PD1m, the nth row of photodiodes can include PDn1-PDnm, and assuming that the first column of photodiodes is the first photodiode, the first photodiode in the first row of photodiodes can be PD11, and the first photodiode in the nth row of photodiodes can be PDn1. n is a positive integer less than or equal to N. In the embodiment of the present application, the first switch tube 203 in the at least one voltage detection circuit 20 includes TG11-TG1m, TG21-TG2m,..., TG(n-1)1-TG(n-1)m, TGn1-TGnm, the second switch tube 204 includes SF1-SFn, the reset switch tube 205 includes RST1-RSTn, the row selection switch tube 206 includes SET1-SETn, and the floating amplifier 201 includes FD1-FDn.

[0048] Alternatively, m represents the number of rows of photodiodes, which can be understood as follows: for each column, a mixed analog-to-digital conversion circuit 207 is arranged, which can read out the digital voltage value of a column of photodiodes. As shown, Figure 3 As shown, the first row of photodiodes can include PD11-PD1m, the nth row of photodiodes can include PDn1-PDnm, and assuming that the first column of photodiodes is the first photodiode, the first photodiode in the first row of photodiodes can be PD11, and the first photodiode in the nth row of photodiodes can be PDn1. n is a positive integer less than or equal to N. In the embodiment of the present application, the first switch tube 203 in the at least one voltage detection circuit 20 includes TG11-TG1m, TG21-TG2m,..., TG(n-1)1-TG(n-1)m, TG1n-TGmn, the second switch tube 204 includes SF1-SFn, the reset switch tube 205 includes RST1-RSTn, the row selection switch tube 206 includes SET1-SETn, and the floating amplifier 201 includes FD1-FDn.

[0049] Alternatively, please refer to Figure 4In some embodiments, the hybrid analog-digital conversion circuit 207 comprises an integral detection circuit 2071, a module-digital proportional module 2072, a third switch 2073 and a digital-analog hybrid processing module 2074, the integral detection circuit 2071 is connected with the positive output end of the reference DC power supply 202 through the third switch 2073, and the integral detection circuit is electrically connected with the reference level end-Vref and the digital-analog hybrid processing module 2074 respectively; the first input end of the module-digital proportional module 2072 is electrically connected with the common connection end of the third switch 2073 and the integral detection circuit 2071, and the second input end of the module-digital proportional module 2072 is electrically connected with the positive output end of the reference DC power supply 202 through the third switch 2073, and the output end of the module-digital proportional module 2072 is electrically connected with the digital-analog hybrid processing module 2074; wherein,

[0050] The third switch 2073 is used for controlling the positive output end of the reference DC power supply 202 to be electrically connected with the first input end of the module-digital proportional module 2072 or the second input end of the module-digital proportional module 2072, the integral detection circuit 2071 is used for detecting the digital voltage value corresponding to the analog voltage of the output of a first light-sensitive diode in the m light-sensitive diodes 101, the module-digital proportional module 2072 is used for detecting the ratio of the output analog voltage of m-1 second light-sensitive diodes to the first light-sensitive diode in the m light-sensitive diodes 101, and the digital-analog hybrid processing module is used for determining the digital voltage value of the m-1 second light-sensitive diodes according to the digital voltage value of the first light-sensitive diode and the ratio.

[0051] In the embodiments of the present application, the third switch 2073 can be a single-pole double-throw switch, when the third switch 2073 controls the first input end of the module-digital proportional module 2072 to be conductively connected with the positive output end of the reference DC power supply 202, the analog voltage of the first light-sensitive diode can be read and output to the module-digital proportional module 2072 and the integral detection circuit 2071, so that the integral detection circuit detects the digital voltage value corresponding to the analog voltage of the first light-sensitive diode.

[0052] When the third switch 2073 controls the second input end of the module-digital proportional module 2072 to be conductively connected with the positive output end of the reference DC power supply 202, the analog voltages of the m-1 second light-sensitive diodes can be read in sequence and output to the second input end of the module-digital proportional module 2072 in series, and the module-digital proportional module 2072 can output a proportional vector, which is used for representing the ratio of each second light-sensitive diode to the first light-sensitive diode.

[0053] It should be noted that when the analog voltages of the m-1 second photodiodes are input to the analog-digital proportional module 2072 in parallel, the analog-digital proportional module 2072 needs to support the parallel input mode, that is, needs to include multiple second input terminals, and when the analog-digital proportional module 2072 includes multiple second input terminals, the analog voltages of the m-1 second photodiodes can be input in parallel in groups.

[0054] Optionally, in some embodiments, the integral detection circuit 2071 includes an integral circuit 20711, a sample-and-hold amplifier (SHA) 20712, a first comparator 20713, a counter 20714, a logic module 20715, and an encoder 20716.

[0055] An input terminal of the integral circuit 20711 is electrically connected with the reference level terminal -Vref, and an output terminal of the integral circuit is connected with one input terminal of the first comparator 20713;

[0056] An input terminal of the sample-and-hold amplifier 20712 is electrically connected with the positive output terminal of the reference DC power supply 202 through the third switch 2073, and the input terminal of the sample-and-hold amplifier 20712 is electrically connected with the first input terminal of the analog-digital proportional module 2072, and an output terminal of the sample-and-hold amplifier 20712 is connected with another input terminal of the first comparator 20713;

[0057] An output terminal of the first comparator 20713 is electrically connected with the logic module 20715;

[0058] The logic module 20715 is electrically connected with a control terminal of the integral circuit 20711, and the logic module 20715 is electrically connected with the counter 20714 and the encoder 20716 respectively;

[0059] The encoder 20716 is electrically connected with the counter 20714 and the digital-analog hybrid processing module 2074 respectively.

[0060] In the embodiment of the present application, the integral circuit can include a second comparator, a resistor, a capacitor, and a fourth switch, a first input terminal of the second comparator is electrically connected with the reference level terminal -Vref through the resistor, the first input terminal of the second comparator is electrically connected with an output terminal of the second comparator through the capacitor, a second input terminal of the second comparator is grounded, the fourth switch is connected in parallel across the capacitor, and the fourth switch is electrically connected with the logic module 20715.

[0061] It should be noted that the integral circuit 20711 is controlled by the logic module 20715 to open and close the fourth switch tube at a fixed frequency, so that -Vref is boosted at a fixed step and Vc is output. Vc is connected to the input end of the comparison circuit. Taking the m photodiodes 101 as the first row of photodiodes 101 as an example, the analog voltage output by the first row of photodiodes 101 is V11-V1m. V11 is input into the first comparator 20713 and the analog-digital proportional module 2072. V12-V1m also need to be input into the analog-digital proportional module 2072.

[0062] The second comparator judges whether Vc reaches V11. When Vc reaches V11, the first comparator 20713 outputs a signal to the logic module 20715, which controls the encoder 20716 to output the corresponding V11 digital value (i.e., the digital voltage value) to the digital-analog hybrid processing module 2074.

[0063] V12-V1m are input into the analog-digital proportional module 2072. The analog-digital proportional module 2072 takes V11 as the reference voltage and calculates the proportional vectors of V12-V1m relative to V11. Assuming that V11 is 10V and V12 is 15V, the proportional vector of V12 is 1.5. Similarly, the proportional vectors of other photodiodes 101 can also be calculated. The proportional vectors also need to be input into the digital-analog hybrid processing module 2074.

[0064] The digital-analog hybrid processing module 2074 can calculate the proportional vectors and the V11 digital value to obtain all digital values of V12-V1m. For example, the digital value of V11 is 500LSB, and the proportional vector of V12 is 1.5, so the digital value of V12 is 750LSB.

[0065] Optionally, the embodiment of the present application further provides an electronic device, which comprises a pixel circuit. The structure of the pixel circuit can refer to the above-mentioned embodiments, which will not be described here. Since the electronic device provided by the embodiment of the present application comprises the pixel circuit in the above-mentioned embodiments, the electronic device provided by the embodiment of the present application has all the beneficial effects of the pixel circuit in the above-mentioned embodiments.

[0066] Optionally, referring to Figure 5 , the embodiment of the present application further provides an image acquisition method, which is applied to the above-mentioned electronic device, as shown in Figure 5 , the method comprises:

[0067] Step 501, detecting the digital voltage value corresponding to the analog voltage output by a first photodiode in the m photodiodes and the ratio of the output analog voltage of m-1 second photodiodes in the m photodiodes to the first photodiode.

[0068] determining the digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio of the output analog voltage of the m-1 second photodiodes to the first photodiode;

[0069] generating an image according to the digital voltage value of the first photodiode and the digital voltage values of the m-1 second photodiodes;

[0070] The m photodiodes include at least one row or at least one column of the photodiodes in the photodiode array.

[0071] In the embodiment, the digital voltage values of the m-1 second photodiodes are determined according to the digital voltage value of the first photodiode and the ratio of the output analog voltage of the m-1 second photodiodes to the first photodiode, so that the digital voltage values of the m photodiodes can be obtained by integrating the light signal only once, thereby reducing the time for obtaining the digital voltage values of the photodiodes and further reducing the time delay of image generation.

[0072] Optionally, detecting the ratio of the output analog voltage of the m-1 second photodiodes to the first photodiode includes:

[0073] detecting the output analog voltage of the first photodiode and the output analog voltage of the m-1 second photodiodes;

[0074] inputting the output analog voltage of the first photodiode and the output analog voltage of the m-1 second photodiodes into the analog-digital proportional module respectively to obtain the ratio of the output analog voltage of the m-1 second photodiodes to the first photodiode.

[0075] Optionally, the inputting the output analog voltage of the first photodiode and the output analog voltage of the m-1 second photodiodes into the analog-digital proportional module includes:

[0076] inputting the output analog voltage of the first photodiode into the first input end of the analog-digital proportional module at the first time;

[0077] inputting the output analog voltage of the m-1 second photodiodes into the second input end of the analog-digital proportional module at different times respectively;

[0078] The time when the output analog voltage of the second photodiode is input into the second input end of the analog-digital proportional module is after the first time.

[0079] In the description of the application, reference has been made to descriptive terms such as "one embodiment", "some embodiments", "an embodiment", "example", "specific example" or "some examples" etc. Such terminology means that a particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the application. The illustrative appearances of such terminology in various places in the specification does not necessarily refer to the same embodiment or example. Moreover, it is appreciated that the specific features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0080] Although embodiments of this application have been shown and described, it is to be understood that various modifications, substitutions, combinations, and variations can be made therein without departing from the spirit and scope of the application, which is defined by the appended claims and their equivalents.

Claims

1. A pixel circuit, characterized in that, The application relates to a voltage detection circuit. The voltage detection circuit comprises a photodiode array and at least one voltage detection circuit, wherein, m photodiodes in the photodiode array are electrically connected with one voltage detection circuit; The m photodiodes comprise at least one row or at least one column of the photodiodes in the photodiode array; The voltage detection circuit comprises a floating amplifier, a reference direct-current power supply, a first switch tube, a second switch tube, a row selection switch tube and a hybrid analog-digital conversion circuit, wherein the number of the first switch tubes is m, and the m first switch tubes are connected with the m photodiodes one by one. The first end of the floating amplifier is electrically connected with the cathodes of the m photodiodes through the m first switch tubes, and the first end of the floating amplifier is connected with the control end of the second switch tube; the second end of the floating amplifier is grounded, and the anodes of the m photodiodes are grounded. The positive output end of the reference direct-current power supply is electrically connected with a high-level end through the row selection switch tube and the second switch tube in sequence, and the positive output end of the reference direct-current power supply is also connected with the hybrid analog-digital conversion circuit. The hybrid analog-digital conversion circuit is used for detecting the digital voltage value corresponding to the analog voltage of the output of a first photodiode in the m photodiodes and the ratio of the output analog voltage of m-1 second photodiodes to the output analog voltage of the first photodiode, and determining the digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio. The hybrid analog-digital conversion circuit comprises an integral detection circuit, a module for converting a module into a proportion, a third switch and a digital-analog hybrid processing module; the integral detection circuit is connected with the positive output end of the reference direct-current power supply through the third switch, and the integral detection circuit is electrically connected with a reference level end and the digital-analog hybrid processing module respectively; the first input end of the module for converting a module into a proportion is electrically connected with the common connection end of the third switch and the integral detection circuit, and the second input end of the module for converting a module into a proportion is electrically connected with the positive output end of the reference direct-current power supply through the third switch; and the output end of the module for converting a module into a proportion is electrically connected with the digital-analog hybrid processing module.

2. The pixel circuit of claim 1, wherein, The voltage detection circuit further comprises a reset switch tube, and the first end of the floating amplifier is also electrically connected with the high-level end through the reset switch tube.

3. The pixel circuit of claim 2, wherein, Each row of photodiodes is electrically connected with the same floating amplifier through the first switch tubes, or each column of photodiodes is electrically connected with the same floating amplifier through the first switch tubes.

4. The pixel circuit of claim 3, wherein, The photodiode array comprises m*N photodiodes, wherein, N represents the number of rows of photodiodes, and m represents the number of columns of photodiodes, and the m photodiodes are one row of photodiodes; Or, m represents the number of rows of photodiodes, and N represents the number of columns of photodiodes, and the m photodiodes are one column of photodiodes.

5. The pixel circuit according to any one of claims 2 to 4, characterized in that, The third switch is used for controlling the positive output end of the reference direct current power supply to be electrically connected with the first input end of the analog-digital proportional module or the second input end of the analog-digital proportional module, the integral detection circuit is used for detecting a digital voltage value corresponding to an analog voltage of an output of a first one of the m photodiodes, the analog-digital proportional module is used for detecting a ratio of the output analog voltage of the first photodiode to output analog voltages of m-1 second photodiodes of the m photodiodes, and the digital-analog hybrid processing module is used for determining digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio.

6. The pixel circuit of claim 5, wherein, The integral detection circuit comprises an integral circuit, a sample-and-hold device, a first comparator, a counter, a logic module and an encoder. An input end of the integral circuit is electrically connected with the reference level end, and an output end of the integral circuit is connected with one input end of the first comparator. An input end of the sample-and-hold device is electrically connected with the positive output end of the reference direct current power supply through the third switch, and the input end of the sample-and-hold device is electrically connected with the first input end of the analog-digital proportional module, and an output end of the sample-and-hold device is connected with another input end of the first comparator. An output end of the first comparator is electrically connected with the logic module. The logic module is electrically connected with a control end of the integral circuit, and the logic module is electrically connected with the counter and the encoder respectively. The encoder is electrically connected with the counter and the digital-analog hybrid processing module respectively.

7. An electronic device, comprising: The pixel circuit comprises any one of the pixel circuits in claims 1 to 6.

8. An image acquisition method applied to the electronic device of claim 7, characterized in that, The pixel circuit comprises: detecting a digital voltage value corresponding to an analog voltage of an output of a first one of the m photodiodes based on the integral detection circuit, and detecting a ratio of the output analog voltage of the first photodiode to output analog voltages of m-1 second photodiodes of the m photodiodes based on the analog-digital proportional module; determining digital voltage values of the m-1 second photodiodes according to the digital voltage value of the first photodiode and the ratio based on the digital-analog hybrid processing module; generating an image according to the digital voltage value of the first photodiode and the digital voltage values of the m-1 second photodiodes. The m photodiodes comprise at least one row or at least one column of the photodiodes in the photodiode array.

9. The method of claim 8, wherein, The detecting the ratio of the output analog voltage of the first photodiode to output analog voltages of m-1 second photodiodes of the m photodiodes comprises: detecting the output analog voltage of the first photodiode and the output analog voltages of the m-1 second photodiodes of the m photodiodes; inputting the output analog voltage of the first photodiode and the output analog voltages of the m-1 second photodiodes of the m photodiodes into the analog-digital proportional module respectively to obtain the ratio of the output analog voltage of the first photodiode to the output analog voltages of the m-1 second photodiodes of the m photodiodes.

10. The method of claim 9, wherein, The method comprises the following steps: inputting the output analog voltage of the first photodiode and the output analog voltage of m-1 second photodiodes of the m photodiodes into a module voltage proportion module, respectively, comprises: inputting the output analog voltage of the first photodiode into a first input end of the module voltage proportion module at a first time; inputting the output analog voltage of the m-1 second photodiodes into a second input end of the module voltage proportion module at different times, respectively; wherein the time when the output analog voltage of the second photodiode is input into the second input end of the module voltage proportion module is after the first time.

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