Dielectric relaxation metrology structures, systems, and methods and semiconductor devices

Abstract

The present disclosure relates to a dielectric relaxation measurement structure, system and method and a semiconductor device, wherein the dielectric relaxation measurement structure is used to measure the dielectric relaxation of a capacitor in the semiconductor device, the semiconductor device comprising a substrate, and the capacitor being formed on the substrate; the dielectric relaxation measurement structure comprising: a charging probe set and a measurement probe set formed on the substrate, the charging probe set comprising a first charging probe connected with a first electrode layer of the capacitor and a second charging probe connected with a second electrode layer of the capacitor, the first charging probe and the second charging probe being conductive with a charging device to enable charging of the capacitor; the measurement probe set comprising a first measurement probe connected with the first electrode layer of the capacitor and a second measurement probe connected with the second electrode layer of the capacitor, the first measurement probe and the second measurement probe being conductive with a detection device to enable detection of the dielectric relaxation of the capacitor after stopping charging of the capacitor. The present disclosure can improve the accuracy of dielectric relaxation detection.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor chips, and specifically relates to a dielectric relaxation measurement structure, system, and method, as well as a semiconductor device. Background Technology

[0002] With the continuous development of the DRAM (Dynamic Random Access Memory) chip industry, the size of capacitors is constantly shrinking and the storage density is increasing. At the same time, it also requires DRAM read and write speeds to be further accelerated. Therefore, dielectric relaxation has become an unavoidable influencing factor. Among them, dielectric relaxation time is very short. How to effectively characterize dielectric relaxation and achieve rapid and accurate screening of dielectric materials is a technical problem that urgently needs to be solved. Summary of the Invention

[0003] This disclosure provides a dielectric relaxation measurement structure, system, method, and semiconductor device to improve the accuracy of dielectric relaxation detection.

[0004] This disclosure provides a dielectric relaxation measurement structure for measuring the dielectric relaxation of a capacitor in a semiconductor device. The semiconductor device includes a substrate, and the capacitor is formed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer. The dielectric relaxation measurement structure includes:

[0005] A charging probe group is formed on the substrate. The charging probe group includes a first charging probe electrically connected to the first electrode layer and a second charging probe electrically connected to the second electrode layer. The first charging probe and the second charging probe are used to conduct with a charging device to charge the capacitor.

[0006] A measurement probe group is formed on the substrate. The measurement probe group includes a first measurement probe electrically connected to the first electrode layer and a second measurement probe electrically connected to the second electrode layer. The first measurement probe and the second measurement probe are used to conduct to a detection device when the charging device stops charging the capacitor, so as to detect the dielectric relaxation of the capacitor.

[0007] In one exemplary embodiment of this disclosure, the dielectric relaxation measurement structure further includes a first conductive structure and a second conductive structure formed on the substrate; wherein,

[0008] The first charging probe and the first measuring probe are spaced apart. One end of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first electrode layer.

[0009] The second charging probe and the second measuring probe are spaced apart. One end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second electrode layer.

[0010] In one exemplary embodiment of this disclosure, the semiconductor device further includes a planarization layer formed on the substrate, the planarization layer covering the capacitor; wherein,

[0011] The first charging probe, the second charging probe, the first measurement probe, and the second measurement probe are formed on the surface of the planarization layer away from the capacitor;

[0012] The first conductive structure penetrates the planarization layer, the top end of the first conductive structure is electrically connected to the first measurement probe and the first charging probe, and the bottom end of the first conductive structure is in contact with the first electrode layer.

[0013] The second conductive structure penetrates the planarization layer, the top end of the second conductive structure is electrically connected to the second measurement probe and the second charging probe, and the bottom end of the second conductive structure is in contact with the second electrode layer.

[0014] In one exemplary embodiment of this disclosure, the first electrode layer is parallel to the substrate, the first electrode layer includes a first main region and a first edge region surrounding the first main region, the second electrode layer is formed on the side of the first electrode layer away from the substrate, and the orthographic projections of the second electrode layer and the dielectric material layer on the substrate lie within the orthographic projection of the first main region on the substrate; wherein,

[0015] The first conductive structure is disposed around the second conductive structure. The orthographic projection of the first conductive structure on the substrate overlaps with the orthographic projection of the first edge region on the substrate, and the bottom end of the first conductive structure is in contact with the first edge region. The orthographic projection of the second conductive structure on the substrate is located within the orthographic projection of the second electrode layer on the substrate.

[0016] In an exemplary embodiment of this disclosure, the first conductive structure includes a first adapter portion and a first via portion. The first adapter portion is located on the surface of the planarization layer away from the capacitor and is electrically connected to the first measurement probe and the first charging probe. The orthographic projection of the first via portion on the substrate is located within the orthographic projection of the first adapter portion on the substrate. The first via portion penetrates the planarization layer, and the top end of the first via portion contacts the first adapter portion, and the bottom end of the first via portion contacts the first edge region.

[0017] The second conductive structure includes a second transition portion and a second via portion. The second transition portion is located on the surface of the planarization layer away from the capacitor and is electrically connected to the second measurement probe and the second charging probe. The orthographic projection of the second via portion on the substrate is located within the orthographic projection of the second transition portion on the substrate. The second via portion penetrates the planarization layer, and the top end of the second via portion is in contact with the second transition portion, and the bottom end of the second via portion is in contact with the second electrode layer.

[0018] The first adapter portion is arranged around the second adapter portion, and multiple first through-hole portions are arranged at intervals along the circumference to surround the second through-hole portions.

[0019] In one exemplary embodiment of this disclosure, the orthographic projections of the first charging probe, the second charging probe, the first measurement probe, and the second measurement probe on the substrate do not overlap with the orthographic projection of the capacitor on the substrate;

[0020] The dielectric relaxation measurement structure further includes a first lead and a second lead, the first lead and the second lead being formed on the surface of the planarization layer away from the capacitor, the first lead and the second lead including a main section and a branch section, the main section and the branch section having a first end and a second end, the first end of the branch section being located between the first end and the second end of the main section and connected to the main section;

[0021] In the first lead: the first end of the main section is in contact with the first adapter, the second end of the main section is in contact with one of the first charging probe and the first measurement probe, and the second end of the branch section is in contact with the other of the first charging probe and the first measurement probe.

[0022] In the second lead: the first end of the main section is in contact with the second adapter, the second end of the main section is in contact with one of the second charging probe and the second measuring probe, and the second end of the branch section is in contact with the other of the second charging probe and the second measuring probe.

[0023] The first adapter has a clearance opening through which the main section of the second lead passes, and the main section of the second lead and the first adapter have a gap at the clearance opening.

[0024] In one exemplary embodiment of this disclosure, the second end of the main section of the first lead is in contact with the first measurement probe, and the first charging probe is located on the side of the first measurement probe away from the first adapter.

[0025] The second end of the main section of the second lead is in contact with the second measurement probe, and the second charging probe is located on the side of the second measurement probe away from the second adapter.

[0026] In one exemplary embodiment of this disclosure, the orthographic projection of the dielectric material layer on the substrate completely coincides with the orthographic projection of the second electrode layer on the substrate, and the second electrode layer and the dielectric material layer include a second main region and a second edge region surrounding the second main region;

[0027] The orthographic projection of the second conductive structure on the substrate lies within the orthographic projection of the second main region on the substrate.

[0028] In one exemplary embodiment of this disclosure, the semiconductor device further includes an interlayer dielectric layer formed on the substrate, located on the side of the planarization layer close to the substrate;

[0029] The interlayer dielectric layer covers the edge of the first main region and the edge region, and the interlayer dielectric layer has a through hole, which is exposed in the middle of the first main region.

[0030] The second edge region overlaps the surface of the interlayer dielectric layer away from the first electrode layer, and the second main region is formed within the through hole;

[0031] Wherein, when the first conductive structure penetrates the planarization layer and contacts the first electrode layer, it also penetrates the interlayer dielectric layer to contact the first edge region.

[0032] In one exemplary embodiment of this disclosure, the dielectric relaxation measurement structure further includes:

[0033] A grounding probe is formed on the side of the planarization layer away from the substrate for grounding;

[0034] A grounding shield extends through the planarization layer. The top end of the grounding shield is electrically connected to the grounding probe, and the bottom end of the grounding shield extends toward the substrate. The orthographic projection of the grounding shield on the substrate is located on at least two opposite sides of the orthographic projection of the capacitor on the substrate.

[0035] In one exemplary embodiment of this disclosure, the surface of the grounding shield near the substrate is lower than or flush with the surface of the capacitor near the substrate.

[0036] In one exemplary embodiment of this disclosure, the orthographic projections of the first charging probe, the first measurement probe, the second charging probe, and the second measurement probe on the substrate do not overlap with the orthographic projection of the capacitor on the substrate;

[0037] The horizontal distance between the grounding shield and the capacitor is less than the horizontal distance between the first charging probe, the first measuring probe, the second charging probe, the second measuring probe and the capacitor.

[0038] In one exemplary embodiment of this disclosure, the first charging probe and the first measurement probe form a first probe group, and the second charging probe and the second measurement probe form a second probe group, and the first probe group and the second probe group are arranged in a first direction.

[0039] The first conductive structure and the second conductive structure are located between the first probe group and the second probe group. The surface of the first conductive structure facing the first probe group is connected to the first charging probe and the first measurement probe through a first lead. The surface of the second conductive structure facing the second probe group is connected to the second charging probe and the second measurement probe through a second lead.

[0040] The first lead and the second lead are formed on the surface of the planarization layer away from the capacitor. The surface of the ground shield away from the substrate is flush with or higher than the surfaces of the first lead and the second lead near the planarization layer.

[0041] Two grounding shields are provided and arranged in a second direction. The capacitor is located between the two grounding shields, and the second direction intersects the first direction.

[0042] The two grounding shields are arranged at intervals on the side near the first probe group to form a first clearance notch for the first lead to pass through, and the first lead has a gap at the first clearance notch. The two grounding shields are arranged at intervals on the side near the second probe group to form a second clearance notch for the second lead to pass through, and the second lead has a gap at the second clearance notch. Each grounding shield is electrically connected to the grounding probe through a grounding lead.

[0043] In one exemplary embodiment of this disclosure, the ground lead is formed on the side of the planarization layer away from the substrate; and / or

[0044] The grounding probe is formed on the side of one of the first probe group and the second probe group that is away from the first conductive structure and the second conductive structure.

[0045] In one exemplary embodiment of this disclosure, the grounding shield is an elongated strip structure extending in the first direction; or

[0046] The grounding shield includes a main shield extending in the first direction and a secondary shield located at both ends of the main shield, the secondary shield extending in the second direction.

[0047] In one exemplary embodiment of this disclosure, the first measurement probe is disposed closer to the first conductive structure than the first charging probe;

[0048] The second measurement probe is positioned closer to the second conductive structure than the second charging probe.

[0049] A second aspect of this disclosure provides a semiconductor device comprising:

[0050] Substrate;

[0051] A capacitor, formed on the substrate, the capacitor including a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer; and

[0052] A dielectric relaxation measurement structure is formed on the substrate and includes a charging probe group and a measurement probe group. The charging probe group includes a first charging probe electrically connected to a first electrode layer and a second charging probe electrically connected to a second electrode layer. The first charging probe and the second charging probe are configured to be connected to a charging device to charge the capacitor. The measurement probe group includes a first measurement probe electrically connected to the first electrode layer and a second measurement probe electrically connected to the second electrode layer. The first measurement probe and the second measurement probe are configured to be connected to a detection device when the charging device stops charging the capacitor, so as to measure the dielectric relaxation of the capacitor.

[0053] In one exemplary embodiment of this disclosure, the first electrode layer is parallel to the substrate, and the second electrode layer is formed on the side of the first electrode layer away from the substrate.

[0054] A third aspect of this disclosure provides a dielectric relaxation measurement system for measuring the dielectric relaxation of a capacitor in a semiconductor device. The semiconductor device includes a substrate, and the capacitor is formed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer. The dielectric relaxation measurement system includes:

[0055] Control device;

[0056] A dielectric relaxation measurement structure is formed on the substrate and includes a charging probe group and a measurement probe group. The charging probe group includes a first charging probe electrically connected to the first electrode layer and a second charging probe electrically connected to the second electrode layer. The measurement probe group includes a first measurement probe electrically connected to the first electrode layer and a second measurement probe electrically connected to the second electrode layer.

[0057] A charging device is electrically connected to the control device. Under the control of the control device, the charging device can connect with the first charging probe and the second charging probe to charge the capacitor. The charging device can also disconnect from the first charging probe and the second charging probe under the action of the control device to stop charging the capacitor.

[0058] The detection device is electrically connected to the control device. The detection device can conduct to the first measurement probe and the second measurement probe under the control of the control device when the charging device stops charging the capacitor, so as to detect the dielectric relaxation of the capacitor.

[0059] In one exemplary embodiment of this disclosure, the detection device includes an ammeter, which is connected in series between the first measurement probe and the second measurement probe under the control of the control device when the charging device stops charging the capacitor; or

[0060] The detection device includes a voltmeter and a jumper wire. The voltmeter can be connected in series between the first measuring probe and the second measuring probe under the action of the control device when the charging device stops charging the capacitor. The jumper wire can be shorted between the first charging probe and the second charging probe under the control of the control device when the charging device stops charging the capacitor.

[0061] This disclosure provides a dielectric relaxation measurement method for measuring the dielectric relaxation of a capacitor in a semiconductor device. The semiconductor device includes a substrate, and the capacitor is formed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer. The dielectric relaxation measurement method includes:

[0062] A dielectric relaxation measurement structure is formed on the substrate. The dielectric relaxation measurement structure includes a charging probe group and a measurement probe group. The charging probe group includes a first charging probe electrically connected to the first electrode layer and a second charging probe electrically connected to the second electrode layer. The measurement probe group includes a first measurement probe electrically connected to the first electrode layer and a second measurement probe electrically connected to the second electrode layer.

[0063] The control charging device is connected in conjunction with the first charging probe and the second charging probe to charge the capacitor;

[0064] After the capacitor is fully charged, the charging device is controlled to stop charging the capacitor. At the same time, the detection device is controlled to connect with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor.

[0065] In an exemplary embodiment of this disclosure, the step of controlling the detection device to cooperate with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor includes:

[0066] A control ammeter is connected in series between the first measuring probe and the second measuring probe to measure the current.

[0067] The dielectric relaxation of the capacitor is characterized by the measured current versus time curve.

[0068] In an exemplary embodiment of this disclosure, the step of controlling the detection device to cooperate with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor includes:

[0069] A control voltmeter is connected in series between the first measurement probe and the second measurement probe, and the first charging probe and the second charging probe are short-circuited to perform voltage measurement;

[0070] The dielectric relaxation of the capacitor is characterized by measured voltage changes. The technical solution provided in this disclosure has at least the following advantages: By setting two sets of probes—one a charging probe set for connecting to the charging device to charge the capacitor, and the other a measurement probe set for connecting to the detection device after charging stops to detect the dielectric relaxation of the capacitor—compared to a solution using a shared probe set for both charging and dielectric relaxation detection, this solution eliminates the need for the switching step of first disconnecting the charging device from the shared probe set and then connecting the detection device to the shared probe set during the dielectric relaxation detection process. This solution allows the detection device to be directly connected to the measurement probe set immediately after the charging device stops charging the capacitor to detect the dielectric relaxation of the capacitor. This saves switching time, reduces measurement errors during dielectric relaxation detection, and provides a more accurate characterization of the dielectric relaxation, thereby achieving rapid and accurate screening of dielectric materials. Attached Figure Description

[0071] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0072] Figure 1 A schematic diagram of the planar structure of the dielectric relaxation measurement structure and the capacitor according to an embodiment of the present disclosure is shown.

[0073] Figure 2 It shows Figure 1 The diagram shows a cross-sectional view of the structure along the AA direction.

[0074] Figure 3 It shows Figure 1 The diagram shows a cross-sectional view of the structure along the BB direction.

[0075] Figure 4 It shows Figure 2 Enlarged structural diagram of section C.

[0076] Figure 5 A schematic diagram of a planar structure for dielectric relaxation measurement and capacitance matching, as shown in another embodiment of this disclosure, is illustrated.

[0077] Figures 6 to 13 The diagram shows a schematic representation of the steps in the manufacturing process corresponding to the formation of the dielectric relaxation measurement structure in a semiconductor device according to an embodiment of this disclosure.

[0078] Figure 14 A schematic flowchart of the dielectric relaxation measurement method shown in the embodiments of this disclosure is illustrated. Detailed Implementation

[0079] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0080] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0081] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0082] Dielectric relaxation is the process by which a dielectric material, after being subjected to (or having an) an external electric field, moves from an instantaneously established polarization state to a new polarization equilibrium state. The time it takes for the dielectric polarization to reach a steady state is called the relaxation time.

[0083] Dielectric relaxation affects the outflow rate of stored charge in a capacitor, thus affecting the read and write speed of chips such as DRAM, which include capacitors. Therefore, how to quickly and accurately select dielectric materials with minimal impact on read and write speed has become an urgent problem to be solved.

[0084] Based on this, the present disclosure provides a dielectric relaxation measurement structure that can be applied to semiconductor devices. Specifically, the semiconductor device may include a substrate and a capacitor formed on the substrate, and the dielectric relaxation measurement structure may be formed on the substrate and electrically connected to the capacitor for measuring the dielectric relaxation of the capacitor in the semiconductor device.

[0085] The following detailed description, with reference to the accompanying drawings, illustrates the relationship between the dielectric relaxation measurement structure and the capacitance in an embodiment of this disclosure. Figures 1 to 3 As shown, the dielectric relaxation measurement structure of this embodiment may include a charging probe group 12 and a measurement probe group 13, both of which are formed on the substrate 10 of the semiconductor device.

[0086] For example, substrate 10 may include a semiconductor substrate 101 and an insulating isolation layer 102 formed on the semiconductor substrate 101. The semiconductor substrate 101 may be a silicon substrate, but is not limited to it; it may also be a substrate formed of other semiconductor materials (e.g., silicon carbide, gallium compounds, germanium compounds). The insulating isolation layer 102 may be a single-layer structure, such as an insulating material layer of SiO2 (silicon dioxide) or SiON (silicon oxynitride), but is not limited to it. The insulating isolation layer 102 may also be a multi-layer stacked structure, such as including sequentially stacked layers of silicon oxide, silicon nitride, silicon oxide, silicon nitride, etc. It should be understood that when the insulating isolation layer 102 is a multi-layer stacked structure, it is not limited to the four layers mentioned in the example; it may also be two, three, five, etc. The number of layers and materials can be determined according to specific circumstances, and will not be described in detail here.

[0087] The capacitor 11, the charging probe group 12, and the measurement probe group 13 can be formed on the same side of the substrate 10 to simplify the fabrication process of the dielectric relaxation measurement structure and reduce the fabrication cost. Specifically, the capacitor 11, the charging probe group 12, and the measurement probe group 13 can form an insulating isolation layer 102 on the side away from the semiconductor substrate 101.

[0088] In this embodiment, combined with Figures 2 to 4 As shown, capacitor 11 may include a first electrode layer 111, a second electrode layer 112, and a dielectric material layer 113 formed between the first electrode layer 111 and the second electrode layer 112.

[0089] For example, the material of the first electrode layer 111 can be a conductive material such as titanium nitride (TiN), and the material of the second electrode layer 112 can be a conductive material such as silicon germanium (SiGe). It should be noted that the first electrode layer 111 and the second electrode layer 112 are not limited to the materials mentioned above, and can also be other conductive materials, as long as the first electrode layer 111 and the second electrode layer 112 of the capacitor 11 can have good conductivity. The dielectric material layer 113 can be a dielectric material with a high K value.

[0090] Combination Figures 1 to 4 As shown, the charging probe group 12 may include a first charging probe 121 electrically connected to the first electrode layer 111 and a second charging probe 122 electrically connected to the second electrode layer 112. The first charging probe 121 and the second charging probe 122 are used to conduct with the charging device to charge the capacitor 11. The measurement probe group 13 may include a first measurement probe 131 electrically connected to the first electrode layer 111 and a second measurement probe 132 electrically connected to the second electrode layer 112. The first measurement probe 131 and the second measurement probe 132 are used to conduct with the detection device when the charging device stops charging the capacitor 11 to detect the dielectric relaxation of the capacitor 11.

[0091] For example, the first charging probe 121, the second charging probe 122, the first measurement probe 131 and the second measurement probe 132 can be conductive materials such as titanium nitride (TiN), but are not limited to these, and can also be other conductive materials, which will not be explained in detail here.

[0092] This scheme uses two sets of probes: a charging probe set 12, which is connected to the charging device to charge the capacitor 11; and a measurement probe set 13, which is connected to the detection device after charging of the capacitor 11 stops to detect the dielectric relaxation of the capacitor 11. Compared with a scheme that uses a single shared probe set for both charging and dielectric relaxation detection, the probes connected to the detection device and the power supply device in this scheme are positioned differently. During the detection of the dielectric relaxation of the capacitor 11, there is no need to disconnect the charging device from the shared probe set and then reconnect the detection device. This scheme allows the detection device to be directly connected to the measurement probe set 13 to detect the dielectric relaxation of the capacitor 11 as soon as the charging device stops charging the capacitor 11. This reduces the time spent during the switching process, lowers the measurement error during dielectric relaxation detection, and provides a more accurate characterization of the dielectric relaxation, thereby enabling rapid and accurate screening of dielectric materials.

[0093] It should be understood that, in order to ensure the normal use of capacitor 11, the first charging probe 121 and the second charging probe 122 in this embodiment need to be set apart, and the first measurement probe 131 and the second measurement probe 132 need to be set apart, so as to avoid the situation where the first electrode layer 111 and the second electrode layer 112 in capacitor 11 are always in a short-circuited state under any state due to the direct contact of the first charging probe 121 and the second charging probe 122 or the direct contact of the first measurement probe 131 and the second measurement probe 132, which would cause capacitor 11 to malfunction.

[0094] In one embodiment of this disclosure, capacitor 11 can be a parallel-plate capacitor. Specifically, in conjunction with... Figures 2 to 4 As shown, the first electrode layer 111 is a planar electrode, that is, the first electrode layer 111 can be parallel to the substrate 10, while the second electrode layer 112 can be formed on the side of the first electrode layer 111 away from the substrate 10. In other words, the first electrode layer 111, the dielectric material layer 113 and the second electrode layer 112 can be stacked sequentially in a direction perpendicular to the substrate 10; wherein, at least a portion of the second electrode layer 112 and the dielectric material layer 113 are parallel to the first electrode layer 111.

[0095] In this embodiment, by setting capacitor 11 as a parallel plate capacitor, the dielectric relaxation of the detected capacitor 11 is mainly related to the material properties of the dielectric material layer 113 itself. This allows for better acquisition of the dielectric relaxation of the dielectric material layer 113, enabling rapid screening of whether the dielectric material meets the chip read / write speed requirements.

[0096] It should be understood that the capacitor 11 in the embodiments of this disclosure is not limited to a parallel plate capacitor, but may also be a capacitor tube. The structure of the capacitor tube will not be described in detail here.

[0097] In this embodiment, as Figure 1 As shown, the first charging probe 121 and the first measuring probe 131 are spaced apart, and the second charging probe 122 and the second measuring probe 132 are spaced apart, so as to avoid the detection device and the power supply device colliding due to the charging probe and the measuring probe being too close.

[0098] Among them, combined Figures 1 to 4 As shown, the dielectric relaxation measurement structure may further include a first conductive structure 14 and a second conductive structure 15 formed on the substrate 10. One end of the first conductive structure 14 is electrically connected to the first measurement probe 131 and the first charging probe 121, and the other end of the first conductive structure 14 is electrically connected to the first electrode layer 111. In other words, both the first measurement probe 131 and the first charging probe 121 are connected to the first conductive structure 14 and connected to the first electrode layer 111 through the first conductive structure 14. One end of the second conductive structure 15 is connected to the second measurement probe 132. The second measuring probe 132 and the second charging probe 122 are electrically connected, and the other end of the second conductive structure 15 is electrically connected to the second electrode layer 112. In other words, both the second measuring probe 132 and the second charging probe 122 are connected to the second conductive structure 15 and connected to the second electrode layer 112 through the second conductive structure 15. By setting the first conductive structure 14 and the second conductive structure 15, the charging position and the detection position on the first electrode layer 111 are the same, and the charging position and the detection position on the second electrode layer 112 are the same, so as to improve the accuracy of dielectric relaxation detection.

[0099] In a specific embodiment of this disclosure, combined with Figures 1 to 3 As shown, the semiconductor device may also include a planarization layer 16 formed on the substrate 10, which covers the capacitor 11. That is, the capacitor 11 may be formed on the substrate 10 first, and then the planarization layer 16 may be formed so that the planarization layer 16 covers the capacitor 11.

[0100] For example, the planarization layer 16 can be a multi-layer stacked structure, such as... Figure 2 and Figure 3As shown, the planarization layer 16 may include a silicon oxide material layer 161 and a silicon nitride material layer 162 formed sequentially. The silicon oxide material layer 161 may be polished to ensure flatness, while the resistivity of the silicon nitride material layer 162 is lower than that of the silicon oxide material layer 161, so as to better encapsulate and protect the underlying capacitor 11.

[0101] It should be noted that the planarization layer 16 is not limited to a multi-layer stacked structure, but can also be a single-layer structure, depending on the specific circumstances.

[0102] Among them, such as Figure 2 As shown, the first charging probe 121, the second charging probe 122, the first measurement probe 131, and the second measurement probe 132 can be formed on the surface of the planarization layer 16 away from the capacitor 11, and the first conductive structure 14 and the second conductive structure 15 can penetrate the planarization layer 16. Specifically, the top end of the first conductive structure 14 is electrically connected to the first measurement probe 131 and the first charging probe 121, and the bottom end of the first conductive structure 14 is in contact with the first electrode layer 111. The top end of the second conductive structure 15 is electrically connected to the second measurement probe 132 and the second charging probe 122, and the bottom end of the second conductive structure 15 is in contact with the second electrode layer 112.

[0103] It should be noted that, in this embodiment, the top end refers to the end of the structure away from the substrate 10, and the bottom end refers to the end of the structure close to the substrate 10.

[0104] In this embodiment, the orthographic projection of the first conductive structure 14 on the substrate 10 may overlap with the orthographic projection of the first electrode layer 111 on the substrate 10, so that at least a portion of the overlapping structure can penetrate the planarization layer 16 and contact the surface of the first electrode layer 111 away from the substrate 10. This ensures contact stability and reduces processing difficulty. Similarly, the orthographic projection of the second conductive structure 15 on the substrate 10 may overlap with the orthographic projection of the second electrode layer 112 on the substrate 10, so that at least a portion of the overlapping structure can penetrate the planarization layer 16 and contact the surface of the second electrode layer 112 away from the substrate 10. This ensures contact stability and reduces processing difficulty.

[0105] Optionally, combined Figure 4As shown, the first electrode layer 111 may include a first main region 1111 and a first edge region 1112 surrounding the first main region 1111. The orthographic projections of the second electrode layer 112 and the dielectric material layer 113 on the substrate 10 are located within the orthographic projection of the first main region 1111 on the substrate 10. The orthographic projection of the first conductive structure 14 on the substrate 10 overlaps with the orthographic projection of the first edge region 1112 on the substrate 10 and is in contact with the first edge region 1112. Compared with the scheme of opening insulating vias in the second electrode layer 112 and the dielectric material layer 113 for the first conductive structure 14 to pass through, this design eliminates the need to design insulating vias in the second electrode layer 112 and the dielectric material layer 113 to allow the first conductive structure 14 to contact the first electrode layer 111, thereby ensuring the overall performance of the capacitor 11.

[0106] The orthographic projection of the second conductive structure 15 on the substrate 10 is located within the orthographic projection of the second electrode layer 112 on the substrate 10, and the first conductive structure 14 can be arranged around the second conductive structure 15. This makes the electric field distribution more uniform and the measurement effect more accurate during dielectric relaxation measurement, and also makes the charging process shorter.

[0107] It should be noted that the surrounding structure mentioned in this disclosure can be either closed or open. Closed surrounding structure refers to a structure with no gaps around the entire circle, while open surrounding structure refers to a structure with at least one or more gaps around the entire circle. When there are multiple gaps, the surrounding structure is divided into multiple surrounding segments arranged at intervals in the circumferential direction.

[0108] Since the dielectric material layer 113 is very thin, typically only a few nanometers, the leakage current at the edges of the dielectric material layer 113 is significant. Edge leakage current is not an intrinsic characteristic of the material and will interfere with the measurement results. Therefore, to improve measurement accuracy, the following design can be implemented:

[0109] The orthographic projection of the dielectric material layer 113 on the substrate 10 completely coincides with the orthographic projection of the second electrode layer 112 on the substrate 10. The second electrode layer 112 and the dielectric material layer 113 include a second main region (not labeled in the figure) and a second edge region (not labeled in the figure) surrounding the second main region. The orthographic projection of the second conductive structure 15 on the substrate 10 is located within the orthographic projection of the second main region of the second electrode layer 112 on the substrate 10. This makes the area measured during dielectric relaxation measurement the middle region of the capacitor 11. Compared with the scheme where the measurement area is the edge region of the capacitor 11, the deviation of the test results caused by leakage at the edge of the capacitor 11 can be avoided. That is, this scheme can improve the accuracy of dielectric relaxation measurement.

[0110] Furthermore, combined Figures 2 to 4As shown, the semiconductor device may further include an interlayer dielectric layer 17 formed on the substrate 10 and located on the side of the planarization layer 16 close to the substrate 10; the interlayer dielectric layer 17 covers the edge position of the first main region 1111 in the first electrode layer 111 and covers the first edge region 1112 in the first electrode layer 111, and the interlayer dielectric layer 17 has a through hole 171, the through hole 171 exposing the middle position of the first main region 1111 in the first electrode layer 111; the second edge regions of the dielectric material layer 113 and the second electrode layer 112 overlap on the surface of the interlayer dielectric layer 17 away from the first electrode layer 111, and the second main regions of the dielectric material layer 113 and the second electrode layer 112 are formed in the through hole 171. By overlapping the second edge regions of the dielectric material layer 113 and the second electrode layer 112 on the surface of the interlayer dielectric layer 17 away from the first electrode layer 111, the distance between the edge of the second electrode layer 112 and the first electrode layer 111 is increased, thereby reducing the influence of edge leakage on the detection results.

[0111] It should be noted that, in combination Figures 2 to 4 As shown, when the first conductive structure 14 penetrates the planarization layer 16 and contacts the first electrode layer 111, it also penetrates the interlayer dielectric layer 17 to contact the first edge region 1112 of the first electrode layer 111.

[0112] In a specific embodiment of this disclosure, combined with Figures 1 to 3 As shown, the first conductive structure 14 may include a first adapter portion 141 and a first via portion 142. The first adapter portion 141 is located on the surface of the planarization layer 16 away from the capacitor 11 and is electrically connected to the first measurement probe 131 and the first charging probe 121. The orthographic projection of the first via portion 142 on the substrate 10 is located within the orthographic projection of the first adapter portion 141 on the substrate 10. The first via portion 142 penetrates the planarization layer 16, and the top end of the first via portion 142 is in contact with the first adapter portion 141. The bottom end of the first via portion 142 is in contact with the first edge region of the first electrode layer 111. The second conductive structure 15 includes a second transition portion 151 and a second via portion 152. The second transition portion 151 is located on the surface of the planarization layer 16 away from the capacitor 11 and is electrically connected to the second measurement probe 132 and the second charging probe 122. The orthographic projection of the second via portion 152 on the substrate 10 is located within the orthographic projection of the second transition portion 151 on the substrate 10. The second via portion 152 penetrates the planarization layer 16, and the top end of the second via portion 152 is in contact with the second transition portion 151, while the bottom end of the second via portion 152 is in contact with the second electrode layer 112.

[0113] Among them, such as Figure 1 and Figure 3As shown, the first adapter 141 is arranged around the second adapter 151, and multiple first vias 142 are arranged at intervals along the circumference to surround the second vias 152. This design results in a more uniform electric field distribution and more accurate measurement during dielectric relaxation measurement, while also reducing material costs.

[0114] It should be noted that, as Figures 2 to 4 As shown, multiple second vias 152 can also be provided, and they are arranged in an array at intervals in the first direction X and the second direction Y.

[0115] In this disclosure, the first direction X and the second direction Y are both parallel to the substrate 10, and the first direction X intersects the second direction Y, specifically they can be perpendicular.

[0116] In one embodiment of this disclosure, reference is made to Figure 2 As shown, the orthographic projections of the first charging probe 121, the second charging probe 122, the first measurement probe 131, and the second measurement probe 132 on the substrate 10 do not overlap with the orthographic projection of the capacitor 11 on the substrate 10, so as to reduce parasitic capacitance during the charging process or the dielectric relaxation measurement process.

[0117] Since the orthographic projections of the first charging probe 121, the second charging probe 122, the first measurement probe 131, and the second measurement probe 132 on the substrate 10 do not overlap with the orthographic projection of the capacitor 11 on the substrate 10, therefore, combined with Figure 1 and Figure 2 As shown, in order to facilitate the connection of the first conductive structure 14 with the first charging probe 121 and the first measurement probe 131, and the connection of the second conductive structure 15 with the second charging probe 122 and the second measurement probe 132, the dielectric relaxation measurement structure may also include a first lead 18a and a second lead 18b, which are formed on the surface of the planarization layer 16 away from the capacitor 11.

[0118] Among them, such as Figure 1As shown, both the first lead 18a and the second lead 18b include a main section 181 and a branch section 182. The main section 181 and the branch section 182 have a first end and a second end. The first end of the branch section 182 is located between the first end and the second end of the main section 181 and is connected to the main section 181. In the first lead 18a: the first end of the main section 181 contacts the first adapter 141, and the second end of the main section 181 contacts the first charging probe 121 and the first measurement probe 1. In the second lead 18b: the first end of the main section 181 is in contact with the second adapter 151, the second end of the main section 181 is in contact with one of the second charging probe 122 and the second measuring probe 132, and the second end of the branch section 182 is in contact with the other of the second charging probe 122 and the second measuring probe 132.

[0119] In this embodiment, the first lead 18a is used to connect the first charging probe 121 and the first measurement probe 131 to the same position on the first adapter 141, and the second lead 18b is used to connect the second charging probe 122 and the second measurement probe 132 to the same position on the second adapter 151, so as to improve the accuracy of dielectric relaxation detection.

[0120] It should be noted that, since the first adapter 141 is arranged around the second adapter 151, in order to facilitate the lead-out of the second lead 18b, such as... Figure 1 As shown, the first adapter 141 may be designed with a clearance opening 1410 for the main section 181 of the second lead 18b to pass through. The main section 181 of the second lead 18b and the first adapter 141 have a gap at the clearance opening 1410, that is, the second lead 18b does not contact the first adapter 141.

[0121] To reduce the influence of parasitic capacitance and inductance, this embodiment can position the measurement probe group 13 closer to the first conductive structure 14 and the second conductive structure 15 compared to the charging probe group 12. Specifically, in combination with Figures 1 to 3 As shown, the first measurement probe 131 is positioned closer to the first conductive structure 14 than the first charging probe 121, and the second measurement probe 132 is positioned closer to the second conductive structure 15 than the second charging probe 122. This design allows the length of the connecting line between the first measurement probe 131 and the first conductive structure 14 to be less than the length of the connecting line between the first charging probe 121 and the first conductive structure 14, and the length of the connecting line between the second measurement probe 132 and the second conductive structure 15 to be less than the length of the connecting line between the second charging probe 122 and the second conductive structure 15. This reduces the influence of parasitic capacitance and parasitic inductance on dielectric relaxation measurement while arranging the probes in a limited space.

[0122] Optionally, when the first charging probe 121 and the first measuring probe 131 are connected to the same position on the first adapter 141 using the first lead 18a, and the second charging probe 122 and the second measuring probe 132 are connected to the same position on the second adapter 151 using the second lead 18b: the second end of the main section 181 of the first lead 18a is in contact with the first measuring probe 131, and the first charging probe 121 is located on the side of the first measuring probe 131 away from the first adapter 141; while the second end of the main section 181 of the second lead 18b is in contact with the second measuring probe 132, and the second charging probe 122 is located on the side of the second measuring probe 132 away from the second adapter 151.

[0123] In an optional embodiment of this disclosure, combined with Figure 1 and Figure 3 As shown, the dielectric relaxation measurement structure also includes a ground probe 191 and a ground shield 192. Specifically, the ground probe 191 can be formed on the side of the planarization layer 16 away from the substrate 10 for grounding; the ground shield 192 penetrates the planarization layer 16, the top end of the ground shield 192 (i.e., the end away from the substrate 10) is connected to the ground probe 191, and the bottom end of the ground shield 192 extends toward the substrate 10. The orthographic projection of the ground shield 192 on the substrate 10 is located on at least two opposite sides of the orthographic projection of the capacitor 11 on the substrate 10. This design can effectively reduce the influence of electromagnetic radiation generated during high-frequency charging and discharging on the dielectric relaxation measurement, thereby improving the measurement accuracy, accurately characterizing the dielectric relaxation of the dielectric material layer 113, and clearly reflecting the influence of the dielectric relaxation of the dielectric material layer 113 on the charging and discharging of the capacitor 11.

[0124] Optionally, the surface of the grounding shield 192 near the substrate 10 is lower than the surface of the capacitor 11 near the substrate 10 (e.g., Figure 3 (As shown) or flush with the surface of capacitor 11 near substrate 10 to better achieve shielding.

[0125] In this embodiment of the disclosure, the horizontal distance between the grounding shield 192 and the capacitor 11 is smaller than the horizontal distance between the first charging probe 121, the first measuring probe 131, the second charging probe 122, the second measuring probe 132 and the capacitor 11. This can bring the zero potential position closer to the capacitor 11 to better achieve the shielding effect.

[0126] It should be noted that the horizontal spacing refers to the distance between two objects in a direction parallel to the substrate 10.

[0127] In this embodiment of the present disclosure, the first charging probe 121 and the first measurement probe 131 can form a first probe group, and the second charging probe 122 and the second measurement probe 132 can form a second probe group. The first probe group and the second probe group are arranged in the first direction X. The first conductive structure 14 and the second conductive structure 15 are located between the first probe group and the second probe group. The surface of the first conductive structure 14 facing the first probe group is connected to the first charging probe 121 and the first measurement probe 131 through the first lead 18a. The surface of the second conductive structure 15 facing the second probe group is connected to the second charging probe 122 and the second measurement probe 132 through the second lead 18b.

[0128] The first lead 18a and the second lead 18b are formed on the surface of the planarization layer 16 away from the capacitor 11, and the surface of the ground shield 192 away from the substrate 10 is flush with the surfaces of the first lead 18a and the second lead 18b near the planarization layer 16 (in combination). Figures 1 to 3 (As shown) or higher than the surface of the first lead 18a and the second lead 18b near the planarization layer 16, that is: the top surface of the grounding shield 192 is flush with the bottom surface of the first lead 18a and the second lead 18b, or the top surface of the grounding shield 192 is higher than the bottom surface of the first lead 18a and the second lead 18b.

[0129] It should be noted that when the surface of the grounding shield 192 away from the substrate 10 is higher than the surface of the first lead 18a and the second lead 18b near the planarization layer 16, the following three cases can be distinguished:

[0130] The first type: the top surface of the grounding shield 192 is located between the top and bottom surfaces of the first lead 18a and the second lead 18b;

[0131] The second type: the top surface of the grounding shield 192 is flush with the top surfaces of the first lead 18a and the second lead 18b.

[0132] The third type: the top surface of the grounding shield 192 is higher than the top surfaces of the first lead 18a and the second lead 18b;

[0133] The specific method to choose depends on the actual processing method, and will not be elaborated on here.

[0134] To prevent the grounding shield 192 from contacting the first lead 18a and the second lead 18b, such as Figure 1As shown, two grounding shields 192 can be provided and arranged in the second direction Y. The capacitor 11 is located between the two grounding shields 192 to ensure good shielding performance. The two grounding shields 192 are arranged at intervals on the side near the first probe group to form a first clearance notch 1921 for the first lead 18a to pass through. The first lead 18a has a gap at the first clearance notch 1921, that is, the first lead 18a does not contact the grounding shield 192. The two grounding shields 192 are arranged at intervals on the side near the second probe group to form a second clearance notch 1922 for the second lead 18b to pass through. The second lead 18b has a gap at the second clearance notch 1922, that is, the second lead 18b does not contact the grounding shield 192.

[0135] Since the two grounding shields 192 are disconnected in the second direction Y, each grounding shield 192 can be connected to the grounding probe 191 via a grounding lead 193.

[0136] In an alternative embodiment, such as Figure 1 As shown, the grounding shield 192 can be an elongated strip structure extending in the first direction X to reduce design difficulty.

[0137] In another alternative embodiment, such as Figure 5 As shown, the grounding shield 192 includes a main shield (not labeled) extending in the first direction X and a secondary shield (not labeled) located at the two extended ends of the main shield. The secondary shield extends in the second direction Y. This design allows for a larger shielding structure around the capacitor 11 to better perform electrostatic shielding.

[0138] In a specific embodiment of this disclosure, such as Figure 3 As shown, the ground lead 193 can be formed on the side of the planarization layer 16 away from the substrate 10 to facilitate the connection between the ground shield 192 and the ground probe 191.

[0139] In a specific embodiment of this disclosure, such as Figure 1 and Figure 2 As shown, a grounding probe 191 is formed on the side of the first probe group and the second probe group that is away from the first conductive structure 14 and the second conductive structure 15, which ensures that each grounding lead 193 is symmetrically designed.

[0140] It should be understood that the embodiments of this disclosure may also omit the first conductive structure 14 and the second conductive structure 15, so that the first charging probe 121 and the first measuring probe are directly connected to the first electrode layer 111, and the second charging probe 122 and the second measuring probe are directly connected to the first electrode layer 111, thereby reducing the design difficulty.

[0141] Furthermore, it should be noted that when the dielectric relaxation measurement structure meets the requirements of the semiconductor device after measuring the dielectric relaxation of the capacitance, it can be cut off from the substrate of the semiconductor device. However, it is not limited to this and can also be retained in the semiconductor device. When the dielectric relaxation measurement structure is retained in the semiconductor device, it can be considered as part of the semiconductor device. That is, this disclosure also provides a semiconductor device including a substrate and a capacitance and dielectric relaxation measurement structure formed on the substrate. The specific details of this dielectric relaxation structure can be found in the structures mentioned in the foregoing embodiments, and will not be repeated here.

[0142] Based on the dielectric relaxation measurement structure mentioned in the aforementioned specific embodiment of this disclosure, this embodiment of the disclosure also provides a method for manufacturing a semiconductor device, which may specifically include steps S100, S101, S102, S103, S104, S105, S106, S107, and S108.

[0143] In step S100, a substrate 10 is provided. For example, the substrate 10 may include the aforementioned semiconductor substrate 101 and an insulating isolation layer 102 formed on the semiconductor substrate 101.

[0144] In step S101, a first conductive film is formed on one side of the substrate 10, and the first conductive film is patterned to remove a portion of the first conductive film while retaining a portion. This retained portion is defined as the first electrode layer 111, as shown below. Figure 6 As shown.

[0145] In step S102, an interlayer dielectric film covering the substrate 10 and the first electrode layer 111 is formed, and the interlayer dielectric film is patterned to form an interlayer dielectric layer 17. The interlayer dielectric layer 17 covers the edge region of the first electrode layer 111, and the interlayer dielectric layer 17 has a through hole 171, which exposes the middle region of the first electrode layer 111. Figure 7 As shown.

[0146] In step S103, a dielectric material film 113a and a conductive film 112a are sequentially formed on the substrate 10. A portion of the dielectric material film 113a and the conductive film 112a are formed on the surface of the interlayer dielectric layer 17 away from the substrate 10, and another portion is located within the through-hole 171, such as... Figure 8 As shown. It should be noted that the portion of the dielectric material film 113a located within the through hole 171 is in contact with the first electrode layer 111.

[0147] In step S104, the dielectric material thin film 113a and the second conductive thin film 112a are simultaneously patterned to form the dielectric material layer 113 and the second electrode layer 112, as shown below. Figure 9 As shown, the edge regions of the dielectric material layer 113 and the second electrode layer 112 overlap on the surface of the interlayer dielectric layer 117 away from the first electrode layer 111, and the central regions of the dielectric material layer 113 and the second electrode layer 112 are formed in the through hole 171.

[0148] In step S105, a planarization layer 16 is formed on the substrate 10. The planarization layer 16 covers the interlayer dielectric layer 17, the dielectric material layer 113, and the second electrode layer 112. For example, the planarization layer 16 can be the aforementioned multilayer stacked structure, that is, it includes a silicon oxide material layer 161 and a silicon nitride material layer 162 formed sequentially, such as... Figure 10 As shown.

[0149] In step S106, a first via H1, a second via H2, and a ground via H3 are formed. The first via H1 penetrates the planarization layer 16 and the interlayer dielectric layer 17 to expose the edge region of the first electrode layer 111. The second via H2 penetrates the planarization layer 16 to expose the middle region of the second electrode layer 112. The ground via H3 penetrates at least the planarization layer 16 and the interlayer dielectric layer 17 and is located on the side of the first via H1 away from the second via H2. The ground via H3 does not overlap with the orthographic projection of the first electrode layer 111 onto the substrate 10. Figure 11 As shown.

[0150] Multiple first through holes H1 can be provided and spaced around the second through hole H2, and multiple second through holes H2 and grounding through holes H3 can also be provided and arranged at intervals. For example... Figure 11 As shown, the grounding via H3 not only penetrates the planarization layer 16 and the interlayer dielectric layer 17, but also a portion of the insulating isolation layer 102.

[0151] For example, the first through hole H1, the second through hole H2, and the grounding through hole H3 can be formed simultaneously using the same patterning process.

[0152] In step S107, a planarization layer 16 is formed and a third conductive film 19a is filled within the first through-hole H1, the second through-hole H2, and the grounding through-hole H3, as shown below. Figure 12 and Figure 13 As shown.

[0153] In step S108, the third conductive film 19a is patterned to form the charging probe group 12, measurement probe group 13, first conductive structure 14, second conductive structure 15, first lead 18a, second lead 18b, ground probe 191, ground shield 192, and ground lead 193 mentioned in any of the foregoing embodiments. (Refer to...) Figures 1 to 4 As shown.

[0154] For example, the patterning process mentioned in the embodiments of this disclosure can be a photolithography process. Photolithography is an important step in the semiconductor device manufacturing process. This step uses exposure and development to etch geometric structures on a photoresist layer to form a photomask with a specific pattern. Then, the pattern on the photomask is transferred to the film layer through an etching process.

[0155] It should be noted that the embodiments disclosed herein are not limited to those manufactured by the manufacturing methods mentioned above, and other manufacturing methods may also be used, as long as they can manufacture the dielectric relaxation measurement structure mentioned in any of the foregoing embodiments.

[0156] This disclosure also provides a dielectric relaxation measurement system, which includes a detection device (not shown in the figure), a charging device (not shown in the figure), a control device (not shown in the figure), and as described above. Figures 1 to 5 The dielectric relaxation measurement structure described in any of the embodiments is not described again here.

[0157] The control device is connected to the charging device and the detection device. The charging device can be connected to the first charging probe 121 and the second charging probe 122 under the action of the control device to charge the capacitor 11. The charging device can also be disconnected from the first charging probe 121 and the second charging probe 122 under the action of the control device to stop charging the capacitor 11. The detection device can be connected to the first measuring probe 131 and the second measuring probe 132 under the action of the control device when the charging device stops charging the capacitor 11 to detect the dielectric relaxation of the capacitor 11.

[0158] It should be noted that during the charging process of the charging device for capacitor 11, the detection device can be disconnected from the first measuring probe 131 and the second measuring probe 132 under the action of the control device, so as to avoid affecting the charging process.

[0159] In an optional embodiment, the detection device may include an ammeter, which can be connected in series between the first measurement probe 131 and the second measurement probe 132 under the action of the control device when the charging device stops charging the capacitor 11, so as to perform current measurement. The dielectric relaxation of the capacitor 11 can be characterized according to the measured current and time curve. That is, the current detection method can be used to characterize the dielectric relaxation of the capacitor 11 in this embodiment.

[0160] In another optional embodiment, the detection device may include a voltmeter and a shorting wire. The voltmeter can be connected in series between the first measuring probe 131 and the second measuring probe 132 under the action of the control device when the charging device stops charging the capacitor 11. The shorting wire can be shorted between the first charging probe 121 and the second charging probe 122 under the action of the control device when the charging device stops charging the capacitor 11, so as to perform voltage testing. The dielectric relaxation of the capacitor 11 is characterized by the voltage change. That is, in this embodiment, the voltage detection method can be used to characterize the dielectric relaxation of the capacitor 11.

[0161] In this method, the voltmeter measures the voltage as it first drops to 0 and then slowly rises. The results indicate that after the voltage drops to 0, the higher the rise and the shorter the time to reach saturation, the better.

[0162] It should be noted that in this embodiment, the charging device can stop charging the capacitor 11 after the capacitor 11 is fully charged.

[0163] This disclosure also provides a method for measuring dielectric relaxation, used to measure the dielectric relaxation of capacitance in a semiconductor device, such as... Figures 1 to 5 As shown, the semiconductor device includes a substrate 10, and a capacitor 11 is formed on the substrate 10. The capacitor 11 includes a first electrode layer 111, a second electrode layer 112, and a dielectric material layer 113 formed between the first electrode layer 111 and the second electrode layer 112, wherein, as... Figure 14 As shown, dielectric relaxation measurement methods include:

[0164] Step S200: A dielectric relaxation measurement structure is formed on the substrate 10, such as... Figures 1 to 5 As shown, the dielectric relaxation measurement structure includes a charging probe group 12 and a measurement probe group 13. The charging probe group 12 includes a first charging probe 121 electrically connected to the first electrode layer 111 and a second charging probe 122 electrically connected to the second electrode layer 112. The measurement probe group 13 includes a first measurement probe 131 electrically connected to the first electrode layer 111 and a second measurement probe 132 electrically connected to the second electrode layer 112.

[0165] Step S201: Control the charging device to connect with the first charging probe 121 and the second charging probe 122 to charge the capacitor 11.

[0166] In step S202, after capacitor 11 is fully charged, the charging device is controlled to stop charging capacitor 11, and the detection device is controlled to connect with the first measurement probe and the second measurement probe to detect the dielectric relaxation of capacitor 11.

[0167] In an optional embodiment, the step of controlling the detection device to cooperate with the first measurement probe 131 and the second measurement probe 132 to detect the dielectric relaxation state of the capacitor 11 may include:

[0168] A control ammeter is connected in series between the first measuring probe 131 and the second measuring probe 132 to measure the current.

[0169] The dielectric relaxation of capacitor 11 is characterized by the measured current versus time curve.

[0170] In another optional embodiment, the step of controlling the detection device to cooperate with the first measurement probe 131 and the second measurement probe 132 to detect the dielectric relaxation state of the capacitor 11 may include:

[0171] A control voltmeter is connected in series between the first measurement probe 131 and the second measurement probe 132, and the first charging probe 121 and the second charging probe 121 are shorted to perform voltage measurement.

[0172] The dielectric relaxation of capacitor 11 is characterized based on the measured voltage change.

[0173] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0174] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0175] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A dielectric relaxation measurement structure for measuring the dielectric relaxation of a capacitor in a semiconductor device, the semiconductor device comprising a substrate, the capacitor formed on the substrate, the capacitor comprising a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer; characterized in that, The dielectric relaxation measurement structure includes: A charging probe group is formed on the substrate, the charging probe group including a first charging probe and a second charging probe; A measurement probe group is formed on the substrate, the measurement probe group including a first measurement probe and a second measurement probe; A first conductive structure is formed on the substrate, wherein the first charging probe and the first measuring probe are spaced apart, one end of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first electrode layer. A second conductive structure is formed on the substrate, wherein the second charging probe and the second measuring probe are spaced apart, one end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second electrode layer. The first charging probe and the first measuring probe form a first probe group, and the second charging probe and the second measuring probe form a second probe group. The first probe group and the second probe group are arranged in a first direction. The first conductive structure and the second conductive structure are located between the first probe group and the second probe group. The first measuring probe is positioned closer to the first conductive structure than the first charging probe, and the second measuring probe is positioned closer to the second conductive structure than the second charging probe. The first charging probe and the second charging probe are used to communicate with the charging device to charge the capacitor. The first measuring probe and the second measuring probe are used to communicate with the detection device when the charging device stops charging the capacitor to detect the dielectric relaxation of the capacitor.

2. The dielectric relaxation measurement structure according to claim 1, characterized in that, The semiconductor device further includes a planarization layer formed on the substrate, the planarization layer covering the capacitor; wherein... The first charging probe, the second charging probe, the first measurement probe, and the second measurement probe are formed on the surface of the planarization layer away from the capacitor; The first conductive structure penetrates the planarization layer, the top end of the first conductive structure is electrically connected to the first measurement probe and the first charging probe, and the bottom end of the first conductive structure is in contact with the first electrode layer. The second conductive structure penetrates the planarization layer, the top end of the second conductive structure is electrically connected to the second measurement probe and the second charging probe, and the bottom end of the second conductive structure is in contact with the second electrode layer.

3. The dielectric relaxation measurement structure according to claim 2, characterized in that, The first electrode layer is parallel to the substrate, and includes a first main region and a first edge region surrounding the first main region. A second electrode layer is formed on the side of the first electrode layer away from the substrate, and the orthographic projections of the second electrode layer and the dielectric material layer onto the substrate lie within the orthographic projection of the first main region onto the substrate. The first conductive structure is disposed around the second conductive structure. The orthographic projection of the first conductive structure on the substrate overlaps with the orthographic projection of the first edge region on the substrate, and the bottom end of the first conductive structure is in contact with the first edge region. The orthographic projection of the second conductive structure on the substrate is located within the orthographic projection of the second electrode layer on the substrate.

4. The dielectric relaxation measurement structure according to claim 3, characterized in that, The first conductive structure includes a first adapter portion and a first via portion. The first adapter portion is located on the surface of the planarization layer away from the capacitor and is electrically connected to the first measurement probe and the first charging probe. The orthographic projection of the first via portion on the substrate is located within the orthographic projection of the first adapter portion on the substrate. The first via portion penetrates the planarization layer, and the top end of the first via portion contacts the first adapter portion, and the bottom end of the first via portion contacts the first edge region. The second conductive structure includes a second transition portion and a second via portion. The second transition portion is located on the surface of the planarization layer away from the capacitor and is electrically connected to the second measurement probe and the second charging probe. The orthographic projection of the second via portion on the substrate is located within the orthographic projection of the second transition portion on the substrate. The second via portion penetrates the planarization layer, and the top end of the second via portion is in contact with the second transition portion, and the bottom end of the second via portion is in contact with the second electrode layer. The first adapter portion is arranged around the second adapter portion, and multiple first through-hole portions are arranged at intervals along the circumference to surround the second through-hole portions.

5. The dielectric relaxation measurement structure according to claim 4, characterized in that, The orthographic projections of the first charging probe, the second charging probe, the first measurement probe, and the second measurement probe on the substrate do not overlap with the orthographic projection of the capacitor on the substrate; The dielectric relaxation measurement structure further includes a first lead and a second lead, the first lead and the second lead being formed on the surface of the planarization layer away from the capacitor, the first lead and the second lead including a main section and a branch section, the main section and the branch section having a first end and a second end, the first end of the branch section being located between the first end and the second end of the main section and connected to the main section; In the first lead: the first end of the main section is in contact with the first adapter, the second end of the main section is in contact with one of the first charging probe and the first measurement probe, and the second end of the branch section is in contact with the other of the first charging probe and the first measurement probe. In the second lead: the first end of the main section is in contact with the second adapter, the second end of the main section is in contact with one of the second charging probe and the second measuring probe, and the second end of the branch section is in contact with the other of the second charging probe and the second measuring probe. The first adapter has a clearance opening through which the main section of the second lead passes, and the main section of the second lead and the first adapter have a gap at the clearance opening.

6. The dielectric relaxation measurement structure according to claim 5, characterized in that, The second end of the main section of the first lead is in contact with the first measurement probe, and the first charging probe is located on the side of the first measurement probe away from the first adapter. The second end of the main section of the second lead is in contact with the second measurement probe, and the second charging probe is located on the side of the second measurement probe away from the second adapter.

7. The dielectric relaxation measurement structure according to claim 3, characterized in that, The orthographic projection of the dielectric material layer on the substrate completely coincides with the orthographic projection of the second electrode layer on the substrate, and the second electrode layer and the dielectric material layer include a second main region and a second edge region surrounding the second main region; The orthographic projection of the second conductive structure on the substrate lies within the orthographic projection of the second main region on the substrate.

8. The dielectric relaxation measurement structure according to claim 7, characterized in that, The semiconductor device further includes an interlayer dielectric layer formed on the substrate, located on the side of the planarization layer closest to the substrate; The interlayer dielectric layer covers the edge of the first main region and the edge region, and the interlayer dielectric layer has a through hole, which is exposed in the middle of the first main region. The second edge region overlaps the surface of the interlayer dielectric layer away from the first electrode layer, and the second main region is formed within the through hole; Wherein, when the first conductive structure penetrates the planarization layer and contacts the first electrode layer, it also penetrates the interlayer dielectric layer to contact the first edge region.

9. The dielectric relaxation measurement structure according to claim 2, characterized in that, Also includes: A grounding probe is formed on the side of the planarization layer away from the substrate for grounding; A grounding shield extends through the planarization layer. The top end of the grounding shield is electrically connected to the grounding probe, and the bottom end of the grounding shield extends toward the substrate. The orthographic projection of the grounding shield on the substrate is located on at least two opposite sides of the orthographic projection of the capacitor on the substrate.

10. The dielectric relaxation measurement structure according to claim 9, characterized in that, The surface of the grounding shield near the substrate is lower than or flush with the surface of the capacitor near the substrate.

11. The dielectric relaxation measurement structure according to claim 9, characterized in that, The orthographic projections of the first charging probe, the first measurement probe, the second charging probe, and the second measurement probe on the substrate do not overlap with the orthographic projection of the capacitor on the substrate; The horizontal distance between the grounding shield and the capacitor is less than the horizontal distance between the first charging probe, the first measuring probe, the second charging probe, the second measuring probe and the capacitor.

12. The dielectric relaxation measurement structure according to claim 11, characterized in that, The surface of the first conductive structure facing the first probe group is connected to the first charging probe and the first measurement probe via a first lead, and the surface of the second conductive structure facing the second probe group is connected to the second charging probe and the second measurement probe via a second lead. The first lead and the second lead are formed on the surface of the planarization layer away from the capacitor. The surface of the ground shield away from the substrate is flush with or higher than the surfaces of the first lead and the second lead near the planarization layer. Two grounding shields are provided and arranged in a second direction. The capacitor is located between the two grounding shields, and the second direction intersects the first direction. The two grounding shields are arranged at intervals on the side near the first probe group to form a first clearance notch for the first lead to pass through, and the first lead has a gap at the first clearance notch. The two grounding shields are arranged at intervals on the side near the second probe group to form a second clearance notch for the second lead to pass through, and the second lead has a gap at the second clearance notch. Each grounding shield is electrically connected to the grounding probe through a grounding lead.

13. The dielectric relaxation measurement structure according to claim 12, characterized in that, The grounding lead is formed on the side of the planarization layer away from the substrate; and / or The grounding probe is formed on the side of one of the first probe group and the second probe group that is away from the first conductive structure and the second conductive structure.

14. The dielectric relaxation measurement structure according to claim 12, characterized in that, The grounding shield is an elongated strip structure extending in the first direction; or The grounding shield includes a main shield extending in the first direction and a secondary shield located at both ends of the main shield, the secondary shield extending in the second direction.

15. A semiconductor device, characterized in that, include: Substrate; A capacitor is formed on the substrate, the capacitor including a first electrode layer, a second electrode layer and a dielectric material layer formed between the first electrode layer and the second electrode layer; as well as A dielectric relaxation measurement structure is formed on the substrate and includes a charging probe group, a measurement probe group, a first conductive structure, and a second conductive structure. The charging probe group includes a first charging probe and a second charging probe. The measurement probe group includes a first measurement probe and a second measurement probe. The first charging probe and the first measurement probe are spaced apart. One end of the first conductive structure is electrically connected to the first measurement probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first electrode layer. The second charging probe and the second measurement probe are spaced apart. One end of the second conductive structure is electrically connected to the second measurement probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second electrode layer. The first charging probe and the first measuring probe form a first probe group, and the second charging probe and the second measuring probe form a second probe group. The first probe group and the second probe group are arranged in a first direction. The first conductive structure and the second conductive structure are located between the first probe group and the second probe group. The first measuring probe is positioned closer to the first conductive structure than the first charging probe, and the second measuring probe is positioned closer to the second conductive structure than the second charging probe. The first charging probe and the second charging probe are used to communicate with the charging device to charge the capacitor. The first measuring probe and the second measuring probe are used to communicate with the detection device when the charging device stops charging the capacitor to measure the dielectric relaxation of the capacitor.

16. The semiconductor device according to claim 15, characterized in that, The first electrode layer is parallel to the substrate, and the second electrode layer is formed on the side of the first electrode layer away from the substrate.

17. A dielectric relaxation measurement system for measuring the dielectric relaxation of a capacitor in a semiconductor device, the semiconductor device comprising a substrate, the capacitor formed on the substrate, the capacitor comprising a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer; characterized in that, The dielectric relaxation measurement system includes: Control device; A dielectric relaxation measurement structure is formed on the substrate and includes a charging probe group, a measurement probe group, a first conductive structure, and a second conductive structure. The charging probe group includes a first charging probe and a second charging probe. The measurement probe group includes a first measurement probe and a second measurement probe. The first charging probe and the first measurement probe are spaced apart. One end of the first conductive structure is electrically connected to the first measurement probe and the first charging probe, and the other end of the first conductive structure is electrically connected to a first electrode layer. The second charging probe and the second measurement probe are spaced apart. One end of the second conductive structure is electrically connected to the second measurement probe and the second charging probe, and the other end of the second conductive structure is electrically connected to a second electrode layer. The first charging probe and the first measurement probe form a first probe group, and the second charging probe and the second measurement probe form a second probe group. The first probe group and the second probe group are arranged in a first direction. The first conductive structure and the second conductive structure are located between the first probe group and the second probe group. The first measurement probe is closer to the first conductive structure than the first charging probe, and the second measurement probe is closer to the second conductive structure than the second charging probe. A charging device is electrically connected to the control device. Under the control of the control device, the charging device can connect with the first charging probe and the second charging probe to charge the capacitor. The charging device can also disconnect from the first charging probe and the second charging probe under the action of the control device to stop charging the capacitor. The detection device is electrically connected to the control device. The detection device can conduct to the first measurement probe and the second measurement probe under the control of the control device when the charging device stops charging the capacitor, so as to detect the dielectric relaxation of the capacitor.

18. The dielectric relaxation measurement system according to claim 17, characterized in that, The detection device includes an ammeter, which is connected in series between the first and second measuring probes under the control of the control device when the charging device stops charging the capacitor; or The detection device includes a voltmeter and a jumper wire. The voltmeter can be connected in series between the first measuring probe and the second measuring probe under the action of the control device when the charging device stops charging the capacitor. The jumper wire can be shorted between the first charging probe and the second charging probe under the control of the control device when the charging device stops charging the capacitor.

19. A method for measuring dielectric relaxation, used to measure the dielectric relaxation of a capacitor in a semiconductor device, the semiconductor device including a substrate, the capacitor formed on the substrate, the capacitor including a first electrode layer, a second electrode layer, and a dielectric material layer formed between the first electrode layer and the second electrode layer, characterized in that, The dielectric relaxation measurement method includes: A dielectric relaxation measurement structure is formed on the substrate. The dielectric relaxation measurement structure includes a charging probe group, a measurement probe group, a first conductive structure, and a second conductive structure. The charging probe group includes a first charging probe and a second charging probe. The measurement probe group includes a first measurement probe and a second measurement probe. The first charging probe and the first measurement probe are spaced apart. One end of the first conductive structure is electrically connected to the first measurement probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first electrode layer. The second charging probe and the second measurement probe are spaced apart. One end of the second conductive structure is electrically connected to the second measurement probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second electrode layer. The first charging probe and the first measurement probe form a first probe group, and the second charging probe and the second measurement probe form a second probe group. The first probe group and the second probe group are arranged in a first direction. The first conductive structure and the second conductive structure are located between the first probe group and the second probe group. The first measurement probe is closer to the first conductive structure than the first charging probe, and the second measurement probe is closer to the second conductive structure than the second charging probe. The control charging device is connected in conjunction with the first charging probe and the second charging probe to charge the capacitor; After the capacitor is fully charged, the charging device is controlled to stop charging the capacitor. At the same time, the detection device is controlled to connect with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor.

20. The dielectric relaxation measurement method according to claim 19, characterized in that, The step of connecting the control detection device with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor includes: A control ammeter is connected in series between the first measuring probe and the second measuring probe to measure the current. The dielectric relaxation of the capacitor is characterized by the measured current versus time curve.

21. The dielectric relaxation measurement method according to claim 19, characterized in that, The step of connecting the control detection device with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor includes: A control voltmeter is connected in series between the first measurement probe and the second measurement probe, and the first charging probe and the second charging probe are short-circuited to perform voltage measurement; The dielectric relaxation of the capacitor is characterized by the measured voltage change.

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