Dielectric relaxation measurement structure, system and method and semiconductor device

Abstract

The present disclosure relates to a dielectric relaxation measurement structure, system, method, and semiconductor device. The dielectric relaxation measurement structure is used to measure the dielectric relaxation of a capacitor in a semiconductor device. The dielectric relaxation measurement structure includes a first conductor layer connected to a conductor sleeve in the capacitor, a second conductor layer connected to a conductor core in the capacitor, and a dielectric insulation layer sandwiched between the first and second conductor layers and connected to a dielectric portion in the capacitor. The structure also includes a first charging probe and a first measuring probe electrically connected to the first conductor layer, and a second charging probe and a second measuring probe electrically connected to the second conductor layer. The first charging probe and the second charging probe are used to conduct with a charging device to charge the capacitor. The first measuring probe and the second measuring probe are used to conduct with a detection device when the charging device stops charging the capacitor to detect the dielectric relaxation of the capacitor. The disclosed solution can improve the accuracy of dielectric relaxation detection.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor chips, and particularly relates to a dielectric relaxation measurement structure, system and method, and a semiconductor device. Background Art

[0002] With the continuous development of the DRAM (Dynamic Random Access Memory) chip industry, in order to increase the storage density of the chip, the capacitor structure used in the chip can be designed as a capacitor tube. Among them, the depth and width of the capacitor tube are relatively large. Especially when a large number of capacitor tubes are stacked together, the distance between the capacitor tubes is close, and electromagnetic waves are generated between them, causing mutual interference, which in turn affects the dielectric loss and dielectric relaxation time. However, dielectric relaxation affects the read and write speed of the chip. Since the dielectric relaxation time is very short, how to effectively characterize the dielectric relaxation of capacitor tubes and achieve rapid and accurate screening of dielectric materials is a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The embodiments of the present disclosure provide a dielectric relaxation measurement structure, system, method, and semiconductor device to improve the accuracy of dielectric relaxation detection of capacitor tubes.

[0004] In a first aspect, the present disclosure provides a dielectric relaxation measurement structure for measuring dielectric relaxation of a capacitor in a semiconductor device. The semiconductor device includes a substrate, the capacitor is formed on the substrate, the capacitor includes a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on the outer periphery of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core. The dielectric relaxation measurement structure is formed on the substrate and includes:

[0005] a first conductor layer covering and contacting a top end of the conductor sleeve, wherein the first conductor layer has a first hollow hole, and in an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole;

[0006] a dielectric insulating layer, a portion of which is formed on a side of the first conductor layer away from the substrate, and another portion of which is located in the first hollow hole and covers the top of the dielectric portion, the dielectric insulating layer having a second hollow hole, wherein in an orthographic projection on the substrate: the second hollow hole is projected into the first hollow hole, and the conductor core is projected into the second hollow hole;

[0007] a second conductor layer, a portion of which is formed on a side of the dielectric insulation layer away from the substrate, and another portion of which is located in the second hollow hole and in contact with the top of the conductor core;

[0008] a charging probe assembly, comprising a first charging probe electrically connected to the first conductor layer and a second charging probe electrically connected to the second conductor layer, wherein the first charging probe and the second charging probe are configured to be electrically connected to a charging device to charge the capacitor tube;

[0009] The measuring probe group includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer. The first measuring probe and the second measuring probe are used to conduct with the detection device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

[0010] In an exemplary embodiment of the present disclosure, the substrate includes a base and an insulating isolation layer formed on the base, the insulating isolation layer is provided with a receiving groove, and the capacitor tube is filled in the receiving groove;

[0011] The first conductor layer, the dielectric insulation layer, the second conductor layer, the charging probe group and the measuring probe group.

[0012] In an exemplary embodiment of the present disclosure, the accommodating groove, the capacitor tube, the first hollow hole, and the second hollow hole are each provided in plurality and matched one to one;

[0013] Wherein, in the orthographic projection on the substrate: the second conductor layer covers each of the capacitor tubes.

[0014] In an exemplary embodiment of the present disclosure, the dielectric relaxation measurement structure further includes a first conductive structure and a second conductive structure, which are formed on a side of the insulating isolation layer away from the substrate; wherein,

[0015] The first charging probe and the first measuring probe are spaced apart from each other, one end of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first conductor layer;

[0016] The second charging probe and the second measuring probe are spaced apart, one end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second conductor layer.

[0017] In an exemplary embodiment of the present disclosure, the dielectric relaxation measurement structure further includes a planarization layer formed on a side of the insulating isolation layer away from the substrate and covering the first conductor layer, the dielectric insulation layer and the second conductor layer; wherein,

[0018] The first charging probe, the second charging probe, the first measurement probe, and the second measurement probe are formed on a surface of the planarization layer away from the substrate;

[0019] The first conductive structure penetrates the planarization layer, the top of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the bottom of the first conductive structure is in contact with the first conductor layer;

[0020] The second conductive structure penetrates the planarization layer, a top end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and a bottom end of the second conductive structure is in contact with the second conductor layer.

[0021] In an exemplary embodiment of the present disclosure, the first conductor layer includes a first main region and a first edge region surrounding the first main region, and in an orthographic projection on the substrate: the second conductor layer and the dielectric insulation layer are projected within the first main region; wherein,

[0022] The first hollow hole is located in the first main area;

[0023] In an orthographic projection on the substrate: the first conductive structure overlaps with the first edge region, and the second conductive structure is projected within the second conductor layer;

[0024] The first conductive structure is disposed around the second conductive structure, and a bottom end of the first conductive structure contacts the first edge region.

[0025] In an exemplary embodiment of the present disclosure, the first conductive structure includes a first transition portion and a first via portion. The first transition portion is located on a surface of the planarization layer away from the substrate and is electrically connected to the first measurement probe and the first charging probe. In an orthographic projection on the substrate, the first via portion is projected within the first transition portion, penetrates the planarization layer, and a top end of the first via portion contacts the first transition portion, while a bottom end of the first via portion contacts the first edge region.

[0026] The second conductive structure includes a second transition portion and a second via portion. The second transition portion is located on a surface of the planarization layer away from the substrate and is electrically connected to the second measurement probe and the second charging probe. In an orthographic projection on the substrate, the second via portion is projected within the second transition portion. The second via portion penetrates the planarization layer, and a top end of the second via portion contacts the second transition portion, while a bottom end of the second via portion contacts the second conductive layer.

[0027] The first transition portion is arranged around the second transition portion, and a plurality of first via portions are provided and arranged at intervals along the circumferential direction to surround the second via portion.

[0028] In an exemplary embodiment of the present disclosure, in an orthographic projection on the substrate: the first charging probe, the second charging probe, the first measurement probe, and the second measurement probe do not overlap with the first conductor layer and the second conductor layer;

[0029] The dielectric relaxation measurement structure further includes a first lead and a second lead, wherein the first lead and the second lead are formed on a surface of the planarization layer away from the substrate, the first lead and the second lead include a main segment and a branch segment, the main segment and the branch segment have a first end and a second end, and the first end of the branch segment is located between the first end and the second end of the main segment and connected to the main segment;

[0030] In the first lead, a first end of a main segment contacts the first transition portion, a second end of the main segment contacts one of the first charging probe and the first measurement probe, and a second end of a branch segment contacts the other of the first charging probe and the first measurement probe.

[0031] In the second lead, a first end of the main segment contacts the second transition portion, a second end of the main segment contacts one of the second charging probe and the second measurement probe, and a second end of the branch segment contacts the other of the second charging probe and the second measurement probe.

[0032] The first transition portion has an avoidance opening for the main section of the second lead to pass through, and a gap is formed between the main section of the second lead and the first transition portion at the avoidance opening.

[0033] In an exemplary embodiment of the present disclosure, the second end of the main section of the first lead is in contact with the first measuring probe, and the first charging probe is located on a side of the first measuring probe away from the first connecting portion;

[0034] The second end of the main section in the second lead is in contact with the second measuring probe, and the second charging probe is located on a side of the second measuring probe away from the second connecting portion.

[0035] In an exemplary embodiment of the present disclosure, in an orthographic projection on the substrate: the dielectric insulation layer completely overlaps with the second conductor layer, and the second conductor layer and the dielectric insulation layer include a second main area and a second edge area surrounding the second main area; wherein,

[0036] The second hollow hole is located in the second main area of ​​the dielectric insulation layer;

[0037] In an orthographic projection on the substrate, the second conductive structure is projected into the second main area of ​​the second conductor layer.

[0038] In an exemplary embodiment of the present disclosure, the dielectric relaxation measurement structure further includes an interlayer dielectric layer formed between the planarization layer and the insulating isolation layer;

[0039] The interlayer dielectric layer covers an edge position of the first main region and covers the first edge region, and the interlayer dielectric layer has a through hole, and the through hole exposes a middle position of the first main region;

[0040] The second edge region overlaps the surface of the interlayer dielectric layer away from the first conductor layer, the second main region is formed in the through hole, and in an orthographic projection on the substrate: the first hollow hole and the second hollow hole are projected into the through hole;

[0041] Wherein, when the first conductive structure penetrates the planarization layer and contacts the first conductor layer, it also penetrates the interlayer dielectric layer to contact the first edge region.

[0042] In an exemplary embodiment of the present disclosure, the dielectric relaxation measurement structure further includes:

[0043] a grounding probe, formed on a side of the planarization layer away from the insulating isolation layer and used for grounding;

[0044] a ground shielding portion, the ground shielding portion passing through the planarization layer, a top end of the ground shielding portion being connected to the ground probe, and a bottom end of the ground shielding portion extending toward the substrate;

[0045] Wherein, in an orthographic projection on the substrate: the second conductor layer is projected within or overlaps with the first conductor layer, and the ground shielding portion is projected on at least two opposite sides of the first conductor layer.

[0046] In an exemplary embodiment of the present disclosure, a surface of the ground shielding portion close to the substrate is lower than a surface of the capacitor tube close to the substrate or is flush with a surface of the capacitor tube close to the substrate.

[0047] In an exemplary embodiment of the present disclosure, in an orthographic projection on the substrate: the first charging probe, the first measurement probe, the second charging probe, the second measurement probe, and the first conductor layer do not overlap;

[0048] A horizontal distance between the ground shield and the first conductor layer is smaller than a horizontal distance between the first charging probe, the first measuring probe, the second charging probe, the second measuring probe, and the first conductor layer.

[0049] In an exemplary embodiment of the present disclosure, the first charging probe and the first measuring probe constitute a first probe group, the second charging probe and the second measuring probe constitute a second probe group, and the first probe group and the second probe group are arranged in a first direction;

[0050] The first conductive structure and the second conductive structure are located between the first probe group and the second probe group, the surface of the first conductive structure facing the first probe group is connected to the first charging probe and the first measurement probe via a first lead, and the surface of the second conductive structure facing the second probe group is connected to the second charging probe and the second measurement probe via a second lead;

[0051] The first lead and the second lead are formed on a surface of the planarization layer away from the insulating isolation layer, and a surface of the ground shield away from the substrate is flush with or higher than a surface of the first lead and the second lead close to the planarization layer;

[0052] Two ground shielding parts are provided and arranged in a second direction, the first conductor layer is located between the two ground shielding parts, and the second direction intersects with the first direction;

[0053] Among them, the two ground shielding parts are arranged at intervals on one side close to the first probe group to form a first avoidance gap for the first lead to pass through, and the first lead has a gap at the first avoidance gap; the two ground shielding parts are arranged at intervals on one side close to the second probe group to form a second avoidance gap for the second lead to pass through, and the second lead has a gap at the second avoidance gap; each of the ground shielding parts is connected to the ground probe through a ground lead.

[0054] In an exemplary embodiment of the present disclosure, the ground lead is formed on a side of the planarization layer away from the insulating isolation layer; and / or

[0055] A side of one of the first probe group and the second probe group away from the first conductive structure and the second conductive structure forms the ground probe.

[0056] In an exemplary embodiment of the present disclosure, the ground shielding portion is a long strip structure extending in the first direction; or

[0057] The ground shield portion includes a main shield portion extending in the first direction and sub-shield portions located at both extending ends of the main shield portion, the sub-shield portions extending in a second direction.

[0058] In an exemplary embodiment of the present disclosure, the first measurement probe is disposed closer to the first conductive structure than the first charging probe;

[0059] The second measuring probe is disposed closer to the second conductive structure than the second charging probe.

[0060] In an exemplary embodiment of the present disclosure, the first conductor layer and the conductor sleeve are an integrally formed structure, the dielectric insulation layer and the dielectric portion are an integrally formed structure, and the second conductor layer and the conductor core are an integrally formed structure.

[0061] A second aspect of the present disclosure provides a semiconductor device, comprising:

[0062] substrate;

[0063] a capacitor tube formed on the substrate, the capacitor tube comprising a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extending in a direction intersecting the substrate, the conductor sleeve being at least sleeved on an outer circumference of the conductor core, and the dielectric portion being formed between the conductor sleeve and the conductor core; and

[0064] A dielectric relaxation measurement structure is formed on the substrate and includes a first conductor layer, a dielectric insulation layer, a second conductor layer, a charging probe group and a measurement probe group; wherein,

[0065] The first conductor layer covers and contacts the top end of the conductor sleeve, and the first conductor layer has a first hollow hole. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole.

[0066] A portion of the dielectric insulation layer is formed on a side of the first conductor layer away from the substrate, and another portion is located in the first hollow hole and covers the top of the dielectric portion. The dielectric insulation layer has a second hollow hole. In an orthographic projection on the substrate, the second hollow hole is projected into the first hollow hole, and the conductor core is projected into the second hollow hole.

[0067] A portion of the second conductor layer is formed on a side of the dielectric insulation layer away from the substrate, and another portion is located in the second hollow hole and in contact with the top of the conductor core;

[0068] The charging probe group includes a first charging probe electrically connected to the first conductor layer and a second charging probe electrically connected to the second conductor layer, wherein the first charging probe and the second charging probe are used to conduct with a charging device to charge the capacitor tube;

[0069] The measuring probe group includes a first measuring probe electrically connected to the first conductor layer and a second measuring probe electrically connected to the second conductor layer. The first measuring probe and the second measuring probe are used to be connected to the detection device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

[0070] A third aspect of the present disclosure provides a dielectric relaxation measurement system for measuring dielectric relaxation of a capacitor in a semiconductor device, wherein the semiconductor device includes a substrate, the capacitor is formed on the substrate, the capacitor includes a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on the outer periphery of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core; wherein the dielectric relaxation measurement system includes:

[0071] control devices;

[0072] A dielectric relaxation measurement structure is formed on the substrate and includes a first conductor layer, a dielectric insulation layer, a second conductor layer, a charging probe group, and a measurement probe group. The first conductor layer covers and contacts the top of the conductor sleeve. The first conductor layer has a first hollow hole. A portion of the dielectric insulation layer is formed on a side of the first conductor layer away from the substrate. Another portion of the dielectric insulation layer is located in the first hollow hole and covers the top of the dielectric portion. The dielectric insulation layer has a second hollow hole. A portion of the second conductor layer is formed on a side of the dielectric insulation layer away from the substrate. Another portion of the second conductive layer is located within the second hollow hole and contacts the top of the conductive tube core. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole, the second hollow hole is projected within the first hollow hole, and the conductive tube core is projected within the second hollow hole. The charging probe set includes a first charging probe electrically connected to the first conductive layer and a second charging probe electrically connected to the second conductive layer. The measuring probe set includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer.

[0073] a charging device electrically connected to the control device, wherein the charging device can be connected to the first charging probe and the second charging probe under the control of the control device to charge the capacitor tube, and the charging device can also be disconnected from the first charging probe and the second charging probe under the control of the control device to stop charging the capacitor tube;

[0074] A detection device is electrically connected to the control device. The detection device can be connected to the first measuring probe and the second measuring probe under the control of the control device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

[0075] In an exemplary embodiment of the present disclosure, the detection device includes an ammeter, which can be connected in series between the first measuring probe and the second measuring probe under the control of the control device when the charging device stops charging the capacitor tube; or

[0076] The detection device includes a voltmeter and a short-circuit wire. The voltmeter can be connected in series between the first measuring probe and the second measuring probe under the action of the control device when the charging device stops charging the capacitor tube. The short-circuit wire can be short-circuited between the first charging probe and the second charging probe under the control of the control device when the charging device stops charging the capacitor tube.

[0077] A fourth aspect of the present disclosure provides a dielectric relaxation measurement method for measuring dielectric relaxation of a capacitor in a semiconductor device, wherein the semiconductor device includes a substrate, the capacitor is formed on the substrate, the capacitor includes a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on an outer circumference of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core. The dielectric relaxation measurement method includes:

[0078] A dielectric relaxation measurement structure is formed on the substrate, the dielectric relaxation measurement structure comprising a first conductor layer, a dielectric insulating layer, a second conductor layer, a charging probe group, and a measurement probe group, wherein the first conductor layer covers and contacts the top of the conductor sleeve, the first conductor layer has a first hollow hole, a portion of the dielectric insulating layer is formed on a side of the first conductor layer away from the substrate, another portion of the dielectric insulating layer is located in the first hollow hole and covers the top of the dielectric portion, the dielectric insulating layer has a second hollow hole, a portion of the second conductor layer is formed on the dielectric insulating layer away from the substrate On one side of the substrate, another portion of the second conductive layer is located within the second hollow hole and contacts the top of the conductive tube core. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole, the second hollow hole is projected within the first hollow hole, and the conductive tube core is projected within the second hollow hole. The charging probe group includes a first charging probe electrically connected to the first conductive layer and a second charging probe electrically connected to the second conductive layer. The measuring probe group includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer.

[0079] Controlling the charging device to cooperate with the first charging probe and the second charging probe to charge the capacitor tube;

[0080] After the capacitor tube is fully charged, the charging device is controlled to stop charging the capacitor tube. At the same time, the detection device is controlled to cooperate with the first measuring probe and the second measuring probe to detect the dielectric relaxation of the capacitor tube.

[0081] In an exemplary embodiment of the present disclosure, the control detection device is connected to the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor tube, including:

[0082] A control ammeter is connected in series between the first measuring probe and the second measuring probe to perform current measurement;

[0083] The dielectric relaxation of the capacitor tube is characterized based on a measured current-time relationship curve.

[0084] In an exemplary embodiment of the present disclosure, the control detection device is connected to the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor tube, including:

[0085] A control voltmeter is connected in series between the first measuring probe and the second measuring probe, and controls the first charging probe and the second charging probe to be short-circuited to perform voltage measurement;

[0086] The dielectric relaxation of the capacitor is characterized based on the measured voltage change.

[0087] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0088] By setting up two groups of probe groups, one group is a charging probe group, which is used to be connected to the charging device to charge the capacitor tube, and the other group is a measuring probe group, which is used to be connected to the detection device after stopping charging the capacitor tube to detect the dielectric relaxation of the capacitor tube. Compared with the scheme of using a group of shared probe groups for both charging and dielectric relaxation detection, this scheme does not need to perform the switching step of first removing the charging device and the shared probe group and then connecting the detection device to the shared probe during the process of detecting the dielectric relaxation of the capacitor tube. This scheme can directly connect the detection device and the measuring probe group to detect the dielectric relaxation of the capacitor tube at the same time as the charging device stops charging the capacitor tube. This can save the time spent on switching, reduce the measurement error in the dielectric relaxation detection process, and more accurately characterize the dielectric relaxation, thereby realizing rapid and accurate screening of dielectric materials.

[0089] In addition, since the depth and width of the capacitor tube are relatively large, the present disclosure can facilitate the connection of the charging probe group and the measuring probe group to the capacitor tube by setting the first conductor layer and the second conductor layer, and the dielectric insulation layer is used to isolate the first conductor layer and the second conductor layer to avoid the situation where the conductor core and the conductor sleeve of the capacitor tube are always in a short-circuited state in any state, causing the capacitor tube to be unable to be used normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0091] Figure 1 A schematic diagram of the planar structure of the dielectric relaxation measurement structure and the capacitor tube shown in an embodiment of the present disclosure is shown.

[0092] Figure 2 Shown Figure 1 The structure shown in FIG is a schematic cross-sectional view along the AA direction.

[0093] Figure 3 Shown Figure 1 The structure shown in FIG is a schematic cross-sectional view along the BB direction.

[0094] Figure 4 Shown Figure 2Schematic diagram of the enlarged structure of part D in the middle.

[0095] Figure 5 A schematic diagram of a planar structure of a dielectric relaxation measurement structure and a capacitor tube in cooperation with another embodiment of the present disclosure is shown.

[0096] Figures 6 to 13 A schematic structural diagram of each step in a manufacturing method corresponding to the formation of a dielectric relaxation measurement structure in a semiconductor device according to an embodiment of the present disclosure is shown.

[0097] Figure 14 A schematic flow chart of a dielectric relaxation measurement method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0098] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0099] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0100] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0101] Dielectric relaxation, also known as dielectric relaxation, is the process by which a dielectric reaches a new polarization equilibrium state from a transient polarization state after an external electric field is applied (or removed). The time it takes for the dielectric polarization to reach a steady state is called the relaxation time.

[0102] Among them, dielectric relaxation affects the outflow rate of stored charge in the capacitor tube, thereby affecting the read and write speeds of chips such as DRAM that include the capacitor tube. Therefore, how to quickly and accurately select dielectric materials with little impact on read and write speeds has become a problem that needs to be solved urgently.

[0103] Based on this, an embodiment of the present disclosure provides a dielectric relaxation measurement structure that can be applied to semiconductor devices. Specifically, the semiconductor device may include a substrate and a capacitor tube formed on the substrate, and the dielectric relaxation measurement structure can be formed on the substrate and electrically connected to the capacitor tube to measure the dielectric relaxation of the capacitor tube in the semiconductor device.

[0104] The dielectric relaxation measurement structure, the capacitor tube, and the coordination relationship between the two according to the embodiment of the present disclosure are described in detail below with reference to the accompanying drawings.

[0105] Combine Figures 1 to 3 As shown, the dielectric relaxation measurement structure of the embodiment of the present disclosure may be formed on the substrate 10 of the semiconductor device. Specifically, the dielectric relaxation measurement structure may include a first conductor layer 111 , a second conductor layer 112 , a dielectric insulation layer 113 , a charging probe set 12 , and a measurement probe set 13 .

[0106] For example, the substrate 10 may include a base 101 and an insulating isolation layer 102 formed on the base 101. The base 101 may be a semiconductor base, such as, but not limited to, a silicon base, and may also be a base formed of other semiconductor materials (e.g., silicon carbide, gallium compounds, or germanium compounds). The insulating isolation layer 102 may be a single-layer structure, such as, but not limited to, an insulating material layer such as SiO2 (silicon dioxide) or SiON (silicon oxynitride). The insulating isolation layer 102 may also be a multi-layer stacked structure, such as, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, and the like stacked in sequence. It should be understood that when the insulating isolation layer 102 is a multi-layer stacked structure, it is not limited to the four layers shown in the example, and may also be two, three, five, or the like. The number of layers and the materials used may vary depending on the specific situation and will not be described in detail herein.

[0107] The capacitor tube C may include a conductor sleeve C1, a conductor core C2, and a dielectric portion C3. The conductor core C2 extends in a direction intersecting the substrate 10; for example, the extension direction of the conductor core C2 may be perpendicular or approximately perpendicular to the substrate 10. The conductor sleeve C1 is at least partially sleeved around the outer periphery of the conductor core C2; ​​for example, the conductor sleeve C1 may be a groove-like structure with a groove bottom, but is not limited thereto. The conductor sleeve C1 may also be a sleeve-like structure with open ends. The dielectric portion C3 may be formed between the conductor sleeve C1 and the conductor core C2 to isolate the conductor sleeve C1 from the conductor core C2.

[0108] For example, the material of the conductor sleeve C1 can be a conductive material such as titanium nitride (TiN), and the material of the conductor core C2 can be a conductive material such as silicon germanium (SiGe). It should be noted that the conductor sleeve C1 and the conductor core C2 are not limited to the materials mentioned above, and can also be other conductive materials, as long as the conductor sleeve C1 and the conductor core C2 of the capacitor tube C can have good conductive properties, and the dielectric part C3 can use a dielectric material with a high K value.

[0109] In a specific embodiment of the present disclosure, Figure 6 As shown, the insulating isolation layer 102 may be provided with a receiving groove 102 a , and the capacitor C may be filled in the receiving groove 102 a .

[0110] For example, multiple receiving grooves 102a and capacitor tubes C can be set, and the capacitor tubes C can be filled one by one in the receiving grooves 102a. In this way, when detecting the dielectric relaxation of the capacitor tubes C, the factors of mutual interference between the capacitor tubes C in the chip are taken into account, so as to more accurately characterize the dielectric relaxation, thereby realizing rapid and accurate screening of dielectric materials.

[0111] The first conductive layer 111, the dielectric insulating layer 113, the second conductive layer 112, the charging probe group 12, and the measuring probe group 13 can be formed on the insulating isolation layer 102 away from the substrate 101. That is, the first conductive layer 111, the dielectric insulating layer 113, the second conductive layer 112, the charging probe group 12, and the measuring probe group 13 can be formed on the same side of the substrate 101 as the capacitor C to reduce the difficulty of connecting them to the capacitor C.

[0112] Since the depth and width of the capacitor tube C are relatively large, the embodiment of the present disclosure facilitates the connection of the charging probe group 12 and the measuring probe group 13 to the capacitor tube C by providing the first conductor layer 111 and the second conductor layer 112. The dielectric insulation layer 113 is used to isolate the first conductor layer 111 and the second conductor layer 112 to avoid the situation where the conductor core C2 and the conductor sleeve C1 of the capacitor tube C are always in a short-circuited state in any state, causing the capacitor tube C to be unable to be used normally.

[0113] Specifically, combined Figures 2 to 4 As shown, the first conductor layer 111 can cover and contact the top of the conductor sleeve C1 to achieve electrical connection between the first conductor layer 111 and the conductor sleeve C1. The first conductor layer 111 has a first hollow hole (not shown in the figure). In the orthographic projection on the substrate 10, the dielectric portion C3 can be projected into the first hollow hole.

[0114] For example, in the orthographic projection on the substrate 10 , the first hollow hole completely overlaps with the inner cavity of the conductor sleeve C1 , but is not limited thereto. The diameter of the first hollow hole may also be slightly larger than the inner diameter of the conductor sleeve C1 and smaller than the outer diameter of the conductor sleeve C1 .

[0115] A portion of the dielectric insulation layer 113 may be formed on a side of the first conductive layer 111 away from the substrate 10, while another portion of the dielectric insulation layer 113 is located within the first hollow hole and covers the top of the dielectric portion C3. In other words, the dielectric insulation layer 113 is in contact with the top of the dielectric portion C3. The dielectric insulation layer 113 may have a second hollow hole (not shown). In an orthographic projection on the substrate 10, the second hollow hole is projected within the first hollow hole, and the conductive tube core C2 is projected within the second hollow hole.

[0116] For example, in the orthographic projection on the substrate 10 , the second hollow hole completely overlaps with the conductor core C2 , but is not limited thereto. The diameter of the second hollow hole may also be slightly larger than the inner diameter of the dielectric portion C3 and smaller than the outer diameter of the dielectric portion C3 .

[0117] A portion of the second conductor layer 112 is formed on a side of the dielectric insulation layer 113 away from the substrate 10, and another portion of the second conductor layer 112 is located in the second hollow hole and contacts the top of the conductor tube core C2 to achieve electrical connection between the second conductor layer 112 and the conductor tube core C2.

[0118] Among them, when there are multiple capacitor tubes C in the semiconductor device, the number of the first hollow holes in the first conductor layer 111 and the second hollow holes in the dielectric insulation layer 113 is the same as the number of capacitor tubes C. The first hollow holes in the first conductor layer 111 and the second hollow holes in the dielectric insulation layer 113 match the capacitor tubes C one-to-one, and the orthographic projection of the second conductor layer 112 on the substrate 101 covers the orthographic projection of each capacitor tube C on the substrate 101 and contacts the conductor tube core C2 of each capacitor tube C. By providing the first conductor layer 111 and the second conductor layer 112, the charging probe group 12 and the measurement probe group 13 can be conveniently connected to each capacitor tube C.

[0119] In a specific embodiment of the present disclosure, the first conductor layer 111 and the conductor sleeve C1 are integrally formed, the dielectric insulation layer 113 and the dielectric portion C3 are integrally formed, and the second conductor layer 112 and the conductor core C2 are integrally formed, so as to simplify the manufacturing steps and save costs.

[0120] It should be noted that the integrated structure mentioned in this embodiment refers to an integrated structure formed by using the same material and the same patterning process.

[0121] Combine Figures 1 to 4As shown, the charging probe group 12 may include a first charging probe 121 electrically connected to the first conductive layer 111 and a second charging probe 122 electrically connected to the second conductive layer 112. The first charging probe 121 and the second charging probe 122 are used to conduct with the charging device to charge the capacitor C. The measuring probe group 13 may include a first measuring probe 131 electrically connected to the first conductive layer 111 and a second measuring probe 132 electrically connected to the second conductive layer 112. The first measuring probe 131 and the second measuring probe 132 are used to conduct with the detection device when the charging device stops charging the capacitor C to detect the dielectric relaxation of the capacitor C.

[0122] For example, the first charging probe 121 , the second charging probe 122 , the first measuring probe 131 , and the second measuring probe 132 may be made of conductive materials such as titanium nitride (TiN), but are not limited thereto and may be made of other conductive materials, which will not be described in detail herein.

[0123] This solution sets up two groups of probe groups, one group is a charging probe group 12, which is used to be connected to the charging device to charge the capacitor tube C, and the other group is a measuring probe group 13, which is used to be connected to the detection device after stopping charging the capacitor tube C to detect the dielectric relaxation of the capacitor tube C. Compared with the solution of using a common probe group for both charging and dielectric relaxation detection, the position of the probe connected to the detection device and the position of the probe connected to the power supply device in the dielectric relaxation measurement structure of this solution are different. In the process of detecting the dielectric relaxation of the capacitor tube C, there is no need to perform the switching step of first removing the charging device and the common probe group and then connecting the detection device to the common probe. This solution can directly connect the detection device and the measuring probe group 13 to detect the dielectric relaxation of the capacitor tube C after the charging device stops charging the capacitor tube C. This can reduce the time consumed in the switching process and reduce the measurement error in the dielectric relaxation detection process, so as to more accurately characterize the dielectric relaxation, thereby realizing rapid and accurate screening of dielectric materials.

[0124] It should be understood that in order to ensure the normal use of the capacitor tube C, the first charging probe 121 and the second charging probe 122 of this embodiment need to be arranged at intervals, and the first measuring probe 131 and the second measuring probe 132 need to be arranged at intervals, so as to avoid the first conductor layer 111 and the second conductor layer 112 being always in a short-circuited state under any state due to direct contact between the first charging probe 121 and the second charging probe 122 or direct contact between the first measuring probe 131 and the second measuring probe 132, thereby preventing the capacitor tube C from being able to function normally.

[0125] In this embodiment, if Figure 1As shown, the first charging probe 121 and the first measuring probe 131 are spaced apart, and the second charging probe 122 and the second measuring probe 132 are spaced apart, so as to avoid collision between the detection device and the power supply device due to the charging probe and the measuring probe being too close.

[0126] Among them, combined Figures 1 to 4 As shown, the dielectric relaxation measurement structure may further include a first conductive structure 14 and a second conductive structure 15 . The first conductive structure 14 and the second conductive structure 15 are formed on the substrate 10 ; for example, they may be formed on a side of the insulating isolation layer 102 away from the base 101 . One end of the first conductive structure 14 is electrically connected to the first measurement probe 131 and the first charging probe 121, and the other end of the first conductive structure 14 is electrically connected to the first conductive layer 111. In other words, the first measurement probe 131 and the first charging probe 121 are both connected to the first conductive structure 14 and connected to the first conductive layer 111 through the first conductive structure 14. One end of the second conductive structure 15 is electrically connected to the second measurement probe 132 and the second charging probe 122, and the other end of the second conductive structure 15 is electrically connected to the second conductive layer 112. In other words, the second measurement probe 132 and the second charging probe 122 are both connected to the second conductive structure 15 and connected to the second conductive layer 112 through the second conductive structure 15. By providing the first conductive structure 14 and the second conductive structure 15, the charging position and the detection position on the first conductive layer 111 and the charging position and the detection position on the second conductive layer 112 can be made the same, thereby improving the accuracy of dielectric relaxation detection.

[0127] In a specific embodiment of the present disclosure, Figures 1 to 3 As shown, the dielectric relaxation measurement structure may further include a planarization layer 16 formed on the substrate 10, specifically on the side of the insulating isolation layer 102 away from the base 101. The planarization layer 16 covers the first conductor layer 111, the second conductor layer 112 and the dielectric insulation layer 113. That is, the first conductor layer 111, the second conductor layer 112 and the dielectric insulation layer 113 may be first formed on the insulating isolation layer 102, and then the planarization layer 16 may be formed so that the planarization layer 16 covers the first conductor layer 111, the second conductor layer 112 and the dielectric insulation layer 113.

[0128] For example, the planarization layer 16 may be a multi-layer stacked structure, such as Figure 2 and Figure 3 As shown, the planarization layer 16 may include: a silicon oxide material layer 161 and a silicon nitride material layer 162 formed in sequence. The silicon oxide material layer 161 may be polished to ensure flatness, and the resistivity of the silicon nitride material layer 162 is lower than the resistivity of the silicon oxide material layer 161, so as to better encapsulate and protect the underlying first conductor layer 111, the second conductor layer 112 and each capacitor tube C.

[0129] It should be noted that the planarization layer 16 is not limited to a multi-layer stacked structure, but may also be a single-layer structure, depending on the specific situation.

[0130] Among them, Figure 2 As shown, the first charging probe 121, the second charging probe 122, the first measurement probe 131, and the second measurement probe 132 can be formed on the surface of the planarization layer 16 away from the substrate 101, and the first conductive structure 14 and the second conductive structure 15 can penetrate the planarization layer 16. Specifically, the top of the first conductive structure 14 is electrically connected to the first measurement probe 131 and the first charging probe 121, and the bottom of the first conductive structure 14 is in contact with the first conductive layer 111. The top of the second conductive structure 15 is electrically connected to the second measurement probe 132 and the second charging probe 122, and the bottom of the second conductive structure 15 is in contact with the second conductive layer 112.

[0131] It should be noted that the top end mentioned in this embodiment refers to the end of the structure away from the substrate 101 , and the bottom end refers to the end of the structure close to the substrate 101 .

[0132] In this embodiment, the orthographic projection of the first conductive structure 14 on the substrate 101 may overlap with the orthographic projection of the first conductor layer 111 on the substrate 101, so that at least the overlapping portion thereof passes through the planarization layer 16 and contacts the surface of the first conductor layer 111 away from the substrate 101, while ensuring contact stability and reducing processing difficulty; similarly, the orthographic projection of the second conductive structure 15 on the substrate 101 may overlap with the orthographic projection of the second conductor layer 112 on the substrate 101, so that at least the overlapping portion thereof passes through the planarization layer 16 and contacts the surface of the second conductor layer 112 away from the substrate 101, while ensuring contact stability and reducing processing difficulty.

[0133] Optionally, combined Figure 4 As shown, the first conductor layer 111 may include a first main region 1111 and a first edge region 1112 surrounding the first main region 1111 , wherein the aforementioned first hollow hole is located in the first main region 1111 .

[0134] In this embodiment, the orthographic projections of the second conductor layer 112 and the dielectric insulation layer 113 on the substrate 101 are located within the orthographic projection of the first main area 1111 on the substrate 101; the orthographic projection of the first conductive structure 14 on the substrate 101 overlaps with the orthographic projection of the first edge area 1112 on the substrate 101 and contacts the first edge area 1112. Compared with the solution of providing insulating vias on the second conductor layer 112 and the dielectric insulation layer 113 for the first conductive structure 14 to pass through, this design allows the first conductive structure 14 to contact the first conductor layer 111 without providing insulating vias on the second conductor layer 112 and the dielectric insulation layer 113, thereby ensuring the integrity of the second conductor layer 112 and the dielectric insulation layer 113, thereby better charging and discharging each capacitor tube C.

[0135] The orthographic projection of the second conductive structure 15 on the substrate 101 is located within the orthographic projection of the second conductor layer 112 on the substrate 101, and the first conductive structure 14 can be arranged around the second conductive structure 15. This makes the electric field distribution more uniform during the dielectric relaxation measurement, the measurement effect more accurate, and the charging process time is shortened.

[0136] It should be noted that the surrounding mentioned in the present disclosure can be a closed surrounding or a non-closed surrounding. The closed surrounding means that the surrounding structure is arranged without any gaps in the entire circle, while the non-closed surrounding means that the surrounding structure has at least one gap or multiple gaps in the entire circle. When there are multiple gaps, the surrounding structure will be divided into multiple surrounding segments arranged at intervals in the circumferential direction.

[0137] When the first conductor layer 111 and the second conductor layer 112 are used to charge and discharge the capacitor C, the dielectric insulating layer 113 is usually designed to be very thin, typically only a few nanometers thick. This results in significant leakage at the edges of the dielectric insulating layer 113, which can interfere with measurement results. Therefore, in order to improve measurement accuracy, the following design can be employed:

[0138] The orthographic projection of the dielectric insulation layer 113 on the substrate 101 completely overlaps with the orthographic projection of the second conductor layer 112 on the substrate 101, and the second conductor layer 112 and the dielectric insulation layer 113 include a second main area (not numbered in the figure) and a second edge area (not numbered in the figure) surrounding the second main area. It should be noted that the second hollow hole is located in the second main area of ​​the dielectric insulation layer 113.

[0139] Among them, the orthographic projection of the second conductive structure 15 on the substrate 101 is located within the orthographic projection of the second main area of ​​the second conductor layer 112 on the substrate 101, so that the area measured during the dielectric relaxation measurement is closer to the middle area between the first conductor layer 111 and the second conductor layer 112. Compared with the solution where the measurement area is the edge area, it can avoid the situation where leakage at the edges of the first conductor layer 111 and the second conductor layer 112 causes deviation in the test results, that is, this solution can improve the accuracy of dielectric relaxation measurement.

[0140] Further, combined with Figures 2 to 4 As shown, the dielectric relaxation measurement structure may further include an interlayer dielectric layer 17 formed between the planarization layer 16 and the insulating isolation layer 102; the interlayer dielectric layer 17 covers the edge position of the first main region 1111 in the first conductor layer 111 and covers the first edge region 1112 of the first conductor layer 111, and the interlayer dielectric layer 17 has a through hole 171, which exposes the middle position of the first main region 1111 in the first conductor layer 111; the second edge region of the dielectric insulation layer 113 and the second conductor layer 112 overlaps on the surface of the interlayer dielectric layer 17 away from the first conductor layer 111, and the second main region of the dielectric insulation layer 113 and the second conductor layer 112 is formed in the through hole 171. By overlapping the second edge region of the dielectric insulation layer 113 and the second conductor layer 112 on the surface of the interlayer dielectric layer 17 away from the first conductor layer 111, the distance between the edge of the second conductor layer 112 and the first conductor layer 111 is increased, thereby reducing the influence of edge leakage on the detection result.

[0141] It should be noted that, combined with Figures 2 to 4 As shown, the first conductive structure 14 penetrates the planarization layer 16 and contacts the first conductor layer 111 , and also penetrates the interlayer dielectric layer 17 to contact the first edge region 1112 of the first conductor layer 111 . Furthermore, the first hollow hole and the second hollow hole are projected into the through hole 171 .

[0142] In a specific embodiment of the present disclosure, Figures 1 to 3As shown, the first conductive structure 14 may include a first transition portion 141 and a first via portion 142. The first transition portion 141 is located on the surface of the planarization layer 16 away from the substrate 101 and is electrically connected to the first measurement probe 131 and the first charging probe 121. The orthographic projection of the first via portion 142 on the substrate 101 is located within the orthographic projection of the first transition portion 141 on the substrate 101. The first via portion 142 passes through the planarization layer 16, and the top end of the first via portion 142 contacts the first transition portion 141, and the bottom end of the first via portion 142 contacts the first edge region of the first conductor layer 111. The second conductive structure 15 includes a second transition portion 151 and a second via portion 152. The second transition portion 151 is located on the surface of the planarization layer 16 away from the substrate 101 and is electrically connected to the second measurement probe 132 and the second charging probe 122. The orthographic projection of the second via portion 152 on the substrate 101 is located within the orthographic projection of the second transition portion 151 on the substrate 101. The second via portion 152 passes through the planarization layer 16, and the top end of the second via portion 152 contacts the second transition portion 151, and the bottom end of the second via portion 152 contacts the second conductive layer 112.

[0143] Among them, such as Figure 1 and Figure 3 As shown, the first adapter portion 141 is arranged around the second adapter portion 151, and a plurality of first via portions 142 are provided and arranged at intervals along the circumferential direction to surround the second via portion 152. This design makes the electric field distribution more uniform during the dielectric relaxation measurement process, the measurement effect more accurate, and can also reduce material costs.

[0144] It should be noted that if Figures 2 to 4 As shown, a plurality of second via portions 152 may be provided, and arranged in an array in the first direction X and the second direction Y at intervals.

[0145] The first direction X and the second direction Y mentioned in the disclosed solution are both directions parallel to the substrate 101 , and the first direction X and the second direction Y intersect, and may be perpendicular to each other.

[0146] In one embodiment of the present disclosure, reference Figure 2 As shown, the orthographic projections of the first charging probe 121 , the second charging probe 122 , the first measuring probe 131 , and the second measuring probe 132 on the substrate 101 do not overlap with the orthographic projections of the first conductive layer 111 and the second conductive layer 112 on the substrate 101 , thereby reducing parasitic capacitance during the charging process or the dielectric relaxation measurement process.

[0147] Since the orthographic projections of the first charging probe 121, the second charging probe 122, the first measuring probe 131 and the second measuring probe 132 on the substrate 101 do not overlap with the orthographic projections of the first conductor layer 111 and the second conductor layer 112 on the substrate 101, Figure 1 and Figure 2 As shown, in order to facilitate the connection between the first conductive structure 14 and the first charging probe 121 and the first measurement probe 131, and the connection between the second conductive structure 15 and the second charging probe 122 and the second measurement probe 132, the dielectric relaxation measurement structure may further include a first lead 18a and a second lead 18b, and the first lead 18a and the second lead 18b are formed on the surface of the planarization layer 16 away from the substrate 101.

[0148] Among them, such as Figure 1 As shown, the first lead 18a and the second lead 18b each include a main section 181 and a branch section 182. The main section 181 and the branch section 182 have a first end and a second end. The first end of the branch section 182 is located between the first end and the second end of the main section 181 and is connected to the main section 181. In the first lead 18a, the first end of the main section 181 contacts the first adapter 141, and the second end of the main section 181 contacts the first charging probe 121 and the first measuring probe 1 31, and the second end of the branch section 182 contacts the other of the first charging probe 121 and the first measuring probe 131; in the second lead 18b: the first end of the main section 181 contacts the second adapter 151, the second end of the main section 181 contacts one of the second charging probe 122 and the second measuring probe 132, and the second end of the branch section 182 contacts the other of the second charging probe 122 and the second measuring probe 132.

[0149] In this embodiment, the first lead 18 a is used to connect the first charging probe 121 and the first measurement probe 131 to the same position on the first adapter 141 , and the second lead 18 b is used to connect the second charging probe 122 and the second measurement probe 132 to the same position on the second adapter 151 , thereby improving the accuracy of dielectric relaxation detection.

[0150] It should be noted that, since the first transition portion 141 is arranged around the second transition portion 151, in order to facilitate the extraction of the second lead 18b, as shown in FIG. Figure 1 As shown, the first transition portion 141 may be designed with an avoidance opening 1410 for the main section 181 of the second lead 18b to pass through, and there is a gap between the main section 181 of the second lead 18b and the first transition portion 141 at the avoidance opening 1410, that is, the second lead 18b does not contact the first transition portion 141.

[0151] In order to reduce the influence of parasitic capacitance and parasitic inductance, the present embodiment can arrange the measuring probe group 13 closer to the first conductive structure 14 and the second conductive structure 15 than the charging probe group 12. Figures 1 to 3As shown, the first measurement probe 131 is arranged closer to the first conductive structure 14 than the first charging probe 121, and the second measurement probe 132 is arranged closer to the second conductive structure 15 than the second charging probe 122. This design allows the length of the connection line between the first measurement probe 131 and the first conductive structure 14 to be shorter than the length of the connection line between the first charging probe 121 and the first conductive structure 14, and the length of the connection line between the second measurement probe 132 and the second conductive structure 15 to be shorter than the length of the connection line between the second charging probe 122 and the second conductive structure 15. This allows the probes to be arranged within a limited space while reducing the impact of parasitic capacitance and parasitic inductance on dielectric relaxation measurement.

[0152] Optionally, when the first lead 18 a is used to connect the first charging probe 121 and the first measuring probe 131 to the same position on the first adapter 141, and the second lead 18 b is used to connect the second charging probe 122 and the second measuring probe 132 to the same position on the second adapter 151: the second end of the main section 181 of the first lead 18 a contacts the first measuring probe 131, and the first charging probe 121 is located on a side of the first measuring probe 131 away from the first adapter 141; while the second end of the main section 181 of the second lead 18 b contacts the second measuring probe 132, and the second charging probe 122 is located on a side of the second measuring probe 132 away from the second adapter 151.

[0153] In an optional embodiment of the present disclosure, combined with Figure 1 and Figure 3 As shown, the dielectric relaxation measurement structure further includes a ground probe 191 and a ground shield 192. Specifically, the ground probe 191 can be formed on a side of the planarization layer 16 away from the insulating isolation layer 102 for grounding; the ground shield 192 penetrates the planarization layer 16, and the top end of the ground shield 192 (i.e., the end away from the substrate 101) is connected to the ground probe 191. The bottom end of the ground shield 192 extends toward the substrate 101. The orthographic projection of the ground shield 192 on the substrate 101 is located on at least two opposite sides of the orthographic projection of the first conductor layer 111 on the substrate 101. This design can effectively reduce the impact of electromagnetic radiation generated during high-frequency charging and discharging on dielectric relaxation measurement, thereby improving measurement accuracy, accurately characterizing dielectric relaxation, and clearly reflecting the impact of dielectric relaxation on the charging and discharging of the capacitor C.

[0154] In this embodiment, the orthographic projection of the second conductor layer 112 on the substrate 101 coincides with or is located within the orthographic projection of the first conductor layer 111 on the substrate 101. Thus, when the ground shielding portion 192 is projected onto opposite sides of the first conductor layer 111, the second conductor layer 112 and each capacitor tube C are located within the shielding area formed by the ground shielding portion 192, effectively reducing the impact of electromagnetic radiation generated during high-frequency charging and discharging on dielectric relaxation measurement.

[0155] Optionally, the surface of the ground shielding portion 192 close to the substrate 101 is lower than the surface of the capacitor tube C close to the substrate 101 (eg Figure 3 as shown) or flush with the surface of the capacitor tube C close to the substrate 101 to better achieve shielding effect.

[0156] In the disclosed embodiment, the horizontal spacing between the ground shield 192 and the first conductive layer 111 is smaller than the horizontal spacing between the first charging probe 121, the first measuring probe 131, the second charging probe 122, and the second measuring probe 132 and the first conductive layer 111. This allows the zero potential position to be moved closer to the first conductive layer 111, thereby providing a better shielding effect.

[0157] It should be noted that the horizontal distance refers to the distance between two objects in a direction parallel to the substrate 101 .

[0158] In the embodiment of the present disclosure, the first charging probe 121 and the first measuring probe 131 may constitute a first probe group, the second charging probe 122 and the second measuring probe 132 may constitute a second probe group, and the first probe group and the second probe group are arranged in the first direction X; and the first conductive structure 14 and the second conductive structure 15 are located between the first probe group and the second probe group, and the surface of the first conductive structure 14 facing the first probe group is connected to the first charging probe 121 and the first measuring probe 131 through the first lead 18a, and the surface of the second conductive structure 15 facing the second probe group is connected to the second charging probe 122 and the second measuring probe 132 through the second lead 18b.

[0159] The first lead 18a and the second lead 18b are formed on the surface of the planarization layer 16 away from the insulating isolation layer 102, and the surface of the ground shielding portion 192 away from the substrate 101 is flush with the surface of the first lead 18a and the second lead 18b close to the planarization layer 16 (combined with the surface of the ground shielding portion 192). Figures 1 to 3 That is, the top surface of the ground shield portion 192 is flush with the bottom surfaces of the first lead 18a and the second lead 18b, or is higher than the surface of the first lead 18a and the second lead 18b close to the planarization layer 16.

[0160] It should be noted that when the surface of the ground shield portion 192 away from the substrate 101 is higher than the surface of the first lead 18 a and the second lead 18 b close to the planarization layer 16 , there are three situations as follows:

[0161] The first type: the top surface of the ground shield portion 192 is located between the top surface and the bottom surface of the first lead 18a and the second lead 18b;

[0162] The second type: the top surface of the ground shield portion 192 is flush with the top surfaces of the first lead 18a and the second lead 18b;

[0163] The third type: the top surface of the ground shield portion 192 is higher than the top surfaces of the first lead 18a and the second lead 18b;

[0164] The specific method to be selected can be determined according to the actual processing method, and will not be elaborated here.

[0165] In order to prevent the ground shield 192 from contacting the first lead 18a and the second lead 18b, as shown in FIG. Figure 1 As shown, two ground shielding parts 192 can be provided and arranged in the second direction Y, and the first conductor layer 111 is located between the two ground shielding parts 192 to ensure good shielding performance. The two ground shielding parts 192 are spaced apart on one side close to the first probe group to form a first avoidance gap 1921 for the first lead 18a to pass through, and the first lead 18a has a gap at the first avoidance gap 1921, that is, the first lead 18a does not contact the ground shielding part 192, and the two ground shielding parts 192 are spaced apart on one side close to the second probe group to form a second avoidance gap 1922 for the second lead 18b to pass through, and the second lead 18b has a gap at the second avoidance gap 1922, that is, the second lead 18b does not contact the ground shielding part 192.

[0166] Since the two ground shielding portions 192 are separated in the second direction Y, each ground shielding portion 192 can be connected to the ground probe 191 via a grounding lead 193 .

[0167] In an alternative embodiment, if Figure 1 As shown, the ground shielding portion 192 may be a long strip structure extending in the first direction X to reduce design difficulty.

[0168] In another alternative embodiment, if Figure 5 As shown, the ground shielding portion 192 includes a main shielding portion (not numbered in the figure) extending in the first direction X and auxiliary shielding portions (not numbered in the figure) located at the two extended ends of the main shielding portion, and the auxiliary shielding portion extends in the second direction Y. This design allows a shielding structure with a larger area to be provided around the first conductor layer 111 to better play an electrostatic shielding role.

[0169] In a specific embodiment of the present disclosure, Figure 3 As shown, the ground lead 193 may be formed on a side of the planarization layer 16 away from the insulating isolation layer 102 to facilitate the connection between the ground shielding portion 192 and the ground probe 191 .

[0170] In a specific embodiment of the present disclosure, Figure 1 and Figure 2 As shown, a ground probe 191 is formed on a side of one of the first probe group and the second probe group away from the first conductive structure 14 and the second conductive structure 15 , so that the ground leads 193 can be symmetrically designed.

[0171] It should be understood that the first conductive structure 14 and the second conductive structure 15 may not be provided in the embodiment of the present disclosure. The first charging probe 121 and the first measuring probe may be directly connected to the first conductor layer 111, respectively, and the second charging probe 122 and the second measuring probe may be directly connected to the first conductor layer 111, respectively, to reduce the design difficulty.

[0172] Furthermore, it should be noted that, after measuring the dielectric relaxation of the capacitor tube in the semiconductor device and finding that the dielectric relaxation measurement structure meets the requirements of the semiconductor device, the dielectric relaxation measurement structure can be cut from the substrate 10 of the semiconductor device, but the present invention is not limited thereto and can also be retained in the semiconductor device. When the dielectric relaxation measurement structure remains in the semiconductor device, the dielectric relaxation measurement structure can be considered as part of the semiconductor device. In other words, the present embodiment further provides a semiconductor device comprising a substrate 10 and a capacitor tube C and a dielectric relaxation measurement structure formed on the substrate 10. The capacitor tube C and the dielectric relaxation measurement structure can be specifically described with reference to the structures described in the aforementioned embodiments and will not be repeated here.

[0173] Based on the dielectric relaxation measurement structure mentioned in the aforementioned specific embodiment of the present disclosure, the embodiment of the present disclosure also provides a method for manufacturing a semiconductor device. This manufacturing method may specifically include steps S100, S101, S102, S103, S104, S105, S106, S107, and S108.

[0174] In step S100 , an insulating isolation layer 102 is formed on a substrate 101 .

[0175] In step S101, the insulating isolation layer 102 is patterned to form a plurality of spaced-apart receiving grooves 102a on the insulating isolation layer 102. Figure 6 As shown, the substrate 10 is formed.

[0176] In step S102, a first conductive film is formed on one side of the substrate 101, and the first conductive film is patterned to remove a portion of the first conductive film and retain a portion. The retained portion is the first conductor layer 111 mentioned in the above embodiment and the conductor sleeve C1 located in the receiving groove 102a. The conductor sleeve C1 can be a groove-shaped structure with a groove bottom. The position where the first conductor layer 111 and the groove of the conductor sleeve C1 are opposite to each other is a first hollow hole, such as Figure 7 shown.

[0177] In step S103, an interlayer dielectric film is formed to cover the insulating isolation layer 102, the first conductor layer 111, and the conductor sleeve C1, and the interlayer dielectric film is patterned to form an interlayer dielectric layer 17. The interlayer dielectric layer 17 covers the edge area of ​​the first conductor layer 111, and the interlayer dielectric layer 17 has through holes 171. The through holes 171 expose the middle area of ​​the first conductor layer 111 and each conductor sleeve C1. Figure 8 shown.

[0178] In step S104, a dielectric material film 113a and a second conductive film 112a are sequentially formed on the substrate 101. Figure 9 As shown, the dielectric material film 113a and the second conductive film 112a are patterned at the same time to remove a portion of the dielectric material film 113a and the second conductive film 112a and retain a portion, as shown in FIG. Figure 10 As shown, the retained portion of the dielectric material film 113a includes the aforementioned dielectric insulation layer 113 and the dielectric portion C3 located in the conductor sleeve C1. The dielectric portion C3 can be a groove-shaped structure with a groove bottom. The position of the dielectric portion C3 relative to the groove of the dielectric portion C3 is a second hollow hole. The retained portion of the second conductive film 112a includes the aforementioned second conductor layer 112 and the conductor core C2. The edge areas of the dielectric insulation layer 113 and the second conductor layer 112 overlap the surface of the interlayer dielectric layer 117 away from the first conductor layer 111, and the central areas of the dielectric insulation layer 113 and the second conductor layer 112 are formed in the through hole 171.

[0179] In step S105, a planarization layer 16 is formed on the substrate 101. The planarization layer 16 covers the interlayer dielectric layer 17, the dielectric insulation layer 113, the second conductive layer 112, and the first conductive layer 111. For example, the planarization layer 16 may be the aforementioned multi-layer stacked structure, i.e., including a silicon oxide material layer 161 and a silicon nitride material layer 162 formed in sequence.

[0180] In step S106, a first through hole H1, a second through hole H2, and a ground through hole H3 are formed. The first through hole H1 penetrates the planarization layer 16 and the interlayer dielectric layer 17 to expose the edge area of ​​the first conductor layer 111. The second through hole H2 penetrates the planarization layer 16 to expose the middle area of ​​the second conductor layer 112. The ground through hole H3 penetrates at least the planarization layer 16 and the interlayer dielectric layer 17 and is located on the side of the first through hole H1 away from the second through hole H2. The ground through hole H3 does not overlap with the orthographic projection of the first conductor layer 111 on the substrate 101. Figure 11 shown.

[0181] The first through hole H1 can be provided in plurality and spaced around the second through hole H2. The second through hole H2 and the grounding through hole H3 can also be provided in plurality and spaced. Figure 11 As shown, the ground via H3 not only penetrates the planarization layer 16 and the interlayer dielectric layer 17 , but also penetrates a portion of the insulating isolation layer 102 .

[0182] For example, the first through hole H1 , the second through hole H2 , and the ground through hole H3 may be formed simultaneously by a same patterning process.

[0183] In step S107, a third conductive film 19a is formed to cover the planarization layer 16 and fill the first through hole H1, the second through hole H2 and the ground through hole H3. Figure 12 and Figure 13 shown.

[0184] In step S108, the third conductive film 19a is patterned to form the charging probe group 12, the measuring probe group 13, the first conductive structure 14, the second conductive structure 15, the first lead 18a, the second lead 18b, the grounding probe 191, the grounding shield 192, and the grounding lead 193 mentioned in any of the above embodiments. Figures 1 to 4 shown.

[0185] For example, the patterning process mentioned in the embodiment of the present disclosure may be a photolithography (full name in English: photolithography) process, which is an important step in the semiconductor device manufacturing process. This step uses exposure and development to engrave a geometric structure on the photoresist layer to form a photomask with a specific pattern, and then the pattern on the photomask is transferred to the film layer through an etching process.

[0186] It should be noted that the embodiments of the present disclosure are not limited to the above-mentioned manufacturing methods, and other manufacturing methods may also be used as long as they can manufacture the dielectric relaxation measurement structure mentioned in any of the above-mentioned embodiments.

[0187] The present disclosure also provides a dielectric relaxation measurement system for measuring the dielectric relaxation of a capacitor C in a semiconductor device. The dielectric relaxation measurement system may include a detection device (not shown in the figure), a charging device (not shown in the figure), a control device (not shown in the figure), and the aforementioned Figures 1 to 5 The dielectric relaxation measurement structure described in any embodiment will not be repeated here for the structure of the dielectric relaxation measurement structure and the capacitor C.

[0188] Among them, the control device is connected to the charging device and the detection device. Under the action of the control device, the charging device can be connected to the first charging probe 121 and the second charging probe 122 to charge the capacitor tube C. The charging device can also be disconnected from the first charging probe 121 and the second charging probe 122 under the action of the control device to stop charging the capacitor tube C; the detection device can be connected to the first measuring probe 131 and the second measuring probe 132 under the action of the control device while the charging device stops charging the capacitor tube C to detect the dielectric relaxation of the capacitor tube C.

[0189] It should be noted that, when the charging device is charging the capacitor C, the detection device can be disconnected from the first measuring probe 131 and the second measuring probe 132 under the control of the control device to avoid affecting the charging process.

[0190] In an optional embodiment, the detection device may include an ammeter, which can be connected in series between the first measuring probe 131 and the second measuring probe 132 under the action of the control device when the charging device stops charging the capacitor tube C to perform current measurement. The dielectric relaxation of the capacitor tube C can be characterized based on the tested current and time curve. That is, this embodiment can use a current detection method to characterize the dielectric relaxation of the capacitor tube C.

[0191] In another optional embodiment, the detection device may include a voltmeter and a short-circuit wire. The voltmeter can be connected in series between the first measuring probe 131 and the second measuring probe 132 under the action of the control device when the charging device stops charging the capacitor tube C, and the short-circuit wire can be short-circuited between the first charging probe 121 and the second charging probe 122 under the action of the control device when the charging device stops charging the capacitor tube C to perform a voltage test, and the dielectric relaxation of the capacitor tube C can be characterized by the voltage change. That is, this embodiment can use a voltage detection method to characterize the dielectric relaxation of the capacitor tube C.

[0192] The voltage measured by the voltmeter first drops to 0 and then slowly rises. The characterization results show that after the voltage drops to 0, the higher the rise height, the shorter the time to reach saturation.

[0193] It should be noted that the charging device of this embodiment can stop charging the capacitor tube C after the capacitor tube C is fully charged.

[0194] The present disclosure also provides a dielectric relaxation measurement method for measuring the dielectric relaxation of a capacitor C in a semiconductor device. The capacitor C in the semiconductor device can refer to the structure described in any of the above embodiments and will not be repeated here. Figure 14 As shown, the dielectric relaxation measurement method includes:

[0195] Step S200: forming a dielectric relaxation measurement structure on the substrate 10. The dielectric relaxation measurement structure may refer to the structure described in any of the above embodiments, such as Figures 1 to 5 As shown, no repetition is made here;

[0196] Step S201: Control the charging device to connect with the first charging probe 121 and the second charging probe 122 to charge the capacitor C.

[0197] In step S202 , after the capacitor C is fully charged, the charging device is controlled to stop charging the capacitor C, and the detection device is controlled to cooperate with the first measurement probe and the second measurement probe to detect the dielectric relaxation of the capacitor C.

[0198] In an optional embodiment, the step of controlling the detection device to cooperate with the first measurement probe 131 and the second measurement probe 132 to detect the dielectric relaxation of the capacitor C may include:

[0199] The control ammeter is connected in series between the first measuring probe 131 and the second measuring probe 132 to perform current measurement;

[0200] The dielectric relaxation of the capacitor C is characterized based on the measured current-time relationship curve.

[0201] In another optional embodiment, the step of controlling the detection device to cooperate with the first measurement probe 131 and the second measurement probe 132 to detect the dielectric relaxation of the capacitor C may include:

[0202] The voltmeter is connected in series between the first measuring probe 131 and the second measuring probe 132 , and the first charging probe 121 and the second charging probe 121 are short-circuited to perform voltage measurement.

[0203] The dielectric relaxation of the capacitor C is characterized based on the measured voltage change.

[0204] Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0205] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0206] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A dielectric relaxation measurement structure for measuring the dielectric relaxation of a capacitor in a semiconductor device, wherein the semiconductor device comprises a substrate, the capacitor is formed on the substrate, the capacitor comprises a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on the outer circumference of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core; characterized in that: The dielectric relaxation measurement structure is formed on the substrate and includes: a first conductor layer covering and contacting a top end of the conductor sleeve, wherein the first conductor layer has a first hollow hole, and in an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole; a dielectric insulating layer, a portion of which is formed on a side of the first conductor layer away from the substrate, and another portion of which is located in the first hollow hole and covers the top of the dielectric portion, the dielectric insulating layer having a second hollow hole, wherein in an orthographic projection on the substrate: the second hollow hole is projected into the first hollow hole, and the conductor core is projected into the second hollow hole; a second conductor layer, a portion of which is formed on a side of the dielectric insulation layer away from the substrate, and another portion of which is located in the second hollow hole and in contact with the top of the conductor core; a charging probe assembly, comprising a first charging probe electrically connected to the first conductor layer and a second charging probe electrically connected to the second conductor layer, wherein the first charging probe and the second charging probe are configured to be electrically connected to a charging device to charge the capacitor tube; The measuring probe group includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer. The first measuring probe and the second measuring probe are used to conduct with the detection device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

2. The dielectric relaxation measurement structure according to claim 1, wherein: The substrate includes a base and an insulating isolation layer formed on the base, the insulating isolation layer is provided with a receiving groove, and the capacitor tube is filled in the receiving groove; The first conductor layer, the dielectric insulation layer, the second conductor layer, the charging probe group, and the measuring probe group are formed on a side of the insulating isolation layer away from the substrate.

3. The dielectric relaxation measurement structure according to claim 2, wherein: The accommodating groove, the capacitor tube, the first hollow hole and the second hollow hole are all provided in plurality and matched one by one; Wherein, in the orthographic projection on the substrate: the second conductor layer covers each of the capacitor tubes.

4. The dielectric relaxation measurement structure according to claim 2 or 3, characterized in that: It also includes a first conductive structure and a second conductive structure, which are formed on a side of the insulating isolation layer away from the substrate; wherein, The first charging probe and the first measuring probe are spaced apart from each other, one end of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the other end of the first conductive structure is electrically connected to the first conductor layer; The second charging probe and the second measuring probe are spaced apart, one end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and the other end of the second conductive structure is electrically connected to the second conductor layer.

5. The dielectric relaxation measurement structure according to claim 4, wherein: It also includes a planarization layer formed on a side of the insulating isolation layer away from the substrate and covering the first conductor layer, the dielectric insulation layer and the second conductor layer; wherein, The first charging probe, the second charging probe, the first measurement probe, and the second measurement probe are formed on a surface of the planarization layer away from the substrate; The first conductive structure penetrates the planarization layer, the top of the first conductive structure is electrically connected to the first measuring probe and the first charging probe, and the bottom of the first conductive structure is in contact with the first conductor layer; The second conductive structure penetrates the planarization layer, a top end of the second conductive structure is electrically connected to the second measuring probe and the second charging probe, and a bottom end of the second conductive structure is in contact with the second conductor layer.

6. The dielectric relaxation measurement structure according to claim 5, wherein: The first conductor layer includes a first main region and a first edge region surrounding the first main region, and in an orthographic projection on the substrate: the second conductor layer and the dielectric insulation layer are projected within the first main region; wherein, The first hollow hole is located in the first main area; In an orthographic projection on the substrate: the first conductive structure overlaps with the first edge region, and the second conductive structure is projected within the second conductor layer; The first conductive structure is disposed around the second conductive structure, and a bottom end of the first conductive structure contacts the first edge region.

7. The dielectric relaxation measurement structure according to claim 6, wherein: The first conductive structure includes a first transition portion and a first via portion. The first transition portion is located on a surface of the planarization layer away from the substrate and is electrically connected to the first measurement probe and the first charging probe. In an orthographic projection on the substrate, the first via portion is projected within the first transition portion, penetrates the planarization layer, and a top end of the first via portion contacts the first transition portion, while a bottom end of the first via portion contacts the first edge region. The second conductive structure includes a second transition portion and a second via portion. The second transition portion is located on a surface of the planarization layer away from the substrate and is electrically connected to the second measurement probe and the second charging probe. In an orthographic projection on the substrate, the second via portion is projected within the second transition portion. The second via portion penetrates the planarization layer, and a top end of the second via portion contacts the second transition portion, while a bottom end of the second via portion contacts the second conductive layer. The first transition portion is arranged around the second transition portion, and a plurality of first via portions are provided and arranged at intervals along the circumferential direction to surround the second via portion.

8. The dielectric relaxation measurement structure according to claim 7, wherein: In an orthographic projection on the substrate, the first charging probe, the second charging probe, the first measurement probe, and the second measurement probe do not overlap with the first conductor layer and the second conductor layer; The dielectric relaxation measurement structure further includes a first lead and a second lead, wherein the first lead and the second lead are formed on a surface of the planarization layer away from the substrate, the first lead and the second lead include a main segment and a branch segment, the main segment and the branch segment have a first end and a second end, and the first end of the branch segment is located between the first end and the second end of the main segment and connected to the main segment; In the first lead, a first end of a main segment contacts the first transition portion, a second end of the main segment contacts one of the first charging probe and the first measurement probe, and a second end of a branch segment contacts the other of the first charging probe and the first measurement probe. In the second lead, a first end of the main segment contacts the second transition portion, a second end of the main segment contacts one of the second charging probe and the second measurement probe, and a second end of the branch segment contacts the other of the second charging probe and the second measurement probe. The first transition portion has an avoidance opening for the main section of the second lead to pass through, and a gap is formed between the main section of the second lead and the first transition portion at the avoidance opening.

9. The dielectric relaxation measurement structure according to claim 8, wherein: The second end of the main section of the first lead is in contact with the first measuring probe, and the first charging probe is located on a side of the first measuring probe away from the first connecting portion; The second end of the main section in the second lead is in contact with the second measuring probe, and the second charging probe is located on a side of the second measuring probe away from the second connecting portion.

10. The dielectric relaxation measurement structure according to claim 6, wherein: In an orthographic projection on the substrate: the dielectric insulating layer completely overlaps with the second conductor layer, and the second conductor layer and the dielectric insulating layer include a second main area and a second edge area surrounding the second main area; wherein, The second hollow hole is located in the second main area of ​​the dielectric insulation layer; In an orthographic projection on the substrate, the second conductive structure is projected into the second main area of ​​the second conductor layer.

11. The dielectric relaxation measurement structure according to claim 10, wherein: Also included is an interlayer dielectric layer formed between the planarization layer and the insulating isolation layer; The interlayer dielectric layer covers an edge position of the first main region and covers the first edge region, and the interlayer dielectric layer has a through hole, and the through hole exposes a middle position of the first main region; The second edge region overlaps the surface of the interlayer dielectric layer away from the first conductor layer, the second main region is formed in the through hole, and in an orthographic projection on the substrate: the first hollow hole and the second hollow hole are projected into the through hole; Wherein, when the first conductive structure penetrates the planarization layer and contacts the first conductor layer, it also penetrates the interlayer dielectric layer to contact the first edge region.

12. The dielectric relaxation measurement structure according to claim 5, wherein: Also includes: a grounding probe, formed on a side of the planarization layer away from the insulating isolation layer and used for grounding; a ground shielding portion, the ground shielding portion passing through the planarization layer, a top end of the ground shielding portion being connected to the ground probe, and a bottom end of the ground shielding portion extending toward the substrate; Wherein, in an orthographic projection on the substrate: the second conductor layer is projected within or overlaps with the first conductor layer, and the ground shielding portion is projected on at least two opposite sides of the first conductor layer.

13. The dielectric relaxation measurement structure according to claim 12, wherein: The surface of the ground shielding portion close to the substrate is lower than the surface of the capacitor tube close to the substrate or is flush with the surface of the capacitor tube close to the substrate.

14. The dielectric relaxation measurement structure according to claim 12, wherein: In an orthographic projection on the substrate, the first charging probe, the first measuring probe, the second charging probe, the second measuring probe, and the first conductive layer do not overlap; A horizontal distance between the ground shield and the first conductor layer is smaller than a horizontal distance between the first charging probe, the first measuring probe, the second charging probe, the second measuring probe, and the first conductor layer.

15. The dielectric relaxation measurement structure according to claim 14, wherein: The first charging probe and the first measuring probe form a first probe group, the second charging probe and the second measuring probe form a second probe group, and the first probe group and the second probe group are arranged in a first direction; The first conductive structure and the second conductive structure are located between the first probe group and the second probe group, the surface of the first conductive structure facing the first probe group is connected to the first charging probe and the first measurement probe via a first lead, and the surface of the second conductive structure facing the second probe group is connected to the second charging probe and the second measurement probe via a second lead; The first lead and the second lead are formed on a surface of the planarization layer away from the insulating isolation layer, and a surface of the ground shield away from the substrate is flush with or higher than a surface of the first lead and the second lead close to the planarization layer; Two ground shielding parts are provided and arranged in a second direction, the first conductor layer is located between the two ground shielding parts, and the second direction intersects with the first direction; Among them, the two ground shielding parts are arranged at intervals on one side close to the first probe group to form a first avoidance gap for the first lead to pass through, and the first lead has a gap at the first avoidance gap; the two ground shielding parts are arranged at intervals on one side close to the second probe group to form a second avoidance gap for the second lead to pass through, and the second lead has a gap at the second avoidance gap; each of the ground shielding parts is connected to the ground probe through a ground lead.

16. The dielectric relaxation measurement structure according to claim 15, wherein: The ground lead is formed on a side of the planarization layer away from the insulating isolation layer; and / or A side of one of the first probe group and the second probe group away from the first conductive structure and the second conductive structure forms the ground probe.

17. The dielectric relaxation measurement structure according to claim 15, wherein: The ground shielding portion is a long strip structure extending in the first direction; or The ground shield portion includes a main shield portion extending in the first direction and sub-shield portions located at both extending ends of the main shield portion, the sub-shield portions extending in a second direction.

18. The dielectric relaxation measurement structure according to claim 4, wherein: The first measuring probe is disposed closer to the first conductive structure than the first charging probe; The second measuring probe is disposed closer to the second conductive structure than the second charging probe.

19. The dielectric relaxation measurement structure according to claim 1, wherein: The first conductor layer and the conductor sleeve are an integrally formed structure, the dielectric insulation layer and the dielectric portion are an integrally formed structure, and the second conductor layer and the conductor core are an integrally formed structure.

20. A semiconductor device, characterized in that: include: substrate; a capacitor tube formed on the substrate, the capacitor tube comprising a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extending in a direction intersecting the substrate, the conductor sleeve being at least sleeved on an outer circumference of the conductor core, and the dielectric portion being formed between the conductor sleeve and the conductor core; and A dielectric relaxation measurement structure is formed on the substrate and includes a first conductor layer, a dielectric insulation layer, a second conductor layer, a charging probe group and a measurement probe group; wherein, The first conductor layer covers and contacts the top end of the conductor sleeve, and the first conductor layer has a first hollow hole. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole. A portion of the dielectric insulation layer is formed on a side of the first conductor layer away from the substrate, and another portion is located in the first hollow hole and covers the top of the dielectric portion. The dielectric insulation layer has a second hollow hole. In an orthographic projection on the substrate, the second hollow hole is projected into the first hollow hole, and the conductor core is projected into the second hollow hole. A portion of the second conductor layer is formed on a side of the dielectric insulation layer away from the substrate, and another portion is located in the second hollow hole and in contact with the top of the conductor core; The charging probe group includes a first charging probe electrically connected to the first conductor layer and a second charging probe electrically connected to the second conductor layer, wherein the first charging probe and the second charging probe are used to conduct with a charging device to charge the capacitor tube; The measuring probe group includes a first measuring probe electrically connected to the first conductor layer and a second measuring probe electrically connected to the second conductor layer. The first measuring probe and the second measuring probe are used to be connected to the detection device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

21. A dielectric relaxation measurement system for measuring dielectric relaxation of a capacitor in a semiconductor device, wherein the semiconductor device comprises a substrate, the capacitor is formed on the substrate, the capacitor comprises a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on the outer circumference of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core; characterized in that: The dielectric relaxation measurement system comprises: control devices; A dielectric relaxation measurement structure is formed on the substrate and includes a first conductor layer, a dielectric insulation layer, a second conductor layer, a charging probe group, and a measurement probe group. The first conductor layer covers and contacts the top of the conductor sleeve. The first conductor layer has a first hollow hole. A portion of the dielectric insulation layer is formed on a side of the first conductor layer away from the substrate. Another portion of the dielectric insulation layer is located in the first hollow hole and covers the top of the dielectric portion. The dielectric insulation layer has a second hollow hole. A portion of the second conductor layer is formed on a side of the dielectric insulation layer away from the substrate. Another portion of the second conductive layer is located within the second hollow hole and contacts the top of the conductive tube core. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole, the second hollow hole is projected within the first hollow hole, and the conductive tube core is projected within the second hollow hole. The charging probe set includes a first charging probe electrically connected to the first conductive layer and a second charging probe electrically connected to the second conductive layer. The measuring probe set includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer. a charging device electrically connected to the control device, wherein the charging device can be connected to the first charging probe and the second charging probe under the control of the control device to charge the capacitor tube, and the charging device can also be disconnected from the first charging probe and the second charging probe under the control of the control device to stop charging the capacitor tube; A detection device is electrically connected to the control device. The detection device can be connected to the first measuring probe and the second measuring probe under the control of the control device when the charging device stops charging the capacitor tube to detect the dielectric relaxation of the capacitor tube.

22. The dielectric relaxation measurement system according to claim 21, wherein: The detection device includes an ammeter, which can be connected in series between the first measuring probe and the second measuring probe under the control of the control device when the charging device stops charging the capacitor tube; or The detection device includes a voltmeter and a short-circuit wire. The voltmeter can be connected in series between the first measuring probe and the second measuring probe under the action of the control device when the charging device stops charging the capacitor tube. The short-circuit wire can be short-circuited between the first charging probe and the second charging probe under the control of the control device when the charging device stops charging the capacitor tube.

23. A dielectric relaxation measurement method for measuring dielectric relaxation of a capacitor in a semiconductor device, wherein the semiconductor device comprises a substrate, the capacitor is formed on the substrate, the capacitor comprises a conductor sleeve, a conductor core, and a dielectric portion, the conductor core extends in a direction intersecting the substrate, the conductor sleeve is at least sleeved on the outer circumference of the conductor core, and the dielectric portion is formed between the conductor sleeve and the conductor core, wherein: The dielectric relaxation measurement method comprises: A dielectric relaxation measurement structure is formed on the substrate, the dielectric relaxation measurement structure comprising a first conductor layer, a dielectric insulating layer, a second conductor layer, a charging probe group, and a measurement probe group, wherein the first conductor layer covers and contacts the top of the conductor sleeve, the first conductor layer has a first hollow hole, a portion of the dielectric insulating layer is formed on a side of the first conductor layer away from the substrate, another portion of the dielectric insulating layer is located in the first hollow hole and covers the top of the dielectric portion, the dielectric insulating layer has a second hollow hole, a portion of the second conductor layer is formed on the dielectric insulating layer away from the substrate On one side of the substrate, another portion of the second conductive layer is located within the second hollow hole and contacts the top of the conductive tube core. In an orthographic projection on the substrate, the dielectric portion is projected within the first hollow hole, the second hollow hole is projected within the first hollow hole, and the conductive tube core is projected within the second hollow hole. The charging probe group includes a first charging probe electrically connected to the first conductive layer and a second charging probe electrically connected to the second conductive layer. The measuring probe group includes a first measuring probe electrically connected to the first conductive layer and a second measuring probe electrically connected to the second conductive layer. Controlling the charging device to cooperate with the first charging probe and the second charging probe to charge the capacitor tube; After the capacitor tube is fully charged, the charging device is controlled to stop charging the capacitor tube. At the same time, the detection device is controlled to cooperate with the first measuring probe and the second measuring probe to detect the dielectric relaxation of the capacitor tube.

24. The dielectric relaxation measurement method according to claim 23, wherein: The control detection device is connected with the first measuring probe and the second measuring probe to detect the dielectric relaxation of the capacitor tube, including: A control ammeter is connected in series between the first measuring probe and the second measuring probe to perform current measurement; The dielectric relaxation of the capacitor tube is characterized based on a measured current-time relationship curve.

25. The dielectric relaxation measurement method according to claim 23, wherein: The control detection device is connected with the first measuring probe and the second measuring probe to detect the dielectric relaxation of the capacitor tube, including: A control voltmeter is connected in series between the first measuring probe and the second measuring probe, and controls the first charging probe and the second charging probe to be short-circuited to perform voltage measurement; The dielectric relaxation of the capacitor is characterized based on the measured voltage change.

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