Adaptive memory access management

Abstract

Dynamic random access memory (DRAM) data can be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of the data that is the subject of an access request and a second portion of the data that is the subject of an access request can be accessed concurrently via a first pseudo channel and a second pseudo channel, respectively. In the non-broadcast mode, the data that is the subject of an access request can be accessed via a selected pseudo channel of the first pseudo channel and the second pseudo channel.

Description

Background Art

[0001] A computing device may include multiple subsystems that communicate with each other via a bus or other interconnections. Such a computing device may be, for example, a portable computing device ("PCD"), such as a laptop or palmtop computer, a cellular phone or smart phone, a portable digital assistant, a portable game console, etc. There is another type of PCD that can be used in automotive applications. The communication subsystem may be included in the same integrated circuit chip or in different chips. "System on chip" or "SoC" is an example of such a chip that integrates many components to provide system-level functions. For example, an SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processor ("NPU"). The SoC may include other processing subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, etc. Various processors may be used as memory clients to initiate memory transactions with the memory subsystem. The main memory or system memory in PCDs and other computing devices typically includes dynamic random access memory ("DRAM").

[0002] As DRAM technology has evolved, the memory arrays in successive generations of DRAM have been organized in increasingly complex and flexible ways designed to provide higher performance than previous generations. For example, memory arrays have been organized into banks, and banks have been organized into groups of banks, and so on. In addition, the way in which memory buses are organized into channels has continued to evolve as the width of the memory bus has increased.

[0003] Memory controller architectures may attempt to exploit these more complex DRAM organization features to improve performance of memory clients. However, a computing device may have several memory clients (e.g., CPU, GPU, NPU, etc.), and not all memory clients may benefit equally from a particular memory controller architecture. Summary of the invention

[0004] Systems, methods, computer-readable media, and other examples for accessing data in a dynamic random access memory (DRAM) are disclosed. Data can be accessed in a broadcast mode or a non-broadcast mode by selecting a memory controller.

[0005] An exemplary method for accessing data in a DRAM may include providing, by a memory controller, a command having a selectable pseudo-channel broadcast mode indication to the DRAM. The exemplary method may also include: when the state of the pseudo-channel broadcast mode indication indicates the broadcast mode, the memory controller concurrently accesses a first portion of the requested data in the DRAM via a first pseudo-channel in response to the command, and accesses a second portion of the requested data from the DRAM via a second pseudo-channel. The exemplary method may also include, when the state of the pseudo-channel broadcast mode indication indicates the non-broadcast mode, the memory controller accesses the requested data in the DRAM via a selected pseudo-channel of the first pseudo-channel and the second pseudo-channel in response to the command.

[0006] An exemplary system for accessing data in a DRAM may include a memory controller and a physical interface coupled to the memory controller and the DRAM. The memory controller may be configured to provide a command with a selectable pseudo-channel broadcast mode indication to the DRAM. The memory controller may also be configured to concurrently access a first portion of the requested data in the DRAM via a first pseudo-channel and access a second portion of the requested data from the DRAM via a second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a broadcast mode. The memory controller may also be configured to access the requested data in the DRAM via a selected pseudo-channel of the first pseudo-channel and the second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a non-broadcast mode.

[0007] Another exemplary system for accessing data in a DRAM may include a component for providing a command with a selectable pseudo-channel broadcast mode indication to the DRAM. The exemplary system may also include a component for concurrently accessing a first portion of requested data in the DRAM via a first pseudo-channel and accessing a second portion of the requested data from the DRAM via a second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a broadcast mode. The exemplary system may also include a component for accessing the requested data in the DRAM via a selected pseudo-channel of the first pseudo-channel and the second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a non-broadcast mode.

[0008] An exemplary DRAM may include multiple DRAM storage arrays and a DRAM command interface. The DRAM command interface may be configured to receive a command with a selectable pseudo-channel broadcast mode indication. The DRAM command interface may also be configured to concurrently access a first portion of requested data in the DRAM storage array via a first pseudo-channel and access a second portion of requested data in the DRAM storage array via a second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a broadcast mode. The DRAM command interface may also be configured to access requested data in the DRAM storage array via a selected pseudo-channel of the first pseudo-channel and the second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates a non-broadcast mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the accompanying drawings, unless otherwise specified, like reference numerals refer to like parts in the various views. For reference numerals with letter character designations (such as "102A" or "102B"), the letter character designations may distinguish between two similar parts or elements in the same figure. When a reference numeral is intended to encompass all parts having the same reference numeral in all figures, the letter character designation of the reference numeral may be omitted.

[0010] Figure 1 is a block diagram illustrating a system for accessing data in a DRAM according to an exemplary embodiment.

[0011] Figure 2A is a diagram showing a method according to an exemplary embodiment Figure 1 A timing diagram of an example of the operation of the system.

[0012] Figure 2B yes Figure 2A Continuation of the timing diagram.

[0013] Figure 3A is a diagram showing a method according to an exemplary embodiment Figure 1 A timing diagram of another operation example of the system.

[0014] Figure 3B yes Figure 3A Continuation of the timing diagram.

[0015] Figure 4A is a diagram showing a method according to an exemplary embodiment Figure 1 A timing diagram of yet another example of the operation of the system.

[0016] Figure 4B yes Figure 4A Continuation of the timing diagram.

[0017] Figure 5 is a flow chart illustrating a method for accessing data in a DRAM according to an exemplary embodiment.

[0018] Figure 6 is a flow chart illustrating a method for issuing a memory command based on a memory access request according to an exemplary embodiment.

[0019] Figure 7 is a block diagram of a memory controller according to an exemplary embodiment.

[0020] Figure 8 is a block diagram of a computing device according to an exemplary embodiment.

[0021] Fig. 9 is a table illustrating aspects of selecting a broadcast memory access scheme or a non-broadcast memory access scheme based on client type. DETAILED DESCRIPTION

[0022] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "illustrative" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] like Figure 1 As shown, system 100 may include a system on a chip ("SoC") 102 coupled to at least one dynamic random access memory ("DRAM") device 104 via a memory bus 106. Although not shown for clarity, system 100 may be included in a computing device, which may be of any type.

[0024] DRAM device 104 may be double data rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to as "DDR" for brevity. As DDR technology develops, DDR versions such as fourth generation low power DDR ("LPDDR4") and fifth generation low power DDR ("LPDDR5") have been developed.

[0025] The DRAM device 104 may include two memory array groups 108: a first memory array group 108A and a second memory array group 108B. Although not shown for clarity, each memory array group 108 may be organized in the form of eight memory bank groups ("BGs"), and each of the eight memory bank BGs may be organized in the form of two memory banks. Therefore, in the illustrated embodiment, each memory array group 108 includes 16 memory banks.

[0026] The first memory array group 108A may be coupled to a first input / output ("I / O") interface 110A of the DRAM device 104, and the second memory array group 108B may be coupled to a second I / O interface 110B of the DRAM device 104. The number of data lines coupling each memory array group 108 to its corresponding I / O interface 110A or 110B may be, for example, 256 bits.

[0027] In the illustrated embodiment, the memory bus 106 may be 32 bits wide (i.e., include 32 data lines). In the illustrated embodiment, the data lines may be organized in the form of 16 low-order bits (i.e., two low-order data bytes) and 16 high-order bits (e.g., two high-order data bytes). Figure 1 In addition to the data lines, the memory bus 106 may also include a first read strobe signal associated with the low-order data byte DQ[0:15] and a second read strobe signal associated with the high-order data byte DQ[16:31]. The first read strobe signal and the second read strobe signal may be in the form of differential signals (i.e., a pair of true and complement signals), and may be in the form of differential signals. Figure 1 The memory bus 106 may also include a first data clock signal associated with the low-order data byte DQ[0:15] and a second data clock signal associated with the high-order data byte QB[16:31]. The first data clock signal and the second data clock signal may be in the form of differential signals and may be in the form of differential signals. Figure 1 The memory bus 106 may further include a first data mask inversion signal ("DMI0") associated with the low-order data bytes DQ[0:15] and a second data mask inversion signal ("DMI1") associated with the high-order data bytes QB[16:31].

[0028] The low-order data byte signal DQ[0:15], the first data mask inversion signal DMI0, the first data clock signal (WCK0_t, WCK0_c) and the first read select signal (RDQS0_t, RDQS0_c) may be coupled to the first I / O interface 110A. The high-order data byte signal DQ[16:31], the second data mask inversion signal DMI1, the second digital clock signal (WCK1_t, WCK1_c) and the second read select signal (RDQS1_t, RDQS1_c) may be coupled to the second I / O interface 110B.

[0029] Another portion of the memory bus 106 may include control signals. The control signals may include a command and address ("CA") bus. The CA bus may be of any size and may be Figure 1 The control signal may also include a clock signal associated with the CA bus. The clock signal associated with the CA bus may be in the form of a differential signal and may be Figure 1 The control signals may also include a chip select (“CS”) signal and a reset (“RESET”) signal. The DRAM device 104 may include a command / address and clock interface 112 configured to receive the control signal portion of the memory bus 106.

[0030] Conceptually, the memory bus 106 can be configured as two pseudo channels: a first pseudo channel 114A and a second pseudo channel 114B. The first pseudo channel 114A (also referred to as "PC0") can include a low-order data byte signal DQ[0:15], a first data mask inversion signal DMI0, a first data clock signal (WCK0_t, WCK0_c), a first read select signal (RDQS0_t, RDQS0_c), a clock signal associated with the CA bus (CK_t, CK_c), a chip select signal, and a reset signal. The second pseudo channel 114B (also referred to as "PC1") can include a high-order data byte signal DQ[16:31], a second data mask inversion signal DMI1, a second digital clock signal (WCK1_t, WCK1_c), a second read select signal (RDQS1_t, RDQS1_c), a clock signal associated with the CA bus (CK_t, CK_c), a chip select signal, and a reset signal. Note that the control signal portion of the memory bus (including the clock signals (CK_t, CK_c), chip select signals, and reset signals associated with the CA bus) is shared by or is common to the first pseudo channel 114A and the second pseudo channel 114B. The first pseudo channel 114A and the second pseudo channel 114B are referred to herein as "pseudo" channels rather than actual channels because they share their control signals.

[0031] SoC 102 may include a physical memory interface or "PHY" 116 coupled to memory bus 106 and a memory controller 118 coupled to PHY 116. Memory controller 118 may communicate with any of various processing engines 122, such as multi-core central processing unit ("CPU") 121A, graphics processing unit ("GPU") and multimedia engine 122B, neural processing unit ("NPU") 122C, etc., through a bus-like interconnect 120 (sometimes referred to as a fabric). Any of processing engines 122 may act as a client device with respect to DRAM device 104 to initiate memory access operations with DRAM device 104 through memory controller 118. Although in Figure 1 In the illustrated embodiment, there are three client devices, but in other embodiments there may be any number of client devices.

[0032] exist Figure 2A-2B In the timing diagram 200, the system 100 ( Figure 1 ) operation. Also refer to Figure 1 , the exemplary operation (timing diagram 200) shows that the memory controller 118 concurrently receives (via PHY 116) a first portion of some requested data from the DRAM (i.e., DRAM device 104) via the first pseudo channel 114A, and receives a second portion of the requested data from the DRAM via the second pseudo channel 114B. This operation shown in the timing diagram 200 is referred to herein as a "broadcast" mode. As described below, the system 100 can selectively perform memory read operations in a broadcast mode or a non-broadcast mode. The memory controller 118 can initiate data access in response to a request received from a client device, as further described below.

[0033] like Figure 2A As shown, before time T0 and through time T1, the memory controller 118 may issue a CAS command that includes a pseudo channel broadcast ("PCB") mode indication set to indicate a state of a broadcast mode. For example, a predetermined bit of the CAS command may be a PCB mode bit set to a value of "1" (i.e., PCB=1) to indicate a broadcast mode. Then, before time T2 and through time T3, the memory controller 118 may issue a read command. The read command may also include a PCB mode bit set to a value of "1" (i.e., PCB=1) to indicate a broadcast mode. For simplicity, in Figure 2A In the , the notation "CAS PCB = 1" indicates a CAS command, and "Read PCB = 1" indicates a read command, but it should be understood that the command may include other bits. For example, the write clock to clock synchronization option bit may be asserted: WS_RD = 1.

[0034] The read command may include an indication of the amount of data requested, such as Figure 2A-2B 64 bytes in the example shown. The read command may also include a burst length ("BL") indication, such as Figure 2A-2B The burst length in the example shown is 16. As will be appreciated by one of ordinary skill in the art, the chip select signal may be asserted during CAS and read commands. For simplicity, other aspects of the timing diagram 200 and the timing of the memory controller 118 and the DRAM device 104 ( Figure 1 ) and the like (which are similarly well understood by those of ordinary skill in the art) are not described here.

[0035] continue Figure 2B In response to the read command, after a delay or time interval starting at time T3, the first 32-byte portion of the requested 64-byte data can arrive from the DRAM (DRAM device 104) to the memory bus 106 ( Figure 1 ), i.e., DQ[0:15]. This time interval may be equal to the read delay ("RL") starting at time T3 plus four cycles of the clock signal (WCK0_t, CK_c) or the read select signal (RDQS0_t, RDQS0_c). In the notation where "nCK" represents "number of clock cycles", this time interval may be represented as RL+4nCK, i.e., RL plus four clock cycles. Similarly, in response to the read command, after the same delay or time interval RL+4nCK starting at time T3, the second 32-byte portion of the requested 64-byte data may arrive from the DRAM to the second pseudo channel 114B portion of the memory bus 106, i.e., DQ[16:31]. That is, when a read operation is performed in broadcast mode, the first and second portions of the requested data volume arrive concurrently with each other at the first pseudo channel 114A and the second pseudo channel 114B, respectively, after the time interval RL+4nCK. Although not shown in the timing diagram 200 , the memory controller 118 subsequently transmits the requested data back to the requesting client device.

[0036] exist Figure 3A-3B In the timing diagram 300, the system 100 ( Figure 1 ) operation example. Figure 1 , the exemplary operation (timing diagram 300) shows that the memory controller 118 sequentially receives (via PHY 116) a first portion of some requested data from the DRAM (i.e., DRAM device 104) via the first pseudo channel 114A and receives a second portion of the requested data from the DRAM via the second pseudo channel 114B. The timing diagram 300 shows an example of the system 100 operating in a "non-broadcast" mode.

[0037] like Figure 3AAs shown, before time T0 and through time T1, the memory controller 118 may issue a first CAS command, which includes a PCB mode indication set to indicate a state of non-broadcast mode, and a pseudo channel selection indication ("PCS") set to indicate the state of a selected pseudo channel in the first pseudo channel 114A (PC0) and the second pseudo channel 114B (PC1). In the example shown, the above-mentioned PCB mode bit may be set to a value of "0" (i.e., PCB=0) to indicate the non-broadcast mode. In the example shown, another predetermined bit of the first CAS command may be a PCS bit set to a value of "0" (i.e., PCS=0) to indicate the selection of the first pseudo channel 114A (PC0). Then, before time T2 and through time T3, the memory controller 118 may issue a first read command. The first read command may also include a PCB mode bit set to a value of "0" to indicate a state of non-broadcast mode, and a PCS bit set to a value of "0" to indicate the selection of the first pseudo channel 114A (PC0). For simplicity, in Figure 3A In the example, the symbol "CAS PC0" indicates the first CAS command, and "Read" indicates the first read command, but it should be understood that in this example, the first CAS command and the first read command include PCB=0 and PCS=0. The first CAS command may also include similar Figure 3A Other bits indicated in, such as WS_RD=1.

[0038] Before time T4 and through time T5, the memory controller 118 may issue a second CAS command, which includes a PCB mode indication set to a state indicating a non-broadcast mode, and a PCS indication set to a state indicating a selection of the second pseudo channel 114B (PC1). That is, in the example shown: PCB=0 and PCS=1. Then, before time T6 and through time T7, the memory controller 118 may issue a second read command. The second read command may also include a PCB mode bit set to a value of "0" to indicate a non-broadcast mode, and a PCS bit set to a value of "0" to indicate a selection of the first pseudo channel 114A (PC0). For simplicity, in Figure 3A In the example, the symbol "CAS PC1" indicates the second CAS command, and "Read" indicates the second read command, but it should be understood that in this example, the second CAS command and the second read command include PCB=0 and PCS=1. The second CAS command may also include similar Figure 3A Other bits indicated in, such as WS_RD=1.

[0039] exist Figure 3A-3BIn the example shown, each of the first read command and the second read command may also include an indication of the amount of requested data, for example, 32 bytes for a total of 64 bytes of requested data. Figure 3A-3B In the example shown, the read command may also include a BL indication of 16. For simplicity, other aspects of the timing diagram 300 and the memory controller 118 and DRAM device 104 ( Figure 1 ) and the like (which are well understood by those of ordinary skill in the art) are not described here.

[0040] exist Figure 3B Continuing in response to the first read command, after a delay or time interval ( Figure 3A ), the first 32-byte portion of the requested 64-byte data may arrive from the DRAM to the memory bus 106 ( Figure 1 Similarly, in response to the second read command, after another delay or time interval starting at time T7, the second 32-byte portion of the requested 64-byte data may arrive from the DRAM at the second pseudo channel 114B portion of the memory bus 106, i.e., DQ[16:31]( Figure 3A ). When a read operation is performed in non-broadcast mode, the first and second parts of the requested data volume arrive at the first pseudo channel 114A (PC0) and the second pseudo channel 114B (PC1) in sequence in response to the first read command and the second read command, respectively. That is, when a read operation is performed in non-broadcast mode, the first part of the requested data arrives at DQ[0:15] first, and the second part of the requested data arrives at DQ[15:31] after the first part arrives at DQ[0:15]. Figure 3A-3B In the example shown, the total delay or time interval from the first read command to the arrival of all 64 bytes of the requested data is RL+8 nCK. Although not shown in the timing diagram 300, the memory controller 118 subsequently transmits the requested data back to the requesting client device.

[0041] exist Figure 4A-4B In the timing diagram 400, the system 100 ( Figure 1 ) operation example. Figure 1 , the exemplary operation (timing diagram 400) shows that the memory controller 118 sequentially receives (via PHY 116) a first portion of some requested data from the DRAM (i.e., DRAM device 104) via the first pseudo channel 114A and receives a second portion of the requested data from the DRAM via the second pseudo channel 114B. The timing diagram 400 shows another example of the system 100 operating in the "non-broadcast" mode.

[0042] like Figure 4A As shown, before time T0 and through time T1, the memory controller 118 may issue a first CAS command, which includes a PCB mode indication set to indicate a state of non-broadcast mode, and a PCS indication set to indicate a state of selection of the first pseudo channel 114A (PC0). That is, in the example shown: PCB=0 and PCS=0. Then, before time T2 and through time T3, the memory controller 118 may issue a first read command. The first read command may also include a PCB mode bit set to a value of "0" to indicate a non-broadcast mode, and a PCS bit set to a value of "0" to indicate selection of the first pseudo channel 114A (PC0). For simplicity, in Figure 4A In the example, the symbol "CASPC0" indicates the first CAS command, and "Read" indicates the first read command, but it should be understood that in this example, the first CAS command and the first read command include PCB=0 and PCS=0. The first CAS command may also include similar Figure 4A Other bits indicated in, such as WS_RD=1.

[0043] Before time T4 and through time T5, the memory controller 118 may issue a second CAS command, which includes a PCB mode indication set to a state indicating a non-broadcast mode, and a PCS indication set to a state indicating a selection of the second pseudo channel 114B (PC1). That is, in the example shown: PCB=0 and PCS=1. Then, before time T6 and through time T7, the memory controller 118 may issue a second read command. The second read command may also include a PCB mode bit set to a value of "0" to indicate a non-broadcast mode, and a PCS bit set to a value of "0" to indicate a selection of the first pseudo channel 114A (PC0). For simplicity, in Figure 4A In the example, the symbol "CAS PC1" indicates the second CAS command, and "Read" indicates the second read command, but it should be understood that in this example, the second CAS command and the second read command include PCB=0 and PCS=1. The second CAS command may also include similar Figure 4A Other bits indicated in, such as WS_RD=1.

[0044] Each of the first read command and the second read command may also include an indication of the amount of requested data, e.g. Figure 4A-4B In the example shown, this is 64 bytes (per read command). Figure 4A-4BIn the example shown, the read command may also include a BL indication of 32. For simplicity, other aspects of the timing diagram 400 and the memory controller 118 and DRAM device 104 ( Figure 1 ) and the like (which are well understood by those of ordinary skill in the art) are not described here.

[0045] exist Figure 4B Continuing in FIG. 1 , in response to the first read command, after a delay or time interval starting from time T3, the first 32-byte portion of the requested data may arrive from the DRAM at the first pseudo channel 114A (PC0), i.e., DQ[0:15] ( Figure 4A Similarly, in response to the second read command, after another delay or time interval starting from time T7, the second 32-byte portion of the requested data may arrive from the DRAM at the second pseudo channel 114B (PC1), i.e., DQ[16:31] ( Figure 4A ). Then, again in response to the first read command, the third 32-byte portion of the request data can arrive from the DRAM to the first pseudo channel 114A (PC0), i.e., DQ[0:15]. And again in response to the second read command, the fourth 32-byte portion of the request data can arrive from the DRAM to the second first pseudo channel 114B (PC1), i.e., DQ[16:31]. That is, the first 64 bytes of the request data arrive at DQ[0:15], and the second 64 bytes of the request data arrive at DQ[15:31]. In this example, the delay or time interval from the first read command to the arrival of the 64 bytes of the request data on DQ[0:15] is RL+12nCK. Similarly, in this example, the delay or time interval from the second read command to the arrival of the 64 bytes of the request data on DQ[16:31] is RL+12nCK. Although not shown in the timing diagram 300, the memory controller 118 then transmits the request data back to the requesting client device.

[0046] It should be understood that the above timing diagram 200 ( Figure 2A-2B )、300( Figure 3A-3B ) and 400( Figure 4A-4B ) described in the system 100 ( Figure 1) are not the only examples of operation of system 100. Additional examples of operation of system 100 will be readily apparent to one of ordinary skill in the art in view of the teachings herein. For example, although the above-described examples of operation of system 100 relate to read accesses, there may be additional examples related to write accesses. Furthermore, it should be understood that while timing diagrams 200-400 illustrate some important aspects of the operation of system 100, there may also be other aspects not shown in timing diagrams 200-400, such as aspects that are well known to one of ordinary skill in the art. For example, as one of ordinary skill in the art will appreciate, the memory controller may issue various other commands associated with a DRAM access sequence, such as activate ("ACT"), precharge ("PRE"), and the like.

[0047] exist Figure 5 In the method 500 for reading data from a DRAM, a flowchart is shown. As shown in box 502, a memory controller may provide a read command with a selectable PCB mode indication to the DRAM. The first read command is associated with a request for data (e.g., by a client device). As shown in box 504, in response to the read command, when the state of the PCB mode indication indicates a broadcast mode, the memory controller may concurrently receive a first portion and a second portion of the requested data from the DRAM via a first pseudo channel and a second pseudo channel, respectively. As shown in box 504, in response to the read command, when the state of the PCB mode indication indicates a non-broadcast mode, the memory controller may receive the requested data from the DRAM via a selected pseudo channel of the first pseudo channel and the second pseudo channel. The read command may include a PCS indication to indicate which of the first pseudo channel and the second pseudo channel is selected.

[0048] exist Figure 6 In the embodiment of the present invention, a method 600 for controlling a memory access request is shown in the form of a flow chart. As shown in block 602, a memory controller may receive a memory access request from a client device. The memory access request may include a target address and may also include other information, such as a flag, an access priority indication, etc.

[0049] As shown in block 604, the memory controller may determine whether the received memory access request is associated with a broadcast mode. Whether a memory access request is associated with a broadcast mode may be determined in any manner. In an exemplary embodiment, a memory access request having a target address within a first range may be associated with a broadcast mode. That is, if the target address is within the first range, the memory access request is associated with the broadcast mode. However, if the target address is not within the first range, the memory access request is not associated with the broadcast mode (and therefore may be associated with a non-broadcast mode). Different types of client devices may issue memory access requests with target addresses within different address ranges based on the client type. For example, a CPU may use a target address within a first range, while a GPU may use a destination address within a range other than the first range (i.e., the second range), and so on. In another exemplary embodiment, a memory access request may include a flag. If the memory access request includes a flag, the memory access request is associated with a broadcast mode. However, if the memory access request does not include a flag, the memory access request is not associated with the broadcast mode (and therefore may be associated with a non-broadcast mode). Different client devices may include or not include the flag in their memory access requests. In yet another exemplary embodiment, whether a memory access request is associated with a broadcast mode may be determined based on a memory access priority associated with the requesting client device.

[0050] As shown in box 606, if the memory controller determines that the memory access request is associated with a broadcast mode, the memory controller may set the PCB mode indication (e.g., set to "1") to indicate the broadcast mode in any of the various commands that the memory controller may issue in association with the memory access request. For example, such commands may include activate ("ACT"), write ("WRITE"), read ("READ"), and precharge ("PRE"), among others. As shown in box 608, if the memory controller determines that the memory access request is not associated with a broadcast mode, the memory controller may set the PCB mode indication (e.g., set to "0") to indicate a non-broadcast mode in any such command. As shown in box 610, the memory controller may cause the memory access operation to be performed through a physical interface or PHY that is coupled to the DRAM via a memory bus.

[0051] like Figure 7As shown, the memory controller 700 may include a first DRAM read data first-in-first-out ("FIFO") buffer 702, a second DRAM read data FIFO buffer 704, a first interleaved storage buffer 706, a second interleaved storage buffer 708, a data processor 710, a client read data buffer 712, a DRAM command queue 714, a read data pending command queue 716, and a client read command buffer 718. The memory controller 700 may be the memory controller 118 ( Figure 1 ) example. It should be understood that the memory controller 700 Figure 7 The foregoing elements are shown in conceptual form, and may be configured in operation by control logic (not shown), for example, by operation of one or more processors (such as configured by software or firmware), by operation of one or more finite state machines, or by operation of any other type of control logic. Figure 7 Elements of the memory controller 700 that are related to other memory controller functions other than those described herein are also not shown. For example, in addition to the memory controller functions described herein, the memory controller 700 can be configured to generate command sequences in response to memory access requests received from client devices or in response to other conditions. For example, such other conditions can include requiring that the DRAM be periodically refreshed, and the memory controller 700 can be configured to generate refresh-related commands.

[0052] DRAM command queue 714 can be configured to receive commands via PHY ( Figure 7 The memory controller 700 may be configured to temporarily store the read data received from the DRAM via the first pseudo channel PC0. The second DRAM read data FIFO buffer 704 may be configured to store the read data received from the DRAM via the second pseudo channel PC1.

[0053] In an operation example where each of two consecutive read commands requests 32 bytes of data, each of the first DRAM read data FIFO buffer 702 and the second DRAM read data FIFO buffer 704 can be configured to receive 128 bits of read data from the PHY in response to each read command. Each of the first DRAM read data FIFO buffer 702 and the second DRAM read data FIFO buffer 704 can be configured to receive 256 bits of read data in two memory controller clock cycles. The first interleaved storage buffer 706 and the second interleaved storage buffer 708 can be configured to store data output by the first DRAM read data FIFO buffer 702 and the second DRAM read data FIFO buffer 704, respectively. In this example (of a 32-byte request), during the first memory controller clock cycle, the first interleaved storage buffer 706 can send 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712 via the data processor 710. In this example, during the second memory controller clock cycle, the first interleaved storage buffer 706 may send another 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712 via the data processor 710. Also, in this example, during the third memory controller clock cycle, the second interleaved storage buffer 708 may send 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client read data buffer 712 via the data processor 710. Also, in this example, during the fourth memory controller clock cycle, the second interleaved storage buffer 708 may send another 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client read data buffer 712 via the data processor 710. Thus, in this example (of a 32-byte request), in the first two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the first pseudo channel PC0, and in the next two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the second pseudo channel PC1. That is, in the example where data is received in response to a 32-byte request, the client read data buffer 712 receives 32 bytes of read data from each of the first pseudo channel PC0 and the second pseudo channel PC1 in four memory controller clock cycles.

[0054] When the read data is stored in the client read data buffer 712, the read data pending command queue 716 can provide information identifying the read command associated with the read data to the client read command buffer 718. The client read data buffer 712 and the client read command buffer 718 are configured to send the received read data together with the information identifying the associated command to the requesting client. Each read access request received from the client may include information identifying the requesting client, which may be referred to as a "client ID". Based on the client ID, the read data and the information identifying the command may be sent together or otherwise associated with each other to the requesting client. As described above, each command may include a PCB mode indication to indicate whether the DRAM should provide the request data to the memory controller 700 in a broadcast mode or in a non-broadcast mode. The read data pending command queue 716 may use the PCB mode indication to control the interleaved storage buffers 706 and 708.

[0055] In another example of operation, where a read command requests 64 bytes of data, each of the first DRAM read data FIFO buffer 702 and the second DRAM read data FIFO buffer 704 can be configured to receive 128 bits of read data from the PHY in response to each read command, as described in the 32-byte request example above. Each of the first DRAM read data FIFO buffer 702 and the second DRAM read data FIFO buffer 704 can be configured to receive 256 bits of read data in two memory controller clock cycles, as described in the 32-byte request example above. However, in this example (of a 64-byte request): during a first memory controller clock cycle, the first interleaved storage buffer 706 may send 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712; during a second memory controller clock cycle, the first interleaved storage buffer 706 may send another 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712; during a third memory controller clock cycle, the second interleaved storage buffer 708 may send 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client read data buffer 712; during a fourth memory controller clock cycle, the second interleaved storage buffer 708 may send another 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client via the data processor 710 read data buffer 712; during the fifth memory controller clock cycle, the first interleaved storage buffer 706 can send an additional 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712; during the sixth memory controller clock cycle, the first interleaved storage buffer 706 can send an additional 128 bits of data received from the DRAM on the first pseudo channel PC0 to the client read data buffer 712; during the seventh memory controller clock cycle, the second interleaved storage buffer 708 can send an additional 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client read data buffer 712; and during the eighth memory controller clock cycle, the second interleaved storage buffer 708 can send an additional 128 bits of data received from the DRAM on the second pseudo channel PC1 to the client read data buffer 712.

[0056] Thus, in this example (of a 64-byte request): in the first two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the first pseudo channel PC0; in the next two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the second pseudo channel PC1; in the next two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the first pseudo channel PC0; and in the next two memory controller clock cycles, the client read data buffer 712 receives 32 bytes of data received from the DRAM on the second pseudo channel PC1. That is, in the example in which data is received in response to a 64-byte request, in eight memory controller clock cycles, the client read data buffer 712 receives 64 bytes of read data from each of the first pseudo channel PC0 and the second pseudo channel PC1.

[0057] exist Figure 8 In FIG. 8 , an example of a portable computing device (“PCD”) 800 is shown in which exemplary embodiments of systems, methods, computer-readable media, and other examples of accessing data in DRAM may be provided. For clarity, some data buses, clock signals, power supply voltages, etc. are not shown in FIG. Figure 8 Not shown in FIG.

[0058] PCD 800 may include SoC 802. SoC 802 may include CPU 804, NPU 805, GPU 806, DSP 807, analog signal processor 808 or other processors. CPU 804 may include one or more CPU cores, such as a first CPU core 804A, a second CPU core 804B, and so on, up to an Nth CPU core 804N.

[0059] The display controller 810 and the touch screen controller 812 can be coupled to the CPU 804. A touch screen display 814 external to the SoC 802 can be coupled to the display controller 810 and the touch screen controller 812. The PCD 800 can also include a video decoder 816 coupled to the CPU 804. A video amplifier 818 can be coupled to the video decoder 816 and the touch screen display 814. A video port 820 can be coupled to the video amplifier 818. A universal serial bus (“USB”) controller 822 can also be coupled to the CPU 804, and a USB port 824 can be coupled to the USB controller 822. A subscriber identity module (“SIM”) card 826 can also be coupled to the CPU 804.

[0060] One or more memories may be coupled to CPU 804. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 828 and DRAM 830 and 831. Such memory may be external to SoC 802, such as DRAM 830, or internal to SoC 802, such as DRAM 831. A DRAM controller 832 coupled to CPU 804 may control writing data to and reading data from DRAM 830 and 831. DRAM controller 832 may be the DRAM controller 118 (described above). Figure 1 ) or 700( Figure 7 ) example.

[0061] A stereo audio CODEC 834 may be coupled to the analog signal processor 808. In addition, an audio amplifier 836 may be coupled to the stereo audio CODEC 834. A first stereo speaker 838 and a second stereo speaker 840 may be coupled to the audio amplifier 836, respectively. In addition, a microphone amplifier 842 may be coupled to the stereo audio CODEC 834, and a microphone 844 may be coupled to the microphone amplifier 842. A frequency modulation ("FM") radio tuner 846 may be coupled to the stereo audio CODEC 834. An FM antenna 848 may be coupled to the FM radio tuner 846. In addition, a stereo headset 850 may be coupled to the stereo audio CODEC 834. Other devices that may be coupled to the CPU 804 include one or more digital (e.g., CCD or CMOS) cameras 852.

[0062] A modem or RF transceiver 854 can be coupled to the analog signal processor 808 and the CPU 804. An RF switch 856 can be coupled to the RF transceiver 854 and the RF antenna 858. In addition, a keypad 860, a mono headset with a microphone 862, and a vibrator device 864 can be coupled to the analog signal processor 808.

[0063] SoC 802 may have one or more internal or on-chip thermal sensors 870A and may be coupled to one or more external or off-chip thermal sensors 870B. An analog-to-digital converter ("ADC") controller 872 may convert the voltage drop generated by thermal sensors 870A and 870B into a digital signal. Power supply 874 and PMIC 876 may provide power to SoC 802.

[0064] PCD 800 is just one example of a device or system in which exemplary embodiments of systems, methods, computer-readable media, and other embodiments for accessing data in DRAM may be provided. Other examples may include other types of computing devices or computing systems, such as those used in data centers, automobiles, and other environments.

[0065] The firmware or software may be stored in any of the above-described memories, such as DRAM 830 or 831, SRAM 828, etc., or may be stored in local memory that is directly accessible by the processor hardware on which the software or firmware is executed. The execution of such firmware or software may control aspects of any of the above-described methods, or configure aspects of any of the above-described systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in the patent dictionary.

[0066] exist Fig. 9 , table 900 shows that the memory controller can adopt different memory access schemes based on the client device type. For example, the memory controller can adopt the broadcast memory access scheme shown in the first column of table 900 in response to a read request received from a latency-sensitive client, and can adopt the non-broadcast memory access scheme shown in the second column of table 900 in response to a read request received from a bandwidth-sensitive client. Examples of latency-sensitive clients can include CPUs, modems, or similar clients. Examples of memory bandwidth-sensitive clients can include GPUs, NPUs, or similar clients.

[0067] As shown in the first column of Table 900, when the broadcast memory access scheme is adopted, the memory controller can access the DRAM as if the DRAM is organized in the form of 8 memory bank groups, each memory bank group includes two memory banks. The latency of accessing 32 bytes of data using the broadcast memory access scheme is RL+4nCK. The latency of accessing 64 bytes of data using the broadcast memory access scheme (i.e., BL=16) is also RL+4nCK. The latency of accessing 128 bytes of data using the broadcast memory access scheme (BL=32) is RL+12nCK.

[0068] As shown in the second column of table 900, when a non-broadcast memory access scheme is adopted, the memory controller can access the DRAM as if the DRAM is organized in the form of 16 memory bank groups, each memory bank group including two memory banks, even though the DRAM can be as described above with respect to Figure 1The memory arrays are physically organized as described (i.e., two memory array groups, each memory array group is organized in the form of eight memory bank groups, each memory bank group includes two memory banks). The latency for accessing 32 bytes of data using the non-broadcast access scheme is RL+4nCK. The latency for accessing 64 bytes of data using the non-broadcast memory access scheme is RL+12nCK. The latency for accessing 128 bytes of data using the non-broadcast memory access scheme is RL+16nCK if performed as two consecutive reads in different memory bank groups (BL=32), or RL+28nCK if performed as two consecutive reads in the same memory bank group (BL=32).

[0069] Alternative embodiments will become apparent to those skilled in the art to which the invention pertains.Thus, while selected aspects have been shown and described in detail, it will be appreciated that various alterations and modifications may be made thereto.

[0070] Implementation examples are described in the following numbered clauses:

[0071] 1. A method for accessing data in a dynamic random access memory (DRAM), comprising:

[0072] providing, by a memory controller, to the DRAM a command with a selectable pseudo channel broadcast mode indication, the command being associated with the requested data;

[0073] When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, the memory controller concurrently accesses a first portion of the requested data in the DRAM via a first pseudo channel and accesses a second portion of the requested data in the DRAM via a second pseudo channel; and

[0074] When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, the requested data in the DRAM is accessed by the memory controller via a selected one of the first pseudo channel and the second pseudo channel in response to the command.

[0075] 2. The method of claim 1, wherein the DRAM is a low power double data rate (LPDDR).

[0076] 3. The method according to claim 1, wherein:

[0077] The command has a pseudo channel selection indication;

[0078] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and

[0079] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

[0080] 4. The method of claim 1 , wherein providing the command comprises:

[0081] receiving a memory access request from a client device;

[0082] determining whether the memory access request is associated with the broadcast mode;

[0083] When the memory access request is associated with the broadcast mode, setting the state of the pseudo channel broadcast mode indication to indicate the broadcast mode; and

[0084] When the memory access request is not associated with the broadcast mode, the state of the pseudo channel broadcast mode indication is set to indicate the non-broadcast mode.

[0085] 5. A method according to claim 4, wherein whether the memory access request is associated with the broadcast mode is determined based on at least one of: a target address included in the memory access request; a flag included in the memory access request; and a priority associated with the memory access request.

[0086] 6 . The method of claim 1 , wherein providing the command comprises providing the command to the DRAM via a command bus common to the first pseudo channel and the second pseudo channel.

[0087] 7. The method of claim 6 , wherein concurrently accessing the first portion of the requested data via the first pseudo channel and accessing the second portion of the requested data via the second pseudo channel comprises: accessing the first portion of the requested data from a first storage array group via a first portion of a data bus, and accessing the second portion of the requested data in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group comprising a plurality of memory bank groups, each memory bank group comprising a plurality of memory banks.

[0088] 8 . The method of claim 7 , wherein the plurality of memory bank groups consists of eight memory bank groups, and the plurality of memory banks consists of two memory banks.

[0089] 9. The method of claim 1, further comprising returning the request data along with information identifying the command to a requesting host device.

[0090] 10. A system for accessing data in a dynamic random access memory (DRAM), comprising:

[0091] a physical interface coupled to the DRAM; and

[0092] The memory controller is configured as:

[0093] providing a command with a selectable pseudo channel broadcast mode indication to the DRAM, the command being associated with the requested data;

[0094] When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, concurrently accessing a first portion of the requested data in the DRAM via a first pseudo channel and accessing a second portion of the requested data in the DRAM via a second pseudo channel; and

[0095] When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, the requested data in the DRAM is accessed via a selected one of the first pseudo channel and the second pseudo channel in response to the command.

[0096] 11. The system of claim 10, wherein the memory controller is included in a system on chip (SoC) and is configured to receive a memory access request from a requesting host device among a plurality of host devices on the SoC.

[0097] 12. The system of claim 10, wherein:

[0098] The command has a pseudo channel selection indication;

[0099] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and

[0100] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

[0101] 13. The system of claim 10, wherein the memory controller is configured to provide the command by being configured to:

[0102] receiving a memory access request from a client device, the memory access request having a target address;

[0103] determining whether the memory access request is associated with the broadcast mode;

[0104] When the memory access request is associated with the broadcast mode, setting the state of the pseudo channel broadcast mode indication to indicate the broadcast mode; and

[0105] When the memory access request is not associated with the broadcast mode, the state of the pseudo channel broadcast mode indication is set to indicate the non-broadcast mode.

[0106] 14. A system according to claim 10, wherein whether the memory access request is associated with the broadcast mode is determined based on at least one of: a target address included in the memory access request; a flag included in the memory access request; and a priority associated with the memory access request.

[0107] 15. The system of claim 10, wherein the memory controller is configured to provide the command by providing the command to the DRAM via a command bus configured to be common to the first pseudo channel and the second pseudo channel.

[0108] 16. The system of claim 15 , wherein the memory controller is configured to concurrently access the first portion of the requested data via the first pseudo channel and access the second portion of the requested data via the second pseudo channel by being configured to access the first portion of the requested data in a first storage array group via a first portion of a data bus and access the second portion of the requested data in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group comprising a plurality of memory bank groups, each memory bank group comprising a plurality of memory banks.

[0109] 17. The system of claim 16, wherein the plurality of memory bank groups consists of eight memory bank groups, and the plurality of memory banks consists of two memory banks.

[0110] 18. The system of claim 10, wherein the memory controller is further configured to return the request data along with information identifying the command to a requesting host device.

[0111] 19. A system for accessing data in a dynamic random access memory (DRAM), comprising:

[0112] means for providing a command with a selectable pseudo channel broadcast mode indication to the DRAM, the command being associated with the request data;

[0113] means for concurrently accessing a first portion of the requested data in the DRAM via a first pseudo channel and a second portion of the requested data in the DRAM via a second pseudo channel in response to the command when the state of the pseudo channel broadcast mode indication indicates a broadcast mode; and

[0114] means for accessing the requested data in the DRAM via a selected one of the first pseudo channel and the second pseudo channel in response to the command when the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode.

[0115] 20. The system of claim 19, wherein the means for providing, the means for concurrently accessing, and the means for accessing are included in a system on a chip (SoC), and wherein the system further comprises means for receiving a memory access request from a requesting host device among a plurality of host devices on the SoC.

[0116] 21. The system of claim 19, wherein:

[0117] The command has a pseudo channel selection indication;

[0118] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and

[0119] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

[0120] 22. The system of claim 19, wherein the means for providing the command comprises means for providing the command to the DRAM via a command bus common to the first pseudo channel and the second pseudo channel.

[0121] 23. The system of claim 22, wherein the means for concurrently accessing the first portion of the requested data via the first pseudo channel and accessing the second portion of the requested data via the second pseudo channel comprises: means for accessing the first portion of the requested data in a first storage array group via a first portion of a data bus, and for accessing the second portion of the requested data in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group comprising a plurality of storage body groups, each storage body group comprising a plurality of storage bodies.

[0122] 24. The system of claim 23, wherein the plurality of memory bank groups consists of eight memory bank groups and the plurality of memory banks consists of two memory banks.

[0123] 25. The system of claim 19, further comprising means for returning the request data along with information identifying the command to a requesting host device.

[0124] 26. A dynamic random access memory (DRAM), comprising:

[0125] multiple DRAM memory arrays; and

[0126] DRAM command interface, configured as:

[0127] receiving a command having a selectable pseudo channel broadcast mode indication, the command being associated with request data;

[0128] When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, concurrently accessing a first portion of the requested data in the DRAM memory array via a first pseudo channel and accessing a second portion of the requested data in the DRAM memory array via a second pseudo channel; and

[0129] When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, in response to the command, the requested data in the DRAM storage array is accessed via a selected one of the first pseudo channel and the second pseudo channel.

[0130] 27. The DRAM of claim 26, wherein:

[0131] The command has a pseudo channel selection indication;

[0132] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and

[0133] When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

[0134] 28. The DRAM of claim 26, wherein the DRAM command interface is common to the first pseudo channel and the second pseudo channel.

[0135] 29. The DRAM of claim 26 , wherein the DRAM command interface is configured to concurrently access the first portion of the requested data via the first pseudo channel and access the second portion of the requested data via the second pseudo channel by being configured to access the first portion of the requested data in the first storage array group via a first portion of the data bus and access the second portion of the requested data in the second storage array group via a second portion of the data bus, wherein each of the first storage array group and the second storage array group includes a plurality of storage body groups, and each storage body group includes a plurality of storage bodies.

[0136] 30. The DRAM according to claim 29, wherein the plurality of memory bank groups consists of eight memory bank groups, and the plurality of memory banks consists of two memory banks.

Claims

1. A method for accessing data in a dynamic random access memory DRAM, comprising: providing, by a memory controller, to the DRAM a command with a selectable pseudo channel broadcast mode indication, the command being associated with the requested data; When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, the memory controller concurrently accesses a first portion of the requested data in the DRAM via a first pseudo channel and accesses a second portion of the requested data in the DRAM via a second pseudo channel; as well as When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, the requested data in the DRAM is accessed by the memory controller via a selected one of the first pseudo channel and the second pseudo channel in response to the command.

2. The method of claim 1, wherein the DRAM is a low power double data rate (LPDDR).

3. The method according to claim 1, wherein: The command has a pseudo channel selection indication; When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

4. The method of claim 1 , wherein providing the command comprises: receiving a memory access request from a client device; determining whether the memory access request is associated with the broadcast mode; When the memory access request is associated with the broadcast mode, setting the state of the pseudo channel broadcast mode indication to indicate the broadcast mode; as well as When the memory access request is not associated with the broadcast mode, the state of the pseudo channel broadcast mode indication is set to indicate the non-broadcast mode.

5. A method according to claim 4, wherein whether the memory access request is associated with the broadcast mode is determined based on at least one of: a target address included in the memory access request; a flag included in the memory access request; and a priority associated with the memory access request.

6. The method of claim 1 , wherein providing the command comprises: The command is provided to the DRAM via a command bus common to the first pseudo channel and the second pseudo channel.

7. The method of claim 6, wherein concurrently accessing the first portion of the request data via the first pseudo channel and accessing the second portion of the request data via the second pseudo channel comprises: The first portion of the requested data is accessed from a first storage array group via a first portion of a data bus, and the second portion of the requested data is accessed in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group including a plurality of memory bank groups, each memory bank group including a plurality of memory banks. 8 . The method of claim 7 , wherein the plurality of memory bank groups consists of eight memory bank groups, and the plurality of memory banks consists of two memory banks.

9. The method according to claim 1, further comprising: The request data is returned to the requesting host device along with information identifying the command.

10. A system for accessing data in a dynamic random access memory DRAM, comprising: a physical interface coupled to the DRAM; as well as The memory controller is configured as: providing a command with a selectable pseudo channel broadcast mode indication to the DRAM, the command being associated with the requested data; When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, concurrently accessing a first portion of the requested data in the DRAM via a first pseudo channel and accessing a second portion of the requested data in the DRAM via a second pseudo channel; as well as When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, the requested data in the DRAM is accessed via a selected one of the first pseudo channel and the second pseudo channel in response to the command. 11 . The system of claim 10 , wherein the memory controller is included in a system on chip (SoC) and is configured to receive a memory access request from a requesting host device among a plurality of host devices on the SoC.

12. The system of claim 10, wherein: The command has a pseudo channel selection indication; When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

13. The system of claim 10, wherein the memory controller is configured to provide the command by being configured to: receiving a memory access request from a client device, the memory access request having a target address; determining whether the memory access request is associated with the broadcast mode; When the memory access request is associated with the broadcast mode, setting the state of the pseudo channel broadcast mode indication to indicate the broadcast mode; as well as When the memory access request is not associated with the broadcast mode, the state of the pseudo channel broadcast mode indication is set to indicate the non-broadcast mode.

14. A system according to claim 13, wherein whether the memory access request is associated with the broadcast mode is determined based on at least one of: a target address included in the memory access request; a flag included in the memory access request; and a priority associated with the memory access request.

15. The system of claim 10, wherein the memory controller is configured to provide the command by providing the command to the DRAM via a command bus configured to be common to the first pseudo channel and the second pseudo channel.

16. The system of claim 15 , wherein the memory controller is configured to concurrently access the first portion of the requested data via the first pseudo channel and access the second portion of the requested data via the second pseudo channel by being configured to access the first portion of the requested data in a first storage array group via a first portion of a data bus and access the second portion of the requested data in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group comprising a plurality of memory bank groups, each memory bank group comprising a plurality of memory banks.

17. The system of claim 16, wherein the plurality of memory bank groups consists of eight memory bank groups, and the plurality of memory banks consists of two memory banks.

18. The system of claim 10, wherein the memory controller is further configured to return the request data along with information identifying the command to a requesting host device.

19. A system for accessing data in a dynamic random access memory DRAM, comprising: means for providing a command with a selectable pseudo channel broadcast mode indication to the DRAM, the command being associated with the request data; means for concurrently accessing a first portion of the requested data in the DRAM via a first pseudo channel and a second portion of the requested data in the DRAM via a second pseudo channel in response to the command when the state of the pseudo channel broadcast mode indication indicates a broadcast mode; as well as means for accessing the requested data in the DRAM via a selected one of the first pseudo channel and the second pseudo channel in response to the command when the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode.

20. The system of claim 19, wherein the means for providing, the means for concurrently accessing, and the means for accessing are included in a system on a chip (SoC), and wherein the system further comprises a means for receiving a memory access request from a requesting host device among a plurality of host devices on the SoC.

21. The system of claim 19, wherein: The command has a pseudo channel selection indication; When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

22. The system of claim 19, wherein the means for providing the command comprises means for providing the command to the DRAM via a command bus common to the first pseudo channel and the second pseudo channel.

23. The system of claim 22, wherein the means for concurrently accessing the first portion of the request data via the first pseudo channel and accessing the second portion of the request data via the second pseudo channel comprises: A component for accessing the first portion of the requested data in a first storage array group via a first portion of a data bus, and for accessing the second portion of the requested data in a second storage array group via a second portion of the data bus, each of the first storage array group and the second storage array group including a plurality of storage body groups, each storage body group including a plurality of storage bodies.

24. The system of claim 23, wherein the plurality of memory bank groups consists of eight memory bank groups and the plurality of memory banks consists of two memory banks.

25. The system of claim 19, further comprising means for returning the request data along with information identifying the command to a requesting host device.

26. A dynamic random access memory DRAM, comprising: Multiple DRAM storage arrays; as well as DRAM command interface, configured as: receiving a command having a selectable pseudo channel broadcast mode indication, the command being associated with request data; When the state of the pseudo channel broadcast mode indication indicates a broadcast mode, in response to the command, concurrently accessing a first portion of the requested data in the DRAM memory array via a first pseudo channel and accessing a second portion of the requested data in the DRAM memory array via a second pseudo channel; as well as When the state of the pseudo channel broadcast mode indication indicates a non-broadcast mode, in response to the command, the requested data in the DRAM storage array is accessed via a selected one of the first pseudo channel and the second pseudo channel.

27. The dynamic random access memory DRAM according to claim 26, wherein: The command has a pseudo channel selection indication; When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode, and the state of the pseudo channel selection indication indicates the first pseudo channel, in response to the command, the first pseudo channel is selected; and When the state of the pseudo channel broadcast mode indication indicates the non-broadcast mode and the state of the pseudo channel selection indication indicates the second pseudo channel, the second pseudo channel is selected in response to the command.

28. The dynamic random access memory DRAM according to claim 26, wherein the DRAM command interface is common to the first pseudo channel and the second pseudo channel.

29. A dynamic random access memory DRAM according to claim 26, wherein the DRAM command interface is configured to: access the first part of the requested data in the first storage array group via a first part of the data bus, and access the second part of the requested data in the second storage array group via a second part of the data bus, so as to concurrently access the first part of the requested data via the first pseudo channel and access the second part of the requested data via the second pseudo channel, each of the first storage array group and the second storage array group including a plurality of storage body groups, and each storage body group including a plurality of storage bodies. 30 . The dynamic random access memory DRAM according to claim 29 , wherein the plurality of memory bank groups consist of eight memory bank groups, and the plurality of memory banks consist of two memory banks.

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