A ground penetrating radar pulse signal source generation circuit

Abstract

The application provides a ground penetrating radar pulse signal source generation circuit, and the method comprises the circuit which comprises input matching circuit, first stage signal amplification circuit, intermediate matching circuit, second stage signal amplification circuit and output matching circuit connected in sequence, wherein: the input matching circuit is used for accessing a small power excitation source signal output via an FPGA and providing input impedance matching for the small power excitation source signal; the first stage amplification circuit is used for performing first stage power amplification on the small power excitation source signal and outputting generated medium power excitation source signal to the intermediate matching circuit, and the intermediate matching circuit provides interstage impedance matching; the second stage signal amplification circuit is used for performing second stage power amplification on the medium power excitation source signal to generate a large power excitation source signal meeting ground penetrating radar detection requirements; and the output matching circuit is used for providing output impedance matching.

Description

Technical Field

[0001] This application relates to the field of pulse ground-penetrating radar signal processing technology, and more specifically, to a ground-penetrating radar pulse signal source generation circuit. Background Technology

[0002] In recent years, ground-penetrating radar (GPR) has become an important remote sensing tool in many fields, serving as the most effective method for imaging ultra-shallow underground layers. Its detection range extends from a few centimeters to tens of meters underground, offering high resolution, with ultra-shallow layer resolution reaching the centimeter level. In geophysical exploration, GPR is used to study the distribution of bedrock, soil layers, groundwater, and ice layers. In construction engineering, GPR is used as an instrument for non-destructive detection of underground space information, and it also has wide applications in wall detection, bridge detection, and railway foundation detection. In bioengineering, GPR imaging technology enables non-destructive detection of plant root volume and tree trunk internal structure. In archaeology, GPR can be used to confirm the location and structure of underground tombs. In military applications, it is often used to detect landmines and firearms left underground from war.

[0003] Ground-penetrating radar (GPR) uses high-frequency electromagnetic waves to detect the internal material distribution patterns of a target medium. A signal generation unit generates high-frequency electromagnetic waves, which are then emitted by a transmitting antenna. These electromagnetic waves are reflected when they encounter objects or interfaces with different electrical properties. The reflected electromagnetic wave signals are received by a receiving antenna positioned at a specific location. By analyzing and processing the waveform, amplitude, phase, and frequency characteristics of the reflected echo signals, information such as the spatial location, structure, shape, and depth of the underground medium can be determined. Although the theory of GPR has been recognized for a long time, practical GPR systems have only gradually matured in recent decades. Due to its unique advantages such as being non-destructive, efficient, high-resolution, and capable of detecting a wide range of targets, the application areas of GPR are gradually expanding.

[0004] Because electromagnetic waves propagate very quickly, ground-penetrating radar (GPR) systems require the use of pulse signals with extremely small duty cycles to avoid aliasing between direct and echo signals, resulting in narrow pulses in the time domain. In currently developed pulse GPR systems, the main problems to be solved by the narrow pulse signal transmission circuit include the stability of the narrow pulse waveform (pulse width, amplitude), frequency stability, pulse repetition frequency, the signal form of the pulse source (unipolar, bipolar), and the matching of the signal bandwidth with the antenna bandwidth.

[0005] Currently, methods for generating nanosecond and sub-nanosecond narrow pulses include those based on devices such as step recovery diodes and avalanche transistors, as well as methods using high-pressure gas dischargers. The high-pressure gas discharger method can generate instantaneous high-voltage pulses exceeding 100kV, but the pulse repetition frequency is low, typically less than 1kHz, and exhibits significant jitter. Step recovery diode-based methods produce very narrow pulses, ranging from tens to hundreds of picoseconds, but their amplitude is small, typically a few volts. Avalanche transistor-based pulse signal sources are currently the most widely used, capable of generating narrow pulses with a pulse width of 1-2ns and an output pulse amplitude ranging from tens to thousands of volts. However, their disadvantages include the need for high power supply voltage, a low repetition frequency, and a fixed center frequency that is difficult to modify.

[0006] In summary, current ground-penetrating radar pulse signal sources have shortcomings to varying degrees, such as low power, fixed center frequency, and insufficient repetition frequency. Summary of the Invention

[0007] The purpose of this application is to provide a ground-penetrating radar pulse signal generation circuit that allows the center frequency and pulse width of the output signal to be continuously adjustable, and the repetition frequency to be very high, making it suitable for the field of pulse ground-penetrating radar.

[0008] This application also provides a ground-penetrating radar pulse signal generation circuit, the circuit comprising an input matching circuit, a first-stage signal amplification circuit, an intermediate matching circuit, a second-stage signal amplification circuit, and an output matching circuit connected in sequence, wherein:

[0009] The input matching circuit is used to receive the low-power excitation source signal output via the FPGA and to provide input impedance matching for the low-power excitation source signal.

[0010] The first-stage amplifier circuit is used to amplify the low-power excitation source signal in the first stage and output the generated medium-power excitation source signal to the intermediate matching circuit, which provides interstage impedance matching.

[0011] The second-stage signal amplification circuit is used to amplify the medium-power excitation source signal in the second stage to generate a high-power excitation source signal that meets the detection requirements of ground-penetrating radar.

[0012] The output matching circuit is used to provide output impedance matching.

[0013] In one embodiment, the input matching circuit includes capacitor C1, capacitor C2, and inductor L1, wherein:

[0014] The first end of the capacitor C1 is connected in series with the inductor L1, and the end connected in series is grounded through the capacitor C2.

[0015] The second terminal of capacitor C1 is connected to the first output terminal of transformer RF3, and the second output terminal of transformer RF3 is grounded.

[0016] In one embodiment, the first-stage amplifier circuit includes resistors R1, R2, R4, R5, an adjustable resistor R6, capacitors C3, C12, and C13, and a MOSFET M1, wherein:

[0017] The first end of resistor R1 is connected in series with one end of resistor R4. The other end of resistor R4 is pulled up to the power supply through resistor R5 and grounded through adjustable resistor R6.

[0018] One end of resistors R1 and R4 connected in series is also connected to inductor L1, and the second end of resistor R1 is connected to the drain of MOSFET M1 via resistor R2 and capacitor C3. 、 and the gate connected to MOSFET M1;

[0019] Capacitors C12 and C13 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R6 and pulled up to the power supply via resistor R5.

[0020] In one embodiment, the intermediate matching circuit includes capacitors C4, C5, and C6, and inductor L2, wherein:

[0021] Capacitor C4 and capacitor C6 are connected in parallel. One end of capacitor C5 is connected to capacitor C4 and the drain of MOSFET M1, and the other end of capacitor C5 is connected to capacitor C6 and inductor L2.

[0022] In one embodiment, the second-stage amplifier circuit includes resistors R3, R7, R8, an adjustable resistor R9, capacitors C16, C17, and C7, and a MOSFET M2, wherein:

[0023] The first end of resistor R3 is connected to the gate of MOSFET M2, the drain of MOSFET M2 is connected to capacitor C7, and the other end of capacitor C7 is grounded.

[0024] The second end of resistor R3 is connected to resistor R7 and inductor L2 respectively, and the other end of resistor R7 is pulled up to the power supply via resistor R8;

[0025] The other end of the resistor R7 is grounded via the adjustable resistor R9. Capacitors C16 and C17 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R9 and pulled up to the power supply via resistor R8.

[0026] In one embodiment, the output matching circuit includes capacitors C8, C9, C10, C11, and inductor L3, wherein:

[0027] Capacitors C8, C9, and C10 are connected in parallel, with one end of the parallel connection connected to capacitor C11, and the other end of capacitor C11 connected to the second I / O port JP2 of the FPGA.

[0028] One end of inductor L3 is connected to capacitor C8, and the other end is connected to capacitor C9. The end of capacitor C8 connected to inductor L3 is also connected to the drain of MOSFET M2.

[0029] In one embodiment, a bias circuit is further connected between the first-stage signal amplification circuit and the intermediate matching circuit, wherein:

[0030] The bias circuit is used to provide corresponding static operating points for the first-stage signal amplification circuit and the second-stage signal amplification circuit, respectively, and to maintain the entire circuit in a stable operating state by suppressing the dispersion of the field-effect transistor parameters and the influence of temperature changes.

[0031] The quiescent operating point of the first-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M1 are maintained at V. GS1 =1.2V, and the operating voltage between the drain and source is maintained at V. DS1 =7.2V, MOSFET M1 is operating in the saturation region;

[0032] The quiescent operating point of the second-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M2 are maintained at V. GS2 =1.3V, and the operating voltage between the drain and source is maintained at V. DS2 =7.2V, MOSFET M2 is operating in Class A amplification mode.

[0033] In one embodiment, the bias circuit includes capacitor C14, capacitor C15, inductor L4, inductor L5, and capacitor E1, wherein:

[0034] One end of inductor L4 is connected to the drain of MOSFET M1, and the other end is connected to capacitors C14 and C15, wherein capacitors C14 and C15 are connected in parallel.

[0035] One end of inductor L5 is connected to inductor L4, and the other end is connected to capacitor E1.

[0036] In one embodiment, a drain stage turn-off control circuit is further connected between the second-stage signal amplification circuit and the output matching circuit, wherein:

[0037] The drain-level shutdown control circuit is used to amplify the shutdown pulse signal output through the third IO port JP3 of the FPGA in two stages, and apply the amplified signal to the drain of the MOSFET M2. By changing the operating state of the MOSFET M2, the power supply of the MOSFET M2 can be turned off at the effective signal transmission time, forcing the output signal to decay rapidly and avoiding signal tailing distortion.

[0038] In one embodiment, the drain turn-off control circuit includes transformer RF1, transformer RF2, capacitor C20, capacitor C21, resistor R12, resistor R13, resistor R14, adjustable resistor RP1, transistor Q1, and MOSFET M3, wherein:

[0039] The input terminal of transformer RF1 is connected to the third IO port JP3 of FPGA. The first output terminal of transformer RF1 is connected to the base of transistor Q1, resistor R13, and adjustable resistor RP1 via capacitor C20 and resistor R12, respectively.

[0040] The other end of resistor R13 is connected to the second output terminal of transformer RF1 and to the emitter of transistor Q1 via resistor R14;

[0041] The end of resistor R14 connected to the emitter of transistor Q1 is also connected to the first input terminal of transformer RF2 via capacitor C21, and the end of resistor R13 connected to resistor R14 is also connected to the second input terminal of transformer RF2.

[0042] The first output terminal of transformer RF2 is connected to the drain of MOSFET M2 and the gate of MOSFET M3, respectively.

[0043] The second output terminal of transformer RF2 is connected to the gate of MOSFET M3, and the drain of MOSFET M3 is connected to the power supply of the second-stage MOSFET drain.

[0044] As can be seen from the above, the ground-penetrating radar pulse signal generation circuit provided in this application has the following aspects: First, it converts the low-power excitation source signal output from the first IO port of the FPGA into a high-power excitation source signal suitable for ground-penetrating radar detection requirements through a two-stage amplifier circuit. Each stage of the amplifier circuit has a corresponding impedance matching circuit connected to one side, which can effectively suppress noise interference in the circuit to achieve stable signal output. Second, the bias circuit connected between the first-stage signal amplifier circuit and the intermediate matching circuit forms an RF blocking network through a high-frequency capacitor and a high-frequency choke connected to the drain of the MOS transistor. This network provides effective static operating points for both the first-stage and second-stage signal amplifier circuits, ensuring the entire circuit remains in a stable operating state. Third, the drain-stage turn-off control circuit connected between the second-stage signal amplifier circuit and the output matching circuit can turn off the power supply of the MOS transistor M2 at the effective signal transmission time, forcing the output signal to decay rapidly and avoiding signal tailing distortion, thereby solving the tailing phenomenon that occurs in narrow pulse amplification of the MOS amplifier circuit.

[0045] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solution of this application, the accompanying drawings used in this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0047] Figure 1 A schematic diagram of the system structure of a ground-penetrating radar pulse signal generation circuit provided in this application;

[0048] Figure 2 A schematic diagram of the circuit structure for the input matching circuit;

[0049] Figure 3 A schematic diagram of the circuit connection structure for the input matching circuit and the first-stage amplifier circuit;

[0050] Figure 4 This is a schematic diagram of the circuit connection structure of the first-stage amplifier circuit, the intermediate matching circuit, and the bias circuit.

[0051] Figure 5 This is a schematic diagram of the circuit connection structure of the intermediate matching circuit and the second-stage amplifier circuit.

[0052] Figure 6 This is a schematic diagram of the circuit connection structure of the second-stage amplifier circuit, output matching circuit, drain turn-off control circuit, and second-stage MOS drain power supply.

[0053] Figure 7 This is a block diagram of a two-stage amplifier.

[0054] Figure 8 A schematic diagram of the system structure of another ground-penetrating radar pulse signal source generation circuit provided in this application;

[0055] Figure 9 The input and output power characteristics of the first-stage amplifier tube;

[0056] Figure 10 The input and output power characteristics of the second-stage amplifier tube;

[0057] Figure 11 This is a schematic diagram of the waveform test for the output signal;

[0058] Figure 12 This is a schematic diagram for testing the repetition frequency of the output signal.

[0059] Figure 13 A schematic diagram of the output waveform for early shutdown;

[0060] Figure 14 This is a schematic diagram of the output waveform after bias adjustment. Detailed Implementation

[0061] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0062] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0063] Please refer to Figure 1 , Figure 1This is a schematic diagram of the system structure of a ground-penetrating radar pulse signal generation circuit according to some embodiments of this application. The circuit includes an input matching circuit, a first-stage signal amplification circuit, an intermediate matching circuit, a second-stage signal amplification circuit, and an output matching circuit connected in sequence, wherein:

[0064] The input matching circuit is used to access the low-power excitation source signal output via the first IO port JP1 of the FPGA and to provide input impedance matching for the low-power excitation source signal.

[0065] The first-stage amplifier circuit is used to amplify the low-power excitation source signal and output the generated medium-power excitation source signal to the intermediate matching circuit, which provides interstage impedance matching.

[0066] The second-stage signal amplification circuit is used to amplify the medium-power excitation source signal in the second stage to generate a high-power excitation source signal that meets the detection requirements of ground-penetrating radar.

[0067] The output matching circuit is used to provide output impedance matching.

[0068] Based on the system structure of the ground-penetrating radar pulse signal source generation circuit described above, it should be noted that the design of high-frequency high-power amplifiers usually uses dedicated high-speed MOSFETs. Unlike low-speed amplifier circuits, high-speed circuits usually need to consider impedance matching during the design process.

[0069] It should be noted that, please refer to Figure 2 After passing through the input matching circuit (i.e. Figure 2 The input impedance matching network (illustrated in the diagram) performs input impedance matching on the low-power excitation source signal, which then passes through the first-stage amplifier circuit (i.e., Figure 3 The first-stage MOS amplifier (illustrated in the diagram) performs a power amplification on the first received signal generated after input impedance matching. For further details, please refer to... Figure 4 The generated medium-power excitation source signal will be transmitted to the intermediate matching circuit (i.e., Figure 4 The intermediate matching network (illustrated in the diagram) provides interstage impedance matching through the intermediate matching circuit. Finally, please refer to... Figure 5 Currently, it will pass through the second-stage signal amplification circuit (i.e. Figure 5 The second-stage MOS amplifier (illustrated in the diagram) performs a second-stage power amplification on the second received signal generated after inter-stage impedance matching, and then... Figure 6 Schematic output matching circuit (i.e.) Figure 6 The output impedance is matched using the output matching network shown in the diagram.

[0070] It should be noted that this application draws inspiration from Class A RF power amplifiers commonly used in audio radios. These amplifiers possess excellent linearity and are therefore frequently used as preamplifiers and output power stages in wireless transmitters. Since high-speed, high-power MOSFETs have certain power requirements for the input signal, and FPGAs are insufficient to drive them directly, this application employs a two-stage high-frequency amplifier design, as shown in the block diagram below. Figure 3 As shown.

[0071] based on Figure 7 It should be noted that the two-stage high-frequency amplifier used in this application employs RD01MUS2B as the first-stage amplifier and RD07MUS2B as the second-stage amplifier. The first-stage amplifier RD01MUS2B primarily amplifies the low-power digital signal output from the FPGA to a medium-power signal sufficient to drive the second-stage amplifier. The second-stage amplifier RD07MUS2B primarily amplifies this medium-power signal to a high-power signal capable of meeting the detection requirements of ground-penetrating radar.

[0072] It should be further noted that, under linear operating conditions, the total power gain G of the two-stage amplifier described above... tot It is equal to the product of the gains G1 and G2 of the two individual amplifier stages, which, on a logarithmic axis in dB, is G tot It can be calculated using the following formula:

[0073] C tot =G1+G2#.

[0074] As can be seen from the above, the ground-penetrating radar pulse signal generation circuit disclosed in this application, in the first aspect, converts the low-power excitation source signal output from the first IO port of the FPGA into a high-power excitation source signal suitable for the detection requirements of ground-penetrating radar through a two-stage amplifier circuit. Each stage of the amplifier circuit has a corresponding impedance matching circuit connected to one side, which can effectively suppress noise interference in the circuit to achieve stable signal output. In the second aspect, the bias circuit connected between the first-stage signal amplifier circuit and the intermediate matching circuit forms an RF blocking network through a high-frequency capacitor and a high-frequency choke connected to the drain of the MOS transistor. This network provides effective static operating points for both the first-stage and second-stage signal amplifier circuits, ensuring the entire circuit remains in a stable operating state. In the third aspect, the drain-stage turn-off control circuit connected between the second-stage signal amplifier circuit and the output matching circuit can turn off the power supply of the MOS transistor M2 at the effective signal transmission time, forcing the output signal to decay rapidly and avoiding signal tailing distortion, thereby solving the tailing phenomenon that occurs in narrow pulse amplification of the MOS amplifier circuit.

[0075] In one embodiment, please refer to Figure 2The input matching circuit includes capacitor C1, capacitor C2 and inductor L1, wherein: the first end of capacitor C1 is connected in series with inductor L1, and the end of the series connection is grounded through capacitor C2; the second end of capacitor C1 is connected to the first output terminal of transformer RF3, and the second output terminal of transformer RF3 is grounded.

[0076] Specifically, the circuit structure of the input matching circuit can be found in [reference needed]. Figure 2 To understand. From Figure 2 It can be seen that one end of capacitor C1 is connected to the first output terminal of transformer RF3, and the other end of capacitor C1 is connected to one end of inductor L1 and one end of capacitor C2 respectively. The other end of inductor L1 serves as the output terminal of the input matching circuit and is connected to the input terminal of the first stage amplifier circuit.

[0077] In one embodiment, please refer to Figure 3 The first-stage amplifier circuit includes resistors R1, R2, R4, R5, an adjustable resistor R6, capacitors C3, C12, and C13, and a MOSFET M1, wherein:

[0078] The first end of resistor R1 is connected in series with one end of resistor R4. The other end of resistor R4 is pulled up to the power supply via resistor R5 and grounded via adjustable resistor R6.

[0079] One end of resistors R1 and R4 connected in series is also connected to inductor L1, and the second end of resistor R1 is connected to the drain of MOSFET M1 via resistor R2 and capacitor C3. 、 And the gate connected to the MOSFET M1.

[0080] For details, please refer to Figure 3 Resistor R1 is connected to inductor L1 to absorb reflections on the microstrip line, while resistor R2 and capacitor C3 form the negative feedback path for MOSFET M1. The drain of MOSFET M1 serves as the output of the first-stage amplifier circuit and is connected to the input of the intermediate matching network.

[0081] Capacitors C12 and C13 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R6 and pulled up to the power supply via resistor R5.

[0082] For details, please refer to Figure 3One end of capacitors C12 and C13 is grounded, and the other ends are connected in parallel. The parallel end is connected to one end of the adjustable resistor R6, and the adjustment terminal of R6 is grounded. It should be noted that the resistance value of the adjustable resistor R6 can be adjusted according to changes in the power supply output voltage. This allows for further reduction of the chip area without requiring a large-value resistor, overcoming the problem of larger chip size caused by larger resistors.

[0083] In one embodiment, please refer to Figure 4 The intermediate matching circuit includes capacitors C4, C5, and C6, and inductor L2. Specifically, capacitors C4 and C6 are connected in parallel, one end of capacitor C5 is connected to capacitor C4 and the drain of MOSFET M1, and the other end of capacitor C5 is connected to capacitor C6 and inductor L2.

[0084] For details, please refer to Figure 4 The circuit structure of the intermediate matching circuit is basically the same as that of the input matching circuit. The difference is that one end of capacitor C5 is connected to the output of the first-stage amplifier circuit and grounded through capacitor C4. The other end of inductor L2 serves as the output of the intermediate matching circuit and is connected to the input of the second-stage amplifier circuit.

[0085] In one embodiment, please refer to Figure 5 The second-stage amplifier circuit includes resistors R3, R7, R8, an adjustable resistor R9, capacitors C16, C17, and C7, and a MOSFET M2. The first end of resistor R3 is connected to the gate of MOSFET M2, and the drain of MOSFET M2 is connected to capacitor C7. The other end of capacitor C7 is grounded. The second end of resistor R3 is connected to resistor R7 and inductor L2. The other end of resistor R7 is pulled up to the power supply via resistor R8. The other end of resistor R7 is also grounded via the adjustable resistor R9. Capacitors C16 and C17 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R9 and the other end pulled up to the power supply via resistor R8.

[0086] For details, please refer to Figure 5 The circuit structure of the second-stage amplifier circuit is basically the same as that of the first-stage amplifier circuit, except that the second-stage amplifier circuit does not have a negative feedback path. The drain of MOSFET M2 serves as the output terminal of the second-stage amplifier circuit and is connected to the input terminal of the output matching network.

[0087] In one embodiment, please refer to Figure 6The output matching circuit includes capacitors C8, C9, C10, C11, and inductor L3. Capacitors C8, C9, and C10 are connected in parallel, with one end of the parallel connection connected to capacitor C11. The other end of capacitor C11 is connected to the second IO port JP2 of the FPGA. One end of inductor L3 is connected to capacitor C8, and the other end is connected to capacitor C9. The end of capacitor C8 connected to inductor L3 is also connected to the drain of MOSFET M2.

[0088] In one embodiment, please refer to Figure 8 A bias circuit is also connected between the first-stage signal amplification circuit and the intermediate matching circuit. The bias circuit provides corresponding static operating points for the first-stage and second-stage signal amplification circuits, respectively, suppressing the dispersion of the field-effect transistor parameters and the influence of temperature changes, thus maintaining the entire circuit in a stable operating state.

[0089] The quiescent operating point of the first-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M1 are maintained at V. GS1 =1.2V, and the operating voltage between the drain and source is maintained at V. DS1 =7.2V, MOSFET M1 is operating in the saturation region.

[0090] It should be noted that the current of the excitation source signal output from the FPGA pin is 12mA. If the output voltage of the single-ended output signal is selected as 2.5V, then the output power of the FPGA pin is P. FPGA =14.8dBm. At a typical quiescent operating point, the gate-source voltage V0... GS1 =1.0V, and the drain and source V DS1 The input and output power characteristic curves of a MOSFET at 7.2V and a frequency of 155MHz are shown below. Figure 9 As shown. The first-stage amplifier transistor operates at input P... in1 At 0dBm, the output power can reach 24dBm.

[0091] Therefore, for the low-power signal output from the FPGA, after impedance matching to the MOSFET M1, its gate voltage is in the millivolt range. To reduce power loss in the circuit, without causing cutoff distortion and ensuring a certain voltage gain, this application considers selecting a low quiescent operating point. Therefore, in the current embodiment, the gate-source voltage of the MOSFET M1 is selected as 1.2V, and the operating voltage between its drain and source is 7.2V, so that the MOSFET M1 can operate in the saturation region.

[0092] The quiescent operating point of the second-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M2 are maintained at V. GS2=1.3V, and the operating voltage between the drain and source is maintained at V. DS2 =7.2V, MOSFET M2 is operating in Class A amplification mode.

[0093] Specifically, for MOSFET M2, in a typical case for p in2 With an input signal of 20dBm, the power amplifier output can reach 37dBm. The input-output power curve is shown below. Figure 10 As shown. The first-stage output power meets the minimum input requirements of the second-stage amplification. The output signal of the first-stage power amplifier, after passing through the interstage impedance matching circuit, still reaches the milliwatt level between the gate and drain of the MOSFET M2. Therefore, in this application, the gate-source voltage is selected to be 1.3V, and the operating voltage between the drain (D) and source (S) is selected to be 7.2V, so that the MOSFET M2 operates in Class A amplification mode.

[0094] In one embodiment, please refer to Figure 4 The bias circuit includes capacitor C14, capacitor C15, inductor L4, inductor L5, and capacitor E1, wherein: one end of inductor L4 is connected to the drain of MOSFET M1, and the other end is connected to capacitors C14 and C15, wherein capacitors C14 and C15 are connected in parallel; one end of inductor L5 is connected to inductor L4, and the other end is connected to capacitor E1.

[0095] Regarding the aforementioned bias circuit, it should be noted that since the drain bias voltage has a certain power, if a purely resistive bias circuit is used, this bias circuit is highly sensitive to changes in the parameters of the MOSFET M1 and exhibits poor temperature stability. Based on this, this application designs an RF blocking network to separate the high-frequency signal from the DC bias. The RF blocking network is constructed using high-frequency capacitors C14, C15, and E1, and a high-frequency choke (RFC, i.e., inductors L4 and L5) connected to the drain of the field-effect transistor (i.e., MOSFET M1), to reduce the impact of MOSFET parameter changes on overall stability. In summary, the bias circuit disclosed in this application provides an appropriate static operating point for active devices under specific operating conditions and suppresses the dispersion of MOSFET parameters and the influence of temperature changes, thereby maintaining a stable operating state.

[0096] In one embodiment, please refer to Figure 8 Between the second-stage signal amplification circuit and the output matching circuit, a drain-stage shutdown control circuit is also connected. The drain-stage shutdown control circuit is used to amplify the shutdown pulse signal output through the third IO port JP3 of the FPGA in two stages, and apply the amplified signal to the drain of the MOS transistor M2. By changing the operating state of the MOS transistor M2, the power supply of the MOS transistor M2 can be turned off at the effective signal transmission time, forcing the output signal to decay rapidly and avoiding signal tailing distortion.

[0097] Specifically, the design concept of the drain-stage turn-off control circuit proposed in this application is as follows: First, a continuous signal is output from the FPGA's I / O port (JP1) to the high-frequency power amplifier circuit (i.e., a two-stage amplifier circuit). If both stages of the high-frequency power amplifier circuit are in the on state, the input signal will be amplified into a continuous sinusoidal power signal with the same frequency. At the same time, a control signal with a very small duty cycle is output from another FPGA I / O port (JP3). After amplification, this signal is transmitted to the drain of the MOS transistor M2 in the second-stage signal amplifier circuit, periodically changing the operating state of the second-stage signal amplifier circuit.

[0098] In one embodiment, please refer to Figure 6 The drain-level turn-off control circuit includes transformer RF1, transformer RF2, capacitor C20, capacitor C21, resistor R12, resistor R13, resistor R14, adjustable resistor RP1, transistor Q1, and MOSFET M3. The input terminal of transformer RF1 is connected to the third I / O port JP3 of the FPGA. The first output terminal of transformer RF1 is connected to the base of transistor Q1, resistor R13, and adjustable resistor RP1 via capacitor C20 and resistor R12, respectively. The other end of resistor R13 is connected to the second output terminal of transformer RF1. The first input terminal of transformer RF2 is connected to the first input terminal of transformer RF2 via resistor R14 and the emitter of transistor Q1 via resistor R14. The second input terminal of transformer RF2 is connected to the drain of MOSFET M2 and the gate of MOSFET M3. The third output terminal of transformer RF2 is connected to the gate of MOSFET M3. The drain of MOSFET M3 is externally connected to the power supply of the second-stage MOSFET drain.

[0099] It should be noted that the switching control of the second-stage MOS drain power supply uses a switching transistor. Considering the requirements of business applications, this switching transistor needs to have a nanosecond-level response speed and a certain current output capability. While both transistors and MOSFETs can be used as fast switching devices, the power dissipation of a transistor in the on-state is greater than that of a MOSFET. Therefore, this application uses MOSFET M3 as the drain turn-off switch. By turning off the power supply of MOSFET M3 at the effective time point of the required detection signal transmission, the output signal is forced to decay rapidly, thereby solving the waveform tailing distortion phenomenon.

[0100] It should be further noted that the instrument used for testing in this application is an Agilent DSO7052B oscilloscope, which has two channels and can effectively sample high-speed signals. During testing, both the high-frequency continuous signal (i.e., the low-power excitation source signal) and the shutdown control signal (i.e., the shutdown pulse signal) were provided by the FPGA. The high-frequency continuous signal had a frequency of 150MHz and a duty cycle of 50%. Simultaneously, the FPGA's internal phase-locked loop provided a 300MHz clock for counting. The final output shutdown control signal had a frequency of 1.5MHz and a high-level duration of one clock cycle. After adjusting the bias voltage Vbe of the emitter follower in the shutdown section to 0.16V, the output waveform is as follows. Figure 11 and Figure 12 As shown.

[0101] Depend on Figure 11 and Figure 12 It can be seen that although the input signal to the amplifier circuit is a continuous signal, after the turn-off control, the final output waveform is a 3-wavelet structure with no obvious tail. The overall pulse width is about 20ns and has a relatively high repetition frequency of 1.48MHz.

[0102] Additionally, since the width of the FPGA's I / O output pulse signal cannot be infinitely narrow, the driver shutdown signal was terminated early during the test, keeping the emitter follower bias voltage Vbe = 0.16V constant. The output waveform at this time is as follows: Figure 13 As shown. It should be noted that, Figure 13 One channel displays the waveform of the final output of the power amplifier, while the other channel displays the shutdown control signal output by the FPGA.

[0103] based on Figure 13 As can be seen, compared to the waveform before adjusting the turn-off delay, the adjusted output signal has a narrower width and less trailing. Finally, by slightly adjusting the bias voltage of the emitter follower, the following result is obtained: Figure 14 The output signal waveform is shown below. Based on... Figure 14 It can be seen that the output signal has a stable center frequency, large amplitude, and narrow signal width, making it well-suited for use in ground-penetrating radar systems.

[0104] In summary, this application designs a ground-penetrating radar signal source based on the fundamental principle of MOS amplifier circuits. Testing shows that this signal source can output a signal with a repetition frequency of 1.5MHz, a center frequency of 150MHz, and a pulse width of less than 20ns. Furthermore, to address the issue of tailing oscillations that easily occur during high-speed pulse amplification of MOS transistors, this application proposes a drain-off control method, which effectively solves this problem through FPGA control. Compared to traditional ground-penetrating radar signal sources, the high-power excitation signal generated through two-stage amplification and drain-off control has the advantages of stable center frequency and high repetition frequency, making it suitable for pulse-based ground-penetrating radar applications.

[0105] In the embodiments provided in this application, the functional circuits can be integrated together to form an independent part, or each circuit can exist separately, or two or more circuits can be integrated to form an independent part.

[0106] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0107] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A ground-penetrating radar pulse signal generation circuit, characterized in that, The circuit includes an input matching circuit, a first-stage signal amplification circuit, an intermediate matching circuit, a second-stage signal amplification circuit, and an output matching circuit connected in sequence, wherein: The input matching circuit is used to receive the low-power excitation source signal output via the first IO port JP1 of the FPGA and to provide input impedance matching for the low-power excitation source signal. The first-stage signal amplification circuit is used to amplify the low-power excitation source signal in the first stage and output the generated medium-power excitation source signal to the intermediate matching circuit, which provides interstage impedance matching. The first-stage signal amplification circuit includes resistors R1, R2, R4, R5, an adjustable resistor R6, capacitors C3, C12, and C13, and a MOSFET M1. Specifically: the first end of resistor R1 is connected in series with one end of resistor R4; the other end of resistor R4 is pulled up to the power supply via resistor R5 and grounded via the adjustable resistor R6; the series connection of resistors R1 and R4 is also connected to inductor L1; the second end of resistor R1 is connected to the drain of MOSFET M1 via resistor R2 and capacitor C3, and to the gate of MOSFET M1; capacitors C12 and C13 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R6 and pulled up to the power supply via resistor R5. The second-stage signal amplification circuit is used to amplify the medium-power excitation source signal in the second stage to generate a high-power excitation source signal that meets the detection requirements of ground-penetrating radar. The output matching circuit is used to provide output impedance matching.

2. The circuit according to claim 1, characterized in that, The input matching circuit includes capacitor C1, capacitor C2, and inductor L1, wherein: The first end of the capacitor C1 is connected in series with the inductor L1, and the end connected in series is grounded through the capacitor C2. The second terminal of capacitor C1 is connected to the first output terminal of transformer RF3, and the second output terminal of transformer RF3 is grounded.

3. The circuit according to claim 1, characterized in that, The intermediate matching circuit includes capacitors C4, C5, and C6, and inductor L2, wherein: Capacitor C4 and capacitor C6 are connected in parallel. One end of capacitor C5 is connected to capacitor C4 and the drain of MOSFET M1, and the other end of capacitor C5 is connected to capacitor C6 and inductor L2.

4. The circuit according to claim 3, characterized in that, The second-stage signal amplification circuit includes resistors R3, R7, R8, an adjustable resistor R9, capacitors C16, C17, and C7, and a MOSFET M2, wherein: The first end of resistor R3 is connected to the gate of MOSFET M2, the drain of MOSFET M2 is connected to capacitor C7, and the other end of capacitor C7 is grounded. The second end of resistor R3 is connected to resistor R7 and inductor L2 respectively, and the other end of resistor R7 is pulled up to the power supply via resistor R8. The other end of the resistor R7 is grounded via the adjustable resistor R9. Capacitors C16 and C17 are connected in parallel, with one end of the parallel connection connected to the adjustable resistor R9 and pulled up to the power supply via resistor R8.

5. The circuit according to claim 4, characterized in that, The output matching circuit includes capacitors C8, C9, C10, and C11, and inductor L3, wherein: Capacitors C8, C9, and C10 are connected in parallel, with one end of the parallel connection connected to capacitor C11, and the other end of capacitor C11 connected to the second I / O port JP2 of the FPGA. One end of inductor L3 is connected to capacitor C8, and the other end is connected to capacitor C9. The end of capacitor C8 connected to inductor L3 is also connected to the drain of MOSFET M2.

6. The circuit according to claim 1, characterized in that, A bias circuit is also connected between the first-stage signal amplification circuit and the intermediate matching circuit, wherein: The bias circuit is used to provide corresponding static operating points for the first-stage signal amplification circuit and the second-stage signal amplification circuit, respectively, and to maintain the entire circuit in a stable operating state by suppressing the dispersion of the field-effect transistor parameters and the influence of temperature changes. The quiescent operating point of the first-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M1 are maintained at V. GS1 =1.2V, and the operating voltage between the drain and source is maintained at V. DS1 =7.2V, MOSFET M1 is operating in the saturation region; The quiescent operating point of the second-stage signal amplifier circuit includes: the gate and source voltages of MOSFET M2 are maintained at V. GS2 =1.3V, and the operating voltage between the drain and source is maintained at V. DS2 =7.2V, MOSFET M2 is operating in Class A amplification mode.

7. The circuit according to claim 6, characterized in that, The bias circuit includes capacitor C14, capacitor C15, inductor L4, inductor L5, and capacitor E1, wherein: One end of inductor L4 is connected to the drain of MOSFET M1, and the other end is connected to capacitors C14 and C15, wherein capacitors C14 and C15 are connected in parallel. One end of inductor L5 is connected to inductor L4, and the other end is connected to capacitor E1.

8. The circuit according to claim 1, characterized in that, A drain turn-off control circuit is also connected between the second-stage signal amplification circuit and the output matching circuit, wherein: The drain-level shutdown control circuit is used to amplify the shutdown pulse signal output through the third IO port JP3 of the FPGA in two stages, and apply the amplified signal to the drain of the MOSFET M2. By changing the operating state of the MOSFET M2, the power supply of the MOSFET M2 can be turned off at the effective signal transmission time, forcing the output signal to decay rapidly and avoiding signal tailing distortion.

9. The circuit according to claim 8, characterized in that, The drain-level turn-off control circuit includes transformer RF1, transformer RF2, capacitor C20, capacitor C21, resistor R12, resistor R13, resistor R14, adjustable resistor RP1, transistor Q1, and MOSFET M3, wherein: The input terminal of transformer RF1 is connected to the third IO port JP3 of FPGA. The first output terminal of transformer RF1 is connected to the base of transistor Q1, resistor R13, and adjustable resistor RP1 via capacitor C20 and resistor R12, respectively. The other end of resistor R13 is connected to the second output terminal of transformer RF1 and to the emitter of transistor Q1 via resistor R14; The end of resistor R14 connected to the emitter of transistor Q1 is also connected to the first input terminal of transformer RF2 via capacitor C21, and the end of resistor R13 connected to resistor R14 is also connected to the second input terminal of transformer RF2. The first output terminal of transformer RF2 is connected to the drain of MOSFET M2 and the gate of MOSFET M3, respectively. The second output terminal of transformer RF2 is connected to the gate of MOSFET M3, and the drain of MOSFET M3 is connected to the power supply of the second-stage MOSFET drain.

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