Low dropout linear regulator

Abstract

Embodiments of this disclosure provide a low-dropout linear regulator. The low-dropout linear regulator includes an error amplifier, an output power transistor, a voltage divider feedback circuit, and a voltage buffer. The non-inverting input of the error amplifier is coupled to a first terminal of the voltage divider feedback circuit, the inverting input of the error amplifier is coupled to a reference signal terminal, and the output of the error amplifier is coupled to the voltage buffer via a first node. The voltage buffer is coupled to the control terminal of the output power transistor via a second node. The first terminal of the output power transistor is coupled to a first voltage terminal, and the second terminal of the output power transistor is coupled to a second terminal of the voltage divider feedback circuit and the output terminal of the low-dropout linear regulator. The voltage buffer is configured to control the voltage difference between the first and second nodes.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to low-dropout linear regulators. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in integrated circuits to provide the power supply voltage required inside the integrated circuit. Figure 1 An exemplary circuit diagram of an LDO 100 is shown. (e.g.) Figure 1 As shown, the LDO 100 may include an error amplifier, an output power transistor Mpout, a first resistor R1, and a second resistor R2. The output terminal out of the LDO 100 can be coupled to a load (in... Figure 1 The diagram shows the load current source Iout. For an ultra-low quiescent current LDO with a quiescent current in the hundreds of nanoamps range, the sum of the resistances of the first resistor R1 and the second resistor R2 is typically greater than 100 MΩ. The width-to-length ratio of the LDO's output power transistor Mpout is usually large to provide the LDO's output current and low output impedance. The source-drain current Ids of the output power transistor Mpout is approximately equal to the load current Iout (i.e., the current of the load current source Iout). When the load current Iout = 0 A, the source-drain current Ids of the output power transistor Mpout is typically only tens of nanoamps, at which point the source-gate voltage Vsg of the output power transistor Mpout is very small, close to 0 V. Figure 1 In the example, the output power transistor Mpout is a PMOS transistor. When the PMOS transistor is in a fast process corner or at high temperatures, the source-gate voltage Vsg of the output power transistor Mpout will become smaller, and the gate (node ​​pgate) voltage of the output power transistor Mpout may be approximately equal to the source voltage Vcc of the output power transistor Mpout. In ultra-low quiescent current LDOs, the ultra-low quiescent current makes the LDO very suitable for low-power applications. Ultra-low quiescent current LDOs include low-voltage ultra-low quiescent current LDOs. Low-voltage ultra-low quiescent current LDOs can accept lower operating voltages and are used in applications with lower input voltages. Summary of the Invention

[0003] The embodiments described herein provide a low-dropout linear regulator.

[0004] According to a first aspect of this disclosure, a low-dropout linear regulator is provided. The low-dropout linear regulator includes: an error amplifier, an output power transistor, a voltage divider feedback circuit, and a voltage buffer. The non-inverting input of the error amplifier is coupled to a first terminal of the voltage divider feedback circuit. The inverting input of the error amplifier is coupled to a reference signal terminal. The output of the error amplifier is coupled to the voltage buffer via a first node. The voltage buffer is coupled to the control terminal of the output power transistor via a second node. The first terminal of the output power transistor is coupled to a first voltage terminal. The second terminal of the output power transistor is coupled to a second terminal of the voltage divider feedback circuit and the output terminal of the low-dropout linear regulator. The voltage buffer is configured to control the voltage difference between the first node and the second node. The voltage buffer includes: a first current source circuit, a first control circuit, a current mirror circuit, a load current mirror circuit, and a second control circuit. The first current source circuit is configured to provide a first constant current from its output terminal to the first control circuit. The first control circuit is configured to control the voltage difference between the first node and the second node, and to provide a first distribution current to the current mirror circuit via a third node based on the voltage of the first node, the voltage of the second node, and the first constant current. A current mirror circuit is configured to generate a first mirror current of the first distribution current and provide the first mirror current to the second control circuit. A load current mirror circuit is configured to generate a second mirror current based on the load current of the low-dropout linear regulator and provide the second mirror current to the second control circuit via a fourth node. The second control circuit is configured to control the voltage difference between the first node and the second node based on the first mirror current and the second mirror current.

[0005] In some embodiments of this disclosure, the first control circuit includes a first transistor and a second transistor. The control electrode of the first transistor is coupled to a first node. The first electrode of the first transistor is coupled to the output terminal of a first current source circuit. The second electrode of the first transistor is coupled to a third node. The control electrode of the second transistor is coupled to the second electrode of the second transistor and a second node. The first electrode of the second transistor is coupled to the output terminal of the first current source circuit.

[0006] In some embodiments of this disclosure, the aspect ratio of the first transistor is N times that of the second transistor. N is greater than 1.

[0007] In some embodiments of this disclosure, the current mirror circuit includes a third transistor, a fourth transistor, and a voltage control circuit. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the control electrode of the fourth transistor. The first electrode of the third transistor is coupled to a first voltage terminal. The second electrode of the third transistor is coupled to a third node. The first electrode of the fourth transistor is coupled to the first voltage terminal. The second electrode of the fourth transistor is coupled to a first terminal of the voltage control circuit. The second terminal of the voltage control circuit is coupled to a second node. The voltage control circuit is configured to control the voltage at the second electrode of the fourth transistor such that the fourth transistor operates in the linear region and to transmit the source-drain current of the fourth transistor to the second node.

[0008] In some embodiments of this disclosure, the aspect ratio of the fourth transistor is K times that of the third transistor. K is greater than 1.

[0009] In some embodiments of this disclosure, the voltage control circuit includes a fifth transistor, a sixth transistor, and a second current source circuit. The control electrode of the fifth transistor is coupled to the output terminal of the second current source circuit. The first electrode of the fifth transistor is coupled to the second electrode of a fourth transistor. The second electrode of the fifth transistor is coupled to a second node. The control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the output terminal of the second current source circuit. The first electrode of the sixth transistor is coupled to a first voltage terminal. The second current source circuit is configured to provide a second constant current from the output terminal of the second current source circuit to the sixth transistor.

[0010] In some embodiments of this disclosure, the aspect ratio of the fifth transistor is J times that of the sixth transistor. J is greater than 1.

[0011] In some embodiments of this disclosure, the load current mirror circuit includes a seventh transistor. The control electrode of the seventh transistor is coupled to the control electrode of the output power transistor. The first electrode of the seventh transistor is coupled to a first voltage terminal. The second electrode of the seventh transistor is coupled to a fourth node.

[0012] In some embodiments of this disclosure, the aspect ratio of the output power transistor is m times the aspect ratio of the seventh transistor. m is greater than 1.

[0013] In some embodiments of this disclosure, the second control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor. The control electrode of the eighth transistor is coupled to a first node. The first electrode of the eighth transistor is coupled to a fourth node. The second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the ninth transistor. The control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor. The first electrode of the ninth transistor is coupled to a second voltage terminal. The first electrode of the tenth transistor is coupled to a second voltage terminal. The second electrode of the tenth transistor is coupled to the control electrode and the second electrode of the eleventh transistor. The control electrode of the eleventh transistor is coupled to the control electrode of the output power transistor. The first electrode of the eleventh transistor is coupled to the fourth node.

[0014] In some embodiments of this disclosure, the low-dropout linear regulator is a low-voltage ultra-low quiescent current (LDO).

[0015] According to a second aspect of this disclosure, a low-dropout linear regulator is provided. The low-dropout linear regulator includes: an error amplifier, an output power transistor, a first resistor, a second resistor, a first current source circuit, a second current source circuit, and a first to an eleventh transistor. The non-inverting input of the error amplifier is coupled to the second terminal of the first resistor and the first terminal of the second resistor. The inverting input of the error amplifier is coupled to a reference signal terminal. The output of the error amplifier is coupled to the control terminals of the first and eighth transistors. The control terminal of the output power transistor is coupled to the control terminals of the second, seventh, and eleventh transistors. The first terminal of the output power transistor is coupled to a first voltage terminal. The second terminal of the output power transistor is coupled to the first terminal of the first resistor and the output terminal of the low-dropout linear regulator. The second terminal of the second resistor is coupled to a second voltage terminal. The first terminal of the first transistor is coupled to the output terminal of the first current source circuit. The second terminal of the first transistor is coupled to the control terminal and the second terminal of the third transistor. The control terminal and the second terminal of the second transistor are coupled to the second terminal of the fifth transistor. The first terminal of the second transistor is coupled to the output terminal of the first current source circuit. A first current source circuit is configured to provide a first constant current from its output to a first transistor and a second transistor. The first terminal of a third transistor is coupled to a first voltage terminal. The control terminal of a fourth transistor is coupled to the control terminal of the third transistor. The first terminal of the fourth transistor is coupled to the first voltage terminal. The second terminal of the fourth transistor is coupled to the first terminal of a fifth transistor. The control terminal of the fifth transistor is coupled to the control terminal and the second terminal of a sixth transistor. The second terminal of the sixth transistor is coupled to the output of a second current source circuit. The first terminal of the sixth transistor is coupled to the first voltage terminal. A second current source circuit is configured to provide a second constant current from its output to the sixth transistor. The first terminal of a seventh transistor is coupled to the first voltage terminal. The second terminal of the seventh transistor is coupled to the first terminals of both an eighth transistor and an eleventh transistor. The second terminal of the eighth transistor is coupled to the control terminal and the second terminal of a ninth transistor. The control terminal of the ninth transistor is coupled to the control terminal of a tenth transistor. The first terminal of the ninth transistor is coupled to a second voltage terminal. The first terminal of the tenth transistor is coupled to a second voltage terminal. The second terminal of the tenth transistor is coupled to the control terminal and the second terminal of the eleventh transistor.

[0016] In some embodiments of this disclosure, the aspect ratio of the first transistor is N times that of the second transistor. N is greater than 1.

[0017] In some embodiments of this disclosure, the aspect ratio of the fourth transistor is K times that of the third transistor. K is greater than 1.

[0018] In some embodiments of this disclosure, the aspect ratio of the fifth transistor is J times that of the sixth transistor. J is greater than 1.

[0019] In some embodiments of this disclosure, the aspect ratio of the output power transistor is m times the aspect ratio of the seventh transistor. m is greater than 1.

[0020] In some embodiments of this disclosure, the low-dropout linear regulator is a low-voltage ultra-low quiescent current (LDO). Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0022] Figure 1 This is an exemplary circuit diagram of an LDO;

[0023] Figure 2 This is an exemplary circuit diagram of an error amplifier;

[0024] Figure 3 This is an exemplary circuit diagram of a low-dropout linear regulator;

[0025] Figure 4 This is a schematic block diagram of a low-dropout linear regulator according to embodiments of the present disclosure; and

[0026] Figure 5 This is an exemplary circuit diagram of a low-dropout linear regulator according to an embodiment of the present disclosure.

[0027] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0030] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily MOS (Metal Oxide Semiconductor) transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0031] Figure 2 It shows Figure 1 An exemplary circuit diagram of the error amplifier in the example. Figure 2 In the example, transistors Mp+, Mp-, Mp1, Mp2, Mp1c, and Mp2c are PMOS transistors. Transistors Mn1c, Mn2c, Mn1, and Mn2 are NMOS transistors. The control electrode of transistor Mp+ is coupled to the feedback signal terminal V. FB The control electrode of transistor Mp- is coupled to the reference signal terminal V. REF The current source It provides a constant current It to transistors Mp+ and Mp-. The drains of transistors Mp2c and Mn2c are coupled to the node pgate. The sources of transistors Mp1 and Mp2 are coupled to the voltage terminal Vcc.

[0032] refer to Figure 1 When the load current Iout = 0A, the gate (node ​​pgate) voltage of the output power transistor Mpout (which can be represented by Vpgate in this context) may be approximately equal to the source voltage Vcc of the output power transistor Mpout. When the voltage difference between Vpgate and Vcc is very small, Figure 2The transistors Mp2 and Mp2c inside the error amplifier will both enter the linear region, which will reduce the output impedance of the error amplifier and thus affect its DC open-loop gain Av. This could cause the open-loop gain Av to drop to a fraction of its original value, or even a fraction of its original value. Because (V FB –V REF )×Av=Vpgate, when the open-loop gain Av decreases, V FB –V REF The difference becomes larger, which makes the output voltage accuracy of the LDO very poor.

[0033] In response to the above problems, Figure 3 A low-dropout linear regulator 300 is proposed. For example... Figure 3 As shown, a voltage buffer is inserted between the output terminal eaout of the error amplifier and the gate (node ​​pgate) of the output power transistor Mpout. This is intended to ensure that when the voltage difference between Vpgate and Vcc is very small, the voltage Veaout at the output terminal eaout of the error amplifier maintains an appropriate voltage difference with Vpgate, thus preventing... Figure 2 The transistors Mp2 and Mp2c inside the error amplifier enter the linear region.

[0034] Figure 3 The voltage buffer in the LDO consists of a current source Is and a transistor Mpb. The current source Is provides current Is to the transistor Mpb. The transistor Mpb can be implemented using a PMOS transistor. The voltage at the output terminal eaout of the error amplifier is Veaout = Vpgate – Vsg_Mpb, where Vsg_Mpb represents the source-gate voltage of the transistor Mpb. To avoid Veaout being close to Vpgate, Vsg_Mpb can be increased. The magnitude of Vsg_Mpb depends on the current Is and the aspect ratio of the transistor Mpb. To increase Vsg_Mpb, the current Is can be increased or the aspect ratio of the transistor Mpb can be decreased. For ultra-low quiescent current LDOs, the current Is cannot be very large. However, decreasing the aspect ratio of the transistor Mpb will result in a large impedance at the pgate node. This impedance, combined with the large capacitance at the pgate node, forms a pole that degrades the stability of the LDO. Therefore, in Figure 3 In the example, increasing Vsg_Mpb cannot prevent Veaout from being similar to Vpgate.

[0035] also, Figure 3 The minimum operating voltage Vcc must be greater than Vsg_Mpout( Figure 3 The source-gate voltage of transistor Mpout in the transistor) + Vsg_Mpb( Figure 3 The source-gate voltage of transistor Mpb in the transistor is +Vdsat_Mn2( Figure 2The overdrive voltage of transistor Mn2 in the transistor is +Vdsat_Mn2c. Figure 2 (The overdrive voltage of transistor Mn2c). Assuming the source-gate voltages of transistors Mpout and Mpb need to reach 0.8V, and the overdrive voltages of transistors Mn2 and Mn2c need to reach 0.2V, then Vcc needs to be above 2.0V. Figure 3 The circuit structure is not suitable for low-voltage LDOs.

[0036] Embodiments of this disclosure present a low-dropout linear regulator. Figure 4 A schematic block diagram of a low-dropout linear regulator 400 according to an embodiment of the present disclosure is shown. Figure 4 As shown, the low-dropout linear regulator 400 may include: an error amplifier, an output power transistor Mpout, a voltage divider feedback circuit 460, and a voltage buffer. The non-inverting input of the error amplifier can be coupled to the first terminal of the voltage divider feedback circuit 460. The inverting input of the error amplifier can be coupled to the reference signal terminal V. REF The output of the error amplifier can be coupled to a voltage buffer via a first node eaout. The voltage buffer can be coupled to the control terminal of the output power transistor Mpout via a second node pgate. The first terminal of the output power transistor Mpout can be coupled to a first voltage terminal V1. The second terminal of the output power transistor Mpout can be coupled to the second terminal of the voltage divider feedback circuit and the output terminal out of the low-dropout linear regulator. The voltage divider feedback circuit 460 may include: a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 (as the second terminal of the voltage divider feedback circuit 460) is coupled to the output terminal out of the low-dropout linear regulator. The second terminal of the first resistor R1 (as the first terminal of the voltage divider feedback circuit 460) is coupled to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is coupled to a second voltage terminal V2. The output terminal out of the low-dropout linear regulator can be coupled to an external load. Figure 4 The load current source Iout is shown in the diagram. A voltage buffer can be configured to control the voltage difference between the first node eaout and the second node pgate (the voltage difference discussed herein refers to the absolute value of the voltage difference) such that the voltage difference between the voltage Veaout of the first node eaout and the voltage V1 of the first terminal of the output power transistor Mpout is greater than a first voltage threshold. This first voltage threshold is set to avoid… Figure 2 The transistors Mp2 and Mp2c inside the error amplifier enter the linear region.

[0037] exist Figure 4 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The output power transistor Mpout is implemented using a PMOS transistor.

[0038] The voltage buffer may include: a first current source circuit 410, a first control circuit 420, a current mirror circuit 430, a load current mirror circuit 440, and a second control circuit 450.

[0039] The first current source circuit 410 may be coupled to the first control circuit 420. The first current source circuit 410 may be configured to provide a first constant current I1 from the output of the first current source circuit 410 to the first control circuit 420.

[0040] The first control circuit 420 can be coupled to the first current source circuit 410, the current mirror circuit 430, the load current mirror circuit 440, the second control circuit 450, the first node eaout, and the second node pgate. The first control circuit 420 can be configured to: when the voltage difference (|Vpgate-V1|) between the voltage Vpgate of the second node and the voltage V1 of the first terminal of the output power transistor Mpout is less than a second voltage threshold, control the voltage difference between the first node eaout and the second node pgate to be greater than a third voltage threshold, so that the voltage difference between Veaout and V1 is greater than the first voltage threshold. This avoids... Figure 2 The transistors Mp2 and Mp2c inside the error amplifier enter the linear region. The first control circuit 420 can also be configured to provide a first distribution current I11 to the current mirror circuit 430 via the third node N3 based on the voltage of the first node eaout, the voltage of the second node pgate, and the first constant current I1.

[0041] The current mirror circuit 430 can be coupled to the first control circuit 420, the load current mirror circuit 440, the second control circuit 450, the second node pgate, and the first voltage terminal V1. The current mirror circuit 430 can be configured to generate a first mirror current I11' of the first distribution current I11 and provide the first mirror current I11' to the second control circuit 450.

[0042] The load current mirror circuit 440 can be coupled to the first control circuit 420, the current mirror circuit 430, the second control circuit 450, the second node pgate, and the first voltage terminal V1. The load current mirror circuit 440 can be configured to generate a second mirror current Iout' based on the load current Iout of the low dropout linear regulator 400, and provide the second mirror current Iout' to the second control circuit 450 via the fourth node N4.

[0043] The second control circuit 450 can be coupled to the first control circuit 420, the current mirror circuit 430, the load current mirror circuit 440, the first node eaout, and the second node pgate. The second control circuit 450 can be configured to: when the voltage difference between the second node pgate voltage Vpgate and the voltage V1 at the first terminal of the output power transistor Mpout is greater than a second voltage threshold, control the voltage difference between the first node eaout and the second node pgate to be greater than a fourth voltage threshold and less than a third voltage threshold based on the first mirror current I11' and the second mirror current Iout', so that the voltage difference between Veaout and V1 is greater than the first voltage threshold. This avoids... Figure 2 The transistors Mp2 and Mp2c inside the error amplifier enter the linear region.

[0044] Figure 5 An exemplary circuit diagram of a low-dropout linear regulator 500 according to an embodiment of the present disclosure is shown. Figure 5 As shown, the first current source circuit 510 may include a current source I1. The first control circuit 520 may include a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to a first node eaout. The first electrode of the first transistor M1 is coupled to the output terminal of the first current source circuit 510. The second electrode of the first transistor M1 is coupled to a third node N3. The control electrode of the second transistor M2 is coupled to the second electrode of the second transistor M2 and a second node pgate. The first electrode of the second transistor M2 is coupled to the output terminal of the first current source circuit 510. The first current source circuit 510 can provide a first constant current I1 to the first transistor M1 and the second transistor M2.

[0045] The current mirror circuit 530 may include a third transistor M3, a fourth transistor M4, and a voltage control circuit 531. The control electrode of the third transistor M3 is coupled to the second electrode of the third transistor M3 and the control electrode of the fourth transistor M4. The first electrode of the third transistor M3 is coupled to a first voltage terminal V1. The second electrode of the third transistor M3 is coupled to a third node N3. The first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1. The second electrode of the fourth transistor M4 is coupled to the first terminal of the voltage control circuit 531. The second terminal of the voltage control circuit 531 is coupled to a second node pgate. The voltage control circuit 531 may be configured to control the voltage at the second electrode of the fourth transistor M4 so that the fourth transistor M4 operates in the linear region and to transfer the source-drain current of the fourth transistor M4 to the second node pgate.

[0046] The voltage control circuit 531 may include a fifth transistor M5, a sixth transistor M6, and a second current source circuit. The control electrode of the fifth transistor M5 is coupled to the output terminal of the second current source circuit. The first electrode of the fifth transistor M5 (serving as the first terminal of the voltage control circuit 531) is coupled to the second electrode of the fourth transistor M4. The second electrode of the fifth transistor M5 (serving as the second terminal of the voltage control circuit 531) is coupled to the second node pgate. The control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6 and the output terminal of the second current source circuit. The first electrode of the sixth transistor M6 is coupled to a first voltage terminal V1. The second current source circuit may include a current source I2 and is configured to provide a second constant current I2 from the output terminal of the second current source circuit to the sixth transistor M6.

[0047] The load current mirror circuit 540 may include a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the control electrode of the output power transistor Mpout. The first electrode of the seventh transistor M7 is coupled to the first voltage terminal V1. The second electrode of the seventh transistor M7 is coupled to the fourth node N4. Thus, the seventh transistor M7 and the output power transistor Mpout form a current mirror.

[0048] The second control circuit 550 may include: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The control electrode of the eighth transistor M8 is coupled to the first node eaout. The first electrode of the eighth transistor M8 is coupled to the fourth node N4. The second electrode of the eighth transistor M8 is coupled to the control electrode and the second electrode of the ninth transistor M9. The control electrode of the ninth transistor M9 is coupled to the control electrode of the tenth transistor M10. The first electrode of the ninth transistor M9 is coupled to the second voltage terminal V2. The first electrode of the tenth transistor M10 is coupled to the second voltage terminal V2. The second electrode of the tenth transistor M10 is coupled to the control electrode and the second electrode of the eleventh transistor M11. The control electrode of the eleventh transistor M11 is coupled to the control electrode of the output power transistor Mpout. The first electrode of the eleventh transistor M11 is coupled to the fourth node N4. In the second control circuit 550, the ninth transistor M9 and the tenth transistor M10 can form a current mirror.

[0049] exist Figure 5In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, eleventh transistor M11, and the output power transistor Mpout are PMOS transistors. The first transistor M1, second transistor M2, ninth transistor M9, and tenth transistor M10 are NMOS transistors. The aspect ratio of the first transistor M1 is N times that of the second transistor M2. The aspect ratio of the fourth transistor M4 is K times that of the third transistor M3. The aspect ratio of the fifth transistor M5 is J times that of the sixth transistor M6. The aspect ratio of the output power transistor Mpout is m times that of the seventh transistor M7. Where N, K, J, and m are all greater than 1.

[0050] When the load current Iout = 0A or is less than the first current threshold, Vpgate and V1 are approximately equal (as mentioned above, (|Vpgate - V1|) is less than the second voltage threshold at this time). Here, the first current threshold is the current value that makes the gate voltage of the output power transistor Mpout approximately equal to the source voltage. At this time, the eleventh transistor M11 is turned off, and the second transistor M2 is turned on. The substrates of the first transistor M1 and the second transistor M2 can be grounded to increase the turn-on voltage Vthn of the first transistor M1 and the second transistor M2 by utilizing the body effect. Even if the first transistor M1 and the second transistor M2 are in a fast process corner or at high temperature, the gate-source voltage Vgs of the first transistor M1 and the second transistor M2 will be relatively large, causing both the first transistor M1 and the second transistor M2 to operate in the saturation region.

[0051] As described above, the aspect ratio of the fifth transistor M5 is J times that of the sixth transistor M6, meaning the aspect ratio of the sixth transistor M6 is less than that of the fifth transistor M5. Therefore, the source-gate voltage Vsg_M5 of the fifth transistor M5 is less than the source-gate voltage Vsg_M6 of the sixth transistor M6. The drain voltage Vd_M4 of the fourth transistor M4 is V1 - (Vsg_M6 - Vsg_M5). By controlling the ratio J of the aspect ratio of the fifth transistor M5 to that of the sixth transistor M6, (Vsg_M6 - Vsg_M5) can be made less than a predetermined value. Thus, the value of Vd_M4 can be controlled to make the fourth transistor M4 operate in the linear region. Here, the predetermined value is the source-drain voltage Vsd_M4 of the fourth transistor M4 when it operates in the linear region. In this case, by adjusting the width-to-length ratio coefficient K of the third transistor M3 and the fourth transistor M4, the drain-source currents in the third transistor M3 and the fourth transistor M4 can be made equal. Therefore, the first constant current I1 is evenly distributed in the third transistor M3 and the fourth transistor M4, and thus also evenly distributed in the first transistor M1 and the second transistor M2.

[0052] As described above, the aspect ratio of the first transistor M1 is N times that of the second transistor M2, so Vgs_M2 > Vgs_M1, where Vgs_M2 represents the gate-source voltage of the second transistor M2, and Vgs_M1 represents the gate-source voltage of the first transistor M1. The output terminal voltage Veaout of the error amplifier is Veaout = Vpgate - Vgs_M2 + Vgs_M1 = Vpgate - (Vgs_M2 - Vgs_M1). Here, (Vgs_M2 - Vgs_M1) > 0V. The magnitude of (Vgs_M2 - Vgs_M1) is related to the aspect ratio of the first transistor M1 and the aspect ratio of the second transistor M2. Adjusting the magnitude of N can make (Vgs_M2 - Vgs_M1) greater than the following difference, and this difference makes Veaout be controlled to be small enough (as described above, when (|Vpgate - V1|) is less than the second voltage threshold, the voltage difference between Veaout and Vpgate is greater than the third voltage threshold) so that the transistors Mp2c and Mp2 in the error amplifier both operate in the saturation region. This can increase the output impedance of the error amplifier, thereby increasing the DC open-loop gain Av of the error amplifier, and ensuring that the output voltage accuracy of the low-dropout linear regulator 500 does not deteriorate under no-load or light-load conditions. At this time, Veaout and Vpgate are relatively close to V1, and the eighth transistor M8 and the eleventh transistor M11 are cut off. Therefore, no current flows through the eighth transistor M8 and the eleventh transistor M11.

[0053] When the load current Iout gradually increases to be greater than the first current threshold and less than the second current threshold, Vpgate gradually decreases. Because Veaout = Vpgate - (Vgs_M2 - Vgs_M1), Veaout also decreases accordingly. Because Veaout < Vpgate, the eighth transistor M8 will conduct first, and the eleventh transistor M11 remains cut off. Here, the second current threshold is the load current value that makes the eighth transistor M8 conduct and the eleventh transistor M11 cut off.

[0054] As described above, the aspect ratio of the output power transistor Mpout is m times that of the seventh transistor M7. By setting the value of m, the current Ids_M7 when the seventh transistor M7 is critically saturated can be made Ids_M7 = Iout / m <= I1×1 / x. Here, x is greater than 2, and Ids_M7 is equivalent to Figure 4The second mirror current Iout' in []. When the eighth transistor M8 is turned on, the current Ids_M7 can flow into the ninth transistor M9. Since the ninth transistor M9 and the tenth transistor M10 form a current mirror, the maximum current in the tenth transistor M10 is also I1×1 / x. Because the eleventh transistor M11 is turned off, the current of the tenth transistor M10 is only provided by the fourth transistor M4. The current of the fourth transistor M4 is I1×1 / 2 and is distributed to the tenth transistor M10 and the second transistor M2. Therefore, the current of the second transistor M2 is at least equal to I1×1 / 2–I1×1 / x. And the current of the first transistor M1 is I1×1 / 2. Although the current of the first transistor M1 is greater than that of the second transistor M2, the aspect ratio of the first transistor M1 is N times that of the second transistor M2. By setting N, (Vgs_M2 - Vgs_M1)>0V can still be achieved. Therefore, Veaout is still less than Vpgate, but the difference between Veaout and Vpgate gradually becomes smaller.

[0055] When the load current Iout gradually increases to be greater than the second current threshold, Vpgate continues to decrease (as described above, at this time, (|Vpgate - V1|) is greater than the second voltage threshold) until the eleventh transistor M11 is turned on. Assume that at this time, the current Ids_M7 of the seventh transistor M7 = Iout / m >= I1×y, where y is greater than or equal to 2. Then the difference between Veaout and Vpgate is close to 0V (for example, greater than the fourth voltage threshold and less than the third voltage threshold). Here, the fact that the difference between Veaout and Vpgate is close to 0V can be proved by contradiction.

[0056] Assume that the voltage difference between the voltage Veaout of the first node eaout and the voltage Vpgate of the second node pgate exceeds the third threshold voltage at this time, Veaout < Vpgate. The current Ids_M7 of the seventh transistor M7 all flows into the eighth transistor M8 and the ninth transistor M9. Since the ninth transistor M9 and the tenth transistor M10 form a current mirror, the current in the tenth transistor M10 is also Ids_M7 (Ids_M7 >= I1×y). The current in the tenth transistor M10 can only be provided by the fourth transistor M4, but the maximum current that the fourth transistor M4 can provide is I1×1 / 2. Therefore, the tenth transistor M10 will pull down Vpgate and make the tenth transistor M10 enter the linear region. But at this time, Vpgate will be much lower than Veaout, and the eleventh transistor M11 is turned on, so that Ids_M7 all flows into the eleventh transistor M11, which contradicts the assumption that Ids_M7 all flows into the eighth transistor M8 and the ninth transistor M9. Therefore, when the load current Iout is greater than the second current threshold, the difference between Veaout and Vpgate is close to 0V.

[0057] In this scenario, the current in the first transistor M1 is (N / N+1)×I1, and the current in the second transistor M2 is (1 / N+1)×I1. If N is large, the current in the second transistor M2 can be ignored, thus the current in the first transistor M1 is approximately I1, and therefore the current I11 in the third transistor M3 is approximately I1. Since the third transistor M3 and the fourth transistor M4 form a current mirror, the maximum current I11' in the fourth transistor M4 is also I1. The current I11' (I11' = I1) in the fourth transistor M4 is supplied to the tenth transistor M10. Since the ninth transistor M9 and the tenth transistor M10 form a current mirror, the total current supplied to the ninth transistor M9 and the tenth transistor M10 is equally divided. When Ids_Mp7 = I1×y, the total current supplied to the ninth transistor M9 and the tenth transistor M10 is the current I1×y from the seventh transistor M7 and the current I1 from the fourth transistor M4, i.e., I1×(1+y). Therefore, the current in both the ninth transistor M9 and the tenth transistor M10 is I1×(1+y) / 2. Since part of the current I1 in the tenth transistor M10 is provided by the fourth transistor M4, the current in the eleventh transistor M11 is I1×(1+y) / 2-I1. The current in the eighth transistor M8 is equal to the current in the ninth transistor M9, so the currents in the eighth transistor M8 and the eleventh transistor M11 differ by I1. By setting the width-to-length ratio of the eighth transistor M8 and the eleventh transistor M11, it can be made that (Vpgate – Veaout) = I1 / gm, where gm is the transconductance of the eighth transistor M8 and the eleventh transistor M11. Since I1 is relatively small, setting gm can make Veaout approximately equal to Vpgate. As the load current Iout increases, the current Ids_M7 (i.e., Iout') of the seventh transistor M7 also increases. Thus, the transconductance gm of the eighth transistor M8 and the eleventh transistor M11 also increases, making Veaout closer to Vpgate. Therefore, if the load current Iout continues to increase and Vpgate continues to decrease, Veaout will still be approximately equal to Vpgate. In this way, transistors Mp2 and Mp2c in the error amplifier will not enter the linear region, and the error amplifier will still maintain its high output impedance and high gain.

[0058] Furthermore, the impedance of the second node pgate is the parallel combination of the reciprocal of the transconductance of the second transistor M2 (1 / gm_M2) and the reciprocal of the transconductance of the eleventh transistor M11 (1 / gm_M11), and the transconductance gm_M11 of the eleventh transistor M11 varies with the load current Iout. The larger the load current Iout, the larger the transconductance gm_M11 of the eleventh transistor M11, thus making the impedance of the second node pgate smaller. This dynamically compensates for the impedance of the second node pgate, thereby improving the stability of the LDO.

[0059] Furthermore, the minimum operating voltage V1 of the low-dropout linear regulator according to embodiments of this disclosure only needs to be greater than Vsg_Mpout( Figure 4 and Figure 5 The source-gate voltage of transistor Mpout in the transistor) + Vdsat_Mn2( Figure 2 The overdrive voltage of transistor Mn2 in the transistor is +Vdsat_Mn2c. Figure 2 (The overdrive voltage of transistor Mn2c). Assuming the source-gate voltage of transistor Mpout needs to reach 0.8V, and the overdrive voltage of transistors Mn2 and Mn2c needs to reach 0.2V, then V1 only needs to reach 1.2V. Figure 4 and Figure 5 Its structure is suitable for low-voltage, ultra-low quiescent current LDO circuits.

[0060] In summary, the low dropout linear regulator according to the embodiments of this disclosure is suitable for low-voltage ultra-low quiescent current LDOs, can maintain the high output impedance and high gain of the error amplifier, improve the accuracy of the LDO output voltage, and improve the stability of the LDO.

[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0062] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0063] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0064] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A low-dropout linear regulator, comprising: Error amplifier, output power transistor, voltage divider feedback circuit, and voltage buffer; Wherein, the non-inverting input terminal of the error amplifier is coupled to the first terminal of the voltage divider feedback circuit, the inverting input terminal of the error amplifier is coupled to the reference signal terminal, and the output terminal of the error amplifier is coupled to the voltage buffer via the first node; The voltage buffer is coupled to the control electrode of the output power transistor via a second node; The first terminal of the output power transistor is coupled to the first voltage terminal, and the second terminal of the output power transistor is coupled to the second terminal of the voltage divider feedback circuit and the output terminal of the low dropout linear regulator. The voltage buffer is configured to control the voltage difference between the first node and the second node; The voltage buffer includes: a first current source circuit, a first control circuit, a current mirror circuit, a load current mirror circuit, and a second control circuit. The first current source circuit is configured to provide a first constant current to the first control circuit from the output terminal of the first current source circuit; The first control circuit is configured to control the voltage difference between the first node and the second node, and to provide a first distribution current to the current mirror circuit via the third node based on the voltage of the first node, the voltage of the second node, and the first constant current. The current mirror circuit is configured to generate a first mirror current of the first distributed current and to provide the first mirror current to the second control circuit. The load current mirror circuit is configured to generate a second mirror current based on the load current of the low dropout linear regulator, and to provide the second mirror current to the second control circuit via the fourth node; The second control circuit is configured to control the voltage difference between the first node and the second node based on the first mirror current and the second mirror current.

2. The low-dropout linear regulator according to claim 1, wherein, The first control circuit includes: a first transistor and a second transistor. Wherein, the control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the output terminal of the first current source circuit, and the second electrode of the first transistor is coupled to the third node; The control electrode of the second transistor is coupled to the second terminal of the second transistor and the second node, and the first terminal of the second transistor is coupled to the output terminal of the first current source circuit.

3. The low-dropout linear regulator according to claim 2, wherein, The aspect ratio of the first transistor is N times that of the second transistor, where N is greater than 1.

4. The low-dropout linear regulator according to claim 1, wherein, The current mirror circuit includes: a third transistor, a fourth transistor, and a voltage control circuit. Wherein, the control electrode of the third transistor is coupled to the second electrode of the third transistor and the control electrode of the fourth transistor, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the third node; The first terminal of the fourth transistor is coupled to the first voltage terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the voltage control circuit. The second terminal of the voltage control circuit is coupled to the second node. The voltage control circuit is configured to control the voltage of the second terminal of the fourth transistor so that the fourth transistor operates in the linear region and to pass the source-drain current of the fourth transistor to the second node.

5. The low-dropout linear regulator according to claim 4, wherein, The aspect ratio of the fourth transistor is K times that of the third transistor, where K is greater than 1.

6. The low-dropout linear regulator according to claim 4 or 5, wherein, The voltage control circuit includes: a fifth transistor, a sixth transistor, and a second current source circuit. Wherein, the control electrode of the fifth transistor is coupled to the output terminal of the second current source circuit, the first electrode of the fifth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is coupled to the second node; The control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the output terminal of the second current source circuit, and the first electrode of the sixth transistor is coupled to the first voltage terminal; The second current source circuit is configured to provide a second constant current from the output terminal of the second current source circuit to the sixth transistor.

7. The low-dropout linear regulator according to claim 6, wherein, The aspect ratio of the fifth transistor is J times that of the sixth transistor, where J is greater than 1.

8. The low-dropout linear regulator according to claim 1, wherein, The load current mirror circuit includes: a seventh transistor, The control electrode of the seventh transistor is coupled to the control electrode of the output power transistor, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the fourth node.

9. The low-dropout linear regulator according to claim 1, wherein, The second control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor. Wherein, the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the fourth node, and the second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the ninth transistor; The control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, and the first electrode of the ninth transistor is coupled to the second voltage terminal; The first terminal of the tenth transistor is coupled to the second voltage terminal, and the second terminal of the tenth transistor is coupled to the control terminal and the second terminal of the eleventh transistor; The control electrode of the eleventh transistor is coupled to the control electrode of the output power transistor, and the first electrode of the eleventh transistor is coupled to the fourth node.

10. A low-dropout linear regulator, comprising: Error amplifier, output power transistor, first resistor, second resistor, first current source circuit, second current source circuit, and first to eleventh transistors; Wherein, the non-inverting input terminal of the error amplifier is coupled to the second terminal of the first resistor and the first terminal of the second resistor, the inverting input terminal of the error amplifier is coupled to the reference signal terminal, and the output terminal of the error amplifier is coupled to the control terminal of the first transistor and the control terminal of the eighth transistor. The control terminal of the output power transistor is coupled to the control terminals of the second transistor, the seventh transistor, and the eleventh transistor. The first terminal of the output power transistor is coupled to the first voltage terminal, and the second terminal of the output power transistor is coupled to the first terminal of the first resistor and the output terminal of the low dropout linear regulator. The second end of the second resistor is coupled to the second voltage terminal; The first terminal of the first transistor is coupled to the output terminal of the first current source circuit, and the second terminal of the first transistor is coupled to the control terminal and the second terminal of the third transistor. The control electrode and the second electrode of the second transistor are coupled to the second electrode of the fifth transistor, and the first electrode of the second transistor is coupled to the output terminal of the first current source circuit; The first current source circuit is configured to provide a first constant current from the output of the first current source circuit to the first transistor and the second transistor; The first terminal of the third transistor is coupled to the first voltage terminal; The control electrode of the fourth transistor is coupled to the control electrode of the third transistor, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor; The control electrode of the fifth transistor is coupled to the control electrode and the second electrode of the sixth transistor; The second terminal of the sixth transistor is coupled to the output terminal of the second current source circuit, and the first terminal of the sixth transistor is coupled to the first voltage terminal. The second current source circuit is configured to provide a second constant current from the output terminal of the second current source circuit to the sixth transistor; The first terminal of the seventh transistor is coupled to the first voltage terminal, and the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor and the first terminal of the eleventh transistor; The second terminal of the eighth transistor is coupled to the control terminal and the second terminal of the ninth transistor; The control electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, and the first electrode of the ninth transistor is coupled to the second voltage terminal; The first terminal of the tenth transistor is coupled to the second voltage terminal, and the second terminal of the tenth transistor is coupled to the control terminal and the second terminal of the eleventh transistor.

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