Verification System and Verification Method

Abstract

This invention discloses a verification system and verification method, including a first test interface module for receiving test data, obtaining a first digital signal based on the test data, transmitting the first digital signal to an FPGA verification platform via a rate conversion module, the FPGA verification platform performing logical operations on the first digital signal to obtain a second digital signal, transmitting the second digital signal to a second test interface module via the rate conversion module, the second test interface module obtaining verification data based on the second digital signal, and providing the verification data to a verification module, the verification module determining whether the verification data meets preset conditions to obtain simulation verification results, the rate conversion module having a first transmission rate with the first and second test interface modules, and the rate conversion module having a second transmission rate with the FPGA verification platform, the first transmission rate being greater than the second transmission rate, thereby facilitating ASIC portability, enhancing verification reliability, and saving development cycle.

Description

Technical Field

[0001] This invention relates to the field of circuit design verification technology, and in particular to a verification system and verification method. Background Technology

[0002] The logical correctness of ASIC (Application Specific Integrated Circuit) chips can be verified using FPGA (Field Programming Gate Array) verification systems. Compared to simulations using simulators or accelerators, FPGA verification more closely approximates the logic of the ASIC chip. Through collaborative hardware and software development, it can closely resemble the chip's real-world application scenario before tape-out, achieving the goal of fully verifying chip functionality. FPGA verification ensures the reliability and stability of functional modules, facilitates chip performance evaluation, and shortens the time-to-market for chip products. FPGA prototyping plays an irreplaceable role in current digital chip design. FPGA prototyping is currently the mainstream and mature chip verification method—it verifies the ASIC's functionality by porting RTL (Registry Transfer Level) code to the FPGA, and ASIC development can begin after the basic functional verification of the integrated circuit (IC) is passed.

[0003] Figure 1 A schematic diagram of the structure of a prior art FPGA-based verification system is shown. See also Figure 1 The verification system includes an FPGA verification platform 100 and a test interface circuit 200. The FPGA verification platform 100 includes a core logic module 111 located in the clock domain 110 and an interface (IO) logic module 112 located in the clock domain 120. Figure 1 The verification system shown divides the core logic module 111 and the interface logic module 121 into two clock domains, which can improve the communication speed of the interface logic module 121 to the test interface circuit 200. However, the amount of code porting from the core logic module 111 to the interface logic module 121 is too large, which will reduce the logic consistency between the FPGA verification code and the ASIC, reduce the reliability of verification, and thus affect the development cycle.

[0004] Therefore, a new verification system and verification method are needed to solve the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a verification system and verification method that can be easily ported to ASIC, enhance the reliability of verification, and save development cycle.

[0006] According to one aspect of the present invention, a verification system is provided, the verification system being implemented based on a field-programmable gate array (FPGA), the verification system including a test interface circuit, a rate conversion module, and an FPGA verification platform, wherein the rate conversion module is disposed between the test interface circuit and the FPGA verification platform, wherein the rate conversion module and the test interface circuit have a first transmission rate, the rate conversion module and the FPGA verification platform have a second transmission rate, and the first transmission rate is greater than the second transmission rate.

[0007] Optionally, the verification system further includes a verification module. The test interface circuit includes a first test interface module and a second test interface module. The first test interface module receives test data, obtains a first digital signal based on the test data, and transmits the first digital signal to the field-programmable gate array (FPGA) verification platform through the rate conversion module. The FPGA verification platform performs logical operations on the first digital signal to obtain a second digital signal, and transmits the second digital signal to the second test interface module through the rate conversion module. The second test interface module obtains verification data based on the second digital signal and provides the verification data to the verification module. The verification module determines whether the verification data meets preset conditions to obtain simulation verification results.

[0008] Optionally, the rate conversion module includes: a buffer unit for buffering the first digital signal and the second digital signal; a processing unit for receiving the first digital signal and buffering it in the buffer unit, and for reading the buffered first digital signal and outputting it to the field-programmable gate array verification platform when the data buffered in the buffer unit reaches a preset data amount; the processing unit is also used to receive the second digital signal and buffer it in the buffer unit, and for reading the buffered second digital signal and outputting it to the second test interface module when the data buffered in the buffer unit reaches a preset data amount; the processing unit includes a processor or a programmable logic chip.

[0009] Optionally, the first test interface module includes a physical layer receiving unit and a receiving interface, and the test data is output as the first digital signal after passing through the receiving interface and the physical layer receiving unit; the second test interface module includes a physical layer transmitting unit and a transmitting interface, and the second digital signal is output as the verification data after passing through the physical layer transmitting unit and the transmitting interface.

[0010] Optionally, the verification system has an interface logic verification function. The verification module is configured to determine whether the verification data is equal to the test data when performing the interface logic verification. If the verification data is equal to the test data, the verification data meets the preset condition; otherwise, the verification data does not meet the preset condition.

[0011] Optionally, the verification system has a core logic verification function. The verification module is configured to determine whether the verification data is equal to the expected data obtained after the test data is processed by the core logic when performing the core logic verification. If the verification data is equal to the expected data obtained after the test data is processed by the core logic, the verification data meets the preset condition; otherwise, the verification data does not meet the preset condition.

[0012] Optionally, the field-programmable gate array (FPGA) verification platform includes an interface logic module and a core logic module disposed in the same clock domain; the interface logic module includes a receiving interface logic unit for performing receiving interface logic operations on the first digital signal, and a transmitting interface logic unit for performing transmitting interface logic operations on the second digital signal; the core logic module is used to perform logic operations on the first digital signal to obtain the second digital signal, wherein, when the core logic module has multiple core logic units, the first digital signal is sequentially subjected to logic operations by the multiple core logic units to obtain the second digital signal.

[0013] According to another aspect of the present invention, a verification method is provided, the verification method being implemented based on a field-programmable gate array (FPGA). The verification method includes a first test interface module receiving test data and obtaining a first digital signal based on the test data, and transmitting the first digital signal to a rate conversion module at a first transmission rate; the rate conversion module transmitting the first digital signal to an FPGA verification platform at a second transmission rate; the FPGA verification platform performing logical operations on the first digital signal to obtain a second digital signal, and transmitting the second digital signal to the rate conversion module at the second transmission rate; the rate conversion module transmitting the second digital signal to a second test interface module at the first transmission rate; the second test interface module obtaining verification data based on the second digital signal, and outputting the verification data to a verification module; the verification module determining whether the verification data meets preset conditions; if the verification data does not meet the preset conditions, modifying the logic module of the FPGA verification platform, and repeating the above steps until the verification data meets the preset conditions, wherein the first transmission rate is greater than the second transmission rate.

[0014] Optionally, the rate conversion module transmitting the first digital signal to the field-programmable gate array (FPGA) verification platform at a second transmission rate includes the processing unit of the rate conversion module receiving the first digital signal and buffering it in the buffer unit of the rate conversion module, and the processing unit reading the buffered first digital signal and outputting it to the FPGA verification platform when the data buffered in the buffer unit reaches a preset data amount; the FPGA verification platform transmitting the second digital signal to the second test interface module through the rate conversion module includes: the processing unit of the rate conversion module receiving the second digital signal and buffering it in the buffer unit of the rate conversion module, and the processing unit reading the buffered second digital signal and outputting it to the second test interface module when the data buffered in the buffer unit reaches a preset data amount.

[0015] Optionally, the verification method includes interface logic verification and core logic verification. When performing interface logic verification, determining whether the verification data meets preset conditions includes determining whether the verification data is equal to the test data. If the verification data is equal to the test data, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions. When performing core logic verification, determining whether the verification data meets preset conditions includes determining whether the verification data is equal to the data expected to be obtained after the test data undergoes core logic operation. If the verification data is equal to the data expected to be obtained after the test data undergoes core logic operation, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions.

[0016] The verification system and method provided by this invention solve the problem of large code porting volume of internal logic modules in the FPGA verification platform by setting the core logic module and interface logic module in the same clock domain, thereby enhancing verification reliability and saving development cycle. A rate conversion module is set between the FPGA verification platform and the test interface circuit, with a first transmission rate between the rate conversion module and the test interface circuit, and a second transmission rate between the rate conversion module and the FPGA verification platform. The first transmission rate is greater than the second transmission rate. This not only allows the FPGA verification platform of the verification system to operate under a lower clock state, further reducing the difficulty of ASIC porting and saving chip development cycle, but also improves the communication speed between the FPGA verification platform and the test interface circuit. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of the structure of a prior art FPGA-based verification system is shown;

[0019] Figure 2 A schematic diagram of an FPGA-based verification system is shown.

[0020] Figure 3 A schematic diagram of the structure of an FPGA-based verification system according to an embodiment of the present invention is shown;

[0021] Figures 4a-4d A schematic diagram illustrating the implementation of an FPGA-based verification system according to an embodiment of the present invention is shown.

[0022] Figure 5 A flowchart of an FPGA-based verification method according to an embodiment of the present invention is shown. Detailed Implementation

[0023] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0026] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] Figure 2 A schematic diagram of an FPGA-based verification system is shown. See also Figure 2 The verification system includes an FPGA verification platform 300 and a test interface circuit 400. The FPGA verification platform 300 includes a core logic module 311 and an interface (IO) logic module 312 located in the clock domain 310.

[0028] Although setting the core logic module 311 and the interface logic module 312 in the same clock domain 310 can solve the problem of large code porting between the core logic module 311 and the interface logic module 312, the signal transmission between the FPGA verification platform 300 and the test interface circuit 400 has problems such as low transmission rate and inability to directly output signals to the PHY (Physical Layer). Moreover, with the development of integrated circuit design, the scale of integrated circuits is getting larger and the integration is getting higher, and the number of internal operation modules and interfaces of integrated circuits is increasing. In the FPGA verification stage of large-scale chips, due to the large amount of deep combinational logic in the RTL code, timing convergence problems will occur when the RTL code is implemented on the FPGA verification platform 300, making it impossible to directly interface with the test interface circuit 400 on the market.

[0029] To address the aforementioned problems, the inventors of this invention propose a novel FPGA-based verification system and method.

[0030] Figure 3 A schematic diagram of an FPGA-based verification system according to an embodiment of the present invention is shown. See also Figure 3The verification system includes an FPGA verification platform 1000, a rate conversion module 2000, a test interface circuit 3000, and a verification module 4000. The rate conversion module 2000 is located between the test interface circuit 3000 and the field-programmable gate array verification platform 1000.

[0031] The test interface circuit 3000 is used to receive test data and obtain a first digital signal based on the test data. The first digital signal is then transmitted to the FPGA verification platform 1000 through the rate conversion module 2000. The FPGA verification platform 1000 is used to perform logical operations on the first digital signal to obtain a second digital signal. The second digital signal is then transmitted to the test interface circuit 3000 through the rate conversion module 2000.

[0032] The rate conversion module 2000 has a first transmission rate with the test interface circuit 3000, and the rate conversion module 2000 has a second transmission rate with the FPGA verification platform 1000, wherein the first transmission rate is greater than the second transmission rate.

[0033] The FPGA verification platform 1000 includes a core logic module 1110 and an interface logic module 1120, both located in the clock domain 1100. The core logic module 1110 performs logical operations on a first digital signal to obtain a second digital signal, and the interface logic module 1120 performs interface logic operations on the second digital signal.

[0034] The rate conversion module 2000 includes a cache unit 2100 and a processing unit 2200. The cache unit 2100 caches a first digital signal and a second digital signal from the processing unit 2200. The processing unit 2200 receives the first digital signal from the test interface circuit 3000 at a first transmission rate and caches it in the cache unit 2100. When the data cached in the cache unit 2100 reaches a preset data amount, the processing unit 2200 reads the cached first digital signal and transmits it to the FPGA verification platform 1000 at a second transmission rate. The processing unit 2200 also receives the second digital signal from the interface logic module 1120 at the second transmission rate and caches it in the cache unit 2100. When the data cached in the cache unit 2100 reaches a preset data amount, the processing unit 2200 reads the cached second digital signal and outputs it to the test interface circuit 3000 at the first transmission rate. The processing unit 2200 may include, for example, a processor or a programmable logic chip.

[0035] The verification system provided in this embodiment of the invention can realize interface (IO) logic verification and core logic verification.

[0036] When performing interface logic verification, the core logic module 1110 outputs the first digital signal as the second digital signal through a pass-through logic operation; the verification module 4000 is configured to determine whether the verification data is equal to the test data. If the verification data is equal to the test data, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions.

[0037] When performing core logic verification (such as AI algorithm logic verification), the core logic module 1110 performs core logic operations on the first digital signal to obtain the second digital signal. The verification module 4000 is configured to determine whether the verification data is equal to the expected data obtained after the core operation on the test data. If the verification data is equal to the expected data obtained after the core operation on the test data, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions.

[0038] When the verification data meets the preset conditions, the logic verification is completed. When the verification data does not meet the preset conditions, the logic modules (core logic modules, interface logic modules, etc.) of the FPGA verification platform 1000 can be modified according to the verification data, and the logic verification can be performed again until the logic verification passes.

[0039] Furthermore, the interface connecting the processing unit 2200 to the FPGA verification platform 1000 is determined by the interface of the FPGA verification platform 1000, and the interface connecting the processing unit 2200 to the test interface circuit 3000 is determined by the interface of the test interface circuit 3000. When the interfaces of the FPGA verification platform 1000 and the test interface circuit 3000 are the same, the two interfaces of the processing unit 2200 are the same; otherwise, the two interfaces of the processing unit 2200 are different.

[0040] The FPGA-based verification system provided by this invention sets the transmission rate between the rate conversion module 2000 and the first test interface module 3100 and the second test interface module 3200 to a first transmission rate, and sets the transmission rate between the rate conversion module 2000 and the FPGA verification platform 1000 to a second transmission rate, with the first transmission rate being greater than the second transmission rate. This improves the communication speed between the FPGA verification platform 1000 and the test interface circuit 3000, and allows the FPGA verification platform to operate at a lower clock state, making it easier to port to ASICs and reducing the difficulty of ASIC porting. By setting the core logic module 1110 and the interface logic module 1120 in the same clock domain 1100, the workload and difficulty of code porting during the chip design stage can be reduced, and the reliability of verification can be improved. Therefore, this verification system can realize FPGA verification of large-scale ASIC chips. In addition, since the transmission rate between the test interface module 3000 and the rate conversion module 2000 is a high-speed first transmission rate, the rate conversion module 2000 can directly transmit data with the physical layer of the test interface module 3000.

[0041] The verification system provided in this embodiment of the invention can be applied only to the sending channel, only to the receiving channel, or simultaneously to both the sending and receiving channels.

[0042] Figures 4a-4d A schematic diagram of an implementation of an FPGA-based verification system according to an embodiment is shown. Figure 4a A schematic diagram of the verification system applied to the transmission channel is shown. See also Figure 4a The test interface circuit 3000 includes a second test interface module 3200, and the interface logic unit 1120 includes a transmission interface logic unit 1122. The second test interface module 3200 includes a physical layer transmission unit 3210 and a transmission unit 3220. The second test interface module 3200 may be, for example, a 4K transmitter chip, and the verification module 4000 may be, for example, a television (TV).

[0043] During logic testing, the core logic module 1110 performs logical operations on the first digital signal to obtain a second digital signal. The second digital signal is then transmitted to the processing unit 2200 after undergoing logical operations via the transmission interface logic unit 1122. The processing unit 2200 receives the second digital signal and outputs it to the buffer unit 2100. When the data buffered in the buffer unit 2100 reaches a preset data volume, the buffered second digital signal is read and transmitted to the physical layer transmission unit 3210. The second digital signal, after passing through the physical layer transmission unit 3210 and the transmission unit 3220, yields verification data. The verification module 4000 receives the verification data and determines whether it meets preset conditions to obtain the simulation verification result. In the case of transmission verification only, the first digital signal is downloaded to a computer and then logically operated and transmitted via the FPGA verification platform 1000.

[0044] Figure 4b A schematic diagram of the verification system applied to the receiving channel is shown. See also Figure 4b The test interface circuit 3000 includes a first test interface module 3100, and the interface logic unit 1120 includes a receiving interface logic unit 1121. The first test interface module 3100 includes a physical layer receiving unit 3120 and a receiving unit 3110. The first test interface module 3100 may be, for example, a 4K receiver chip.

[0045] During logic testing, test data is received by receiving unit 3110 and physical layer receiving unit 3120 to obtain a first digital signal. Processing unit 2200 receives the first digital signal from physical layer receiving unit 3120 and outputs it to buffer unit 2100. When the data buffered in buffer unit 2100 reaches a preset data amount, it reads the buffered first digital signal and transmits it to receiving interface logic unit 1121. Core logic module 1110 performs logical operations on the first digital signal to obtain a second digital signal. When only receiving verification is performed, the second digital signal can be directly read by a computer via FPGA verification platform 1000, for example.

[0046] Figure 4c A schematic diagram is shown where the verification system is applied to both the transmit and receive channels. See also Figure 4c The test interface circuit 3000 includes a first test interface module 3100 and a second test interface module 3200. The interface logic module 1120 includes a receiving interface logic unit 1121 and a transmitting interface logic unit 1122. The first test interface module 3100 includes a physical layer receiving unit 3120 and a receiving unit 3110. The second test interface module 3200 includes a physical layer transmitting unit 3210 and a transmitting unit 3220.

[0047] During logic testing, test data is received by receiving unit 3110 and physical layer receiving unit 3120 to obtain a first digital signal. Processing unit 2200 receives the first digital signal from physical layer receiving unit 3120 and outputs it to buffer unit 2100. When the data buffered in buffer unit 2100 reaches a preset data amount, it reads the buffered first digital signal and transmits it to receiving interface logic unit 1121. Core logic module 1110 performs logic operations on the first digital signal to obtain a second digital signal. Transmitting interface logic unit 1122 performs transmitting interface logic operations on the second digital signal. Processing unit 2200 receives the second digital signal from transmitting interface logic unit 1122 and outputs it to buffer unit 2100. When the data buffered in buffer unit 2100 reaches a preset data amount, it reads the buffered second digital signal and transmits it to physical layer transmitting unit 3210. The second digital signal is transmitted through physical layer transmitting unit 3210 and transmitting unit 3220 to obtain verification data. Verification module 4000 receives the verification data and determines whether the verification data meets preset conditions to obtain simulation verification results.

[0048] Figure 4d A schematic diagram is shown of the core logic module of the verification system, which has two core logic operation units. Figure 4d The verification system shown is Figure 4c The verification systems shown are basically the same; the following only explains the differences between them.

[0049] See Figure 4d The core logic module 1110 includes a core logic unit 1111 and a core logic unit 1112. During logic verification, the first digital signal is sequentially processed by the core logic unit 1111 and the core logic unit 1112 to obtain the second digital signal.

[0050] It is understandable that when the core logic module 1110 has multiple core logic units, the first digital signal needs to be logically operated on by all the core logic units in sequence before the second digital signal can be obtained.

[0051] When conducting logic tests, you can test the sending channel first, then the receiving channel, and finally test both the sending and receiving channels simultaneously to reduce the difficulty of testing.

[0052] Figure 5 A flowchart of an FPGA-based verification method according to an embodiment of the present invention is shown.

[0053] See Figure 5 The FPGA-based verification method provided in this embodiment of the invention includes:

[0054] S1: The first test interface module receives test data, obtains a first digital signal based on the test data, and transmits the first digital signal to the rate conversion module at a first transmission rate.

[0055] In step S1, the first test interface module includes a physical layer receiving unit and a receiving interface. The test data is processed by the receiving interface and the physical layer receiving unit to obtain a first digital signal.

[0056] S2: The rate conversion module transmits the first digital signal to the FPGA verification platform at a second transmission rate.

[0057] Step S2 includes: the processing unit of the rate conversion module receives the first digital signal and buffers it in the buffer unit of the rate conversion module; when the data buffered in the buffer unit reaches a preset data amount, the processing unit reads the first digital signal and sends it to the FPGA verification platform. The processing unit may include, for example, a processor or a programmable logic chip. The first transmission rate is greater than the second transmission rate.

[0058] S3: The FPGA verification platform performs logical operations on the first digital signal to obtain the second digital signal, and transmits the second digital signal to the rate conversion module at the second transmission rate.

[0059] The verification methods include interface logic verification and core logic verification. When performing interface logic verification, the FPGA verification platform directly outputs the first digital signal as the second digital signal through pass-through logic operations. When performing core logic verification, the FPGA verification platform performs core logic operations on the first digital signal to obtain the second digital signal.

[0060] S4: The rate conversion module transmits the second digital signal to the second test interface module at the first transmission rate.

[0061] Step S4 includes: the processing unit of the rate conversion module receives the second digital signal and caches the second digital signal in the cache unit of the rate conversion module; when the data cached in the cache unit reaches a preset data amount, the processing unit reads the second digital signal and sends it to the second test interface module.

[0062] S5: The second test interface module obtains the verification data based on the second digital signal and outputs the verification data to the verification module.

[0063] S6: Does the verification module determine whether the verification data meets the preset conditions?

[0064] Step S6 includes determining whether the verification data is equal to the test data during interface logic verification. If the verification data is equal to the test data, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions. During core logic verification, it is determined whether the verification data is equal to the expected data obtained after the core operation on the test data. If the verification data is equal to the expected data obtained after the core operation on the test data, the verification data meets the preset conditions; otherwise, the verification data does not meet the preset conditions.

[0065] S7: If the verification data does not meet the preset conditions, modify the logic module of the FPGA verification platform according to the verification data, and repeat the above steps until the verification data meets the preset conditions and the logic verification is successful.

[0066] In step S7, during interface logic verification, only the interface logic module needs to be modified; during core logic verification, if interface logic verification has already been performed, only the core logic module needs to be modified; if interface logic verification has not been performed, both the interface logic module and the core logic module can be modified simultaneously.

[0067] The verification method provided by this invention sets up a rate conversion module between the FPGA verification platform and the test interface circuit, and makes the rate conversion module and the test interface circuit have a first transmission rate, and the rate conversion module and the FPGA verification platform have a second transmission rate. The first transmission rate is greater than the second transmission rate. This not only allows the FPGA verification platform of the verification system to operate in a lower clock state, reducing the difficulty of ASIC porting and saving chip development cycle, but also improves the communication speed between the FPGA verification platform and the test interface circuit.

[0068] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A verification system implemented based on a field programmable gate array, the verification system comprising a test interface circuit, a rate conversion module, a field programmable gate array verification platform, the rate conversion module is disposed between the test interface circuit and the field programmable gate array verification platform, wherein the rate conversion module has a first transmission rate with the test interface circuit and a second transmission rate with the field programmable gate array verification platform, and the first transmission rate is greater than the second transmission rate, the field programmable gate array verification platform comprises an interface logic module and a core logic module disposed in the same clock domain; the rate conversion module comprises: a cache unit for caching a first digital signal and a second digital signal; a processing unit for receiving the first digital signal and caching it in the cache unit, and when the data cached in the cache unit reaches a preset data amount, reading the cached first digital signal and outputting it to the field programmable gate array verification platform, and the processing unit is also used for receiving the second digital signal and caching it in the cache unit, and when the data cached in the cache unit reaches a preset data amount, reading the cached second digital signal and outputting it to a second test interface module.

2. The verification system of claim 1, wherein, The verification system further comprises a verification module, the test interface circuit comprises a first test interface module and the second test interface module, wherein the first test interface module is used for receiving test data, obtaining the first digital signal according to the test data, and transmitting the first digital signal to the field programmable gate array verification platform through the rate conversion module, the field programmable gate array verification platform is used for performing logical operation on the first digital signal to obtain the second digital signal, and transmitting the second digital signal to the second test interface module through the rate conversion module, the second test interface module obtains verification data according to the second digital signal, and provides the verification data to the verification module, the verification module is used for judging whether the verification data meets a preset condition to obtain a simulation verification result.

3. The verification system of claim 2, wherein, The processing unit comprises a processor or a programmable logic chip.

4. The verification system of claim 2, wherein, the first test interface module comprises a physical layer receiving unit and a receiving interface, and the test data is output as the first digital signal after passing through the receiving interface and the physical layer receiving unit; the second test interface module comprises a physical layer sending unit and a sending interface, and the second digital signal is output as the verification data after passing through the physical layer sending unit and the sending interface.

5. The verification system of claim 2, wherein, The verification system has an interface logic verification function, and the verification module is configured to judge whether the verification data is equal to the test data when performing the interface logic verification, if the verification data is equal to the test data, the verification data meets the preset condition, otherwise, the verification data does not meet the preset condition.

6. The verification system of claim 2, wherein, The verification system has a core logic verification function, and the verification module is configured to judge whether the verification data is equal to data expected to be obtained after the test data is subjected to core logic operation when the core logic verification is performed. If the verification data is equal to the data expected to be obtained after the test data is subjected to core logic operation, the verification data meets the preset condition, otherwise, the verification data does not meet the preset condition.

7. The verification system of claim 1, wherein, The interface logic module comprises a receiving interface logic unit for performing receiving interface logic operation on the first digital signal, and a sending interface logic unit for performing sending interface logic operation on the second digital signal; The core logic module is configured to perform logic operation on the first digital signal to obtain the second digital signal, When the core logic module has a plurality of core logic units, the first digital signal is sequentially subjected to logic operation by the plurality of core logic units to obtain the second digital signal.

8. A verification method based on a field programmable gate array, comprising: a first test interface module receiving test data, obtaining a first digital signal according to the test data, and transmitting the first digital signal to a rate conversion module at a first transmission rate; the rate conversion module transmitting the first digital signal to a field programmable gate array verification platform at a second transmission rate; the field programmable gate array verification platform performing logic operation on the first digital signal to obtain a second digital signal, and transmitting the second digital signal to the rate conversion module at the second transmission rate; the rate conversion module transmitting the second digital signal to a second test interface module at the first transmission rate; the second test interface module obtaining verification data according to the second digital signal, and outputting the verification data to a verification module; the verification module judging whether the verification data meets a preset condition, if the verification data does not meet the preset condition, modifying a logic module of the field programmable gate array verification platform, and repeating the above steps until the verification data meets the preset condition, wherein the first transmission rate is greater than the second transmission rate, and the verification method comprises interface logic verification and core logic verification performed in the same clock domain, the rate conversion module transmitting the first digital signal to the field programmable gate array verification platform at the second transmission rate comprises: a processing unit of the rate conversion module receiving the first digital signal and buffering it in a buffer unit of the rate conversion module, and the processing unit reading the buffered first digital signal and outputting it to the field programmable gate array verification platform when the buffered data reaches a preset data amount; the field programmable gate array verification platform transmitting the second digital signal to the second test interface module through the rate conversion module comprises: The processing unit of the rate conversion module receives the second digital signal and buffers it in the buffer unit of the rate conversion module, and the processing unit reads the buffered second digital signal and outputs it to the second test interface module when the data buffered in the buffer unit reaches a preset data amount. 9.The verification method of claim 8, wherein, When the interface logic verification is performed, the judging whether the verification data meets the preset condition comprises judging whether the verification data is equal to the test data, and if the verification data is equal to the test data, the verification data meets the preset condition, otherwise, the verification data does not meet the preset condition; When the core logic verification is performed, the judging whether the verification data meets the preset condition comprises judging whether the verification data is equal to data expected to be obtained after the test data is operated by the core logic, and if the verification data is equal to the data expected to be obtained after the test data is operated by the core logic, the verification data meets the preset condition, otherwise, the verification data does not meet the preset condition.

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