An overall routing method, device and storage medium for an integrated circuit layout

Abstract

The present application discloses a general wiring method and storage medium for an integrated circuit. The method comprises: S11: constructing a three-dimensional grid model based on a multi-layer general wiring layout of the integrated circuit; S12: extracting a symmetric net based on the three-dimensional grid model, mapping a second symmetric sub-net in the symmetric net to a first symmetric sub-net via a symmetry axis, and calculating the wiring capacity of each general wiring unit of the mapped symmetric net; S13: splitting the multi-terminal net of the first symmetric sub-net in the mapped symmetric net into a double-terminal net, and routing the double-terminal net using a three-dimensional pattern routing; S14: traversing all general wiring units through which the double-terminal nets have been routed, updating the wiring capacity and wiring demand value of each general wiring unit, and calculating a wiring overflow value based on the updated wiring capacity and wiring demand value; and S15: determining whether to perform wiring removal and rerouting based on the calculated wiring overflow value, wherein if the wiring overflow value is less than a threshold, outputting the general wiring result of the double-terminal net; if the wiring overflow value is greater than the threshold, performing wiring removal and rerouting on the double-terminal net.

Description

Technical Field

[0001] The present application relates to the field of VLSI design automation technology, in particular to VLSI automated overall wiring technology. Background Art

[0002] Due to the increasing size of chips and increasing process requirements, EDA tools have become indispensable tools in chip design. During the routing phase, EDA tools' primary goal is to establish connections between different modules. Analog integrated circuits primarily collect, amplify, compare, and transform analog signals. Therefore, the numerous geometric and electrical performance requirements within analog integrated circuits present challenges in automated routing. Different routing constraints are applied to nets corresponding to different circuit performance characteristics.

[0003] Symmetry constraints are one of the many analog constraints that must be met. In analog integrated circuit design, to ensure synchronization and consistency between two signals, it is often necessary to consider the symmetrical structure of component layout and routing, as well as parameter matching of components and nets. Therefore, automated routing for analog circuits requires meeting symmetry constraints. This means that two nets in an axisymmetric net group and some segments in a local axisymmetric net must be symmetrical about a specific axis of symmetry, and nets with symmetry constraints must reside on the same metal layer.

[0004] Automated routing systems for VLSI typically involve two steps: general routing and detailed routing. As a primary factor influencing multiple optimization objectives within the routing task, general routing aims to optimize wire length, number of vias, and routing efficiency, given given routing resources. The output of general routing is a general routing unit-level path for each net. This path routes wires only between coarse-grained general routing units, providing routing guidance for subsequent detailed routing. In the detailed routing phase, this guidance is used to refine the general routing unit-level path into a geometric path.

[0005] In recent years, the rapid development of integrated circuit (IC) manufacturing technology has led to an increasing number and density of bus networks integrated into each chip, inevitably increasing the complexity of the routing stage in chip design. Therefore, how to use overall routing to guide subsequent detailed routing, thereby reducing routing complexity and overall time consumption, has become a pressing issue. Summary of the Invention

[0006] This application is completed in view of the above problems. The purpose of this application is to provide an overall wiring method that meets symmetry constraints when automatically wiring analog integrated circuits, so as to reasonably allocate wiring resources and optimize objective functions such as wiring centerline length, number of through holes, and routing rate while meeting the requirements of the electrical performance of the analog circuit.

[0007] According to a first aspect of the present application, a general wiring method for an integrated circuit is provided, comprising:

[0008] S11: Construct a three-dimensional grid graph model based on the multi-layer overall wiring layout of the integrated circuit;

[0009] S12: extracting a symmetrical network based on the three-dimensional grid model, mapping a second symmetrical sub-network in the symmetrical network to the first symmetrical sub-network via a symmetry axis, and calculating a wiring capacity of each overall wiring unit of the mapped symmetrical network;

[0010] S13: splitting the multi-terminal net of the first symmetrical sub-net in the mapped symmetrical net into dual-terminal nets, and routing the dual-terminal nets using a three-dimensional routing pattern;

[0011] S14: traverse all overall wiring units through which the double-ended wire nets have been routed, update the wiring capacity and wiring requirement value of each overall wiring unit, and calculate the wiring overflow value based on the updated wiring capacity and wiring requirement value; and

[0012] S15: Determine whether to perform wire removal and rerouting based on the calculated wiring overflow value, wherein if the wiring overflow value is less than a threshold, output the overall wiring result of the two-ended network; if the wiring overflow value is greater than the threshold, perform wire removal and rerouting on the two-ended network.

[0013] In a second aspect of the present application, an electronic device is provided, comprising: a memory and a processor;

[0014] The memory stores a computer program, and when the computer program is executed by the processor, the aforementioned overall wiring method is executed.

[0015] In a third aspect of the present application, a computer-readable storage medium is provided, on which computer program instructions are stored, characterized in that the computer program instructions implement the aforementioned overall wiring method when executed by a processor.

[0016] Effects of the Invention

[0017] In this application, based on the characteristics and performance requirements of the signal flow to be carried by the wire net, the wire net is divided into symmetric wire nets and ordinary wire nets. Symmetrical wire nets enjoy higher priority than ordinary wire nets when routing, thereby avoiding mutual interference between complex constraints, and the large amount of calculations required for performance estimation during the routing process are also greatly simplified. Afterwards, through the special treatment of actual obstacles and virtual obstacles, layer allocation and other comprehensive resource scheduling, the overall routing problem of satisfying symmetric constraints in analog circuits is well solved. Taking into account the symmetric constraints in analog circuits, pattern routing is performed on symmetric wire nets, and given routing resources, the line length, number of through holes and routing rate are optimized.

[0018] This application provides guidance for subsequent detailed wiring through improved overall wiring, reduces the complexity of wiring problems, and reduces overall time expenditure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Flowchart of an overall wiring method satisfying symmetry constraints according to an embodiment of the present application;

[0020] Figure 2 This is a diagram of a three-layer overall wiring example according to an embodiment of the present application;

[0021] Figure 3 A three-dimensional grid diagram model corresponding to a three-layer overall wiring example diagram according to an embodiment of the present application;

[0022] Figure 4 The overall wiring result of overall wiring based on the three-dimensional grid graph model according to the embodiment of the present application;

[0023] Figure 5 Schematic diagram of the distribution of obstacles in a symmetrical wire network according to an embodiment of the present application;

[0024] Figure 6 Schematic diagram of processing obstacles in a symmetrical line network through mapping and merging according to an embodiment of the present application;

[0025] Figure 7 Schematic diagram of a minimum Steiner tree of a four-terminal network according to an embodiment of the present application;

[0026] Figure 8 A wiring diagram of a minimum Steiner tree of a four-terminal network according to an embodiment of the present application;

[0027] Figure 9 Schematic diagram of upper L-shaped pattern wiring according to an embodiment of the present application.

[0028] Figure 10 Schematic diagram of lower L-shaped pattern wiring according to an embodiment of the present application.

[0029] Figure 11 Schematic diagram of a multi-source and multi-sink wiring strategy according to an embodiment of the present application.

[0030] Figure 12 1 is a result representing an initial solution of a four-terminal network according to an embodiment of the present application.

[0031] Figure 13 It is a schematic diagram showing the removal of the wire mesh according to an embodiment of the present application.

[0032] Figure 14This is a network distribution diagram after the network in the congested area is removed according to the implementation scheme of the present application.

[0033] Figure 15 This is the final wiring result of the multi-terminal network wiring according to the embodiment of the present application.

[0034] Figure 16 Schematic diagram of a layout including obstacles according to an embodiment of the present application.

[0035] Figure 17 It is a schematic diagram of the overall wiring result according to the embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0037] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0038] Current global routers can be divided into two types of routers based on two routing models. One type of global router is based on a two-dimensional grid graph model. During the routing process, this type of router first compresses the multi-layer grid graph into a single layer, then performs routing on a single layer to obtain an initial solution. Finally, a layer allocation algorithm is executed to project the obtained overflow-free single-layer routing results back to the three-dimensional routing space layer by layer. Global routers based on a two-dimensional grid graph model have been proven to effectively shorten the time spent in the overall routing process, but using this routing model will lose the quality of the optimization target in the overall routing process. Another type of global router is based on a three-dimensional grid graph model. During the routing process, this type of global router directly generates routing results in the multi-layer grid graph. Compared with a two-dimensional router, it can maximize the three-dimensional structure of the grid graph and obtain higher-quality routing results, but it will consume more time.

[0039] This application studies the overall routing algorithm based on a three-dimensional grid graph model and proposes a new overall routing method that satisfies symmetry constraints.

[0040] Before describing the overall wiring method of the present application, several common terms in wiring problems are introduced.

[0041] Routing area: In the overall routing problem, the routing area generally refers to the layout that needs to be routed, which is the area where the overall routing algorithm is modeled and routed.

[0042] Global Routing Cell (GRC): The global routing stage divides the entire routing area into many smaller rectangular areas according to the needs. Each small area is called a global routing cell. Compared with detailed routing, the global routing has a coarser granularity and contains multiple grid lines of detailed routing.

[0043] Global Routing Graph (GRG): The global routing considers each global routing unit (GRC) as a point. Adjacent global routing units (GRCs) are connected by an edge, and the capacity of the edge is the routing resources within the routing area, thus forming a global routing graph.

[0044] Node: In the overall wiring diagram, each overall wiring unit GRC is called a node.

[0045] Edge: The connection path between two adjacent GRCs in a GRC diagram is called an edge. The edge between two GRCs on the same layer is called a line edge. The edge between nodes u and v on the same layer is represented by e(u,v). The edge between two GRCs with the same 2D coordinates but on different layers is called a through-hole edge.

[0046] Net: After the overall routing is completed, each net is assigned to one or more overall routing units. After the routing area is divided, the sub-portion of the net in each routing area is called a net in that routing area.

[0047] Through-hole: A hole used to connect and conduct components between two or more layers of a circuit board.

[0048] Line segments: Global routing allows you to obtain the routing results for each net on a coarse-grained grid. These routing results are composed of a collection of global cells. A line segment represents a straight line path connecting the center points of two global cells in the routing result.

[0049] Wiring capacity: represents the wiring resources within the wiring area. The wiring capacity value includes: c(u,v) represents the capacity value of the edge e(u,v), and c(u) represents the capacity value of the node u.

[0050] Routing demand: represents the actual routing resources used during the routing process. The routing demand value includes: the demand value of edge e(u,v) represented by d(u,v), and the routing demand value of node u represented by d(u).

[0051] Routing Overflow: Routing overflow is calculated as routing capacity minus routing demand. Similar to routing capacity and routing demand, routing overflow is calculated as edge overflow and node overflow. The overflow of edge e(u,v) is represented by o(u,v), while the overflow of node u is represented by o(u). The primary measure of routability in the overall routing is the sum of routing overflow values.

[0052] Routing congestion: Routing congestion occurs when the routing overflow value is greater than zero. Routing congestion means that too many wires are routed in a local area, forming a routing congestion area. This brings difficulties to detailed routing because detailed routing may not find a feasible routing solution while following the overall routing results.

[0053] The overall routing problem can be modeled as a graph-based problem, where the relationship between routing areas and their capacities is abstracted into a graph. During the net routing process, the graph model must contain complete layout information and be able to determine the exact location of the pins on each net. Furthermore, during overall routing, the graph model must reflect the capacity of the routing areas and the relationships between them. After the overall routing is complete, each net is assigned to a series of overall routing units, without specifying the net's specific shape or routing location.

[0054] Based on the layout information and netlist information, the overall wiring input of this application can be abstracted into the following parts:

[0055] Line network: Assume that the line network is represented by the following set N: N = {n1, n2, ..., n k}, where n k Represents a normal circuit, each net corresponds to multiple pins. After the routing algorithm is completed, each net will correspond to a set of line segments.

[0056] Pin: Let set P k ={p1,p2,...,p m} represents the m pins contained in a network, each pin corresponds to a unique pin coordinate (x m ,y m ,z m ), x m Indicates the horizontal and y coordinates of each pin m Indicates the vertical coordinate of each pin, and z mRepresents the layer information of each pin, and there will be no overlap between these coordinates.

[0057] Routing area: The layout that needs to be routed is the area where the overall routing algorithm is modeled and routed.

[0058] The final output of the overall wiring problem is a set of line segments, represented by the set Seg. k ={seg1,seg2,...,seg q This set represents the routing result of the net after the overall routing algorithm, that is, the set of global cells that the routing result passes through. This path is only routed between coarse-grained overall routing cells, providing guidance for subsequent detailed routing.

[0059] The key task of the overall routing stage is to maximize routability to improve the routing efficiency of detailed routing. The overall routing algorithm in this disclosure uses the following indicators as optimization targets for routing.

[0060] Congestion level: Routability is often the most important indicator of overall routing. Congestion level can be expressed by the proportion of overall routing units experiencing overflow. If overflow occurs in an overall routing unit, it indicates that the routing demand for that unit exceeds the available routing capacity, which can also be said to be routing congestion.

[0061] Total wiring length: Generally speaking, the longer the wire network, the greater the delay, and it will also occupy more wiring space resources. Therefore, optimizing the wire network length is also conducive to improving the final wiring quality.

[0062] Via Count: To fully utilize the routing area, the number of vias needs to be minimized. Furthermore, since vias typically have a higher resistance than a metal mesh of the same area, and via arrays require more routing space, reducing the number of vias can reduce wire loading and improve circuit performance.

[0063] Runtime: Runtime is an important consideration and the important optimization metric in this chapter.

[0064] Since the time complexity of commonly used shortest path routing algorithms is relatively high, if a dense uniform grid is established in the overall routing as in the detailed routing, the meaning of the overall routing will be lost.

[0065] The strategy of this application is to "extract" a layer of coarse-grained grid on the fine-grained grid, and on the basis of using the coarse-grained grid, this application realizes the overall routing based on the three-dimensional grid diagram. Compared with detailed routing, the routing grid of the overall routing has a coarser granularity, and each grid is called a global routing unit, which contains multiple grid lines of detailed routing. Each global routing unit is regarded as a point in the global routing problem. There is a capacity edge between the points represented by adjacent units, corresponding to the boundary between adjacent units. The capacity of this edge represents the maximum number of metal wires that can pass through this boundary. The number of metal wires passing through the edge is called usage. Therefore, the resource congestion of the global routing can be estimated by the capacity and usage of each edge. If the number of metal wires passing through a boundary is greater than the capacity of the edge corresponding to this boundary, it is said that overflow occurs on this boundary.

[0066] Compared with maze wiring, pattern wiring can reduce the number of through holes and reduce wiring time. Therefore, this application combines pattern wiring with a layer allocation algorithm and uses three-dimensional pattern wiring based on dynamic programming to complete the initial wiring. The wiring resources are calculated again based on the initial solution and the initial wiring cost of the node is updated according to the overflow information in the overall wiring unit. Then, the wire network passing through the congested area is removed according to the overflow value, and then the bidirectional Dijkstra-based wiring algorithm is used for rewiring. If overflow still occurs after the rewiring is completed, the wiring cost needs to be updated according to the overflow value generated by the wiring result and the wiring removal and rewiring process is performed again until no overflow occurs.

[0067] The flowchart of the overall wiring method based on the three-dimensional grid model of this application is as follows Figure 1 shown.

[0068] The following combination Figure 1 , detailing the overall wiring method of this application based on a three-dimensional grid graph model.

[0069] like Figure 1 As shown, the overall wiring method described in this application includes the following steps:

[0070] S11: Initializing the overall wiring grid, converting the multi-layer overall wiring layout (instance diagram) of the integrated circuit into a three-dimensional grid diagram model;

[0071] In step S11, the layout of the integrated circuit is obtained, and a three-dimensional grid model of the layout of the multi-layer overall wiring of the integrated circuit is constructed according to the layout information, netlist information, etc. of the integrated circuit.

[0072] This application is based on the global routing of a three-dimensional grid graph model. The routing process needs to be performed on multiple metal layers. Each metal layer in the global routing is divided into several rectangular areas of equal size. The rectangular areas are called global routing cells (GRCs). The layout (example diagram) of the multi-layer global routing of an integrated circuit can be converted into a three-dimensional grid graph model G(V,E), where each global routing cell GRC is used as a node v in the grid graph. i , node v i Represents a rectangular area within the routing region. Each mesh edge corresponds to the boundary between two adjacent GRCs in the same layer. Each via edge connects two adjacent GRCs in two adjacent layers. In a given set of nets, each net is connected by a number of pins, each of which resides in a GRC. In the three-dimensional grid graph model G(V,E), for each net, the routing process must find a path connecting the vertices corresponding to all pins in that net through edges and vias.

[0073] Figure 2 A three-layer general wiring example diagram of the present application is shown, wherein each metal layer is divided into a number of general wiring units GRC, and the number of available wiring tracks between two adjacent general wiring units GRC on the same layer is related to the capacity. Figure 3 Shows the Figure 2 The three-dimensional grid graph model corresponding to the three-layer overall wiring instance diagram is shown in FIG, where each node represents a overall wiring unit GRC and each edge includes a line edge or a through-hole edge. Figure 4 The figure shows the overall routing result of an overall routing based on a three-dimensional grid model, which consists of a three-layer grid and four pins.

[0074] S12: extracting a symmetrical network based on the three-dimensional grid model, mapping a second symmetrical sub-network in the symmetrical network to the first symmetrical sub-network via a symmetry axis, and calculating a wiring capacity of each overall wiring unit of the mapped symmetrical network.

[0075] In this application, the nodes and edges in the overall wiring diagram will record the information of wiring capacity, demand and overflow value through the occupation of wiring tracks in the overall wiring unit by components in the layout, and use the capacity of each node and the number of metal wires passing through each edge to judge the congestion level of the overall wiring.

[0076] The following first describes the method of calculating the wiring capacity of the initial overall wiring unit in the present application.

[0077] The wiring capacity of the initial overall wiring unit is calculated based on the three-dimensional grid graph model constructed in step S11.

[0078] In some embodiments, obstacles around the wire net are pre-processed beforehand, and then the wiring capacity of the overall wiring unit of the symmetrical wire net after the obstacles are mapped is calculated.

[0079] For a layout that has not yet been wired, all metal devices in the wiring area are considered obstacles. The various graphic information in the layout are traversed and the rectangles corresponding to the obstacles are expanded outwards. l +1 / 2w l The following graphics are recorded as marked rectangles, where s l and w l are the minimum line spacing and minimum line width of layer l respectively. The area of the marked rectangle is the area where the obstacle needs to be recorded. After the obstacle is marked, the initial wiring capacity will be calculated based on the marked rectangle. In one implementation method, after the obstacle is marked, the initial wiring capacity will be calculated based on the marked rectangle, including: the capacity of the edge e(u,v) represented by c(u,v), which means the maximum number of metal wires that can use the edge, and the size is the number of wiring tracks on the edge that are not occupied by obstacles; and the capacity of the node u represented by c(u), which is the average capacity of the two adjacent edges. The specific calculation method is shown in formula [1]:

[0080]

[0081] Where v and w are two nodes adjacent to node u in the wiring direction.

[0082] In one implementation, for the layout of the symmetrical net, the obstacle a within the wiring range of the first symmetrical sub-net (net i) and the obstacle b within the wiring range of the second symmetrical sub-net (net j) may be set differently (e.g. Figure 5 As shown in Figure 1, if you want to route the first symmetrical sub-net (net i) and then map the routing result of the first symmetrical sub-net (net i) to the second symmetrical sub-net (net j), you need to map the obstacle b within the scope of the second symmetrical sub-net to the obstacle a within the routing scope of the first symmetrical sub-net through the symmetry axis of the symmetrical net when calculating the routing capacity of the initial overall routing unit (as shown in Figure 1). Figure 6 (As shown). This approach allows the routing capacity of symmetrical nets to be taken into account during subsequent routing. Therefore, the overall routing problem for a symmetrical net can be transformed into a routing problem that considers only one symmetrical subnet within a pair of symmetrical nets.

[0083] In some embodiments, step S12 calculates the routing capacity of the initial overall routing unit based on the three-dimensional grid model, including: for any pair of symmetrical nets, mapping obstacle b within the second symmetrical sub-net to obstacle a within the first symmetrical sub-net via the axis of symmetry; then merging obstacle a at the first symmetrical sub-net to be routed with obstacle b within the second symmetrical sub-net obtained from the mapping process. The same process is performed for other symmetrical nets.

[0084] S13: Split the multi-terminal net of the first symmetrical sub-net in the mapped symmetrical net into dual-terminal nets, and perform routing on the dual-terminal nets using a three-dimensional pattern routing.

[0085] The present application uses, for example, the FLUTE algorithm to split the multi-end network of a symmetrical sub-network in the mapped symmetrical network into a dual-end network.

[0086] In some embodiments, after the overall routing grid and net data are initialized, a FLUTE algorithm is used to construct a rectangular Steiner minimum tree of the multi-terminal net, and the multi-terminal net of the first symmetric sub-net in the mapped symmetric net is decomposed into multiple two-terminal nets. After the decomposition is completed, pattern routing (such as three-dimensional pattern routing), that is, pattern routing plus layer allocation, is used to route the multiple two-terminal nets to obtain an initial routing result (i.e., an initial solution) for the overall routing.

[0087] The FLUTE algorithm is a rectangular Steiner tree algorithm based on a fast lookup table. Given n points in a plane without considering obstacles, the FLUTE algorithm constructs a rectangular minimum Steiner tree for all multi-end networks. The rectangular minimum Steiner tree connects all points through some additional points (called Steiner points) outside the n points, and minimizes the sum of all edge distances, where the edge distance is measured using the Manhattan distance. Based on a pre-calculated lookup table, the FLUTE algorithm can quickly construct the optimal minimum rectangular Steiner tree (RSMT) for nine-end networks and networks with fewer than nine ends. For networks with more than nine ends, the FLUTE algorithm uses network segmentation technology to split the large network into several small networks to reduce the scale of the problem until the problem can be solved.

[0088] In one implementation, the minimum Steiner tree of a four-terminal network of the first symmetrical sub-network in the mapped symmetrical network is as follows: Figure 7 As shown, Figure 7 The middle nodes P6 and P5 are additional Steiner points.

[0089] For each multi-terminal net that needs to be routed, after splitting into two-terminal nets, the routing order of each two-terminal net will be determined. A node in the minimum Steiner tree will be randomly selected as the root, and a depth-first search traversal will be performed to visit all other nodes, and they will actually be routed in the reverse order of visiting them in the traversal. Assume that you choose Figure 7 With P4 of the minimum Steiner tree as the root, the depth-first search algorithm visits the nodes in the order of P4, P5, P3, P6, P2, and P1. Then the two-terminal nets are marked as e1, e2, e3, e4, e5, and e6 in reverse order, which is the order of wiring. The wiring order of the minimum Steiner tree is as follows: Figure 8 shown.

[0090] In this application, after the multi-terminal network is split into a double-terminal network, the corresponding wiring mode among the horizontal direct connection, vertical direct connection, upper L-shaped, lower L-shaped wiring modes is selected according to the relative position of the double-terminal network, and then the corresponding wiring mode is selected according to the layer information Z. m Select the layer with the largest wiring capacity among the available wiring layers for wiring, and you can get the initial wiring result of the overall wiring (that is, the initial wiring solution). Repeat this step for other two-ended nets until all two-ended nets complete the pattern wiring.

[0091] Figure 9 、 Figure 10 The schematic diagram of performing mode routing on a double-ended network in some embodiments of the present application is shown. Figure 9 、 Figure 10 The method of performing pattern routing on the split double-ended wire net of the present application is described in detail.

[0092] Assume a multi-terminal network n={(x1,y1),(x2,y2),...,(x n ,y n )} is a set of points in a plane. Using the FLUTE algorithm, a multi-ended net can be split into a double-ended net. A double-ended net n = {(x1, y1), (x2, y2)} is a pair of unordered points. Pattern routing uses horizontal or vertical line segments to connect points (x1, y1) and (x2, y2). When x1 = x2 or y1 = y2, a direct connection can be made without any bends. Otherwise, there are two ways to complete the routing: Figure 9 The wiring in the upper L-type mode is called wiring. Figure 10 The wiring in the middle is called lower L-type mode wiring.

[0093] Traditional pattern routing only generates a 2D topology, while 3D pattern routing combines 2D pattern routing with layer assignment to directly generate a 3D topology. For each two-ended net, a path is selected from 2×Z×Z possible options, where Z is the number of layers.

[0094] In the process of removing and rerouting the wires, the present application adopts, for example, a multi-source and multi-sink wiring strategy to reroute the removed wire network.

[0095] The multi-source, multi-sink shortest routing strategy treats the entire routing tree as a single endpoint. This strategy allows routing to be completed by creating a single path between the two trees, whether routing directly from one endpoint to another or using a portion of an existing routing tree. This approach uses any point on a subtree as a reconnection point to adaptively adjust the network topology, finding the lowest-cost routing path between two routing trees.

[0096] The shortest wiring strategy diagram for multiple sources and multiple sinks is as follows Figure 11 As shown in the figure, the routing area of AB is congested, so AB needs to be removed and re-routed. After removing AB, two routing subtrees T1 and T2 will be formed. If endpoints A and B are directly regarded as source points and sink points for routing, unnecessary detours will be generated. Therefore, all points on subtree T1 are regarded as source points, and all points on subtree T2 are regarded as sink points for maze routing. Figure 11 The dotted path from x to y in the figure is also the optimal path connecting T1 and T2. The routing algorithm here needs to choose the maze algorithm instead of the most efficient A-star algorithm because the A-star algorithm can only perform endpoint-to-endpoint routing and cannot treat the entire routing tree as a single endpoint.

[0097] In some embodiments, when the wire net is split into multi-terminal wire nets, the multi-terminal wire nets are directly wired instead of routing the two-terminal wire nets one by one. For example, Figure 12 It represents the initial routing result (initial solution) of a four-terminal net. Vertex T represents the pin of the multi-terminal net, vertex S represents the Steiner point generated when the multi-terminal net is split, and the shaded part represents the congested area.

[0098] Figure 13 The dashed lines in the figure represent the removed nets. Subtrees T1 and T2 and endpoints T3 and T4 are then routed as a three-terminal net. The MGR algorithm expands the maze from each endpoint until it encounters either of the other two endpoints. After expansion, the algorithm examines the regions visited during multiple wavefront propagation to find the Steiner node with the lowest cost. Once a Steiner node is found, the algorithm backtracks and constructs a path connecting the multiple endpoints.

[0099] S14: traverse all overall wiring units through which the double-ended wire nets have been routed, update the wiring capacity and wiring requirement value of each overall wiring unit, and calculate the wiring overflow value based on the updated wiring capacity and wiring requirement value.

[0100] In the present application, after pattern routing is performed on the split double-ended wire net to obtain an initial routing result (initial solution) of the overall routing, the overflow value of each overall routing unit is calculated respectively.

[0101] S15: Determine whether to perform wire removal and rerouting based on the calculated wiring overflow value, wherein if the wiring overflow value is less than a threshold, output the overall wiring result of the two-ended network; if the wiring overflow value is greater than the threshold, perform wire removal and rerouting on the two-ended network.

[0102] In this application, if the overflow value is zero (ie, no overflow), the wiring result is directly output. Figure 5 The routing results for the first symmetric subnet (net i) are mapped to the second symmetric subnet (net j) along the axis of symmetry. If the overflow value is non-zero, indicating overflow, the process begins with the removal and rerouting phase. Because pattern routing is used when finding the initial solution, congestion is unavoidable in some cases. Therefore, a shortest path algorithm is used to remove and reroute the congested areas.

[0103] Step S15 specifically includes:

[0104] S15-1: If the calculated overflow value is less than the threshold or the current number of iterations exceeds a certain number, it is determined that there is no overflow, and the routing result of the first sub-symmetric line net (net i) is mapped to the second sub-symmetric line net (net j) through the symmetry axis, and the routing result is output, ending the entire process;

[0105] S15-2: If the calculated overflow value is greater than the threshold, it is determined that there is overflow and the process enters the wire removal and rewiring phase.

[0106] During the wire removal and re-routing stage, since pattern routing is used when obtaining the initial solution, congestion is inevitable in some cases. Therefore, the shortest path algorithm is required to remove and re-route the wire network in the congested area.

[0107] The steps in the stitch removal and re-routing phase include:

[0108] (1) Reroute the double-ended network using, for example, the bidirectional Dijkstra algorithm. Based on the rerouted results, the sum of the overflow values of the overall routing units is recalculated. If the overflow value is less than a threshold or the number of rerouted iterations exceeds a certain value, the routing result is mapped to the symmetrical sub-network at the other end through the symmetry axis, and then the routing result is output.

[0109] (2) In each iteration of unbundling and rerouting, the two-ended mesh connections in each congested area are unbundled and rerouted using, for example, the bidirectional Dijkstra algorithm to optimize, for example, the cost function defined in the negotiated routing cost formula [2] of the mesh edge e, which is based on the congestion history.

[0110]

[0111] Indicates the historical cost of edge e when iterating k times. When the routing result overflows, the historical cost will increase. The value of is given by the following formula, where The value of h is 1, inc is a constant.

[0112]

[0113] Therefore, if an edge is repeatedly congested over multiple iterations, its cost will increase significantly. In formula [2], α is a scaling factor that determines the proportion of congestion history and actual overflow value in the cost value.

[0114] (3) Remove the routing results of the nets that cause overflow edges, and use the A* algorithm to search for routing on these nets based on the overall routing unit based on historical costs;

[0115] (4) Return to step (1).

[0116] Below Figure 14 、 Figure 15 The multi-terminal wiring method based on the bidirectional Dijkstra algorithm of the present application is described as an example.

[0117] During routing using the bidirectional Dijkstra algorithm, all endpoints are simultaneously extended outward. Among the waves generated by all endpoint extensions, the wave that meets the fastest is traced back to generate the first routing path. This path is then treated as an endpoint, and multi-terminal net routing continues with the remaining endpoints until all pins are connected.

[0118] Figure 14 This is the network distribution diagram after removing the network in the congested area. Figure 15 The final routing result for a multi-terminal net. When routing a multi-terminal net using the bidirectional Dijkstra algorithm, when all three endpoints are expanded simultaneously, the wave from endpoint T3 will first intersect with the wave from subtree T1T2 at point a. After backtracking at point a to generate a routing path, the path formed by T1T2T3 and endpoint T4 are bidirectionally extended. The bidirectional Dijkstra algorithm consistently finds the shortest path when a path exists between endpoints, and ideally, it searches only half the number of nodes as the unidirectional Dijkstra algorithm.

[0119] The bidirectional Dijkstra-based wire-rewiring and rerouting algorithm operates as follows: Each terminal on the network is considered a wave. For each wave, a priority queue stores the central nodes to be expanded. The same node may appear in the priority queues of multiple waves, as these waves may need to connect through it. Each time, the node with the lowest cost is found from all the priority queues of the waves for expansion.

[0120] Step 1: When performing a multi-source search, each node is initialized by setting two parameters, id1 and id2, for each node. id1 indicates the wave in which the node was first added to the S set; id2 indicates the wave in which the node was expanded. Each wave is represented by id. Each time, the node with the lowest cost is selected from the priority queue as the center point for expansion. After finding the node, the wave number of the node, i.e., the value of id1, is returned.

[0121] Step 2: When expanding to each node, there are three cases based on the values of id1, id2, and id:

[0122] (i) The value of id1 is the initial value, indicating that this node is being expanded as a center point for the first time. When expanding as a center point for the first time, it is necessary to search for its neighboring nodes and calculate their costs. If the node has not been encountered before, or the new cost is smaller than the previous cost, the expanded node is added to the corresponding wave queue or its cost is updated.

[0123] (ii) If the values of id1 and id are the same, it means that the node has been expanded by the same wave before, and this expansion is discarded.

[0124] (iii) If the values of id2 and id are different, it means that a node has been expanded by two different waves. This means that the two waves have been connected. The connection point identifies two different waves. After this expansion, when the two waves meet, they will merge into one wave.

[0125] Step 3: Continue searching until only one wave is left. When only one wave is left, the routing of the current multi-terminal network is completed.

[0126] The following describes in detail the overall wiring method for satisfying symmetry constraints in the integrated circuit layout wiring of this application, using a specific case. The specific steps are as follows:

[0127] S101. Construct a 3D grid model of the overall wiring

[0128] As mentioned above, Figure 2 An example of a three-layer overall wiring of the present application is shown, where the layers are divided into G-cells, and the number of wiring tracks between two adjacent G-cells on the same layer is related to the capacity. Figure 3Shows the Figure 2 The three-layer overall wiring example corresponds to a three-dimensional grid graph model, where each vertex represents a G-cell and each edge represents a boundary or a through-hole. Figure 4 The figure shows the overall routing result of an overall routing based on a three-dimensional grid graph model, which consists of a three-layer grid graph and four pins p1, p2, p3 and p4.

[0129] S102: extracting a symmetrical network based on the three-dimensional grid model, mapping a second symmetrical sub-network in the symmetrical network to the first symmetrical sub-network via a symmetry axis, and calculating a wiring capacity of each overall wiring unit of the mapped symmetrical network.

[0130] In the present application, after constructing the three-dimensional grid model, the obstacles around the multi-terminal wire mesh are pre-processed, and then the initial wiring capacity of each overall wiring unit is calculated.

[0131] Regarding the pre-processing of the obstacle module around the symmetrical network, for the routing of the first symmetrical sub-network (net i) and the second symmetrical sub-network (net j), the obstacle a within the scope of the first symmetrical sub-network (net i) and the obstacle b within the scope of the second symmetrical sub-network (net j) are obviously different (e.g. Figure 5 As shown in the figure, if we directly route the first symmetrical subnet (net i) and then directly symmetric the routing result to the second symmetrical subnet (net j), the routing result of the second symmetrical subnet (net j) may overflow. Therefore, we first map the obstacle b within the second symmetrical subnet (net j) to one side of the first symmetrical subnet (net i) through the symmetry axis (as shown in the figure). Figure 6 As shown), the obstacle b of the second symmetrical sub-line network (net j) mapped to one side of the first symmetrical sub-line network (net i) and the obstacle a originally existing in the first symmetrical sub-line network (net i) are merged.

[0132] After such pre-processing, when routing the first symmetrical sub-net (net i), the routing capacity of the overall routing unit within the second symmetrical sub-net (net j) can be taken into consideration during the routing process.

[0133] After pre-processing the obstacles, the initial wiring capacity of each overall wiring unit is calculated.

[0134] Refer to the following Figure 16 , exemplarily illustrating the method of calculating the initial capacity of each overall wiring unit in this application.

[0135] like Figure 16As shown in the figure, r is an obstacle, the rectangle is the overall wiring unit, the horizontal line in the overall wiring unit is the fine-grained grid and is recorded as the wiring track. The length of the overall wiring unit is L.

[0136] (1) Calculation of wiring capacity

[0137] Let c(u,v) represent the capacity of edge e(u,v), which means the maximum number of metal wires that can use this edge. Its size is the number of tracks on edge e(u,v) that are not occupied by obstacles. Let c(u) represent the capacity of node u, and its size is calculated by the following formula [1]:

[0138]

[0139] Where v and w are two nodes adjacent to node u in the wiring direction.

[0140] (2) Calculation of wiring requirements

[0141] The wiring demand refers to the part of the used capacity in the wiring grid diagram, which is obtained by calculating the number of metal wires and vias added after the wiring is completed at a certain stage. The wiring demand is specifically divided into edge demand and node demand. The number of metal wires passing through the edge e(u,v) is the metal wire demand, recorded as wire(u,v); the number of tracks affected by vias in the overall wiring unit is the via demand, recorded as via(u). Then the demand value d(u,v) of the edge e(u,v) is the sum of the metal wire demand and the via demand, as shown in [3]. The demand value d(v) of the node v is the maximum value of the metal wire demand of the two adjacent edges wire(u,v) and wire(v,w) of the node and the via demand of the node v, as shown in formula [4]. u and w are two nodes adjacent to v in the wiring direction.

[0142]

[0143]

[0144] (3) Calculation of wiring overflow value

[0145] When the demand value exceeds the capacity, overflow occurs. Similar to capacity and demand, overflow is also divided into edge overflow o(u,v) and node overflow o(u), which are calculated as shown in Equations [5] and [6] respectively. If o(u,v)>0 or o(u)>0, it means that the network passes through a congested area and needs to be rerouted.

[0146] o(u,v)=d(u,v)-c(u,v) [5]

[0147] o(u)=d(u)-c(u) [6]

[0148] S103: Splitting the multi-terminal net of the first symmetrical sub-net in the mapped symmetrical net into dual-terminal nets, and routing the dual-terminal nets using a three-dimensional routing pattern;

[0149] After initializing the overall routing grid and net data, the FLUTE algorithm is used to construct a rectangular Steiner minimum tree of multi-terminal nets, and each multi-terminal net is decomposed into multiple two-terminal nets. After decomposition, the overall routing result (initial solution) is obtained using three-dimensional pattern routing, which is a pattern routing plus layer allocation method.

[0150] S104: traverse all overall wiring units through which the double-ended wire nets have been routed, update the wiring capacity and wiring requirement value of each overall wiring unit, and calculate the wiring overflow value according to the updated wiring capacity and wiring requirement value.

[0151] S105: Determine whether to perform wire removal and rerouting based on the calculated wiring overflow value, wherein if the wiring overflow value is less than a threshold, output the overall wiring result of the two-ended network; if the wiring overflow value is greater than the threshold, perform wire removal and rerouting on the two-ended network.

[0152] In this application, if the overflow value is less than the threshold, it is determined that there is no overflow, and the wiring result of the first symmetrical sub-net (net i) is mapped to the second symmetrical sub-net (net j) through the symmetry axis, and then Figure 17 The wiring results are output as shown, ending the entire process.

[0153] On the contrary, if there is overflow, the routing results of the nets that cause the overflow edge are removed, and the A-star algorithm search and routing are performed on these nets on the overall routing unit based on the historical cost to perform the wiring removal and rerouting steps.

[0154] According to the implementation method of the present application, a layer of coarse-grained grid is "extracted" on the fine-grained grid, and the pattern routing is combined with the layer allocation algorithm based on the coarse-grained grid, and the initial routing is completed using a three-dimensional pattern routing based on dynamic programming. The routing resources are calculated again based on the initial solution and the initial routing cost of the node is updated according to the overflow information in the overall routing unit. The wire mesh passing through the congested area is then removed according to the overflow value, and then the bidirectional Dijkstra-based routing algorithm is used for rerouting. If overflow still occurs after the rerouting is completed, the routing cost needs to be updated according to the overflow value generated by the routing result this time and the wiring removal and rerouting process is performed again until no overflow occurs. Using pattern routing for routing can reduce the number of through holes while reducing routing time.

[0155] An embodiment of the present application further provides an overall wiring device for an integrated circuit, comprising a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the overall wiring method described above can be executed.

[0156] The processor can be a newly designed one, or an existing processor can be used to execute the various steps of the overall wiring method of the present application. The types of existing processing units may include but are not limited to: central processing unit (CPU), digital signal processing unit (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic devices.

[0157] An embodiment of the present application further provides a computer-readable storage medium having computer program instructions stored thereon, and when the computer program instructions are executed by a processor, the overall wiring method provided above is implemented.

[0158] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A general wiring method for an integrated circuit, characterized in that: include: S11: Construct a three-dimensional grid graph model based on the multi-layer overall wiring layout of the integrated circuit; S12: extracting a symmetrical network based on the three-dimensional grid model, mapping a second symmetrical sub-network in the symmetrical network to the first symmetrical sub-network via a symmetry axis, and calculating a wiring capacity of each overall wiring unit of the mapped symmetrical network; S13: splitting the multi-terminal net of the first symmetrical sub-net in the mapped symmetrical net into dual-terminal nets, and routing the dual-terminal nets using a three-dimensional routing pattern; S14: traverse all overall wiring units through which the double-ended wire nets have been routed, update the wiring capacity and wiring requirement value of each overall wiring unit, and calculate the wiring overflow value based on the updated wiring capacity and wiring requirement value; as well as S15: determining whether to perform wire removal and rerouting based on the calculated wiring overflow value, wherein if the wiring overflow value is less than a threshold, outputting an overall wiring result of the two-terminal net; If the wiring overflow value is greater than the threshold, the double-ended network is removed and re-routed.

2. The overall wiring method of an integrated circuit according to claim 1, characterized in that: Mapping the second symmetrical sub-net in the symmetrical net to the first symmetrical sub-net through the symmetry axis includes: merging the graphics of obstacles within the first symmetrical sub-net in the symmetrical net with the graphics of obstacles within the second symmetrical sub-net, wherein the obstacles are metal devices on the wiring area of the layout that has not yet been wired.

3. The overall wiring method of an integrated circuit according to claim 1, characterized in that: In step S13, the FLUTE algorithm is used to split the multi-ended network of the first symmetric sub-network in the mapped symmetric network into dual-ended networks.

4. The overall wiring method of an integrated circuit according to claim 1, wherein: In each iteration of the wiring rerouting, the two-ended network connections in each congested area are disconnected and the two-way Dijkstra algorithm is used to perform wiring rerouting on the two-ended network.

5. The overall wiring method of an integrated circuit according to claim 2, wherein: Also includes: Expand the rectangle corresponding to the obstacle to the surrounding area by s l +1 / 2w l The following graphics are recorded as marked rectangles, where s l and w l The minimum line spacing and minimum line width of the wiring on the same layer are respectively used. After the obstacle marking is completed, the wiring capacity of the overall wiring unit of the mapped symmetrical line network is calculated based on the marked rectangle.

6. A general wiring device for an integrated circuit, characterized in that: include: memory and processor; A computer program is stored in the memory, and when the computer program is executed by the processor, the overall wiring method according to any one of claims 1 to 5 is executed.

7. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the overall wiring method according to any one of claims 1 to 5 is implemented.

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