Method of forming a semiconductor structure
By forming non-injection and injection regions on the substrate, defining trench locations using multiple first openings, and combining this with sidewall etching of the layer to be etched, the problem of existing photolithography processes being unable to meet the dimensional accuracy requirements of semiconductor structures is solved, thereby improving the performance of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-05-17
- Publication Date
- 2026-07-24
Smart Images
Figure CN117116849B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] Lithographing is a key process technology for realizing integrated circuit patterns. In lithography, a photosensitive material (photoresist) is coated onto a thin film on a substrate. Light of a wavelength corresponding to the photoresist's photosensitivity is then passed through a mask with a specific pattern and irradiated onto the photoresist surface. After development, a photoresist pattern corresponding to the pattern on the mask is formed. In subsequent integrated circuit processes, the photoresist pattern is used as a barrier layer to selectively etch the underlying thin film, thus completely transferring the pattern from the mask onto the substrate's thin film.
[0003] With the development of integrated circuits, photolithography technology has also undergone development stages such as G-line lithography, I-line lithography, KrF deep ultraviolet lithography, and ArF deep ultraviolet lithography. Exposure light sources include various types such as near-ultra-violet (NUV), mid-ultra-violet (MUV), and deep ultraviolet (DUV).
[0004] However, as the size of semiconductor structures continues to shrink, the precision of existing photolithography processes can no longer meet the dimensional accuracy requirements of semiconductor structures, affecting the performance of the resulting semiconductor structures. Summary of the Invention
[0005] The problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.
[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
[0007] A substrate is provided, the substrate comprising a layer to be etched;
[0008] A first mask layer is formed on the layer to be etched;
[0009] Ion implantation is performed on the first mask layer to form a non-implanted region and an implanted region located around the non-implanted region; the non-implanted region extends along a first direction and a second direction, the first direction being perpendicular to the second direction and the second direction being perpendicular to the first direction.
[0010] After forming the injection region and the non-injection region, a third mask layer is formed on the first mask layer. The third mask layer has a plurality of first openings extending along the first direction. The first openings are located above the non-injection region. On the projection plane parallel to the layer to be etched, the non-injection region is divided by the first openings along the second direction to form a plurality of spaced second trench forming regions.
[0011] The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer;
[0012] Based on the first trench, the second trench forming area is etched away to form a second trench in the first mask layer. The second trench extends along a first direction and is spaced apart from the first trench along a second direction.
[0013] After the second trench is formed, the sidewall layer and the first mask layer are used as masks to pattern the layer to be etched below the first and second trenches, forming the target pattern.
[0014] Optionally, the first opening extends along the first direction to above a portion of the injection area on both sides of the non-injection area.
[0015] Optionally, the step of performing ion implantation on the first mask layer includes:
[0016] A second mask layer is formed on the first mask layer;
[0017] Ion implantation is performed on the first mask layer using the second mask layer as a mask to form a non-implanted region and an implanted region located outside the non-implanted region;
[0018] After forming the non-injection region and the injection region located outside the non-injection region, the second mask layer is removed.
[0019] Optionally, the material of the second mask layer is photoresist, and the process for forming the second mask layer includes a positive development process.
[0020] Optionally, the step of etching away the second trench forming region based on the first trench includes: after forming the first trench, removing the third mask layer; forming a sidewall layer on the sidewall of the first trench; after forming the sidewall layer, etching away the second trench forming region to form the second trench in the first mask layer;
[0021] The step of graphically representing the layers to be etched below the first and second trenches includes: using the sidewall layer and the first mask layer as masks to graphically represent the layers to be etched below the first and second trenches.
[0022] Optionally, the step of forming the sidewall layer includes:
[0023] A sidewall material layer is formed to conformally cover the bottom and sidewalls of the first trench and the top surface of the first mask layer;
[0024] Remove the sidewall material layer located at the bottom of the first trench and the top surface of the first mask layer, and retain the sidewall material layer located on the sidewall of the first trench as the sidewall layer.
[0025] Optionally, the process for forming the sidewall material layer includes atomic layer deposition.
[0026] Optionally, the sidewall layer may be made of one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.
[0027] Optionally, the etching process to remove the remaining non-injection areas is a wet etching process.
[0028] Optionally, the layer to be etched includes a dielectric layer;
[0029] Using the sidewall layer and the first mask layer as masks, the dielectric layer below the first trench and the second trench is patterned, and a plurality of interconnect trenches are formed in the dielectric layer.
[0030] The method further includes forming interconnect lines in the interconnect slots.
[0031] Optionally, the dielectric layer may be made of at least one of the following: low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride.
[0032] Optionally, the layer to be etched includes a hard mask material layer; after the first mask layer is formed, the first mask layer is located on the hard mask material layer;
[0033] After the second trench is formed, the hard mask material layer below the first trench and the second trench is patterned, a third trench is formed in the hard mask material layer at the bottom of the first trench, and a fourth trench is formed in the hard mask material layer at the bottom of the second trench, so that the hard mask material layer forms a hard mask layer.
[0034] The dielectric layer beneath the third and fourth trenches is patterned using the hard mask layer as a mask, and the first interconnect trench and the second interconnect trench are formed in the dielectric layer.
[0035] Optionally, the material of the hard mask material layer includes at least one of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbonate, and silicon oxycarbonitrile.
[0036] Optionally, the process of etching the first mask layer using the third mask layer as a mask is a wet etching process.
[0037] Optionally, the material of the first mask layer includes amorphous silicon.
[0038] Optionally, the material of the third mask layer is photoresist, and the process for forming the third mask layer includes a negative development process.
[0039] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0040] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate including a layer to be etched; forming a first mask layer on the layer to be etched; performing ion implantation on the first mask layer to form a non-implanted region and an implanted region located around the non-implanted region; the non-implanted region extending along a first direction and a second direction, the first direction and the second direction being perpendicular to each other; after forming the implanted region and the non-implanted region, forming a third mask layer on the first mask layer, the third mask layer having a plurality of first openings extending along the first direction, the first openings being located above the non-implanted region, and on a projection plane parallel to the layer to be etched, the non-implanted region being divided by the first openings along the second direction to form a plurality of spaced second trench forming regions; etching the first mask layer using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer; based on the first trench, etching away the second trench forming regions to form a second trench located on the side of the first trench in the first mask layer; and patterning the layer to be etched below the first trench and the second trench to form a target pattern.
[0041] As can be seen, a non-injection region is first formed on the first mask layer, and then a third mask layer is formed on the first mask layer. Multiple first openings extending along the first direction in the third mask layer divide the non-injection region along the second direction, such that first trenches formed at the bottom of the first openings divide the non-injection region into multiple spaced second trench forming regions. That is, the non-injection region and the first trenches together define the pattern and position of the second trenches. Compared with schemes using a single film layer structure or directly defining the pattern and position of the second trenches through etching processes, the non-injection region has a larger size, which can increase the process window of the photolithography process, reduce the difficulty of forming the non-injection region, improve the quality of the formed pattern, and eliminate the limitations of existing photolithography processes, allowing the formed second trenches to meet the corresponding pitch requirements. This, in turn, ensures that the subsequently formed second interconnects meet the corresponding pitch requirements, thus improving the performance of the formed semiconductor structure. Attached Figure Description
[0042] Figures 1 to 10 This is a schematic diagram of the intermediate structures corresponding to each step of a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation
[0043] As can be seen from the background technology, the reverse exposure-etching-exposure-etching process in the existing back-end process (BEOL) is limited by the photolithography process, resulting in low performance of the semiconductor structure formed.
[0044] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a layer to be etched; forming a first mask layer on the layer to be etched; performing ion implantation on the first mask layer to form a non-implanted region and an implanted region located around the non-implanted region; the non-implanted region extending along a first direction and a second direction, the first direction and the second direction being perpendicular to each other; after forming the implanted region and the non-implanted region, forming a third mask layer on the first mask layer, the third mask layer having a plurality of first openings extending along the first direction, the first openings being located above the non-implanted region, and on a projection plane parallel to the layer to be etched, the non-implanted region being divided by the first openings along the second direction to form a plurality of spaced second trench forming regions; etching the first mask layer using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer; based on the first trench, etching away the second trench forming regions to form a second trench located on the side of the first trench in the first mask layer; and patterning the layer to be etched below the first trench and the second trench to form a target pattern.
[0045] As can be seen, a non-injection region is first formed on the first mask layer, and then a third mask layer is formed on the first mask layer. Multiple first openings extending along the first direction in the third mask layer divide the non-injection region along the second direction, such that first trenches formed at the bottom of the first openings divide the non-injection region into multiple spaced second trench forming regions. That is, the non-injection region and the first trenches together define the pattern and position of the second trenches. Compared with schemes using a single film layer structure or directly defining the pattern and position of the second trenches through etching processes, the non-injection region has a larger size, which can increase the process window of the photolithography process, reduce the difficulty of forming the non-injection region, improve the quality of the formed pattern, and eliminate the limitations of existing photolithography processes, allowing the formed second trenches to meet the corresponding pitch requirements. This, in turn, ensures that the subsequently formed second interconnects meet the corresponding pitch requirements, thus improving the performance of the formed semiconductor structure.
[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0047] The following will combine Figures 1 to 10 A method for forming a semiconductor structure according to an embodiment of the present invention will be described in further detail.
[0048] See Figure 1 A substrate is provided, the substrate including a layer 100 to be etched.
[0049] The substrate provides a process platform for subsequent processes.
[0050] The substrate can be a silicon substrate or a germanium substrate, etc. Furthermore, other devices, such as PMOS transistors or NMOS transistors, can be formed in the substrate; the substrate can also form an isolation structure, which can be a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. Similarly, conductive components can also be formed in the substrate, which can be the gate, source, or drain of a transistor, or a metal interconnect structure electrically connected to the transistor, etc.
[0051] In this embodiment, the layer to be etched 100 has a multilayer structure. Specifically, the layer to be etched 100 includes a dielectric layer 101 and a hard mask material layer 102 located on the dielectric layer 101.
[0052] The dielectric layer 101 is then patterned, forming a plurality of first interconnect trenches and second interconnect trenches. First interconnect lines and second interconnect lines are formed in the first interconnect trenches and second interconnect trenches, respectively. The dielectric layer 101 is used to achieve electrical isolation between adjacent first interconnect lines and second interconnect lines. The first interconnect lines and second interconnect lines constitute the target pattern.
[0053] In this embodiment, the hard mask material layer 102 is first patterned to form a hard mask layer, and then the dielectric layer 101 is patterned using the hard mask layer as a mask. This helps to improve the process stability of the patterned dielectric layer 101 and correspondingly improves the accuracy of pattern transfer.
[0054] The dielectric layer 101 is made of low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc. Among them, low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9, and ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6.
[0055] In this embodiment, the dielectric layer 101 is made of an ultra-low k dielectric material, thereby reducing the parasitic capacitance between the metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low k dielectric material can be hydrogenated carbon silicon oxide.
[0056] The hard mask material layer 102 is made of one or more of titanium nitride, tungsten carbide, silicon oxide, silicon carbide, and silicon carbonitride. As an example, the hard mask material layer 102 is made of titanium nitride.
[0057] In practical implementation, depending on actual process requirements, a stress buffer layer can be provided between the hard mask material layer 102 and the dielectric layer 101 to improve the adhesion between the hard mask material layer 102 and the dielectric layer 101 and reduce the stress generated between the film layers. Furthermore, an etching stop layer can be provided between the hard mask material layer 102 and the stress buffer layer, and also on the hard mask material layer 102, to define the stop position of subsequent etching processes, which is beneficial for improving the effect of subsequent patterning processes. The relevant descriptions of the stress buffer layer and the etching stop layer will not be repeated here.
[0058] See Figure 2 and Figure 3 A first mask layer 110 and a second mask layer 120 located on the first mask layer 110 are formed on the layer to be etched 100.
[0059] The first mask layer 110 is used to subsequently form a first trench and a second trench therein by etching.
[0060] In this embodiment, the first mask layer 110 is formed on the hard mask material layer 102.
[0061] In this embodiment, the material of the first mask layer 110 is amorphous silicon. In other embodiments, the first mask layer 110 can also be formed of other suitable materials, which are not limited here.
[0062] The process for forming the first mask layer 110 is chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or high-temperature furnace tube process, etc.
[0063] The second mask layer 120 is used as a mask for subsequent ion implantation processes on the first mask layer.
[0064] In this embodiment, the second mask layer 120 is a photoresist layer. Specifically, the material of the second mask layer 120 is photoresist.
[0065] In this embodiment, the second mask layer 120 is rectangular. Accordingly, the second mask layer 120 is formed using a positive photodiode (PTD) process.
[0066] See Figure 4 Ion implantation is performed on the first mask layer 110 using the second mask layer 120 as a mask to form a non-implanted region I and an implanted region II located around the non-implanted region I; the non-implanted regions extend along a first direction (X direction) and a second direction (Y direction), respectively, with the first direction being perpendicular to the second direction.
[0067] Ion implantation is performed on the first mask layer 110 using the second mask layer 120 as a mask, so that the first mask layer 110 covered by the second mask layer 120 forms a non-implantation region I, and the first mask layer 110 not covered by the second mask layer 120 forms an implantation region II.
[0068] Ion implantation is performed on the first mask layer 110, which correspondingly changes the etching selectivity ratio between the implanted region II and the non-implanted region I formed in the first mask layer 110. Specifically, ion implantation is performed on the first mask layer 110 to increase the etching selectivity ratio between the implanted region II and the non-implanted region I, thereby allowing the implanted region II to be preserved during the subsequent etching process to remove the non-implanted region I.
[0069] The non-injection region I is used to define the positions of the first trench and the second trench subsequently formed in the first mask layer 110. Specifically, the non-injection region I is subsequently divided by the first trench formed in the first mask layer 110, and the divided non-injection region I is used to form the second trench. Therefore, by defining the pattern and position of the second trench together with the non-injection region I, compared with the scheme of using a single film layer structure or directly defining the pattern and position of the second trench through etching process, the size of the formed non-injection region I is larger, which is beneficial to increasing the process window of the photolithography process for forming the non-injection region I and reducing the formation difficulty of the non-injection region I.
[0070] In this embodiment, the second mask layer 120 is rectangular, and the non-injection region I is correspondingly rectangular. Specifically, the non-injection region I extends along a first direction and a second direction perpendicular to the first direction.
[0071] In this embodiment, after forming the non-injection region I and the injection region II, the method further includes the step of removing the second mask layer 120. Specifically, the second mask layer 120 is removed using a wet stripping process or an ashing process.
[0072] See Figure 5After forming the non-injection region I and the injection region II, a third mask layer 130 is formed on the first mask layer 110. The third mask layer 130 has a plurality of first openings 135 extending along the first direction. The first openings 135 are located above the non-injection region I, and on a projection plane parallel to the layer to be etched 100, the non-injection region I is divided by the first openings 135 along the second direction to form a plurality of spaced second trench forming regions III (see...). Figure 6 ).
[0073] The third mask layer 130 is used as a mask for subsequent etching of the first mask layer 110.
[0074] In this embodiment, the material of the third mask layer 130 is photoresist.
[0075] In this embodiment, a negative developing process (NTD) is used to form a third mask layer 130 on the first mask layer 110.
[0076] The first opening 135 is used to define the pattern and location of the first trench subsequently formed in the first mask layer 110. Specifically, the first mask layer 110 at the bottom of the first opening 135 is used for subsequent etching removal, thereby forming the first trench in the first mask layer 110.
[0077] In this embodiment, the first opening 135 is located above the non-injection region I in the first mask layer 110, and the first opening 135 extends along the first direction above the non-injection regions II on both sides of the non-injection region I. Therefore, the size of the first opening 135 along the first direction is larger than the size of the non-injection region I along the first direction.
[0078] Furthermore, on the projection plane parallel to the layer to be etched 100, the non-injection region I along the second direction is divided by the first opening 135, thereby causing the first trench subsequently formed on the first mask layer 110 and located at the bottom of the first opening 135 to divide the non-injection region I into a plurality of spaced second trench forming regions.
[0079] The first mask layer 110 at the bottom of the first opening 135 is subsequently etched to form a corresponding first trench in the first mask layer 110. The first trench divides the non-injection region I into a plurality of second trench forming regions that extend along the first direction and are spaced apart along the second direction for forming the second trench. That is, the pattern and position of the second trench are defined by the non-injection region I and the first trench. Compared with the scheme of using a single film layer structure or directly defining the pattern and position of the second trench through etching process, the limitations of the existing photolithography process can be eliminated, so that the second trench formed subsequently meets the corresponding pitch requirements, and thus the second interconnect formed subsequently meets the corresponding pitch requirements, thereby improving the performance of the formed semiconductor structure.
[0080] In this embodiment, there are two first openings 135. In other embodiments, there may be more or fewer first openings 135, which can be set according to actual needs by those skilled in the art, and no limitation is made here.
[0081] See Figure 6 The first mask layer 110 is etched using the third mask layer 130 as a mask to form a first trench 111 located at the bottom of the first opening 135.
[0082] The first mask layer 110 is etched using the third mask layer 130 as a mask, so that the first mask layer 110 covered by the third mask layer 130 is retained, and the first mask layer 110 exposed at the bottom of the first opening 135 is etched away, thereby forming a first trench 111 at the bottom of the first opening 135 in the first mask layer 110.
[0083] The first trench 111 is used to define the pattern and position of the third trench subsequently formed in the hard mask material layer 102, and to divide the non-injection region II along the second direction into a plurality of second trench forming regions III for forming the second trench.
[0084] In this embodiment, the process of etching the first mask layer 110 using the third mask layer 130 as a mask is a dry etching process. In other embodiments, the process of etching the first mask layer using the third mask layer 130 as a mask can also be a wet etching process or a combination of dry etching and wet etching processes, etc.
[0085] After the first trench 111 is formed, the non-injection region I in the first mask layer 110 along the second direction is divided by the first trench 111. The remaining non-injection region I after division, that is, the second trench forming region III, is used to form a plurality of second trenches that extend along the first direction and are spaced apart from the first trench along the second direction.
[0086] Therefore, the second trench forming region III in the first mask layer 110 for forming the second trench is defined by the non-injection region I formed by the second mask layer 120 and the first trench formed by the third mask layer 130, rather than using multiple second mask layers extending along the first direction or a separate etching process to define the pattern and position of the second trench. Thus, the limitations of the current photolithography process can be eliminated, and a second trench that meets the corresponding pitch requirements can be formed, thereby enabling the corresponding second interconnect line formed in the layer to be etched to meet the corresponding pitch ratio requirements.
[0087] In other embodiments, a SOC layer and a Si-ARC layer can be formed sequentially on the first mask layer before forming the third mask layer on the first mask layer, with the third mask layer located on the Si-ARC layer; the Si-ARC layer, the SOC layer, and the first mask layer are etched sequentially using the third mask layer as a mask until the top surface of the hard mask material layer is exposed, forming the first trench within the first mask layer; after forming the first trench, the first SOC layer, the first Si-ARC layer, and the third mask layer are removed. The relevant descriptions of the formation of the SOC layer and the Si-ARC layer will not be repeated here.
[0088] In this embodiment, after the first trench 111 is formed, the third mask layer 130 is removed.
[0089] In this embodiment, an ashing process is used to remove the third mask layer 130. In other embodiments, a wet stripping process can also be used to remove the third mask layer.
[0090] See Figure 7 A sidewall layer 140 is formed on the sidewall of the first trench 111.
[0091] The sidewall layer 140 is used to define the spacing distance in a second direction between the first trench and the subsequently formed second trench.
[0092] Specifically, the sidewall layer 140 occupies a portion of the space within the first trench 111, thereby creating a predetermined gap between the first trench 111 and the second trench subsequently formed in the first mask layer 110 in the second direction. Therefore, the thickness of the sidewall layer 140 can be set according to the required gap between the first trench 111 and the subsequently formed second trench in the second direction, and is not limited here.
[0093] The sidewall layer 140 can be selected from materials with a higher etch selectivity rate than the hard mask material layer 102, providing a basis for subsequent etching of the hard mask material layer using the sidewall layer 140 and the first mask layer 110 as masks. In this embodiment, the material of the sidewall layer 140 is titanium oxide (TiO). In other embodiments, the material of the sidewall layer can also be aluminum monoxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), or other materials such as nitrides, oxides, oxynitrides, carbides, borides, and combinations thereof.
[0094] The step of forming the sidewall layer 140 includes: forming a sidewall material layer that conformally covers the bottom and sidewalls of the first trench 111 and the top surface of the first mask layer 110; removing the sidewall material layer located at the bottom of the first trench 111 and the top surface of the first mask layer 110, and retaining the sidewall material layer located at the sidewalls of the first trench 111 as the sidewall layer 140.
[0095] In this embodiment, the process for forming the sidewall material layer is atomic layer deposition (ALD). ALD results in a sidewall material layer with good thickness uniformity and excellent step coverage. Furthermore, ALD is a self-limiting reaction process, allowing for precise deposition of one atomic layer per cycle. The resulting film can achieve a single-atom thickness, facilitating precise control over the deposition thickness of the sidewall material layer.
[0096] In other embodiments, the process for forming the sidewall material layer can also be, for example, chemical vapor deposition, physical vapor deposition, or high-temperature furnace tube process.
[0097] Accordingly, since the sidewall material layer conformally covers the bottom and sidewalls of the first trench 111 and the top surface of the first mask layer 110, in this embodiment, an anisotropic maskless etching process can be used to remove the sidewall material layer located at the bottom of the first trench 111 and the top surface of the first mask layer 110, so that the step of forming the sidewall layer 140 does not require a photomask, which helps to save process costs.
[0098] Specifically, using anisotropic dry etching process to perform anisotropic maskless etching process is beneficial to ensure that while removing the sidewall material layer located at the bottom of the first trench 111 and the top surface of the first mask layer 110, the damage to other film layer structures is small, and the lateral etching of the sidewall material layer located on the sidewall of the first trench 111 is reduced.
[0099] See Figure 8After forming the sidewall layer 140, the second trench forming region III is etched away, and a second trench 112 is formed in the first mask layer 120. The second trench 112 extends along the first direction and is arranged at intervals from the first trench 111 along the second direction.
[0100] The second trench 112 is used to define the pattern and location of the second interconnect trench subsequently formed in the layer 100 to be etched.
[0101] In this embodiment, the second trench 112 penetrates the first mask layer 110, that is, the bottom of the second trench 112 exposes the material of the hard mask material layer 102.
[0102] The number of second grooves 112 can be determined according to actual process requirements. In this embodiment, three second grooves 112 are used as an example. In other embodiments, the number of second grooves can be more or less.
[0103] In this embodiment, the etching process for removing the second trench formation region III is a wet etching process. In other embodiments, the etching process for removing the second trench formation region III can also be a dry etching process.
[0104] In order to retain the first mask layer 110 and sidewall layer 140 of the injection region II during the step of forming the second trench 112, the etching rate of the first mask layer 120 of the non-injection region I should be greater than the etching selectivity rates of the first mask layer 110 of the injection region II and the sidewall layer 140, respectively. In this embodiment, during the etching process to form the second trench 112, the etching selectivity ratio of the first mask layer 110 of the non-injection region I to the first mask layer 110 of the injection region II is greater than or equal to 100, such as 150, 200, etc., and the etching selectivity ratio of the first mask layer 110 of the non-injection region I to the sidewall layer 140 is greater than or equal to 20, such as 50, 100, etc.
[0105] See Figure 9 and Figure 10 Using the sidewall layer 140 and the first mask layer 110 as masks, the layer 100 to be etched below the first trench 111 and the second trench 112 is patterned to form a target pattern.
[0106] In this embodiment, the layer to be etched includes a dielectric layer 101. Accordingly, using the sidewall layer 140 and the first mask layer 110 as masks, the layer 100 to be etched below the first trench 111 and the second trench 112 is patterned. That is, using the sidewall layer 140 and the first mask layer 110 as masks, the dielectric layer 101 below the first trench 111 and the second trench 112 is patterned, and a first interconnect trench 1011 and a second interconnect trench 1012 are formed in the dielectric layer 101.
[0107] In this embodiment, the layer to be etched 100 further includes a hard mask material layer 102 located on the dielectric layer 101. The step of patterning the dielectric layer 101 below the first trench 111 and the second trench 112 using the sidewall layer 140 and the first mask layer 110 as masks, and forming the first interconnect trench 1011 and the second interconnect trench 1012 in the dielectric layer 101, includes: patterning the hard mask material layer 102 using the first mask layer 110 and the sidewall layer 140 as masks, and forming a third trench 1021' located at the bottom of the first trench 111 and a fourth trench 1021' located at the bottom of the second trench 112 in the hard mask material layer 102. 022', forming a patterned hard mask layer 102' by the hard mask material layer 102; after forming the third trench 1021' and the fourth trench 1022', removing the sidewall layer 140 and the first mask layer 110; after removing the sidewall layer 140 and the first mask layer 110, using the hard mask layer 102' as a mask, patterning the dielectric layer 101 below the third trench 1021' and the fourth trench 1022', forming the first interconnect trench 1011 and the second interconnect trench 1012 in the dielectric layer 101.
[0108] During the process of patterning the hard mask layer 102', the presence of the first mask layer 110 and the sidewall layer 140 allows the hard mask material layer 102 located below the first mask layer 110 and the sidewall layer 140 to be retained, and allows the hard mask material layer 102 exposed at the bottom of the first trench 111 and the second trench 112 to be removed, thereby forming a third trench 1021 located at the bottom of the first trench 111 in the hard mask material layer 102, and forming a fourth trench 1022 located at the bottom of the second trench 112 in the hard mask material layer 102.
[0109] In this embodiment, the process of etching the hard mask material layer 102 using the first mask layer 110 and the sidewall layer 140 as masks is a dry etching process. Specifically, the process of etching the hard mask material layer 102 is a plasma dry etching process, and the etching angle of the second plasma dry etching process is 90°.
[0110] After forming the third trench 1021' and the fourth trench 1022', the process for removing the sidewall layer 140 and the first mask layer 110 includes a dry etching process and a wet etching process. In this embodiment, a wet etching process is used to remove the sidewall layer 140 and the first mask layer 110.
[0111] To preserve the dielectric layer 101 and the hard mask layer 102, during the removal of the sidewall layer 140 and the first mask layer 110, the etching selectivity rates for the dielectric layer 101 and the hard mask layer 102 should be lower than the etching selectivity rates for the sidewall layer 140 and the first mask layer 110, respectively. The materials of the dielectric layer 101 and the hard mask layer 102 should be selected based on etching selectivity rates lower than those for the sidewall layer 140 and the first mask layer 110, respectively.
[0112] In this embodiment, after removing the sidewall layer 140 and the first mask layer 110, the patterns of the third trench 1021' and the fourth trench 1022' formed in the hard mask material layer 102 continue to be transferred down to the dielectric layer 101 of the layer to be etched 100, and corresponding first interconnect trench 1011 and second interconnect trench 1012 are formed in the dielectric layer 101.
[0113] In this embodiment, after forming the first interconnect trench 1011 and the second interconnect trench 1012 in the dielectric layer 101, metal material is filled into the first interconnect trench 1011 and the second interconnect trench 1012 to form corresponding first interconnect lines and second interconnect lines.
[0114] In this embodiment, the first interconnect and the second interconnect are formed in the same process step to simplify the process, save process costs, and improve work efficiency.
[0115] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a layer to be etched; A first mask layer is formed on the layer to be etched; Ion implantation is performed on the first mask layer to form a non-implanted region and an implanted region located around the non-implanted region; the non-implanted region extends along a first direction and a second direction, respectively, with the first direction and the second direction being perpendicular to each other; A third mask layer is formed on the first mask layer. The third mask layer has a plurality of first openings extending along the first direction. The first openings are located above the non-injection area. On the projection plane parallel to the layer to be etched, the non-injection area is divided by the first openings along the second direction to form a plurality of spaced second trench forming areas. The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer; Based on the first trench, the second trench forming area is etched away to form a second trench in the first mask layer. The second trench extends along a first direction and is spaced apart from the first trench along a second direction. The layer to be etched below the first and second trenches is graphically visualized to form the target pattern.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first opening extends along the first direction to the portion of the injection area on both sides of the non-injection area.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of performing ion implantation on the first mask layer includes: A second mask layer is formed on the first mask layer; Ion implantation is performed on the first mask layer using the second mask layer as a mask to form a non-implanted region and an implanted region located outside the non-implanted region; After forming the non-injection region and the injection region located outside the non-injection region, the second mask layer is removed.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, The material of the second mask layer is photoresist, and the process for forming the second mask layer includes a positive development process.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of etching away the second trench forming area based on the first trench includes: after forming the first trench, removing the third mask layer; forming a sidewall layer on the sidewall of the first trench; after forming the sidewall layer, etching away the second trench forming area to form the second trench in the first mask layer; The step of graphically representing the layers to be etched below the first and second trenches includes: using the sidewall layer and the first mask layer as masks to graphically represent the layers to be etched below the first and second trenches.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The steps for forming the sidewall layer include: A sidewall material layer is formed to conformally cover the bottom and sidewalls of the first trench and the top surface of the first mask layer; Remove the sidewall material layer located at the bottom of the first trench and the top surface of the first mask layer, and retain the sidewall material layer located on the sidewall of the first trench as the sidewall layer.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, The formation process of the sidewall material layer includes atomic layer deposition.
8. The method for forming a semiconductor structure according to claim 6, characterized in that, The sidewall layer is made of one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of etching away the remaining non-injection areas is a wet etching process.
10. The method for forming a semiconductor structure according to claim 1, characterized in that, The layer to be etched includes a dielectric layer; The dielectric layer beneath the first and second trenches is graphically represented, and a first interconnect trench and a second interconnect trench are formed in the dielectric layer. The method further includes: forming a first interconnect line in the first interconnect slot and forming a second interconnect line in the second interconnect slot.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The dielectric layer is made of at least one of the following: low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride.
12. The method for forming a semiconductor structure according to claim 10, characterized in that, The layer to be etched further includes a hard mask material layer; after the first mask layer is formed, the first mask layer is located on the hard mask material layer; After the second trench is formed, the hard mask material layer below the first trench and the second trench is patterned, a third trench is formed in the hard mask material layer at the bottom of the first trench, and a fourth trench is formed in the hard mask material layer at the bottom of the second trench, so that the hard mask material layer forms a hard mask layer. The dielectric layer beneath the third and fourth trenches is patterned using the hard mask layer as a mask, and the first interconnect trench and the second interconnect trench are formed in the dielectric layer.
13. The method for forming a semiconductor structure according to claim 12, characterized in that, The material of the hard mask layer includes at least one of titanium nitride, tungsten carbide, silicon oxide, silicon carbide, and silicon carbonitride.
14. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of etching the first mask layer using the third mask layer as a mask is a wet etching process.
15. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first mask layer includes amorphous silicon.
16. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the third mask layer is photoresist, and the process for forming the third mask layer includes a negative development process.