A time measurement circuit with two-dimensional address modulation TOT pulse function

Abstract

This invention relates to the field of high-resolution time measurement systems and integrated circuit technology, providing a time measurement circuit with a two-dimensional address-modulated TOT pulse, comprising: a common-gate transimpedance amplifier, a high-speed high-gain comparator, a current-mode logic output stage, a common-mode feedback threshold setting circuit, and a two-dimensional address-modulated TOT pulse circuit; the address modulation pulse circuit includes an address modulation pulse width circuit and an address modulation pulse amplitude circuit, wherein the address modulation pulse width circuit includes: multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code; the address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code. This invention allows a single TOT signal to simultaneously carry time information, energy information, and address information, reducing wiring, improving reliability, and increasing integration density.

Description

Technical Field

[0001] This invention relates to the field of high-resolution time measurement system technology, and in particular to a time measurement circuit with two-dimensional address modulation TOT pulse function. Background Technology

[0002] In recent years, high-resolution time measurement has been rapidly developed in fields such as autonomous driving, indoor positioning, 3D recognition, nuclear medicine imaging and particle physics. In particular, time measurement systems based on silicon detectors have significant advantages in terms of integration, reliability and cost.

[0003] Existing high-resolution time measurement systems are mostly based on an amplification-discrimination architecture. That is, the current signal (Iin) output by the detector is first converted into a voltage signal (V1) through a transimpedance amplifier, then this voltage signal is saturated and amplified by high gain, and finally output through current mode logic (CML) to form the final voltage signal (Vout) with an external resistor. Figure 1 The principle of Time-Over-Threshold (TOT) is given. That is, for... Figure 1 For the voltage-form signal shown, the larger the threshold (Vth), the larger the TOT pulse width (Δt) of the output signal, and vice versa. Here, Vout is the voltage signal output by the current-mode logic. Therefore, the high level is typically the supply voltage, and the low level is approximately several hundred millivolts. By reducing the value of the external resistor, Vout can easily be converted into a low-voltage differential signal (LVDS).

[0004] Regarding the specific threshold setting circuit structure, there are currently two circuit system architectures: one is to directly use a voltage comparator, as shown in Figure 2(a); the other is to use a current comparator, as shown in Figure 2(b).

[0005] A voltage comparison-type time measurement circuit obtains the output voltage (V2) of the discriminator (i.e., comparator) by comparing the output voltage (V1) of the transconductance amplifier with the threshold voltage (Vth). A current comparison-type time measurement circuit, on the other hand, first converts the threshold voltage (Vth) into a current (Ifb), compares it with the detector input current (Iin), and then performs saturation amplification to obtain the output voltage (V2) of the discriminator (i.e., comparator).

[0006] A time measurement circuit based on an amplification-discrimination architecture can not only accurately measure time, but also coarsely measure energy using a time-to-energy (TOT) method, serving as a supplement to time measurement. Compared to voltage comparator-based circuits, current comparator-based time measurement circuits offer higher time accuracy and finer threshold adjustment capabilities.

[0007] As the number of channels increases, such as in applications with 1 million or more channels, channel addressing becomes a bottleneck restricting the application of time measurement technology. Current technologies only allow TOT signals to carry time and energy information. The additional hardware and wiring resources required for addressing these signals result in a large, unreliable, and poorly integrated electronic system. In particular, more complex circuits introduce power consumption issues, leading to mechanical and thermal control problems, making it difficult to reduce costs and consequently diminishing the value for scientific research and commercial applications. Summary of the Invention

[0008] This invention primarily addresses the technical problems of existing TOT signals, which can only carry time and energy information. The additional hardware and wiring resources required for addressing these signals result in a large overall electronic system size, low reliability, and poor integration. The invention proposes a time measurement circuit with two-dimensional address modulation TOT pulse function, in which a single TOT signal carries time, energy, and address information simultaneously. This reduces wiring, improves reliability, and enhances integration, significantly alleviating the need for additional hardware and wiring resources for addressing.

[0009] This invention provides a time measurement circuit with two-dimensional address modulation TOT pulse function, comprising: a common-mode feedback threshold setting circuit, a common-gate transimpedance amplifier, a high-speed high-gain comparator, and a current-mode logic output stage;

[0010] It also includes: a two-dimensional address modulation TOT pulse circuit;

[0011] The two-dimensional address modulation TOT pulse circuit includes: an address modulation pulse width circuit;

[0012] The address modulation pulse width circuit includes multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code;

[0013] The first modulation unit includes a first switch SW1x and a first NMOS transistor M1x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0014] One end of the first switch SW1x is connected to the drain of the first NMOS transistor M1x, and the other end of the first switch SW1x serves as the output terminal of the unit; the control terminal of the first switch SW1x is connected to the x-th bit of the first digital code D. ADDR1 [x];

[0015] The source of the first NMOS transistor M1x is connected to ground, and the gate of the first NMOS transistor M1x is connected to the first bias voltage Vbn1 of the common gate transimpedance amplifier.

[0016] The second modulation unit includes a second switch SW2x and a second NMOS transistor M2x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0017] One end of the second switch SW2x is connected to the drain of the second NMOS transistor M2x, and the other end of the second switch SW2x serves as the output terminal of the unit;

[0018] The source of the second NMOS transistor M2x is connected to ground, and the gate of the second NMOS transistor M2x is connected to the first bias voltage Vbn1 of the common-gate transimpedance amplifier; the control terminal of the second switch SW2x is connected to the x-th bit of the first digital code D via the x-th inverter INVx. ADDR1 [x].

[0019] Preferably, the output terminal of the first modulation unit is short-circuited and connected together to the non-inverting input terminal Iinp of the common-gate transimpedance amplifier.

[0020] Preferably, the output terminal of the second modulation unit is short-circuited and connected together to the negative inverting input terminal Inn of the common gate transimpedance amplifier.

[0021] Preferably, it also includes: an address modulation pulse amplitude circuit;

[0022] The address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code;

[0023] The third modulation unit includes a third switch SW3x and a third NMOS transistor M3x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0024] One end of the third switch SW3x is connected to the drain of the third NMOS transistor M3x, and the other end serves as the output terminal of the unit; the control terminal of the third switch SW3x is connected to the x-th bit of the second digital code D. ADDR2 [x];

[0025] The source of the third NMOS transistor M3x is connected to ground, and its gate is connected to the third bias voltage Vbn3 of the common gate transimpedance amplifier.

[0026] Preferably, the output terminal of the third modulation unit is short-circuited and is connected to the common source CS of the current-mode logic output stage;

[0027] The xth second digit code D ADDR2 [x] Controls the bias current of the current-mode logic output stage.

[0028] Preferably, the common-gate transimpedance amplifier includes: a first differential input common-gate transistor M1a, a second differential input common-gate transistor M1b, a first differential bias transistor M2a, a second differential bias transistor M2b, and a load;

[0029] The source of the first differential input common gate transistor M1a is connected to the non-inverting input terminal Iinp, the drain is connected to the load terminal V1p, and the gate is connected to the second bias voltage Vbn2.

[0030] The source of the first differential bias transistor M2a is connected to ground, the drain is connected to the non-inverting input terminal Iinp, and the gate is connected to the first bias voltage Vbn1.

[0031] The source of the second differential input common gate transistor M1b is connected to the negative input terminal Iinn, the drain is connected to the load terminal V1n, and the gate is connected to the second bias voltage Vbn2.

[0032] The source of the second differential bias transistor M2b is connected to ground, the drain is connected to the negative input terminal Iinn, and the gate is connected to the first bias voltage Vbn1.

[0033] Preferably, the current-mode logic output stage includes: a first differential input common source transistor M4a, a second differential input common source transistor M4b, and a third bias transistor M5;

[0034] The source of the first differential input common-source transistor M4a is connected to the common-source terminal CS, the drain is connected to the positive output terminal Voutp, and the gate is connected to the negative input terminal V2n.

[0035] The source of the second differential input common-source transistor M4b is connected to the common-source terminal CS, the drain is connected to the negative output terminal Voutn, and the gate is connected to the positive input terminal V2p.

[0036] The source of the third bias transistor M5 is connected to ground, the drain is connected to the common source terminal CS, and the gate is connected to the third bias voltage Vbn3.

[0037] This invention provides a time measurement circuit with two-dimensional address modulation TOT pulse function, enabling a single TOT signal to simultaneously carry time, energy, and address information. This avoids splitting the input signal in two, naturally eliminating the need for traditional addressing circuits and simplifying the circuitry. In applications with a large number of channels, this reduces wiring, improves reliability, and increases integration, thereby simplifying mechanical structure and thermal control design, and significantly reducing costs. The signal processed by this invention simultaneously carries time, energy, and address information, greatly alleviating the additional hardware and wiring resources required for addressing, offering unparalleled advantages in improving integration and reliability, and especially in reducing costs. Attached Figure Description

[0038] Figure 1 This is a schematic diagram illustrating the principle of threshold time.

[0039] Figure 2(a) is a circuit schematic diagram of the prior art using a voltage comparator.

[0040] Figure 2(b) is a circuit schematic diagram of the prior art using a current comparator.

[0041] Figure 3 This is a circuit schematic diagram of the time measurement circuit with two-dimensional address modulation TOT pulse function provided by the present invention;

[0042] Figure 4(a) is a circuit schematic diagram of the address modulation pulse width circuit provided by the present invention;

[0043] Figure 4(b) is a schematic diagram of the modulation effect of the address modulation pulse width circuit provided by the present invention;

[0044] Figure 5(a) is a circuit schematic diagram of the address modulation pulse amplitude circuit provided by the present invention;

[0045] Figure 5(b) is a schematic diagram of the modulation effect of the address modulation pulse amplitude circuit provided by the present invention;

[0046] Figure 6(a) shows the modulation effect after logical processing of the present invention.

[0047] Figure 6(b) shows the second modulation effect after logical processing of the present invention. Detailed Implementation

[0048] To make the technical problems solved by this invention, the technical solutions adopted, and the technical effects achieved clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings, not all of them.

[0049] like Figure 3 As shown, the time measurement circuit with two-dimensional address modulation TOT pulse function provided in this embodiment of the invention includes: a common-mode feedback threshold setting circuit, a common-gate transimpedance amplifier, a high-speed high-gain comparator, and a current-mode logic output stage.

[0050] This invention provides a low-cost addressing solution based on a current comparison-type time measurement circuit. Address information can be included in the TOT pulse width or the TOT pulse amplitude, thus offering two address modulation pulse methods. Therefore, the time measurement circuit with two-dimensional address modulation TOT pulse functionality of this invention further includes: a two-dimensional address modulation TOT pulse circuit;

[0051] The two-dimensional address modulation TOT pulse circuit includes: an address modulation pulse width circuit and an address modulation pulse amplitude circuit.

[0052] As shown in Figure 4(a), the address modulation pulse width circuit includes: multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code. For example, the first modulation units, second modulation units, and inverters are all configured as n sets, and the first digital code is configured as n bits.

[0053] The first modulation unit includes a first switch SW1x and a first NMOS transistor M1x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0054] One end of the first switch SW1x is connected to the drain of the first NMOS transistor M1x, and the other end of the first switch SW1x serves as the output terminal of the unit; the control terminal of the first switch SW1x is connected to the x-th bit of the first digital code D. ADDR1 [x];

[0055] The source of the first NMOS transistor M1x is connected to ground, and the gate of the first NMOS transistor M1x is connected to the first bias voltage Vbn1 of the common gate transimpedance amplifier.

[0056] The output terminals of the first modulation unit are shorted and connected together to the non-inverting input terminal Iinp of the common-gate transimpedance amplifier.

[0057] The second modulation unit includes a second switch SW2x and a second NMOS transistor M2x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0058] One end of the second switch SW2x is connected to the drain of the second NMOS transistor M2x, and the other end of the second switch SW2x serves as the output terminal of the unit;

[0059] The source of the second NMOS transistor M2x is connected to ground, and the gate of the second NMOS transistor M2x is connected to the first bias voltage Vbn1 of the common-gate transimpedance amplifier; the control terminal of the second switch SW2x is connected to the x-th bit of the first digital code D via the x-th inverter INVx. ADDR1 [x].

[0060] The output of the second modulation unit is shorted and connected to the negative inverting input terminal Iinn of the common gate transimpedance amplifier.

[0061] Through the above connection method, the address modulation pulse width circuit can be connected with the traditional common gate transimpedance amplifier and form a differential structure.

[0062] First digital code D ADDR1 [x] controls the bias current of the first differential input common gate transistor M1a and the second differential input common gate transistor M1b. The modulation effect is shown in Figure 4(b). Generally, the address modulation pulse width circuit can be extended to n bits.

[0063] Furthermore, the common-gate transimpedance amplifier includes: a first differential input common-gate transistor M1a, a second differential input common-gate transistor M1b, a first differential bias transistor M2a, a second differential bias transistor M2b, and a load. The source of the first differential input common-gate transistor M1a is connected to the positive input terminal Iinp, the drain is connected to the load terminal V1p, and the gate is connected to the second bias voltage Vbn2. The source of the first differential bias transistor M2a is connected to ground, the drain is connected to the positive input terminal Iinp, and the gate is connected to the first bias voltage Vbn1. Conversely, the source of the second differential input common-gate transistor M1b is connected to the negative input terminal Iinn, the drain is connected to the load terminal V1n, and the gate is connected to the second bias voltage Vbn2. The source of the second differential bias transistor M2b is connected to ground, the drain is connected to the negative input terminal Iinn, and the gate is connected to the first bias voltage Vbn1.

[0064] As shown in Figure 5(a), the address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code;

[0065] The third modulation unit includes a third switch SW3x and a third NMOS transistor M3x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer;

[0066] One end of the third switch SW3x is connected to the drain of the third NMOS transistor M3x, and the other end serves as the output terminal of the unit; the control terminal of the third switch SW3x is connected to the x-th bit of the second digital code D. ADDR2 [x];

[0067] The source of the third NMOS transistor M3x is connected to ground, and its gate is connected to the third bias voltage Vbn3 of the common gate transimpedance amplifier, which is the gate bias voltage of the third bias transistor M5 in the current mode logic output stage.

[0068] The output terminals of the third modulation unit are shorted and connected together to the common source terminal CS of the current-mode logic output stage.

[0069] The xth second digit code D ADDR2 [x] controls the bias current of the first differential input common source transistor M4a and the second differential input common source transistor M4b.

[0070] Second digital code D ADDR2 [x] controls the bias current of the first differential input common-source transistor M4a and the second differential input common-source transistor M4b. The modulation effect is shown in Figure 5(b). Generally, the address modulation pulse amplitude circuit can be extended to m bits.

[0071] Furthermore, the current-mode logic output stage includes: a first differential input common-source transistor M4a, a second differential input common-source transistor M4b, and a third bias transistor M5. The source of the first differential input common-source transistor M4a is connected to the common-source terminal CS, the drain is connected to the positive output terminal Voutp, and the gate is connected to the negative input terminal V2n. Conversely, the source of the second differential input common-source transistor M4b is connected to the common-source terminal CS, the drain is connected to the negative output terminal Voutn, and the gate is connected to the positive input terminal V2p. The source of the third bias transistor M5 is connected to ground, the drain is connected to the common-source terminal CS, and the gate is connected to the third bias voltage Vbn3. The positive output terminal Voutp can be connected to a first external load resistor R. Lp and the first external load capacitor C Lp The negative output terminal Voutn can be connected to a second external load resistor R. Ln Second external load capacitor C Ln .

[0072] Furthermore, by simultaneously employing the aforementioned address modulation pulse width circuit and address modulation pulse amplitude circuit, an n+m bit two-dimensional addressing function can be achieved.

[0073] The technical solution of this invention can be further expanded, and the tube dimensions of the first modulation unit, the second modulation unit, and the third modulation unit can be designed according to weights. For example, for the address modulation pulse amplitude circuit shown in Figure 5(a), its modulation unit can be designed as follows: D ADDR2 The least significant bit, i.e., D ADDR2 [0] The size of the controlled NMOS transistor (i.e., transistor M30) is the same as that of the third bias transistor M5, D ADDR2 [1] The size of the controlled NMOS transistor (i.e., transistor M31) is twice that of the third bias transistor M5, D ADDR2 [2] The size of the controlled NMOS transistor (i.e., M32 transistor) is 4 times that of the third bias transistor M5, and so on.

[0074] It should be noted that the above circuit, after simple delay and NAND digital logic processing, can easily achieve the modulation effect shown in Figure 6.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications to the technical solutions described in the foregoing embodiments, or equivalent substitutions for some or all of the technical features, do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A time measurement circuit with two-dimensional address modulation TOT pulse function, comprising: Common-mode feedback threshold setting circuit, common-gate transimpedance amplifier, high-speed high-gain comparator, current-mode logic output stage; Its characteristic is that it further includes: a two-dimensional address modulation TOT pulse circuit; The two-dimensional address modulation TOT pulse circuit includes: an address modulation pulse width circuit; The address modulation pulse width circuit includes multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code; The first modulation unit includes a first switch SW1x and a first NMOS transistor M1x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer; One end of the first switch SW1x is connected to the drain of the first NMOS transistor M1x, and the other end of the first switch SW1x serves as the output terminal of the unit; the control terminal of the first switch SW1x is connected to the x-th bit of the first digital code D. ADDR1 [x]; The source of the first NMOS transistor M1x is connected to ground, and the gate of the first NMOS transistor M1x is connected to the first bias voltage Vbn1 of the common gate transimpedance amplifier. The second modulation unit includes a second switch SW2x and a second NMOS transistor M2x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer; One end of the second switch SW2x is connected to the drain of the second NMOS transistor M2x, and the other end of the second switch SW2x serves as the output terminal of the unit; The source of the second NMOS transistor M2x is connected to ground, and the gate of the second NMOS transistor M2x is connected to the first bias voltage Vbn1 of the common-gate transimpedance amplifier; the control terminal of the second switch SW2x is connected to the x-th bit of the first digital code D via the x-th inverter INVx. ADDR1 [x].

2. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 1, characterized in that, The output terminals of the first modulation unit are shorted and connected together to the non-inverting input terminal Iinp of the common-gate transimpedance amplifier.

3. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 2, characterized in that, The output of the second modulation unit is shorted and connected to the negative inverting input terminal Iinn of the common gate transimpedance amplifier.

4. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 1, characterized in that, Also includes: Address modulation pulse amplitude circuit; The address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code; The third modulation unit includes a third switch SW3x and a third NMOS transistor M3x, wherein x takes the values ​​0, 1, 2, ..., n-1, and n is a positive integer; One end of the third switch SW3x is connected to the drain of the third NMOS transistor M3x, and the other end serves as the output terminal of the unit; the control terminal of the third switch SW3x is connected to the x-th bit of the second digital code D. ADDR2 [x]; The source of the third NMOS transistor M3x is connected to ground, and its gate is connected to the third bias voltage Vbn3 of the common gate transimpedance amplifier.

5. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 4, characterized in that, The output terminals of the third modulation unit are shorted and connected together to the common source CS of the current-mode logic output stage; The xth second digit code D ADDR2 [x] Controls the bias current of the current-mode logic output stage.

6. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 1 or 3, characterized in that, The common-gate transimpedance amplifier includes: a first differential input common-gate transistor M1a, a second differential input common-gate transistor M1b, a first differential bias transistor M2a, a second differential bias transistor M2b, and a load; The source of the first differential input common gate transistor M1a is connected to the non-inverting input terminal Iinp, the drain is connected to the load terminal V1p, and the gate is connected to the second bias voltage Vbn2. The source of the first differential bias transistor M2a is connected to ground, the drain is connected to the non-inverting input terminal Iinp, and the gate is connected to the first bias voltage Vbn1. The source of the second differential input common gate transistor M1b is connected to the negative input terminal Iinn, the drain is connected to the load terminal V1n, and the gate is connected to the second bias voltage Vbn2. The source of the second differential bias transistor M2b is connected to ground, the drain is connected to the negative input terminal Iinn, and the gate is connected to the first bias voltage Vbn1.

7. The time measurement circuit with two-dimensional address modulation TOT pulse function according to claim 1 or 5, characterized in that, The current-mode logic output stage includes: a first differential input common source transistor M4a, a second differential input common source transistor M4b, and a third bias transistor M5; The source of the first differential input common-source transistor M4a is connected to the common-source terminal CS, the drain is connected to the positive output terminal Voutp, and the gate is connected to the negative input terminal V2n. The source of the second differential input common-source transistor M4b is connected to the common-source terminal CS, the drain is connected to the negative output terminal Voutn, and the gate is connected to the positive input terminal V2p. The source of the third bias transistor M5 is connected to ground, the drain is connected to the common source terminal CS, and the gate is connected to the third bias voltage Vbn3.

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