Array substrate and display device

Abstract

This application relates to an array substrate and a display device. The array substrate may include a pixel group and a data neutralization circuit. The pixel group includes a first sub-pixel, a neutralization sub-pixel, and a second sub-pixel; a first data line connected to the first sub-pixel; a second data line connected to the second sub-pixel; a neutralization data line connected to the neutralization sub-pixel; and scan lines connected to the first sub-pixel, the second sub-pixel, and the neutralization sub-pixel. The data neutralization circuit is connected to the first data line, the second data line, and the neutralization data line. In a first stage of the horizontal charging phase, the data neutralization circuit can receive a first control signal to control the neutralization data line to be connected to the first data line and disconnected from the second data line. In a second stage of the horizontal charging phase, the data neutralization circuit can receive a second control signal to control the neutralization data line to be disconnected from the first data line and connected to the second data line. This solution can improve vertical resolution while reducing costs.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to an array substrate and a display device. Background Technology

[0002] In TFT-LCD (Thin Film Transistor Liquid Crystal Display), as people's pursuit of display effects increases and the technology matures, the market demand for high-resolution displays is growing. However, as the resolution continues to increase, the cost of the displays also increases. Summary of the Invention

[0003] The purpose of this application is to provide an array substrate and display device that can achieve high resolution while reducing costs.

[0004] This application provides an array substrate, including a display area and a non-display area located at the edge of the display area. The display area includes a plurality of pixel groups arranged in an array along the row and column directions.

[0005] The pixel group includes a first sub-pixel, a second sub-pixel, and a neutral sub-pixel located between the first sub-pixel and the second sub-pixel, which are spaced apart in the row direction. The first sub-pixel, the second sub-pixel, and the neutral sub-pixel have the same display color.

[0006] The pixel group further includes a first data line connected to the first sub-pixel, a second data line connected to the second sub-pixel, a neutralization data line connected to the neutralization sub-pixel, and a scan line connected to the first sub-pixel, the second sub-pixel, and the neutralization sub-pixel;

[0007] The non-display area further includes a data neutralization circuit, connected to the first data line, the second data line, and the neutralization data line; wherein...

[0008] During the charging phase: the scan line can acquire a scan signal to control the first sub-pixel, the second sub-pixel, and the neutralizing sub-pixel to be in an open state; the first data line can acquire a first data signal and charge the first sub-pixel; the second data line can acquire a second data signal and charge the second sub-pixel; the second data signal has the same polarity as the first data signal.

[0009] The charging phase includes at least one first phase and at least one second phase. In the first phase, the data neutralization circuit can receive a first control signal to control the neutralization data line to be connected to the first data line and disconnected from the second data line. In the second phase, the data neutralization circuit can receive a second control signal to control the neutralization data line to be disconnected from the first data line and connected to the second data line.

[0010] In one exemplary embodiment of this application, the data neutralization circuit includes:

[0011] A central control node, which is used to write the first control signal or the second control signal;

[0012] The first transistor has a control terminal connected to the master control node, a first terminal connected to the first data line, and a second terminal connected to the neutralization data line.

[0013] The second transistor has its control terminal connected to the main control node, its first terminal connected to the second data line, and its second terminal connected to the neutralization data line.

[0014] In this transistor, one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.

[0015] In one exemplary embodiment of this application,

[0016] The first sub-pixel, the second sub-pixel, and the neutralizing sub-pixel each include at least a driving transistor and a pixel capacitor. The control terminal of the driving transistor is connected to the scan line, the first terminal of the driving transistor is connected to the corresponding data line, and the second terminal of the driving transistor is connected to the pixel electrode of the pixel capacitor.

[0017] The driving transistor is either a P-type transistor or an N-type transistor, and the first transistor, the second transistor, and the driving transistor are arranged on the same layer.

[0018] In one exemplary embodiment of this application, the display colors of each sub-pixel in the same row are the same, and the display colors of any two adjacent sub-pixels in the same column are different.

[0019] In one exemplary embodiment of this application, during the row charging phase: the data signal of one of two adjacent pixel groups on the same row has the opposite polarity to the data signal of the other;

[0020] The number of data neutralization circuits is the same as the number of pixel groups in a row, and they are connected in a one-to-one correspondence.

[0021] In one exemplary embodiment of this application, the master control nodes of each of the data neutralization circuits are connected in parallel.

[0022] In one exemplary embodiment of this application, the first stage and the second stage have equal durations and are both half the length of the row charging stage.

[0023] In one exemplary embodiment of this application, the data neutralization circuit is disposed near the bonding ends of the first data line and the second data line, and the bonding ends of the first data line and the second data line are configured to be bonded to the source driver chip.

[0024] A second aspect of this application provides a display device comprising a source driver chip, a gate driver chip, a timing controller, and an array substrate as described in any one of the preceding claims.

[0025] The gate driver chip is connected to the scan line, and the source driver chip is connected to the first data line and the second data line.

[0026] The timing controller is connected to the gate driver chip, the source driver chip, and the data neutralization circuit. It is used to control the gate driver chip to provide a scan signal to the scan line, control the source driver chip to provide a first data signal to the first data line, and provide a second data signal to the second data line. In a first stage, it provides a first control signal to the data neutralization circuit and in a second stage, it provides a second control signal to the data neutralization circuit.

[0027] In one exemplary embodiment of this application, the gate driver chip is integrated on the non-display area of ​​the array substrate; and / or

[0028] The display device further includes a counter substrate, liquid crystal molecules, and a backlight module. The counter substrate and the array substrate are disposed in a cell, the liquid crystal molecules are filled between the counter substrate and the array substrate, and the backlight module is located on the side of the array substrate away from the counter substrate.

[0029] The proposed solution has the following beneficial effects:

[0030] By inserting a column of neutralizing subpixels of the same color into two adjacent subpixels of the same color to form a pixel group, and in conjunction with a data neutralization circuit, the data sent to the front-end chip for each pixel group can be two: a first data signal and a second data signal. In reality, three data signals can be displayed: the first data signal, the second data signal, and the neutralizing data signal. This improves the vertical resolution, making the image more detailed, while also reducing the number of front-end chips. For example, the number of source driver chips can be reduced, thereby lowering costs.

[0031] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0034] Figure 1 This is a schematic diagram of the structure of an array substrate mentioned in Embodiment 1 of this application.

[0035] Figure 2 This is a schematic diagram of another array substrate mentioned in Embodiment 1 of this application.

[0036] Figure 3 This is a schematic diagram of another array substrate mentioned in Embodiment 1 of this application.

[0037] Figure 4 This is a timing diagram of the control data neutralization circuit mentioned in Embodiment 1 of this application.

[0038] Figure 5 This is a schematic diagram showing the magnitude of the data signals obtained by the first data line, the second data line, and the neutral data line mentioned in Embodiment 1 of this application.

[0039] Figure 6 This is a schematic diagram of the structure of a display device mentioned in Embodiment 2 of this application.

[0040] Figure 7 This is a schematic diagram of another display device mentioned in Embodiment 2 of this application.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10. Array substrate; 101. Pixel group; 1011. First sub-pixel; 1012. Second sub-pixel; 1013. Neutralizing sub-pixel; Gate, scan line; S1. First data line; S2. Second data line; SA. First data line; 102. Data neutralization circuit;

[0043] 20. Source driver chip; 30. Gate driver chip; 40. Timing controller; 50. Opposing substrate; 60. Liquid crystal molecule; 70. Backlight module;

[0044] Cst, pixel capacitor; DT, driving transistor; T1, first transistor; T2, second transistor; P, master control node; X, row direction; Y, column direction. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0046] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0047] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0048] Example 1

[0049] like Figure 1 As shown, this application embodiment provides an array substrate 10, which may include a display area and a non-display area located at the edge of the display area. The display area may include a plurality of pixel groups 101 arranged in an array along the row direction X and the column direction Y, and the non-display area may include a data neutralization circuit 102.

[0050] Pixel group 101 may include three sub-pixels, three columns of data lines and one row of scan lines. The three sub-pixels correspond to the same display color and are arranged at intervals in the row direction X. They are also connected to the same row of scan lines. In addition, each sub-pixel is also connected to a column of data lines. That is to say, in pixel group 101, sub-pixels are connected to data lines in a one-to-one correspondence.

[0051] like Figure 1As shown, in each pixel group 101: three sub-pixels can be defined as a first sub-pixel 1011, a second sub-pixel 1012, and a neutral sub-pixel 1013 located between the first sub-pixel 1011 and the second sub-pixel 1012. The first sub-pixel 1011, the second sub-pixel 1012, and the neutral sub-pixel 1013 can be connected to the same row of scan lines (Gate). This scan line (Gate) can control the first sub-pixel 1011, the second sub-pixel 1012, and the neutral sub-pixel 1013 to be in an open or closed state. Furthermore, three columns of data lines can be defined... The data lines are a first data line S1, a second data line S2, and a neutralization data line SA. The first data line S1 can be connected to the first sub-pixel 1011, the second data line S2 can be connected to the second sub-pixel 1012, and the neutralization data line SA can be connected to the neutralization sub-pixel 1013. When the first sub-pixel 1011, the second sub-pixel 1012, and the neutralization sub-pixel 1013 are in the open state under the control of the scan line Gate, the data signals on the first data line S1, the second data line S2, and the neutralization data line SA can be correspondingly filled into the sub-pixels connected to them.

[0052] Combination Figure 2 As shown, each sub-pixel may include at least a driving transistor DT and a pixel capacitor Cst. The control terminal of the driving transistor DT is connected to the scan line Gate. The first terminal of the driving transistor DT is connected to the corresponding data line. The second terminal of the driving transistor DT is connected to the pixel electrode of the pixel capacitor Cst. For example, in pixel group 101: the scan line Gate can be simultaneously connected to the control terminals of the driving transistor DT of the first sub-pixel 1011, the second sub-pixel 1012, and the neutralization sub-pixel 1013. The first data line S1 can be connected to the first terminal of the driving transistor DT of the first sub-pixel 1011. The second data line S2 can be connected to the first terminal of the driving transistor DT of the second sub-pixel 1012. The neutralization data line SA can be connected to the first terminal of the driving transistor DT of the neutralization sub-pixel 1013. During the row charging stage, the control terminal of the driving transistor DT can control its first and second terminals to conduct when the scan line Gate obtains a scan signal, so that the data signal on the data line connected to the first terminal of the driving transistor DT can be charged into the pixel capacitor Cst.

[0053] It should be understood that, in combination Figure 2 As shown, the pixel capacitor Cst may also include a common electrode connected to the reference signal terminal Vcom. This common electrode is opposite to and insulated from the pixel electrode to form the pixel capacitor Cst. It should be noted that the reference signal terminal Vcom mentioned in this embodiment may be a constant signal. In addition, the sub-pixel is not limited to including the driving transistor DT, the pixel capacitor Cst, etc., but may also include the data writing transistor, the compensation transistor, etc., depending on the specific situation.

[0054] In this embodiment, combined with Figure 1 and Figure 2 As shown, the data neutralization circuit 102 can be connected to the first data line S1, the second data line S2, and the neutralization data line SA. During the row charging phase: the scan line Gate can acquire a scan signal to control the first sub-pixel 1011 and the second sub-pixel 1012 connected to it to be in an open state. The first data line S1 can acquire a first data signal and charge the first sub-pixel 1011, and the second data line S2 can acquire a second data signal and charge the second sub-pixel 1012. The second data signal has the same polarity as the first data signal. That is, during the row charging phase: the scan line Gate can acquire a scan signal to control the first and second terminals of the driving transistor DT of the first sub-pixel 1011 and the second sub-pixel 1012 to be turned on, so that the first data signal charges the pixel capacitor Cst of the first sub-pixel 1011, and the second data signal charges the pixel capacitor Cst of the second sub-pixel 1012.

[0055] It should be noted that "same polarity" means that both the first and second data signals are either positive or both are negative. For example, if the first data signal is 1V and the second data signal is 2V, then the first and second data signals have the same polarity; if the first data signal is -1V and the second data signal is -2V, then the first and second data signals have the same polarity. However, this is not limited to this. When one of the first and second data signals is 0 and the other is a positive or negative signal, it can also be understood as having the same polarity. For example, if the first data signal is 0 and the second data signal is 1V, then the first and second data signals have the same polarity; if the first data signal is 0 and the second data signal is -1V, then the first and second data signals have the same polarity.

[0056] In this embodiment, combined with Figure 3 and Figure 4 As shown, the charging stage t includes at least one first stage t1 and at least one second stage t2.

[0057] In the first stage t1: the data neutralization circuit 102 can receive the first control signal to control the first data line S1 to be connected to the neutralization data line SA, and control the second data line S2 to be disconnected from the neutralization data line SA. Since the neutralization sub-pixel 1013 is connected to the first sub-pixel 1011 and the second sub-pixel 1012 with the same scan line Gate, in the entire row charging stage t: while the scan line Gate receives the scan signal to control the first sub-pixel 1011 and the second sub-pixel 1012 to be in the open state, it can also control the neutralization sub-pixel 1013 to be in the open state. At this time, the first data signal obtained by the first data line S1 can be written into the neutralization data line SA through the data neutralization circuit 102 and charged into the neutralization sub-pixel 1013.

[0058] In the second stage t2: the data neutralization circuit 102 can receive the second control signal to control the first data line S1 to disconnect from the neutralization data line SA, and control the second data line S2 to connect to the neutralization data line SA. Since the neutralization sub-pixel 1013 is connected to the first sub-pixel 1011 and the second sub-pixel 1012 with the same scan line Gate, during the entire row charging stage t: while the scan line Gate receives the scan signal to control the first sub-pixel 1011 and the second sub-pixel 1012 to be in the open state, it can also control the neutralization sub-pixel 1013 to be in the open state. At this time, the second data signal obtained by the second data line S2 can be written into the neutralization data line SA through the data neutralization circuit 102 and charged into the neutralization sub-pixel 1013.

[0059] In other words, during the entire row charging phase t: the signal charged into the first sub-pixel 1011 can be the first data signal, the signal charged into the second sub-pixel 1012 can be the second data signal, and the signal charged into the neutralizing sub-pixel 1013 can be the neutralizing data signal obtained by neutralizing the first data signal and the second data signal.

[0060] In this embodiment, by inserting a column of neutralizing sub-pixels 1013 of the same color into two adjacent sub-pixels of the same color and cooperating with the data neutralization circuit 102, the data sent by the front-end chip to each pixel group 101 can be two: a first data signal and a second data signal. In reality, three data can be displayed: the first data signal, the second data signal, and the neutralizing data signal. This achieves the effect of improving the vertical resolution, making the picture more delicate, while also reducing the number of front-end chips. For example, the number of source driver chips can be reduced, thereby reducing costs.

[0061] The example given is that the time for the first stage t1 and the second stage t2 are equal and both are half the length of the charging stage t. This makes it easier to control and also easier to calculate the value of the neutralization data signal.

[0062] For example: combining Figure 1 and Figure 5As shown, the first data line S1 provides a first data signal of 2V to the first sub-pixel 1011 in the first row, and the second data line S2 provides a second data signal of 4V to the second sub-pixel 1012 in the first row. Therefore, the neutralization data line SA provides a neutralization data signal of 3V to the neutralization sub-pixel 1013 in the first row, which is the result of the neutralization of the first and second data signals. Similarly, the first data line S1 provides a first data signal of -1V to the first sub-pixel 1011 in the second row, and the second data line S2 provides a second data signal of -1V to the second sub-pixel 1012 in the second row. Therefore, the neutralization data line SA provides a neutralization data signal of -1V to the neutralization sub-pixel 1013 in the second row, which is the result of the neutralization of the first and second data signals. V; The first data line S1 provides a first data signal of 2V to the first sub-pixel 1011 in the third row, and the second data line S2 provides a second data signal of 0V to the second sub-pixel 1012 in the third row. Then, the neutral data line SA provides a data signal of 1V to the neutral sub-pixel 1013 in the third row, which is the neutral data signal after the first data signal and the second data signal are neutralized. The first data line S1 provides a first data signal of -2V to the first sub-pixel 1011 in the fourth row, and the second data line S2 provides a second data signal of -4V to the second sub-pixel 1012 in the fourth row. Then, the neutral data line SA provides a data signal of -3V to the neutral sub-pixel 1013 in the fourth row, which is the neutral data signal after the first data signal and the second data signal are neutralized.

[0063] It should be understood that in the horizontal charging phase t, both the first phase t1 and the second phase t2 are set to one segment. This avoids excessive power loss caused by switching back and forth for control. In addition, the time of the first phase t1 and the second phase t2 is not required to be equal. The proportion of the first phase t1 and the second phase t2 in the horizontal charging phase t can be adjusted according to the actual display requirements to ensure the final display effect.

[0064] In one specific embodiment, such as Figure 3As shown, the data neutralization circuit 102 may include a master control node P, a first transistor T1, and a second transistor T2. The master control node P is used to write a first control signal or a second control signal. The control terminal of the first transistor T1 is connected to the master control node P, the first terminal of the first transistor T1 is connected to the first data line S1, and the second terminal of the first transistor T1 is connected to the neutralization data line SA. The control terminal of the second transistor T2 is connected to the master control node P, the first terminal of the second transistor T2 is connected to the second data line S2, and the second terminal of the second transistor T2 is connected to the neutralization data line SA. Among them, one of the first transistor T1 and the second transistor T2 is an N-type transistor and the other is a P-type transistor. That is to say, the first control signal and the second control signal received by the master control node P are opposite, that is, one of the first control signal and the second control signal is high level and the other is low level.

[0065] In this embodiment, by employing the data neutralization circuit 102 described above, while simultaneously filling the neutralization sub-pixel 1013 with the first data signal and the second data signal at different time periods during row scanning, the number of control lines controlling the operation of the data neutralization circuit 102 can be reduced since the control terminals of the first transistor T1 and the second transistor T2 are both connected to the same master control node P. For example, in this embodiment, the data neutralization circuit 102 only needs one control line connected to the master control node P to simultaneously control the switching states of the first transistor T1 and the second transistor T2 of the data neutralization circuit 102.

[0066] For example, the driving transistor DT can be a P-type transistor or an N-type transistor, and can be set on the same layer as the first transistor T1 and the second transistor T2, so that the same patterning process can be used.

[0067] In this application, "same-layer configuration" refers to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses, thereby simplifying the manufacturing process, saving manufacturing costs, and improving production efficiency.

[0068] For example, when the first transistor T1 is an N-type transistor and the second transistor is a P-type transistor, the first control signal can be a high-level signal and the second control signal can be a low-level signal; and when the driving transistor is an N-type transistor, the corresponding scan signal can be a high-level signal.

[0069] In this embodiment, the display colors of all sub-pixels in the same row are the same, and the display colors of any two adjacent sub-pixels in the same column are different. Taking the Tri-Gate driving architecture as an example, the Tri-Gate driving architecture arranges red, green, and blue sub-pixels vertically (i.e., arranged in the column direction Y). Figure 1 As shown, the display color corresponding to each sub-pixel in the first row is red, the display color corresponding to each sub-pixel in the second row is green, the display color corresponding to each sub-pixel in the third row is blue, the display color corresponding to each sub-pixel in the fourth row is red, and so on. This design can reduce the number of source driver chips, thereby reducing costs.

[0070] In this embodiment, during the row charging phase t: the data signals of one of two adjacent pixel groups 101 on the same row have opposite polarities to the data signals of the other.

[0071] For example, two adjacent pixel groups 101 on the same row can be defined as a first pixel group and a second pixel group. When at least one of the first data signal and the second data signal obtained by the first pixel group is positive, then at least one of the first data signal and the second data signal obtained by the second pixel group can be negative. When at least one of the first data signal and the second data signal obtained by the first pixel group is negative, then at least one of the first data signal and the second data signal obtained by the second pixel group can be positive, so as to reduce crosstalk and improve the display effect.

[0072] In this embodiment, since the data signals of one of two adjacent pixel groups 101 in the same row have opposite polarities to the data signals of the other, each pixel group 101 needs to be matched with a data neutralization circuit 102. That is, the number of data neutralization circuits 102 can be the same as the number of pixel groups 101 in a row, and they are connected one by one.

[0073] Taking UHD (Ultra High Definition) 60Hz as an example, the front end sends in 4K*2K 60Hz data, but can actually display 6K*2K 60Hz data.

[0074] In this system, the master control node P of each data neutralization circuit 102 is connected in parallel, that is, the master control node P of each data neutralization circuit 102 is connected to the same control line. This enables unified control of each pixel group 101, simplifies the control method, and also reduces the wiring design, which is conducive to achieving high PPI (resolution) display.

[0075] In this embodiment, the data neutralization circuit 102 is located near the bonding ends of the first data line S1 and the second data line S2. The bonding ends of the first data line S1 and the second data line S2 are configured to be bonded to the source driver chip. This allows the neutralization data line SA to write data signals from the same side as the first data line S1 and the second data line S2, so as to avoid the voltage drop generated on the first data line S1 and the second data line S2 from affecting the accuracy of the neutralization data signal in the neutralization sub-pixel 1013.

[0076] Example 2

[0077] This embodiment provides a display device, such as... Figure 6 As shown, it may include a source driver chip 20, a gate driver chip 30, a timing controller 40, and an array substrate 10 as described in any one of the embodiments. The gate driver chip 30 is connected to the scan line Gate, the source driver chip 20 is connected to the first data line S1 and the second data line S2, and the timing controller 40 is connected to the gate driver chip 30, the source driver chip 20, and the data neutralization circuit 102. It is used to provide a first control signal to the data neutralization circuit 102 in the first stage t1 and a second control signal to the data neutralization circuit 102 in the second stage t2 while controlling the gate driver chip 30 to provide a scan signal to the scan line Gate and controlling the source driver chip 20 to provide a first data signal to the first data line S1 and a second data signal to the second data line S2.

[0078] The gate drive chip 30 can be integrated on the array substrate 10 and can be understood as a GOA circuit.

[0079] The display device in this embodiment can be a liquid crystal display device, specifically, such as... Figure 7 As shown, in addition to the aforementioned structure, the display device may also include an opposing substrate 50, liquid crystal molecules 60, and a backlight module 70. The opposing substrate 50 and the array substrate 10 are disposed in a cell, the liquid crystal molecules 60 are filled between the opposing substrate 50 and the array substrate 10, and the backlight module 70 is located on the side of the array substrate 10 away from the opposing substrate 50. However, it is not limited to this and may also be an OLED or other display device, depending on the specific circumstances.

[0080] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0081] It should be noted that terms such as "upper," "lower," "left," and "right" are used only for distinction and convenience of description, and do not impose any positional limitations on the embodiments of the present invention. For example, "upper" in practice can refer to "lower," "left," or "right." In this application, unless otherwise explicitly specified and limited, terms such as "assembly" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0082] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. An array substrate, comprising a display area and a non-display area located at the edge of the display area, the display area comprising a plurality of pixel groups arranged in an array along row and column directions, characterized in that, The pixel group includes a first sub-pixel, a second sub-pixel, and a neutral sub-pixel located between the first sub-pixel and the second sub-pixel, which are spaced apart in the row direction. The first sub-pixel, the second sub-pixel, and the neutral sub-pixel have the same display color. The pixel group further includes a first data line connected to the first sub-pixel, a second data line connected to the second sub-pixel, a neutralization data line connected to the neutralization sub-pixel, and a scan line connected to the first sub-pixel, the second sub-pixel, and the neutralization sub-pixel; The non-display area also includes a data neutralization circuit, which includes a master control node, a first transistor, and a second transistor. The control terminal of the first transistor is connected to the master control node, the first terminal of the first transistor is connected to the first data line, and the second terminal of the first transistor is connected to the neutralization data line. The control terminal of the second transistor is connected to the master control node, the first terminal of the second transistor is connected to the second data line, and the second terminal of the second transistor is connected to the neutralization data line. One of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor. During the row charging phase: the scan line acquires a scan signal to control the first sub-pixel, the second sub-pixel, and the neutralizing sub-pixel to be in an open state; the first data line acquires a first data signal and charges the first sub-pixel and the neutralizing sub-pixel; the second data line acquires a second data signal and charges the second sub-pixel and the neutralizing sub-pixel; the second data signal has the same polarity as the first data signal; wherein, the data signal charged to the neutralizing sub-pixel is the neutralized data signal obtained by neutralizing the first data signal and the second data signal. The charging stage includes at least one first stage and at least one second stage. In the first stage: the master control node can receive a first control signal to control the neutralization data line to be connected to the first data line and disconnected from the second data line; in the second stage: the data neutralization circuit can receive a second control signal to control the neutralization data line to be disconnected from the first data line and connected to the second data line. The display colors of all sub-pixels in the same row are the same, and the display colors of any two adjacent sub-pixels in the same column are different.

2. The array substrate according to claim 1, characterized in that, The first sub-pixel, the second sub-pixel, and the neutralizing sub-pixel each include at least a driving transistor and a pixel capacitor. The control terminal of the driving transistor is connected to the scan line, the first terminal of the driving transistor is connected to the corresponding data line, and the second terminal of the driving transistor is connected to the pixel electrode of the pixel capacitor. The driving transistor is either a P-type transistor or an N-type transistor, and the first transistor, the second transistor, and the driving transistor are arranged on the same layer.

3. The array substrate according to claim 1, characterized in that, During the row charging phase: the data signals of one of two adjacent pixel groups on the same row have opposite polarities to the data signals of the other; The number of data neutralization circuits is the same as the number of pixel groups in a row, and they are connected in a one-to-one correspondence.

4. The array substrate according to claim 3, characterized in that, The control nodes of the data and circuits described above are connected in parallel.

5. The array substrate according to claim 1, characterized in that, The first stage and the second stage have equal durations and are both half the length of the row charging stage.

6. The array substrate according to claim 1, characterized in that, The data neutralization circuit is located near the bonding ends of the first data line and the second data line, and the bonding ends of the first data line and the second data line are configured to be bonded to the source driver chip.

7. A display device, characterized in that, Includes a source driver chip, a gate driver chip, a timing controller, and an array substrate as described in any one of claims 1 to 6. The gate driver chip is connected to the scan line, and the source driver chip is connected to the first data line and the second data line. The timing controller is connected to the gate driver chip, the source driver chip, and the data neutralization circuit. It is used to control the gate driver chip to provide a scan signal to the scan line, control the source driver chip to provide a first data signal to the first data line, and provide a second data signal to the second data line. In a first stage, it provides a first control signal to the data neutralization circuit and in a second stage, it provides a second control signal to the data neutralization circuit.

8. The display device according to claim 7, characterized in that, The gate driver chip is integrated on the non-display area of ​​the array substrate; and / or The display device further includes a counter substrate, liquid crystal molecules, and a backlight module. The counter substrate and the array substrate are disposed in a cell, the liquid crystal molecules are filled between the counter substrate and the array substrate, and the backlight module is located on the side of the array substrate away from the counter substrate.

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