A silicon wafer defect classification method based on combined convolution

Abstract

The application relates to a silicon wafer defect classification method based on combined convolution, which comprises the following steps: collecting a defect image data set of a silicon wafer; constructing a defect image detection model of the silicon wafer; inputting a silicon wafer defect image to an input layer; a double-branch convolution network is provided with different direction perception convolution kernels, so that defects can be captured from different angles in a defect image recognition process; a multi-scale convolution network is used to simultaneously capture large-scale and small-scale defect features; a feature fusion layer is used to fuse the output features of the double-branch convolution network and the multi-scale convolution network; a full connection layer contains a plurality of neurons, each neuron representing a silicon wafer defect category; an output layer is used to convert the score of each silicon wafer defect category into a probability output; a silicon wafer defect image in a silicon wafer defect image data set is labeled and input into a detection model for training; and the trained detection model is deployed into a silicon wafer detection system.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor wafer detection technology, and particularly relates to a wafer defect classification method based on combined convolution. BACKGROUND

[0002] A wafer is a basic material for the semiconductor industry, and its quality has a significant impact on the performance of integrated circuits and electronic devices. Various defects may occur during wafer manufacturing, and these defects need to be identified and classified through efficient detection methods. Traditional defect detection methods mainly rely on manual detection, which is inefficient and prone to errors.

[0003] The existing technology has some defects in the wafer defect classification task, mainly including the following points:

[0004] 1. Limited feature extraction capability: Existing image processing and machine learning methods are limited in feature extraction by hand-designed features, which makes it difficult for them to extract effective and rich feature information when processing complex wafer defect images, resulting in limited classification performance.

[0005] 2. Lack of multi-scale feature processing capability: Existing technology cannot effectively process wafer defect features of different scales and complexities. For multi-scale feature processing, more complex algorithms and models need to be designed to capture detailed information of wafer defects, increasing the design difficulty and the computational load of the model.

[0006] 3. Weak generalization ability: Existing technology in wafer defect classification tasks often requires more human intervention and adjustment, limiting the generalization ability of the model. When facing new defect types or different production environments, existing technology may need to be redesigned and adjusted. SUMMARY

[0007] The purpose of the present application is to provide a wafer defect classification method based on combined convolution, which solves the above problems of existing technology.

[0008] The application discloses a silicon wafer defect classification method based on combined convolution, and the method comprises the following steps: step 1, collecting a defect image dataset of a silicon wafer; step 2, constructing a defect image detection model of the silicon wafer, wherein the model comprises an input layer, an initial convolution layer, a maximum pooling layer, a branch layer, a feature fusion layer, a full connection layer and an output layer; the input layer inputs a silicon wafer defect image; the branch layer comprises a double-branch convolution network and a multi-scale convolution network; the double-branch convolution network is provided with convolution kernels in different directions so as to capture defects from different angles in the process of recognizing the silicon wafer defect image; the multi-scale convolution network is used for simultaneously capturing large-scale and small-scale defect features so as to simulate complex silicon wafer defect structures and different silicon wafer defect types; the feature fusion layer fuses the output features of the double-branch convolution network and the multi-scale convolution network; the full connection layer comprises a plurality of neurons, and each neuron represents a silicon wafer defect category; the neurons are classified and activated, and the output features of the feature fusion layer are used for defect classification and recognition; and the output layer converts the scores of each silicon wafer defect category into probability output.

[0009] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the feature fusion layer fuses the output of the double-branch convolution network and the multi-scale convolution network by using a concatenate operation to obtain a fused feature map.

[0010] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the fused feature map is flattened into a one-dimensional vector as the input of the full connection layer, each neuron of the full connection layer has a weight corresponding to the input node, and a bias term is added to the output of each neuron.

[0011] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the output layer comprises five neurons corresponding to silicon wafer crack, water stain, notch, sand particle and stain defects respectively.

[0012] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the double-branch convolution network comprises: the initial convolution layer adopts a large convolution kernel for convolution operation so as to capture the global structure and large-scale features of the silicon wafer and detect long defects such as cracks and notches; the branch layer comprises two branches, each branch adopts a convolution kernel of different size, and corresponds to small and local defects such as water stains and large defects such as sand particles; the output feature maps of the two branches are combined by means of feature fusion so as to comprehensively consider the feature information of defects of different sizes.

[0013] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the multi-scale convolution network comprises: an initial convolution layer uses a large convolution kernel for convolution operation to capture the global structure and large-scale features of the silicon wafer; parallel convolution layers use convolution kernels of different sizes to capture features of different scales, for large defects such as sand grains, the particle features are detected by a large convolution kernel; for small defects such as cracks and water stains, the detailed features are detected by a small convolution kernel; and the output feature maps of the parallel convolution layers are combined in a feature fusion manner to comprehensively consider the feature information of defects of different sizes.

[0014] According to an embodiment of the silicon wafer defect classification method based on combined convolution, for silicon wafer crack defects, the features of the cracks are detected by the direction perception convolution kernel in the double-branch convolution network, and the multi-scale convolution network captures crack texture features of different scales and directions; for silicon wafer water stain defects, the concave-convex features of the water stains are extracted by the local perception domain convolution kernel in the double-branch convolution network, and the multi-scale convolution network performs perception of scale and shape diversity; for silicon wafer notch defects, the local shape and texture features of the notch are obtained by the local perception domain convolution kernel in the double-branch convolution network, and the multi-scale convolution network captures notch information of different scales and depths; for silicon wafer stain and sand grain defects, the edge and texture features in the double-branch convolution network extract the shape and color features of the stain and sand grain, and the multi-scale convolution network captures texture changes of different scales and shapes.

[0015] According to an embodiment of the silicon wafer defect classification method based on combined convolution, step 3 specifically comprises: scaling the silicon wafer image data, generating a silicon wafer defect label file by defect labeling using labelimage, labeling a certain number of silicon wafer defect images, the defects including cracks, water stains, notches, sand grains and stains, dividing the silicon wafer image and the silicon wafer defect label file into a data set and a validation set, and inputting the detection model for training.

[0016] According to an embodiment of the silicon wafer defect classification method based on combined convolution, the method further comprises model evaluation on the trained detection model, evaluating the performance of the detection model on the validation set, including accuracy and recall rate, and adjusting and optimizing the detection model according to the evaluation result to improve the performance of the silicon wafer defect classification.

[0017] According to an embodiment of the silicon wafer defect classification method based on combined convolution, for a silicon wafer crack defect, a full connection layer comprehensively fuses a double-branch convolution network and a multi-scale convolution network for cracks of different scales and directions; for a silicon wafer water mark defect, a full connection layer comprehensively fuses features of different scales and shapes of results of the double-branch convolution network and the multi-scale convolution network to improve the classification effect of the water mark; for a silicon wafer gap defect, a full connection layer comprehensively fuses features of different scales, textures and depths of results of the double-branch convolution network and the multi-scale convolution network to improve the classification accuracy of the gap; for a silicon wafer stain and grit defect, a full connection layer comprehensively fuses features of different textures and scales of results of the double-branch convolution network and the multi-scale convolution network to improve the classification accuracy of the stain and the grit.

[0018] The silicon wafer defect classification method based on combined convolution solves the problem in the silicon wafer defect classification task and can efficiently and accurately perform silicon wafer defect classification. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1a is a schematic diagram of a silicon wafer defect;

[0020] Figure 1b is a schematic diagram of another silicon wafer defect;

[0021] Figure 1c is a schematic diagram of a silicon wafer detection. DETAILED DESCRIPTION

[0022] To make the purpose, content and advantages of the present application clearer, the specific embodiments of the present application are described in further detail below in combination with the drawings and examples.

[0023] The silicon wafer defect classification method based on combined convolution includes:

[0024] Step 1, data set acquisition, including:

[0025] In the defect data collection of the silicon wafer, the defect sample of the silicon wafer with the size of 166-210 mm is collected. In the sample collection, the defect sample under 3 focal lengths is collected, respectively, which are: in focus clear state, on this basis, aperture is increased by 0.1 and reduced by 0.1, to realize the blur collection of the defect. The silicon wafer defect data set under multiple clear states is obtained.

[0026] The silicon wafer image collection method of the embodiment improves the multi-scale nature of the defect and the robustness of the detection. In the production of the silicon wafer, the thickness of the silicon wafer is an important index of the silicon wafer. Therefore, the embodiment can adapt to different silicon wafers. When the thickness exceeds the camera depth of field, the silicon wafer defect is detected.

[0027] Step 2, construct a defect image detection model of the silicon wafer, and the structure of the defect image detection model comprises:

[0028] 2.1 input layer

[0029] The input layer inputs three kinds of definition images with a size of 640x640 (i.e., the input size is 640x640x3).

[0030] 2.2 initial convolution layer

[0031] The initial convolution layer constructs 32 convolution kernels with a size of 7x7, and performs initial convolution on the input image with a step of 2.

[0032] An output feature map with a size of 320x320x32 is outputted.

[0033] 2.3 maximum pooling layer

[0034] A maximum pooling operation with a size of 2x2 is adopted to halve the size of the feature map with a step of 2.

[0035] An output feature map with a size of 160x160x32 is outputted.

[0036] 2.4 branch layer, which is composed of a double-branch convolution network and a multi-scale convolution network.

[0037] The inventors have found through long-term practice that silicon wafer defects not only differ in shape, size and type, but also can exist in different spatial positions and directions. Through various attempts on each link of the whole process of silicon wafer detection, the inventors have found that since a general convolution kernel can only capture features in a certain direction, the recognition ability for defects in different directions is limited, and a single convolution network can not completely capture these diversified features. Therefore, the inventors thought that a double-branch convolution network can be tried to set convolution kernels with different direction perception, so as to have better control and processing ability for such directional defects in the process of silicon wafer defect recognition, and can capture defects from different angles. A single network can miss some characteristics or be not sensitive enough to some types of defects, which can lead to wrong decisions.

[0038] Therefore, it is found through attempts that two branches of convolution network can be used, and the two branches of convolution network can have their own independent learning and optimization strategies. For example, one branch of network can be used to process a type of defect or optimize on a specific scale of feature, while the other branch of network solves other problems. This provides greater flexibility and increases the processing capacity and accuracy of the model. The decision result of the double-branch network is made by both branches, which is equivalent to an additional "voting", which reduces the risk of wrong decisions to a certain extent.

[0039] Two-branch convolutional network can extract different types or levels of defect features, so as to realize feature complementation.

[0040] 2.4.1 Structure of the two-branch convolutional network is:

[0041] Convolutional branch 1 includes:

[0042] I Convolutional layer

[0043] Convolve the input feature map with 64 3x3 convolutional kernels with a step size of 1.

[0044] Output a feature map of 160x160x64.

[0045] II Max-pooling layer

[0046] Use a 2x2 max-pooling operation to halve the feature map size with a step size of 2.

[0047] Output a feature map of 80x80x64.

[0048] III Convolutional layer

[0049] Convolve the feature map with 128 3x3 convolutional kernels with a step size of 1.

[0050] Output a feature map of 80x80x128.

[0051] IV Max-pooling layer

[0052] Use a 2x2 max-pooling operation to halve the feature map size with a step size of 2.

[0053] Output a feature map of 40x40x128.

[0054] Convolutional branch 2 includes:

[0055] I Convolutional layer

[0056] Convolve the input feature map with 32 5x5 convolutional kernels with a step size of 1.

[0057] Output a feature map of 160x160x32.

[0058] II Max-pooling layer

[0059] Use a 2x2 max-pooling operation to halve the feature map size with a step size of 2.

[0060] Output a feature map of 80x80x32.

[0061] III Convolutional layer

[0062] Convolve the input feature map with 64 5x5 convolutional kernels with a step size of 1.

[0063] Output 80x80x64 feature maps.

[0064] IV Max-pooling layer

[0065] A max-pooling operation with a 2x2 kernel is applied to halve the feature map size with a stride of 2.

[0066] Output 40x40x64 feature maps.

[0067] Feature fusion layer:

[0068] The output features of the two branches are fused using concatenate.

[0069] The output size is 40x20x192.

[0070] 2.4.2 Multi-scale convolutional network includes:

[0071] The inventors found that defects on a silicon wafer can occur at different scales. For example, a crack can span the entire wafer, while a tiny piece of debris or a speckle can occupy only a small area. Using a single-scale convolutional network does not yield good results. The inventors realized that a multi-scale convolutional network can capture both large-scale and small-scale defect features simultaneously. Large-scale convolutional layers can detect a wider area, helping the model understand the global layout of a crack or other large-scale defects. Small-scale convolutional layers, on the other hand, can focus on details, such as detecting tiny speckles or capturing the fine structure of a crack. This structure ensures that the model has good accuracy and sensitivity at different scales.

[0072] A multi-scale convolutional network not only focuses on features at a specific scale, but also automatically learns and adapts to the most important features at different scales. This ability gives the model strong generalization capabilities, allowing it to perform well when detecting new, unknown defects.

[0073] By connecting convolutional layers with different kernel sizes in parallel, a multi-scale convolutional network can simulate complex silicon wafer defect structures and diverse defect types.

[0074] The structure of the multi-scale convolutional network includes:

[0075] I Convolutional layer

[0076] Convolve the feature maps output in 3) using 64 3x3 convolutional kernels with a stride of 1.

[0077] Output 160x160x64 feature maps.

[0078] II Max-pooling layer

[0079] The feature map size is halved with a stride of 2 using a 2x2 max pooling operation.

[0080] An output of 80x80x64 feature maps.

[0081] III Three parallel convolutional layers

[0082] One 1x1 convolutional layer with a stride of 1, one convolutional layer using a 3x3 kernel with a stride of 1, and one 5x5 convolutional layer with a stride of 1.

[0083] An output of three 80x80x32 feature maps.

[0084] IV Feature fusion layer

[0085] The output features of the three parallel convolutional layers are fused using concatenate.

[0086] An output of 80x80x96 feature maps.

[0087] V Max pooling layer

[0088] The feature map size is halved with a stride of 2 using a 2x2 max pooling operation, and an output of 40x40x96 feature maps.

[0089] 2.5 Feature fusion layer, comprising:

[0090] The feature fusion layer actually fuses the output feature maps of the double-branch convolutional network and the multi-scale convolutional network to comprehensively utilize the feature information extracted by different branches. The results of the two branch networks can be complementary and fused through the feature fusion layer and the fully connected layer. In the feature fusion layer, the output feature maps of the two branch networks will be fused, and they can usually be connected using the concatenate operation. In this way, the different scale and shape features extracted by different branches will be integrated to improve the classification ability of the diversity of silicon wafer defects. The fused feature maps will be passed as input to the next layer.

[0091] The feature fusion layer specifically fuses the outputs of the double-branch convolutional network and the multi-scale convolutional network in the 4) branch layer using concatenate to obtain 40x40x288 feature maps.

[0092] 2.6 Fully connected layer, comprising:

[0093] In the fully connected layer, the fused feature maps will be flattened into a one-dimensional vector and input into the fully connected layer for classification operation. The fully connected layer can contain multiple neurons, each representing a defect category. By activating these neurons for classification, all fused features are used for final defect classification and recognition.

[0094] The output of the feature fusion layer in 2.5 is flattened into a one-dimensional vector. The 40x40x288 is rearranged in order into a one-dimensional vector with a length of 40x40x288=204800. This one-dimensional vector can be regarded as a linear representation of the input sample features.

[0095] The vector after the flattening process (length 204800) will be used as the input of the fully connected layer. In this fully connected layer, there are 128 neurons. Each neuron has weights corresponding to the input nodes, that is, each neuron has 204800 weights. The weighted sum of the neuron and the input vector will produce the original output value of the neuron: y=w1x1+w2x2+…+w[204800]x[204800], where w represents the weight and x represents the value in the flattened input vector.

[0096] In order to improve the fitting ability of the model, a bias term (bias) is added to the output of each neuron, so the output of the neuron will become y=w1x1+w2x2+…+w[204800]x[204800]+b, where b is the bias of this neuron.

[0097] In order to introduce nonlinear characteristics and enhance the expression ability of the model, a nonlinear activation function is applied to the output of the fully connected layer. The ReLU activation function is selected. ReLU returns the larger value of the input value and 0, that is, ReLU(y)=max(0,y). In this way, the activation value of each neuron can be represented as ReLU(w1x1+w2x2+…+w[204800]x[204800]+b).

[0098] The above steps are repeated for the 128 neurons, and finally a 128-dimensional output vector is obtained. This 128-dimensional vector will be used as the input of the subsequent fully connected layer (output layer).

[0099] 2.7 The output layer includes:

[0100] The last layer is a fully connected layer with 5 neurons corresponding to 5 categories (cracks, water stains, notches, sand particles, and stains). Here, the softmax function is used to convert the score of each category into a probability output.

[0101] Further, the present application is directed to different defect categories of the silicon wafer, including cracks, water stains, notches, stains, and sand particles. The construction process and convolution kernel size selection of the double-branch convolutional network and the multi-scale convolutional network for different defect categories of the silicon wafer include:

[0102] Construction process of the double-branch convolutional network:

[0103] a. Initial convolutional layer: A larger convolutional kernel (e.g., 7x7) is used for convolution operation to capture the global structure and larger scale features of the wafer. For defects like cracks and notches, which are relatively long, a larger convolutional kernel can better detect their shape and location.

[0104] b. Branch layer: It includes two branches, each using a different size of convolutional kernel. For example, for defects like water stains, which are relatively small and local, a branch can use a 3x3 convolutional kernel for feature extraction. For defects like sand particles, which are relatively large, a larger convolutional kernel (e.g., 5x5) can be used to better detect their grain features.

[0105] c. Feature fusion: The output feature maps of the two branches are combined through feature fusion to consider the feature information of defects of different sizes. This can improve the model's classification ability for defects of different sizes.

[0106] Construction process of multi-scale convolutional network:

[0107] a. Initial convolutional layer and parallel convolutional layer: Similarly, the initial convolutional layer uses a larger convolutional kernel (e.g., 7x7) for convolution operation to capture the global structure and larger scale features of the wafer. The parallel convolutional layer uses different sizes of convolutional kernels (e.g., 1x1, 3x3, 5x5) to capture features of different scales. For defects like sand particles, which are relatively large, a larger convolutional kernel can better detect their grain features; for defects like cracks and water stains, which are relatively small, a smaller convolutional kernel can better detect their detailed features.

[0108] b. Feature fusion: The output feature maps of the parallel convolutional layer are combined through feature fusion to consider the feature information of defects of different sizes. This can improve the model's classification ability for defects of different sizes.

[0109] Convolutional kernel size selection:

[0110] Larger convolutional kernels (e.g., 7x7) are used for the initial convolutional layer and the initial convolutional layer of the parallel convolutional layer, which can increase the receptive field and capture the global structure and larger scale features of the wafer.

[0111] Smaller convolutional kernels (e.g., 3x3 and 5x5) are used for the branch layer and the parallel convolutional layer, which can better capture the local detailed features of wafer defects.

[0112] By using different sizes of convolutional kernels in different layers and branches, features of different scales and levels can be extracted. This multi-scale feature extraction capability can better capture the diversity and complexity of wafer defects. Further, feature fusion can comprehensively utilize the feature information of defects of different sizes, improving the model's accuracy and generalization ability for defects of different sizes.

[0113] For a preferred embodiment, the complementarity of the two convolutional networks in the feature fusion layer and the fully connected layer includes:

[0114] Silicon wafer crack: In the fusion layer, the features of the crack can be detected by the direction-aware convolutional kernels in the double-branch convolutional network, while the multi-scale convolutional network can capture the crack texture features of different scales and directions. In the fully connected layer, the fusion results of the two convolutional networks can provide comprehensive performance for cracks of different scales and directions.

[0115] Silicon wafer water spot: In the fusion layer, the concave-convex features of the water spot can be extracted by the local perception domain convolutional kernels in the double-branch convolutional network, while the multi-scale convolutional network can perceive the scale and shape diversity. In the fully connected layer, the fusion results of the two convolutional networks can comprehensively utilize features of different scales and shapes to improve the classification effect of water spots.

[0116] Silicon wafer gap: In the fusion layer, the local shape and texture features of the gap can be obtained by the local perception domain convolutional kernels in the double-branch convolutional network. While the multi-scale convolutional network can capture gap information of different scales and depths. In the fully connected layer, the fusion results of the two convolutional networks can comprehensively consider features of different scales, textures and depths to improve the classification accuracy of the gap.

[0117] Silicon wafer stain and grit: In the fusion layer, the edge and texture features in the double-branch convolutional network can extract the shape and color features of the stain and grit. While the multi-scale convolutional network can capture texture changes of different scales and shapes. In the fully connected layer, the fusion results of the two convolutional networks comprehensively utilize features of different textures and scales to improve the classification accuracy of the stain and grit.

[0118] For a preferred embodiment, the structure and construction process of the feature fusion layer includes:

[0119] The output feature maps of the two branches are connected along the channel dimension using the concatenate operation.

[0120] First, for each branch network, after convolution, activation function (such as ReLU), pooling and other operations, the respective feature maps are obtained.

[0121] The feature maps of the two branches are concatenated in the channel dimension, and they are connected in order. For example, assuming that the output feature map of one branch is [H1, W1, C1] and the output feature map of the other branch is [H2, W2, C2], the shape after the concatenate operation is [H1, W1, C1+C2].

[0122] The fused feature maps are passed as input to the next layer, such as a fully connected layer, for final classification operation.

[0123] Step 3, Model training: Scale the silicon wafer image data to 640x640, use labelimage to generate defect label files for silicon wafer defects, label 1000 silicon wafer defect images, defects include cracks, water stains, gaps, sand, and stains. Divide the images and labels into a dataset with 70% and a validation set with 30%. Use the dataset to input the network for training.

[0124] Step 4, Model evaluation: Evaluate the performance of the model on the validation set, such as accuracy, recall rate, etc. According to the evaluation results, adjust and optimize the model to improve the performance of silicon wafer defect classification.

[0125] Step 5, Model deployment: Deploy the trained model to the actual production environment to detect and classify silicon wafer defects in real time. Figure 1a is a schematic view of a silicon wafer defect; Figure 1b is a schematic view of another silicon wafer defect; Figure 1c is a schematic view of a silicon wafer inspection, as shown in Figure 1a -c.

[0126] There are several types of defects in silicon wafers, such as cracks, water stains, gaps, stains, and sand, which have different performance characteristics at the microscopic level. The machine learning model combining multi-scale convolution and dual-branch convolution can exactly meet this requirement. Crack: Cracks usually appear as thin, elongated lines that span different areas of the silicon wafer. Therefore, the convolution layer of the multi-scale convolution large-scale perception domain can capture the overall structure of the crack, and the convolution layer of the multi-scale convolution small-scale perception domain can capture some fine features of the crack. Chips and sand: These two defects often exhibit local and point-like properties, and may be small and scattered. The convolution layer of the multi-scale convolution small-scale perception domain can effectively identify these small local defects, and the dual-branch network can more accurately identify these point-like and local defects due to its diversity in feature extraction. Stains: The shape and size of stains often vary greatly, and they can appear anywhere on the silicon wafer. Multi-scale convolution can identify and understand these stains from different scales, and the independence of the dual-branch network allows it to capture stain features while preserving their original location information on the silicon wafer. In summary, the model combining multi-scale convolution and dual-branch convolution takes advantage of the main characteristics of silicon wafer defects, effectively improving the accuracy and efficiency of identifying and classifying silicon wafer defects.

[0127] The present application (1) can effectively extract and express the multi-scale features of silicon wafer defects by adopting the combined convolution strategy and the adaptive feature fusion strategy, thereby realizing high-precision defect classification. Compared with traditional methods or existing deep learning methods, the present application has higher accuracy and recall rate in the task of silicon wafer defect classification. (2) In the model training process, data enhancement, end-to-end training strategy and active learning strategy are adopted, which effectively improves the generalization ability of the model. This enables the model to adapt to different types and sizes of silicon wafer defects, and has good robustness. (3) The efficient and accurate performance in the task of silicon wafer defect classification helps to discover and handle problems on the production line in time, thereby improving production efficiency and product quality. This has high practical value for the fields of semiconductor manufacturing, photovoltaic industry and the like.

[0128] The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled persons in the art, several improvements and modifications can be made without departing from the technical principles of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A method for wafer defect classification based on combined convolution, characterized in that, The method comprises the following steps: Step 1, collecting a defect image dataset of a silicon wafer; Step 2, constructing a defect image detection model of the silicon wafer, comprising an input layer, an initial convolutional layer, a max-pooling layer, a branch layer, a feature fusion layer, a fully connected layer, and an output layer; The input layer inputs a defect image of the silicon wafer; The branch layer comprises a double-branch convolutional network and a multi-scale convolutional network; The double-branch convolutional network is provided with convolution kernels in different directions to capture defects from different angles in the process of recognizing the defect image of the silicon wafer; The multi-scale convolutional network is used to capture large-scale and small-scale defect features at the same time to simulate complex defect structures and different types of defects of the silicon wafer; The feature fusion layer fuses the output features of the double-branch convolutional network and the multi-scale convolutional network; The fully connected layer contains a plurality of neurons, each of which represents a defect category of the silicon wafer; the neurons are classified and activated, and the output features of the feature fusion layer are used for defect classification and recognition; The output layer converts the score of each defect category of the silicon wafer into a probability output; Step 3, labeling the defect images of the silicon wafer in the defect image dataset of the silicon wafer and inputting the detection model for training; Step 4, deploying the trained detection model to a silicon wafer detection system.

2. The method of claim 1, wherein, The feature fusion layer uses the concatenate operation to fuse the output of the double-branch convolutional network and the multi-scale convolutional network to obtain a fused feature map.

3. The method of claim 2, wherein, The fused feature map is flattened into a one-dimensional vector as the input of the fully connected layer, and each neuron of the fully connected layer has a weight corresponding to the input node, and a bias term is added to the output of each neuron.

4. The method of claim 1, wherein, The output layer contains 5 neurons, respectively corresponding to the silicon wafer crack, water stain, notch, sand grain and stain defects. The double-branch convolutional network comprises:

5. The method of claim 1, wherein, The initial convolutional layer uses a large convolution kernel for convolution operation to capture the global structure and large-scale features of the silicon wafer to detect long defects such as cracks and notches; The branch layer includes two branches, each of which uses a convolution kernel of different size to correspond to small and local defects such as water stains and large defects such as sand grains; The output feature maps of the two branches are combined by feature fusion to comprehensively consider the feature information of defects of different sizes. The multi-scale convolutional network comprises:

6. The method of claim 1, wherein, The initial convolutional layer uses a larger convolution kernel for convolution operation to capture the global structure and larger-scale features of the silicon wafer; The parallel convolutional layer uses convolution kernels of different sizes to capture features of different scales, and for large defects such as sand grains, the particle features are detected by a large convolution kernel; for small defects such as cracks and water stains, the detailed features are detected by a small convolution kernel; The output feature maps of the parallel convolutional layer are combined by feature fusion to comprehensively consider the feature information of defects of different sizes. For the silicon wafer crack defect, the features of the crack are detected by the direction perception convolution kernel in the double-branch convolutional network, and the multi-scale convolutional network captures the crack texture features of different scales and directions; 7. The method of claim 1, wherein, For the silicon wafer water stain defect, the concave-convex features of the water stain are extracted by the local perception domain convolution kernel in the double-branch convolutional network, and the multi-scale convolutional network performs scale and shape diversity perception. ​ For the silicon wafer notch defect, the local shape and texture features of the notch are obtained by the local perception field convolution kernel in the double-branch convolution network, and the multi-scale convolution network captures the notch information at different scales and depths. For the silicon wafer stain and sand defect, the edge and texture features in the double-branch convolution network extract the shape and color features of the stain and sand, and the multi-scale convolution network captures the texture changes at different scales and shapes.

8. The method of claim 1, wherein, Step 3 specifically includes: scaling the silicon wafer image data, using labelimage to generate a silicon wafer defect label file, labeling a certain number of silicon wafer defect images, and the defects include cracks, water stains, notches, sand and stains, dividing the silicon wafer image and the silicon wafer defect label file into a data set and a validation set, and inputting the detection model for training.

9. The method of claim 8, wherein, It also includes model evaluation of the trained detection model, evaluating the performance of the detection model on the validation set, including accuracy and recall, and adjusting and optimizing the detection model according to the evaluation results to improve the performance of silicon wafer defect classification.

10. The method of claim 7, wherein, For the silicon wafer crack defect, the fully connected layer integrates the double-branch convolution network and the multi-scale convolution network for cracks of different scales and directions; For the silicon wafer water stain defect, the fully connected layer integrates the results of the double-branch convolution network and the multi-scale convolution network to consider features of different scales and shapes to improve the classification effect of water stains; For the silicon wafer notch defect, the fully connected layer integrates the results of the double-branch convolution network and the multi-scale convolution network to consider features of different scales, textures and depths to improve the classification accuracy of the notch; For the silicon wafer stain and sand defect, the fully connected layer integrates the results of the double-branch convolution network and the multi-scale convolution network to consider features of different textures and scales to improve the classification accuracy of the stain and sand.

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