Voltage domain global shutter readout circuit

Abstract

A voltage domain global shutter readout circuit. A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bit line. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor is coupled to the second terminal of the pixel enable transistor and a gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor is coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to global shutter readout circuits for use in reading out image data from an image sensor. BACKGROUND

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular telephones, security cameras, medical, automotive, and other applications. The technology used to manufacture image sensors continues to progress rapidly. For example, the demand for higher resolution and lower power consumption has prompted further miniaturization and integration of these devices.

[0003] Conventionally, an image sensor receives light on an array of pixels, which generates charge in the pixels. The intensity of the light can affect the amount of charge generated in each pixel, with higher intensity generating higher amounts of charge. Correlated double sampling (CDS) is a technique used with CMOS image sensors (CIS) to reduce noise from images read out from an image sensor by sampling image data from the image sensor and removing unwanted offset sampled from reset value readings from the image sensor. In a global shutter CIS design, a sample-and-hold switch is used to sample-and-hold a signal (SHS) reading, and a reset (SHR) reading from the image sensor. The SHR and SHS switches in the sample-and-hold circuitry are controlled to sample the reset level and signal level from the image sensor. After global sampling is complete, a readout from the image sensor is performed to digitize the sampled reset level and signal level. The digitized difference between the reset level and signal level is used in CDS calculations to recover the true image signal. SUMMARY

[0004] One aspect of the present disclosure is directed to a global shutter readout circuit, comprising: a reset transistor coupled between a reset voltage and a bit line from a pixel circuit; a pixel enable transistor having a first terminal coupled to the bit line and the reset transistor; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor such that the pixel enable transistor is coupled between the reset transistor and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a second storage capacitor coupled to the second storage transistor; and a row select transistor coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

[0005] Another aspect of the present disclosure is directed to an imaging system, comprising: a pixel array including a plurality of pixel circuits; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from the pixel array, wherein the readout circuitry includes a plurality of global shutter readout circuits, wherein each global shutter readout circuit comprises: a reset transistor coupled between a reset voltage and a bit line coupled to the pixel array; a pixel enable transistor having a first terminal coupled to the bit line and the reset transistor; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor such that the pixel enable transistor is coupled between the reset transistor and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a second storage capacitor coupled to the second storage transistor; and a row select transistor coupled to the source follower transistor to generate an output signal from the global shutter readout circuit. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 An example of an imaging system in accordance with the teachings of the present disclosure is illustrated.

[0008] Figure 2 A schematic diagram showing an example of a pixel circuit and a voltage domain global shutter readout circuit in an image sensor in accordance with the teachings of the present disclosure.

[0009] Figure 3 A timing diagram illustrating signal values in an example pixel circuit and a voltage domain global shutter readout circuit during a global transfer period in accordance with the teachings of the present disclosure.

[0010] Figure 4 A schematic diagram showing another example of a pixel circuit and a voltage domain global shutter readout circuit in an image sensor in accordance with the teachings of the present disclosure.

[0011] Figure 5 A timing diagram illustrating signal values in another example pixel circuit and a voltage domain global shutter readout circuit during a global discharge period prior to a global transfer period in accordance with the teachings of the present disclosure.

[0012] Figure 6 A schematic diagram showing yet another example of a pixel circuit and a voltage domain global shutter readout circuit in an image sensor in accordance with the teachings of the present disclosure.

[0013] Figure 7 A timing diagram illustrating signal values in yet another example pixel circuit and a voltage domain global shutter readout circuit during a global discharge period prior to a global transfer period in accordance with the teachings of the present disclosure.

[0014] Throughout the figures, corresponding reference characters indicate corresponding components. One skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in each of the figures can be exaggerated relative to other elements to help improve the DETAILED DESCRIPTION

[0015] Examples directed to voltage domain global shutter readout circuits are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects.

[0016] Throughout this specification, references have been made to "one example" or "an example" meant to encompass at least one example of the present application. Therefore, the appearance of the phrase "in one example" or "in an example" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0017] Throughout this specification, several technical terms have been used. Such terms are to take their ordinary meaning in the art unless specifically defined herein or the context of their use will clearly indicate a different meaning. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0018] In various examples described below, improved example voltage domain global readout circuits are disclosed. In various examples, the global readout circuits have less leakage, less fixed pattern noise, improved linearity, reduced global transfer time and reduced size, among other things. For example, there is leakage to ground in existing global shutter readout circuit approaches, which contributes to fixed pattern noise and non-uniformity between pixels in an image due in part to resistive paths to all associated storage capacitors in the entire pixel array. These resistive paths to ground to all storage capacitors further increase the lag time in discharging the capacitors. In various examples described herein, the leakage to ground is truncated or eliminated with a pixel enable transistor included in a global shutter readout circuit according to the teachings of the present disclosure. In other examples, a pixel enable transistor is included in the discharge path of a storage capacitor, with both plates of the storage capacitor coupled to the same reset voltage through the pixel enable transistor, which significantly reduces the discharge time of the storage capacitor according to the teachings of the present disclosure. In still other examples, the bias transistor path and cascode transistor path to ground are removed from the global shutter readout circuit, such that the storage capacitor is reset to the reset voltage through the pixel enable transistor. Removing the bias transistor path and cascode transistor path to ground from the global shutter readout circuit reduces the size of the global shutter readout circuit according to the teachings of the present disclosure, as well as random noise.

[0019] To illustrate, Figure 1 An example of an imaging system 100 having a pixel array with pixel circuitry read out by a voltage domain global shutter readout circuit in accordance with the teachings of this disclosure is shown. In particular, Figure 1 The example depicted in FIG. 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In various examples, the imaging system can be implemented as a CMOS image sensor (CIS), which in one example can be in a stacked chip approach including a pixel die stacked with a logic die or an application specific integrated circuit (ASIC) die. In one example, the pixel die can include the pixel array 102, and the ASIC die can include readout circuitry having global shutter readout circuitry in accordance with the teachings of this disclosure coupled to the pixel array 102 through bit lines 112 included in a pixel level connection. In one example, the ASIC can include control circuitry 110 in addition to readout circuitry 106 and functional logic 108.

[0020] In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, place, object, etc. that can then be used to reproduce an image of the person, place, object, etc.

[0021] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photo generate image charge in response to incident light. Image charge generated in the one or more photodiodes is transferred to a floating diffusion included in each pixel circuit 104, which can be converted to an image signal that is then read out from each pixel circuit 104 by readout circuitry 106 through bit lines 112. In various examples, the readout circuitry 106 can be configured to read out the image signal through column bit lines 112. In various examples, the readout circuitry 106 can include global shutter readout circuitry, current sources, routing circuitry, and comparators or other devices that can be included in an analog-to-digital converter.

[0022] In examples, digital image data values generated by an analog-to-digital converter in the readout circuitry 106 can then be received by functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or others).

[0023] In one example, control circuitry 104 is coupled to pixel array 102 to control operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 104 can generate a global shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with an illumination effect, such as a flash.

[0024] In one example, imaging system 100 can be included in a digital camera, a mobile phone, a laptop computer, etc. Additionally, imaging system 100 can be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination / flash, an electrical input (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware can deliver instructions to imaging system 100, extract image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0025] Figure 2 A schematic diagram showing an example of pixel circuit 204 in an image sensor and an example of global shutter readout circuit 254 according to the teachings of this disclosure is shown. It is noted that, Figure 2 Pixel circuit 204 can be Figure 1 An example of one of pixel circuits 104 described in

[0026] As shown in the example depicted in Figure 2 Pixel circuit 204 can include in a pixel die 226 and global shutter readout circuit 254 can be included in a readout circuit included in ASIC die 228, as shown in the example depicted in In one example, pixel circuit 204 includes a photodiode 214 coupled to generate image charge in response to incident light. A transfer transistor 216 is coupled to transfer the generated image charge from photodiode 214 to a floating diffusion 218 in response to a transfer signal TX. A reset transistor 220 is coupled to a pixel voltage supply (e.g., PIXVD) to reset floating diffusion 218 in response to a reset signal RST. A gate of a source follower transistor 222 is coupled to convert charge in floating diffusion 218 to an image data signal that is coupled to be output through bit line 212 through row select transistor 224 in response to a row select signal GS. In an imaging system that utilizes correlated double sampling (CDS), charge on floating diffusion 218 is also read out through bit line 212 after a floating diffusion reset operation to obtain a reset level, and charge on floating diffusion 218 is also read out through bit line 212 after image charge is transferred to floating diffusion 218 to obtain a signal level.

[0027] Continuing with the depicted example, the global shutter readout circuit 254 includes a reset transistor 230 coupled between a reset voltage (e.g., VD) and a bit line 212 from the pixel circuit 204. In one example, the reset transistor 230 is configured to be controlled in response to a reset row control signal RST_ROW. As shown in the depicted example, the pixel enable transistor 236 includes a first terminal (e.g., a first source / drain terminal) coupled to the bit line 212 and the reset transistor 230. The source follower transistor 248 includes a gate coupled to a second terminal (e.g., a second source / drain terminal) of the pixel enable transistor 236, such that the pixel enable transistor 236 is coupled between the reset transistor 230 and the source follower transistor 248. In one example, the first and second terminals of the pixel enable transistor 236 are coupled together in response to a pixel enable signal PIXEN coupled to a third terminal (e.g., a gate) of the pixel enable transistor 236.

[0028] like Figure 2 As shown in the example, the first storage transistor 240 is coupled to the second terminal of the pixel enable transistor 236 and the gate of the source follower transistor 248. A first storage capacitor 242 is coupled to the first storage transistor 240. As shown, the second storage transistor 244 is also coupled to the second terminal of the pixel enable transistor 236 and the gate of the source follower transistor 248. A second storage capacitor 246 is coupled to the second storage transistor 244. As shown in the depicted example, the first storage transistor 240 is configured to be controlled in response to a sample and hold reset control signal SHR, and the second storage transistor 244 is configured to be controlled in response to a sample and hold signal control signal SHS.

[0029] In this example, row selection transistor 250 is coupled to source follower transistor 248, such that source follower transistor 248 and row selection transistor 250 are coupled between a voltage supply (e.g., AVD) and the output 252 of global shutter readout circuit 254. In operation, row selection transistor 250 is coupled to source follower transistor 248 to generate an output signal from global shutter readout circuit 254 at output 252. As shown in the depicted example, row selection transistor 250 is configured to be controlled in response to the row selection signal RS_ROW.

[0030] In the illustrated example, the floating diffusion 238 is coupled to a second terminal of the pixel enable transistor 236, a gate of the source follower transistor 248, the first storage transistor 240, and the second storage transistor 244, as shown. As such, the first storage transistor 240 and the first storage capacitor 242 are coupled between the floating diffusion 238 and a reference voltage (e.g., VM). Similarly, the second storage transistor 244 and the second storage capacitor 246 are coupled between the floating diffusion 238 and the reference voltage VM.

[0031] In Figure 2 the example depicted in FIG. 2, the global shutter readout circuit 254 also includes a bias transistor 232 coupled between a first terminal of the pixel enable transistor 236 and ground (e.g., AGND). In an example, a cascode transistor 234 is coupled between the first terminal of the pixel enable transistor 236 and the bias transistor 232. In one example, a gate of the bias transistor 232 is coupled to a first bias voltage Vb and a gate of the cascode transistor 234 is coupled to a second bias voltage Vc.

[0032] Figure 3 A timing diagram illustrating signal values in an example pixel circuit and voltage domain global shutter readout circuit during a rolling readout period, in accordance with the teachings of this disclosure, is illustrated. It should be appreciated that, Figure 3 The signals depicted in Figure 2 The example signals depicted in the pixel circuit 204 and global shutter readout circuit 254 shown in FIG. 3, and similarly named and numbered elements described above, are similarly coupled and function below.

[0033] Referring now to the depicted example, Figure 3 A row select signal GS 324, a row select row signal RS ROW 350, a reset row control signal RST ROW 330, a pixel enable signal PIXEN 336, a sample and hold reset control signal SHR 340, a sample and hold signal control signal SHS 344, a second bias voltage Vc 334, and a first bias voltage Vb 332 during a rolling readout period are illustrated. It should be appreciated that during operation of an image sensor circuit (e.g., the pixel circuit 204 and global shutter readout circuit 254 shown in FIG. 3) there can be a global pre-charge period, followed by a rolling readout period, followed by a global discharge period, followed by a global transfer period. Figure 2 Referring back to

[0034] Referring back to Figure 3With the timing diagram example depicted in FIG. 3, it is noted that the row select signal GS 324, the first bias voltage Vb 332, and the second bias voltage Vc 334 are zero throughout the rolling readout period. As illustrated, the reset row control signal RST ROW 330 is configured to turn on the reset transistor 230 to reset the bit line 212 to the reset voltage VD. Next, the row select row signal RS ROW 350 turns on the row select transistor 250, and the pixel enable signal PIXEN 336 is pulsed on and off while the reset transistor 230 is still on to reset the floating diffusion 238 to the reset voltage VD.

[0035] In various examples, when the pixel enable signal PIXEN 336 goes low, the gate-source voltage V GS will be sufficiently low to completely turn off the leakage path from the floating diffusion 238 through the cascode transistor 234 and the bias transistor 232 to ground AGND. Thus, in accordance with the teachings of the present disclosure, the leakage path from the floating diffusion 238 through the cascode transistor 234 and the bias transistor 232 to ground AGND is completely cut off after the pixel enable transistor 236 is turned off during operation. Thus, in accordance with the teachings of the present disclosure, fixed pattern noise and non-uniformity between pixels in an image are reduced or eliminated.

[0036] After the pixel enable signal PIXEN 336 is turned off, the sample and hold reset control signal SHR 340 is pulsed to charge share the black charge sampled during the global transfer period with the reset value sampled at the floating diffusion 238 in the first storage capacitor 242. Next, the pixel enable signal PIXEN 336 is pulsed on and off again while the reset transistor 230 is still on to reset the floating diffusion 238 to the reset voltage VD. After the pixel enable signal PIXEN 336 is turned off, the sample and hold signal control signal SHS 344 is then pulsed to charge share the signal charge sampled during the global transfer period with the reset value sampled at the floating diffusion 238 in the second storage capacitor 246. Next, the row select row signal RS ROW 350 turns off the row select transistor 250 and then the reset row control signal RST ROW 330 is configured to turn off the reset transistor 230 after the rolling readout is complete.

[0037] Figure 4 A schematic diagram showing another example of a pixel circuit 404 and voltage domain global shutter readout circuit 454 in an image sensor in accordance with the teachings of the present disclosure is shown. It is appreciated that the pixel circuit 404 can be as described above in Figure 4 The pixel circuit 404 can be as described above in Figure 1 Another example of one of the pixel circuits 104 included in the pixel array 102 is shown in FIG. 4, and Figure 4The pixel circuit 404 and the voltage domain global shutter readout circuit 454 depicted in the middle share some similarities with the pixel circuit 204 and the global shutter readout circuit 254 discussed in detail above. Figure 2 The pixel circuit 204 and the global shutter readout circuit 254 depicted in the middle share some similarities.

[0038] For example, as Figure 4 As shown in the example depicted in the middle, the pixel circuit 404 can be included in a pixel die 426, and the global shutter readout circuit 454 can be included in a readout circuit included in an ASIC die 428. In one example, the pixel circuit 404 includes a photodiode 414 coupled to generate image charge in response to incident light. A transfer transistor 416 is coupled to transfer the generated image charge from the photodiode 414 to a floating diffusion 418 in response to a transfer signal TX. A reset transistor 420 is coupled to a pixel voltage supply (e.g., PIXVD) to reset the floating diffusion 418 in response to a reset signal RST. A gate of a source follower transistor 422 is coupled to convert charge in the floating diffusion 418 to an image data signal that is coupled to be output through a bit line 412 through a row select transistor 424 in response to a row select signal GS. In an imaging system that utilizes correlated double sampling (CDS), the charge on the floating diffusion 418 is also read out through the bit line 412 after a floating diffusion reset operation to obtain a reset level, and the charge on the floating diffusion 418 is also read out through the bit line 412 after the image charge is transferred to the floating diffusion 418 to obtain a signal level.

[0039] In the example depicted in the middle Figure 4 In the example depicted in the middle, the global shutter readout circuit 454 includes a reset transistor 430 coupled between a reset voltage (e.g., VM) and the bit line 412 from the pixel circuit 404. In one example, the reset transistor 430 is configured to be controlled in response to a reset row control signal RST ROW. As shown in the depicted example, a pixel enable transistor 436 includes a first terminal (e.g., a first source / drain terminal) coupled to the bit line 412 and the reset transistor 430. A source follower transistor 448 includes a gate coupled to a second terminal (e.g., a second source / drain terminal) of the pixel enable transistor 436, such that the pixel enable transistor 436 is coupled between the reset transistor 430 and the source follower transistor 448. In one example, the first and second terminals of the pixel enable transistor 436 are coupled together in response to a pixel enable signal PIXEN coupled to a third terminal (e.g., a gate) of the pixel enable transistor.

[0040] As Figure 4The first storage transistor 440 is coupled to the second terminal of the pixel enable transistor 436 and the gate of the source follower transistor 448, as shown in the illustrated example. The first storage capacitor 442 is coupled to the first storage transistor 440. As shown, the second storage transistor 444 is also coupled to the second terminal of the pixel enable transistor 436 and the gate of the source follower transistor. The second storage capacitor 446 is coupled to the second storage transistor 444. As shown in the depicted example, the first storage transistor 440 is configured to be controlled in response to a sample-and-hold reset control signal SHR, and the second storage transistor 444 is configured to be controlled in response to a sample-and-hold signal control signal SHS.

[0041] In the example, the row select transistor 450 is coupled to the source follower transistor 448 such that the source follower transistor 448 and the row select transistor 450 are coupled between a voltage supply (e.g., AVD) and an output 452 of the global shutter readout circuit 454. In operation, the row select transistor 450 is coupled to the source follower transistor 448 to generate an output signal on the output 452 from the global shutter readout circuit 454. As shown in the depicted example, the row select transistor 450 is configured to be controlled in response to a row select row signal RS ROW.

[0042] In the illustrated example, the floating diffusion 438 is coupled to the second terminal of the pixel enable transistor 436, the gate of the source follower transistor 448, the first storage transistor 440, and the second storage transistor 444, as shown. As such, the first storage transistor 440 and the first storage capacitor 442 are coupled between the floating diffusion 438 and a reference voltage (e.g., VM). Similarly, the second storage transistor 444 and the second storage capacitor 446 are coupled between the floating diffusion 438 and the reference voltage VM.

[0043] Figure 4 One difference between the example depicted in FIG. 4 and the example depicted in FIG. 5 is that, in the example depicted in FIG. 4, Figure 2 One difference between the example depicted in FIG. 4 and the example depicted in FIG. 5 is that, in the example depicted in FIG. 4, Figure 4In the depicted example, the reset transistor 430, the first storage capacitor 442, and the second storage capacitor 446 are all coupled to the same reference voltage (e.g., VM), as shown. Thus, during the discharge operation, the first and second electrodes (e.g., terminals) of the first storage capacitor and the first and second electrodes (e.g., terminals) of the second storage capacitor are all configured to be locally coupled to the same reference voltage (e.g., VM) within the global shutter readout circuit 454 to discharge the first storage capacitor 442 and the second storage capacitor 446 when the reset transistor 430, the pixel enable transistor 436, the first storage transistor 440, and the second storage transistor 444 are turned on. Thus, according to the teachings of this disclosure, the discharge time to initialize the voltage Vr across the first storage capacitor 442 and the voltage Vs across the second capacitor 446 is significantly reduced in the case where the first storage capacitor 442 and the second storage capacitor 442 are discharged to an initial value through a local path of the reset transistor 430, the pixel enable transistor 436, the first storage transistor 440, and the second storage transistor 444.

[0044] In Figure 4 In the depicted example, the global shutter readout circuit 454 also includes a bias transistor 432 coupled between the first terminal of the pixel enable transistor 436 and ground (e.g., AGND). In an example, a cascode transistor 434 is coupled between the first terminal of the pixel enable transistor 436 and the bias transistor 432. In one example, the gate of the bias transistor 432 is coupled to a first bias voltage Vb and the gate of the cascode transistor 434 is coupled to a second bias voltage Vc.

[0045] Figure 5 FIG. illustrates a timing diagram of signal values in another example pixel circuit and voltage domain global shutter readout circuit during a global discharge period prior to global transfer according to the teachings of this disclosure. It should be appreciated that, Figure 5 The signals depicted in Figure 4 The example of the pixel circuit 404 and the signals depicted in the global shutter readout circuit 454 shown in are as described above, and similarly named and numbered elements described above are similarly coupled and function below.

[0046] Referring now to the depicted example, Figure 5The diagram illustrates the following signals during the global discharge cycle prior to the global transfer cycle: row selection signal GS 524, row selection signal RS_ROW 550, reset row control signal RST_ROW 530, pixel enable signal PIXEN 536, sample and hold reset control signal SHR 540, sample and hold signal control signal SHS 544, second bias voltage Vc 534, first bias voltage Vb 532, first storage capacitor voltage Vr 542, and second storage capacitor voltage Vs 546. It should be understood that in image sensor circuits (e.g., Figure 4 During the operation of the pixel circuit 404 and the global shutter readout circuit 454 shown, there may be a global precharge cycle, followed by a rolling readout cycle, followed by a global discharge cycle, and followed by a global transfer cycle.

[0047] Back to reference Figure 5 In the timing diagram example depicted, it should be noted that the row selection signal GS 524, the row selection signal RS_ROW 550, the first bias voltage Vb 532, and the second bias voltage Vc 534 are zero throughout the entire global discharge cycle. As illustrated, the reset row control signal RST_ROW 530 and the pixel enable signal PIXEN 536 are configured to turn on the reset transistor 430 and the pixel enable transistor 436 to reset the bit line 412 and the floating diffuser 438 to the reset voltage VM. Next, the sample and hold reset control signal SHR 540 and the sample and hold signal control signal SHS 544 are configured to turn on the first storage transistor 440 and the second storage transistor 444 to discharge the first storage capacitor voltage Vr 542 and the second storage capacitor voltage Vs 546.

[0048] As illustrated in the depicted example, according to the teachings of the present invention, both the first storage capacitor voltage Vr 542 and the second storage capacitor voltage Vs 546 discharge rapidly because the two electrodes of the first storage capacitor 442 and the two electrodes of the second storage capacitor 446 are locally coupled to the same reference voltage (e.g., VM) within the global shutter readout circuit 454 to discharge the first storage capacitor 442 and the second storage capacitor 442 when the reset transistor 430, the pixel enable transistor 436, the first storage transistor 440, and the second storage transistor 444 are turned on.

[0049] After discharging the first storage capacitor 442 and the second storage capacitor 446, the sample-and-hold reset control signal SHR 540 and the sample-and-hold signal control signal SHS 544 are configured to turn off the first storage transistor 440 and the second storage transistor 444, and then the row control signal RST ROW 530 and the pixel enable signal PIXEN 536 are configured to turn off the pixel enable transistor 436 and the reset transistor 430.

[0050] Figure 6 A schematic diagram showing yet another example of a pixel circuit 604 and a voltage domain global shutter readout circuit 654 in an image sensor according to the teachings of this disclosure. It will be appreciated that, Figure 6 The pixel circuit 604 can be as Figure 1 shown in the example depicted in Figure 6 The pixel circuit 604 and the voltage domain global shutter readout circuit 654 depicted in Figure 4 The pixel circuit 404 and the global shutter readout circuit 454 depicted in Figure 2 The pixel circuit 204 and the global shutter readout circuit 254 depicted in share some similarities.

[0051] For example, as shown in the example depicted in Figure 6 The pixel circuit 604 can be included in a pixel die 626 and the global shutter readout circuit 654 can be included in a readout circuit included in an ASIC die 628. In one example, the pixel circuit 604 includes a photodiode 614 coupled to photo generate image charge in response to incident light. A transfer transistor 616 is coupled to transfer the photo generated image charge from the photodiode 614 to a floating diffusion 618 in response to a transfer signal TX. A reset transistor 620 is coupled to a pixel voltage supply (e.g., PIXVD) to reset the floating diffusion 618 in response to a reset signal RST. A gate of a source follower transistor 622 is coupled to convert charge in the floating diffusion 618 to an image data signal that is coupled to be output through a bit line 612 through a row select transistor 624 in response to a row select signal GS. In an imaging system that utilizes correlated double sampling (CDS), the charge on the floating diffusion 618 is also read out through the bit line 612 after a floating diffusion reset operation to obtain a reset level, and the charge on the floating diffusion 618 is also read out through the bit line 612 after the image charge is transferred to the floating diffusion 618 to obtain a signal level.

[0052] Continuing with the depicted example, the global shutter readout circuit 654 includes a reset transistor 630 coupled between a reset voltage (e.g., VD) and a bit line 612 from the pixel circuit 604. In one example, the reset transistor 630 is configured to be controlled in response to a reset row control signal RST_ROW. As shown in the depicted example, a pixel enable transistor 636 includes a first terminal (e.g., a first source / drain terminal) coupled to the bit line 612 and the reset transistor 630. A source follower transistor 648 includes a gate coupled to a second terminal (e.g., a second source / drain terminal) of the pixel enable transistor 636, such that the pixel enable transistor 636 is coupled between the reset transistor 630 and the source follower transistor 648. In one example, the first and second terminals of the pixel enable transistor 636 are coupled together in response to a pixel enable signal PIXEN coupled to a third terminal (e.g., a gate) of the pixel enable transistor.

[0053] As Figure 6 As shown in the depicted example, a first storage transistor 640 is coupled to the second terminal of the pixel enable transistor 636 and the gate of the source follower transistor 648. A first storage capacitor 642 is coupled to the first storage transistor 640. As shown, a second storage transistor 644 is also coupled to the second terminal of the pixel enable transistor 636 and the gate of the source follower transistor. A second storage capacitor 646 is coupled to the second storage transistor 644. As shown in the depicted example, the first storage transistor 640 is configured to be controlled in response to a sample and hold reset control signal SHR, and the second storage transistor 644 is configured to be controlled in response to a sample and hold signal control signal SHS.

[0054] In an example, a row select transistor 650 is coupled to the source follower transistor 648, such that the source follower transistor 648 and the row select transistor 650 are coupled between a voltage supply (e.g., AVD) and an output 652 of the global shutter readout circuit 654. In operation, the row select transistor 650 is coupled to the source follower transistor 648 to produce an output signal from the global shutter readout circuit 654 on the output 652. As shown in the depicted example, the row select transistor 650 is configured to be controlled in response to a row select row signal RS_ROW.

[0055] In the illustrated example, the floating diffuser 638 is coupled to the second terminal of the pixel enable transistor 636, the gate of the source follower transistor 648, the first storage transistor 640, and the second storage transistor 644, as shown. Thus, the first storage transistor 640 and the first storage capacitor 642 are coupled between the floating diffuser 638 and a reference voltage (e.g., VM). Similarly, the second storage transistor 644 and the second storage capacitor 646 are coupled between the floating diffuser 638 and the reference voltage VM.

[0056] Figure 6 The examples described in the text and Figure 2 One of the differences between the instances depicted is that, Figure 6 In the example depicted, the global shutter readout circuit 654 does not include a bias transistor and a cascode transistor coupled to the first terminal of the pixel enable transistor 636 and / or between the bit line 612 and ground. Therefore, it should be noted that there is no leakage path from the floating diffuser to ground in the global shutter readout circuit 654. Thus, it should be understood that noise is reduced because the random noise (RN) originally contributed by the bias transistor and cascode transistor coupled to the first terminal of the pixel enable transistor 636 and / or between the bit line 612 and ground is removed. It should also be understood that the size of the ASIC die 628 can be small. In one example, the initial voltage Vr across the first storage capacitor 642 and the initial voltage Vs across the second capacitor 646 are reset to the reset voltage (e.g., VD) during the global discharge cycle prior to the global transfer cycle.

[0057] For illustration purposes, Figure 7 The diagram illustrates the timing of signal values ​​in another example pixel circuit and voltage domain global shutter readout circuit during a global discharge cycle prior to the global transfer cycle, according to the teachings of the present invention. It should be understood that... Figure 7 The signal described in the text can be Figure 6 Examples of signals depicted in the pixel circuit 604 and global shutter readout circuit 654 shown herein, and similarly named and numbered elements described above are similarly coupled and function below.

[0058] Now refer to the described example, Figure 7 The diagram illustrates the row selection signal GS 724, row selection signal RS_ROW 750, reset row control signal RST_ROW 730, pixel enable signal PIXEN 736, sample and hold reset control signal SHR 740, sample and hold signal control signal SHS 744, first storage capacitor voltage Vr 742, and second storage capacitor voltage Vs 746 during the global discharge cycle prior to the global transfer cycle. It should be understood that in image sensor circuits (e.g., Figure 6During the operation of the pixel circuit 604 and global shutter readout circuit 654 depicted in the timing diagram example, there can be a global pre-charge period, followed by a rolling readout period, followed by a global discharge period, followed by a global transfer period.

[0059] Referring back Figure 7 In the timing diagram example depicted in FIG. 7, it is noted that the row select signal GS 724 and the row select row signal RS ROW 750 are zero throughout the global discharge period. As illustrated, the reset row control signal RST ROW 730 and the pixel enable signal PIXEN 736 are configured to turn on the reset transistor 630 and the pixel enable transistor 636 to reset the bit line 612 and the floating diffusion 638 to the reset voltage VD. Next, the sample and hold reset control signal SHR 740 and the sample and hold signal control signal SHS 744 are configured to turn on the first storage transistor 640 and the second storage transistor 644 to discharge the first storage capacitor voltage Vr 742 and the second storage capacitor voltage Vs 746 to the reset voltage VD. As such, the initial voltage Vr 742 across the first storage capacitor 642 and the initial voltage Vs 746 across the second capacitor 646 are reset to the reset voltage VD during the global discharge period prior to the global transfer period.

[0060] After the first storage capacitor 642 and the second storage capacitor 646 are discharged to the reset voltage VD, the sample and hold reset control signal SHR 740 and the sample and hold signal control signal SHS 744 are configured to turn off the first storage transistor 640 and the second storage transistor 644, and then the reset row control signal RST ROW 730 and the pixel enable signal PIXEN 736 are configured to turn off the pixel enable transistor 636 and the reset transistor 630.

[0061] The above description of illustrated examples of the present application, including what is described in the Abstract, is not intended to be exhaustive or to limit the application to the precise forms disclosed. While specific examples of the application are described in this document, many modifications are possible.

[0062] These modifications can be made in light of the above detailed description of the application. The terms used in the following claims should not be construed to limit the application to the precise formats disclosed. Rather, the scope of the application is to be determined by the following claims and their equivalents, as interpreted according to established claim interpretation principles.

Claims

1. A global shutter readout circuit comprising: a reset transistor coupled between a reset voltage and a bit line from a pixel circuit; a pixel enable transistor having a first terminal coupled to the bit line and the reset transistor; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor such that the pixel enable transistor is coupled between the reset transistor and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a second storage capacitor coupled to the second storage transistor; and a row select transistor coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

2. The global shutter readout circuit of claim 1, further comprising a floating diffusion, wherein the second terminal of the pixel enable transistor, the gate of the source follower transistor, the first storage transistor, and the second storage transistor are coupled to the floating diffusion.

3. The global shutter readout circuit of claim 2, wherein the first storage transistor and the first storage capacitor are coupled between the floating diffusion and a reference voltage, wherein the second storage transistor and the second storage capacitor are coupled between the floating diffusion and the reference voltage.

4. The global shutter readout circuit of claim 3, further comprising a bias transistor coupled between the first terminal of the pixel enable transistor and ground.

5. The global shutter readout circuit of claim 4, further comprising a cascode transistor coupled between the first terminal of the pixel enable transistor and the bias transistor.

6. The global shutter readout circuit of claim 5, wherein a gate of the bias transistor is coupled to a first bias voltage, wherein a gate of the cascode transistor is coupled to a second bias voltage.

7. The global shutter readout circuit of claim 5, wherein the reset transistor is configured to be turned on to reset the bit line from the pixel circuit to the reset voltage, wherein the pixel enable transistor is configured to be pulsed on and off while the reset transistor is on to reset the floating diffusion to the reset voltage, wherein a leakage path from the floating diffusion through the cascode transistor and the bias transistor to ground is completely cut off after the pixel enable transistor is turned off.

8. The global shutter readout circuit of claim 3, wherein the reset voltage and the reference voltage are the same.

9. The global shutter readout circuit of claim 8, ​ wherein the reset transistor, the pixel enable transistor, the first storage transistor, and the second storage transistor are all configured to be turned on to reset the bit line, the floating diffusion, the first storage capacitor, and the second storage capacitor, wherein the first and second electrodes of the first storage capacitor and the first and second electrodes of the second storage capacitor are all configured to be coupled to the same reference voltage to discharge the first and second storage capacitors when the reset transistor, the pixel enable transistor, the first storage transistor, and the second storage transistor are turned on.

10. The global shutter readout circuit of claim 3, wherein the reset transistor is configured to be turned on to reset the bit line from the pixel circuit to the reset voltage, wherein the pixel enable transistor is configured to be pulsed on and off at the same time as the reset transistor is turned on to reset the floating diffusion to the reset voltage, wherein the first and second storage transistors are configured to be pulsed on and off to charge share black charge sampled during a global transfer period with a reset value sampled at the floating diffusion at the first storage capacitor and to charge share signal charge sampled during the global transfer period with a reset value sampled at the floating diffusion at the second storage capacitor, wherein there is no leakage path in the global shutter readout circuit from the floating diffusion to ground, wherein there is no bias transistor and no cascode transistor coupled between the first terminal of the pixel enable transistor and ground.

11. The global shutter readout circuit of claim 10, wherein an initial voltage across the first storage capacitor and an initial voltage across the second storage capacitor are configured to be reset to the reset voltage during a global discharge period prior to the global transfer period.

12. An imaging system, comprising: a pixel array including a plurality of pixel circuits; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from the pixel array, wherein the readout circuitry includes a plurality of global shutter readout circuits, wherein each global shutter readout circuit comprises: a reset transistor coupled between a reset voltage and a bit line coupled to the pixel array; a pixel enable transistor having a first terminal coupled to the bit line and the reset transistor; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor, such that the pixel enable transistor is coupled between the reset transistor and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a second storage capacitor coupled to the second storage transistor; and a row select transistor coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

13. The imaging system of claim 12, wherein each global shutter readout circuit further comprises a floating diffusion, wherein the second terminal of the pixel enable transistor, the gate of the source follower transistor, the first storage transistor, and the second storage transistor are coupled to the floating diffusion.

14. The imaging system of claim 13, wherein the first storage transistor and the first storage capacitor are coupled between the floating diffusion and a reference voltage, wherein the second storage transistor and the second storage capacitor are coupled between the floating diffusion and the reference voltage.

15. The imaging system of claim 14, wherein each global shutter readout circuit further comprises a bias transistor coupled between the first terminal of the pixel enable transistor and ground.

16. The imaging system of claim 15, wherein each global shutter readout circuit further comprises a cascode transistor coupled between the first terminal of the pixel enable transistor and the bias transistor.

17. The imaging system of claim 16, wherein a gate of the bias transistor is coupled to a first bias voltage, wherein a gate of the cascode transistor is coupled to a second bias voltage.

18. The imaging system of claim 16, wherein the reset transistor is configured to be turned on to reset the bitline from the pixel circuit to the reset voltage, wherein the pixel enable transistor is configured to be pulsed on and off while the reset transistor is on to reset the floating diffusion to the reset voltage, wherein a leakage path from the floating diffusion through the cascode transistor and the bias transistor to ground is completely cut off after the pixel enable transistor is turned off.

19. The imaging system of claim 14, wherein the reset voltage is the same as the reference voltage.

20. The imaging system of claim 19, wherein the reset transistor, the pixel enable transistor, the first storage transistor, and the second storage transistor are all configured to be turned on to reset the bitline, the floating diffusion, the first storage capacitor, and the second storage capacitor, wherein first and second electrodes of the first storage capacitor and first and second electrodes of the second storage capacitor are all configured to be coupled to the same reference voltage to discharge the first storage capacitor and the second storage capacitor when the reset transistor, the pixel enable transistor, the first storage transistor, and the second storage transistor are turned on.

21. The imaging system of claim 14, wherein the reset transistor is configured to be turned on to reset the bit line from the pixel circuit to the reset voltage, wherein the pixel enable transistor is configured to be pulsed on and off while the reset transistor is on to reset the floating diffusion to the reset voltage, wherein the first and second storage transistors are configured to be pulsed on and off to charge share black charge sampled during a global transfer period with reset values sampled at the floating diffusion at the first and second storage capacitors, and to charge share signal charge sampled during the global transfer period with reset values sampled at the floating diffusion at the second and first storage capacitors, wherein there is no leakage path from the floating diffusion to ground in the global shutter readout circuit, wherein there is no bias transistor and no cascode transistor coupled between the first terminal of the pixel enable transistor and ground.

22. The imaging system of claim 21, wherein an initial voltage across the first storage capacitor and an initial voltage across the second storage capacitor are configured to be reset to the reset voltage during a global discharge period prior to the global transfer period.

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