Voltage domain global shutter readout circuit and imaging system

Abstract

This application relates to voltage domain global shutter readout circuit timing. A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal configured to turn on a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to start transitioning to an off level at a second time and complete the transition to the off level at a third time to turn off the pixel enable transistor. The first SH signal is configured to start transitioning to the off level at a fourth time occurring after the second and third times and complete the transition to the off level at a fifth time to turn off the first storage transistor. An off transition duration between the fourth and fifth times is greater than a turn on transition duration of the first SH signal at the first time.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to a global shutter readout circuit for reading out image data from an image sensor. BACKGROUND

[0002] Image sensors have become ubiquitous. Image sensors are widely used in digital cameras, cellular phones, surveillance cameras, medical, automotive, and other applications. The technology for manufacturing image sensors has been advancing at a rapid pace. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] Image sensors conventionally receive light on a pixel array that generates charge in the pixels. The intensity of the light can affect the amount of charge generated in each pixel, with higher intensity generating higher charge amounts. Correlated double sampling (CDS) is a technique used with CMOS image sensors (CIS) to reduce noise in images read out from the image sensor by sampling image data from the image sensor and removing undesired offsets sampled from reset value readings of the image sensor. In a global shutter CIS design, a sample and hold switch is used for a signal hold switch (SHS) reading, and a sample and hold reset (SHR) reading from the image sensor. The SHR and SHS switches in the sample and hold circuitry are controlled to sample the reset level and signal level from the image sensor. After global sampling is complete, a readout from the image sensor is performed to digitize the sampled reset level and signal level. The digitized difference between the reset level and the signal level is used for CDS computation to recover the true image signal. SUMMARY

[0004] In one aspect, the present disclosure relates to a global shutter readout circuit comprising: a pixel enable transistor having a first terminal coupled to a bit line from a pixel circuit; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor such that the pixel enable transistor is coupled between the bit line and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor, wherein the first storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a first sample and hold (SH) signal coupled to a gate of the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; and a second storage capacitor coupled to the second storage transistor, wherein the second storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a second sample and hold (SH) signal coupled to a gate of the second storage transistor, wherein the pixel enable signal is configured to transition to an on level at a first time to turn on the pixel enable transistor during a global transfer period, wherein the first SH signal is configured to transition to the on level at the first time to turn on the first storage transistor, wherein the pixel enable signal is configured to begin transitioning to an off level at a second time, wherein the pixel enable signal is configured to complete the transition to the off level to turn off the pixel enable transistor at a third time, wherein the second and third times occur after the first time, wherein the first SH signal is configured to begin transitioning to the off level at a fourth time, wherein the fourth time occurs after the second and third times, wherein the first SH signal is configured to complete the transition to the off level to turn off the first storage transistor at a fifth time, wherein the first SH signal is configured to transition from the on level to the off level by a slope control such that the fifth time occurs after the fourth time and an off transition duration between the fourth and fifth times is greater than an on transition duration of the first SH signal transitioning from the off level to the on level at the first time.

[0005] In one aspect, the present disclosure relates to an imaging system comprising: a pixel array including a plurality of pixel circuits; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from the pixel array, wherein the readout circuitry includes a plurality of global shutter readout circuits, wherein each global shutter readout circuit comprises: a pixel enable transistor having a first terminal coupled to a bit line from one of the pixel circuits; a source follower transistor having a gate coupled to a second terminal of the pixel enable transistor such that the pixel enable transistor is coupled between the bit line and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor; a first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; a first storage capacitor coupled to the first storage transistor, wherein the first storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a first sample and hold (SH) signal coupled to a gate of the first storage transistor; a second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; and a second storage capacitor coupled to the second storage transistor, wherein the second storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a second sample and hold (SH) signal coupled to a gate of the second storage transistor, wherein the pixel enable signal is configured to transition to an on level at a first time during a global transfer period to turn on the pixel enable transistor, wherein the first SH signal is configured to transition to the on level at the first time to turn on the first storage transistor, wherein the pixel enable signal is configured to begin transitioning to an off level at a second time, wherein the pixel enable signal is configured to complete the transition to the off level to turn off the pixel enable transistor at a third time, wherein the second and third times occur after the first time, wherein the first SH signal is configured to begin transitioning to the off level at a fourth time, wherein the fourth time occurs after the second and third times, wherein the first SH signal is configured to complete the transition to the off level to turn off the first storage transistor at a fifth time, wherein the first SH signal is configured to transition from the on level to the off level by a slope control such that the fifth time occurs after the fourth time and an off transition duration between the fourth and fifth times is greater than an on transition duration of the first SH signal transitioning from the off level to the on level at the first time. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive examples of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views.

[0007] Figure 1 An example of an imaging system in accordance with the teachings of this disclosure is described.

[0008] Figure 2 A schematic diagram showing an example of pixel circuitry and voltage domain global shutter readout circuitry in an image sensor in accordance with the teachings of this disclosure.

[0009] Figure 3 An example timing diagram of signal values in example pixel circuitry and voltage domain global shutter readout circuitry in accordance with the teachings of this disclosure is described.

[0010] Figure 4 Another example timing diagram of signal values in example pixel circuitry and voltage domain global shutter readout circuitry in accordance with the teachings of this disclosure is described.

[0011] Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings. One skilled in the art will appreciate that the elements in the figures are solely for the purpose of illustrating the various embodiments of the application and are not necessarily to scale, and that some of the various embodiments can include more or fewer elements than are illustrated in a given figure. For the purposes of clarity, not every component can be called out or discussed in the embodiment figures, but one skilled in the art will understand that the various embodiments can include one or more of the components discussed in the figures, or additional or different components. Moreover, in the interest of not obscuring the various embodiments, some conventional elements are not shown or described in detail. For example, conventional signal processing, processing, and / or control elements of the various embodiments are not shown or described in detail unless otherwise specified herein. DETAILED DESCRIPTION

[0012] Examples relating to voltage domain global shutter readout circuit timing are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of certain aspects.

[0013] Reference throughout this specification to "one example", "an example", or "the example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present application. Thus, the appearance of the phrases "in one example" or "in one embodiment" or "in at least one example" or "in at least one embodiment" in various places throughout this specification are not necessarily referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0014] Throughout the description, several technical terms are used. Such terms are to be given their ordinary meaning in the art, unless specifically defined herein, or the context of their use would clearly dictate otherwise. It is noted that element names and symbols can be used interchangeably throughout this document (e.g., Si for silicon); however, both have the same meaning.

[0015] In various examples described below, examples of improved voltage domain global readout circuit timing are disclosed. In various examples, the readout of the global readout circuit has improved masking performance as well as improved fixed pattern noise performance. As will be described in various examples, turning off the pixel enable transistor before turning off the sample and hold reset transistor or the sample and hold signal transistor enables the bit line voltage in the example global shutter readout circuit to be sampled first at the floating diffusion without coupling mismatch. When turning off the sample and hold reset transistor or the sample and hold signal transistor to time, the floating diffusion voltage in the global shutter readout circuit is sampled at the first and second storage capacitors according to the teachings of this disclosure without the mismatched coupling effects of the sample and hold reset transistor or the sample and hold signal transistor to the bias voltage Vb. In another example, the pixel enable transistor can also be turned off by slope control according to the teachings of this disclosure, the variation of the sampled black (e.g., noise) and signal levels reduces the variation or variability from left to right in the pixel array.

[0016] To illustrate, Figure 1 One example of an imaging system 100 having a pixel array with pixel circuitry read out with improved timing by a voltage domain global shutter readout circuit according to the teachings of this disclosure is shown. In particular, Figure 1 The example depicted in FIG. 1 illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In various examples, the imaging system can be implemented as a CMOS image sensor (CIS), which in one example can be in a stacked chip approach that includes a pixel die stacked with a logic die application specific integrated circuit (ASIC). In one example, the pixel die can include the pixel array 102, and the ASIC die can include readout circuitry with global shutter readout circuitry according to the teachings of this disclosure coupled to the pixel array 102 through bit lines 112 included in the pixel level connections. In one example, the ASIC can include control circuitry 110 in addition to the readout circuitry 106 and functional logic 108.

[0017] In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in rows (e.g., R1to Ry) and columns (e.g., C1to Cx) to acquire image data of a person, a place, an object, etc., which can then be used to present an image of the person, place, object, etc.

[0018] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photo generate image charges in response to incident light. Image charges generated in the one or more photodiodes are transferred to a floating diffusion included in each pixel circuit 104, which can be converted into an image signal that is then read out from each pixel circuit 104 by the readout circuit 106 over a bit line 112. In various examples, the readout circuit 106 can be configured to read out the image signal over a column bit line 112. In various examples, the readout circuit 106 can include a global shutter readout circuit, a current source, routing circuitry, and a comparator, which can be included in or otherwise included with an analog-to-digital converter.

[0019] In an example, digital image data values generated by the analog-to-digital converter in the readout circuit 106 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post image effects (e.g., cropping, rotating, red-eye removal, adjusting brightness, adjusting contrast, or otherwise).

[0020] In one example, a control circuit 104 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 104 can generate a global shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with an illumination effect, such as a flash.

[0021] In one example, the imaging system 100 can be included in a digital camera, a cell phone, a laptop, etc. Additionally, the imaging system 100 can be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), a memory element, an output (a USB port, a wireless transmitter, an HDMI port, etc.), an illumination device / flash, an electrical input (a keyboard, a touch display, a trackpad, a mouse, a microphone, etc.), and / or a display. The other pieces of hardware can communicate instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0022] Figure 2 A schematic diagram showing an example of a pixel circuit 204 in an image sensor and an example of a global shutter readout circuit 254 in accordance with the teachings of this disclosure is shown. It should be noted that, Figure 2 The pixel circuit 204 can beFigure 1 An example of one of the pixel circuits 104 described in the middle, and like-named and numbered elements referenced below are similar to those coupled and functioning as described above.

[0023] As shown in the example depicted in the middle of Figure 2 The pixel circuit 204 can be included in a pixel die 226, and the global shutter readout circuit 254 can be included in a readout circuit included in an ASIC die 228, as shown in the example depicted in the middle of

[0024] Continuing with the depicted example, the global shutter readout circuit 254 includes a reset transistor 230 coupled between a reset voltage VD 256 and the bit line 212 from the pixel circuit 204. In one example, the reset transistor 230 is configured to be controlled in response to a reset row control signal RST ROW. As shown in the depicted example, a pixel enable transistor 236 includes a first terminal (e.g., a first source / drain terminal) coupled to the bit line 212 and the reset transistor 230. A source follower transistor 248 includes a gate coupled to a second terminal (e.g., a second source / drain terminal) of the pixel enable transistor 236, such that the pixel enable transistor 236 is coupled between the reset transistor 230 and the source follower transistor 248. In one example, the first and second terminals of the pixel enable transistor 236 are coupled together in response to a pixel enable signal PIXEN coupled to a third terminal (e.g., a gate) of the pixel enable transistor 236.

[0025] As Figure 2In the example shown in the example pixel circuit 200, the first storage transistor 240 is coupled to the second terminal of the pixel enable transistor 236 and the gate of the source follower transistor 248. The first storage capacitor 242 is coupled to the first storage transistor 240. As shown, the second storage transistor 244 is also coupled to the second terminal of the pixel enable transistor 236 and the gate of the source follower transistor 248. The second storage capacitor 246 is coupled to the second storage transistor 244. As shown in the depicted example, the first storage transistor 240 is configured to be controlled in response to a sample and hold reset control signal SHR, and the second storage transistor 244 is configured to be controlled in response to a sample and hold signal control signal SHS.

[0026] In the example, the row select transistor 250 is coupled to the source follower transistor 248 such that the source follower transistor 248 and the row select transistor 250 are coupled between a voltage supply (e.g., AVD) and an output 252 of a global shutter readout circuit 254. In operation, the row select transistor 250 is coupled to the source follower transistor 248 to generate an output signal on the output 252 from the global shutter readout circuit 254. As shown in the depicted example, the row select transistor 250 is configured to be controlled in response to a row select row signal RS ROW.

[0027] In the illustrated example, as shown, the floating diffusion 238 is coupled to the second terminal of the pixel enable transistor 236, the gate of the source follower transistor 248, the first storage transistor 240, and the second storage transistor 244. Accordingly, the first storage transistor 240 and the first storage capacitor 242 are coupled between the floating diffusion 238 and a reference voltage (e.g., VM). Similarly, the second storage transistor 244 and the second storage capacitor 246 are coupled between the floating diffusion 238 and the reference voltage VM.

[0028] In Figure 2 In the depicted example, the global shutter readout circuit 254 also includes a bias transistor 232 coupled between the first terminal of the pixel enable transistor 236 and ground (e.g., AGND). In the example, a cascode transistor 234 is coupled between the first terminal of the pixel enable transistor 236 and the bias transistor 232. In one example, the gate of the bias transistor 232 is coupled to a first bias voltage Vb, and the gate of the cascode transistor 234 is coupled to a second bias voltage Vc.

[0029] Figure 3 An example timing diagram of signal values in an example pixel circuit and voltage domain global shutter readout circuit according to the teachings of this disclosure is illustrated. It will be appreciated that, Figure 3 The signals depicted in the example timing diagram can be in Figure 2Examples of the signals depicted in the pixel circuit 204 and the global shutter readout circuit 254, and similarly named and numbered elements referenced below, are coupled and function similarly below.

[0030] Referring now to the depicted example, Figure 3 Reset voltage VD 356, reset row control signal RST ROW 330, sample and hold reset control signal SHR 340, sample and hold signal control signal SHS 344, and row select row signal RS ROW 350 during the readout of the pixel circuit 204 by the global shutter readout circuit 254. As shown in the depicted example, the readout of the pixel circuit 204 by the global shutter readout circuit 254 includes a global pre-charge period 358, followed by a rolling readout period 360, followed by a global discharge period 362, followed by a global transfer period 364.

[0031] During the global pre-charge period 358, it is noted that row select signal GS 324, pixel enable signal PIXEN 336, sample and hold reset control signal SHR 340, and sample and hold signal control signal SHS 344 are all zero or off, and reset voltage VD 356 is a constant voltage (e.g., AVDD). In the depicted example, during the global pre-charge period 358, reset signal RST 320 is initially on, then transfer signal TX 316 is transitioned from off to on, at which time photodiode 214 and floating diffusion 218 are reset. Next, reset signal RST 320 is transitioned to off, then transfer signal TX 316 is transitioned to off, after which reset signal RST 320 is transitioned back to on.

[0032] Next, during the rolling readout period 360, it is noted that row select signal GS 324 and transfer signal TX 316 are both zero or off, and reset signal RST 320 is one or on. As shown during the rolling readout period 360, reset voltage VD 356 is changed from a constant voltage (e.g., AVDD) to a lower voltage (e.g., Vblk) close to the black level, and reset row control signal RST ROW 330 is on, which in turn turns on reset transistor 230 in the global shutter readout circuit 254. Next, row select row signal RS ROW 350 is on, and pixel enable signal PIXEN 336 is on, then off. Next, sample and hold reset control signal SHR 340 is on, then off. Next, pixel enable signal PIXEN 336 is on again, then off, followed by sample and hold signal control signal SHS 344 being on, then off.

[0033] Next, during a global discharge period 362, it is noted that the row select signal GS 324, the transfer signal TX 316, the reset row control signal RST ROW 330, and the row select row signal RS ROW 350 are all zero or off, the reset signal RST 320 is one or on, and the reset voltage VD 356 is a constant voltage (e.g., AVDD). As shown during the global discharge period 362, the pixel enable signal PIXEN 336 is on, then both the sample and hold reset control signal SHR 340 and the sample and hold signal control signal SHS 344 are on, then both are off. Next, the pixel enable signal PIXEN 336 is then off.

[0034] Next, as shown in a global transfer period 364, the row select signal GS 324 transitions to one or on, and the reset row control signal RST ROW 330 increases from the previous zero or off value. In one example, the reset row control signal RST ROW 330 becomes a value for black level clamping at the beginning of the global transfer period 364. Next, the row select row signal RS ROW 350 transitions to a one or on value. Next, the reset signal RST 320 transitions to a zero or off value.

[0035] Next, the pixel enable signal PIXEN 336 is configured to transition to an on level at a first time Tl during the global transfer period 364 to turn on the pixel enable transistor 236. As shown in the example, the sample and hold reset control signal SHR 340 is also configured to transition to an on level to turn on the first storage transistor 240 at the first time Tl. Next, the pixel enable signal PIXEN 336 is configured to begin transitioning to an off level at a second time T2. As shown in the depicted example, the pixel enable signal PIXEN 336 is configured to complete the transition to the off level at a third time T3 to turn off the pixel enable transistor 236. It is appreciated that the time T3 occurs after the time T2, and the time T2 occurs after the time Tl. In the depicted example, it is appreciated that there is substantially no delay between the second time T2 and the third time T3 at which the pixel enable signal PIXEN 336 completes the transition from the on level to the off level. Figure 3

[0036] ​Next, the sample-and-hold reset control signal SHR 340 is configured to transition to an off level at the beginning of the fourth time T4. It should be understood that the fourth time T4 occurs after the second time T2 and the third time T3. As illustrated in the depicted example, the sample-and-hold reset control signal SHR 340 is configured to complete its transition to an off level at the fifth time T5 to turn off the first storage transistor 240. At this time, the reset level is sampled and held in the first storage transistor 242. In the depicted example, the sample-and-hold reset control signal SHR 340 transitions from an on level to an off level by slope control, such that the fifth time T5 occurs after the fourth time T4, and the off transition duration between the fourth time T4 and the fifth time T5 is greater than the on transition duration of the sample-and-hold reset control signal SHR 340 transitioning from an off level to an on level at the first time T1. In one example, the sample and hold reset control signal SHR 340 transitions from an on level to an off level between a fourth time T4 and a fifth time T5 via slope control, which is achieved by a slope control circuit that controls the slope of the falling voltage of the sample and hold reset control signal SHR 340.

[0037] Next, after the fifth time point T5, the transfer signal TX 316 transitions to the ON value. This transfers the image charge in photodiode 214 to the floating diffuser. In one example, the reset row control signal RST_ROW 330 transitions to the signal clamp value at this time. Then, the transfer signal TX 316 transitions to the OFF value.

[0038] Next, after the transfer signal TX 316 transitions to the off value during the global transfer period 364, the pixel enable signal PIXEN 336 is configured to transition to the on level at the sixth time T6 to turn on the pixel enable transistor 236, and the sample and hold signal control signal SHS 344 is configured to transition to the on level at the sixth time T6 to turn on the second storage transistor 244. It should be understood that the sixth time T6 occurs after the fifth time T5 and after the transfer signal TX 316 transitions to the off value.

[0039] Next, the pixel enable signal PIXEN 336 is configured to transition to an off level at the seventh time, and then the pixel enable signal PIXEN 336 is configured to transition to an off level at the eighth time T8 to turn off the pixel enable transistor 236. It should be understood that the seventh time T7 and the eighth time T8 occur after the sixth time. Figure 3 In the example described, it should be understood that there is essentially no delay between the seventh time T7 and the eighth time T8 when the pixel enable signal PIXEN 336 completes the transition from the on level to the off level.

[0040] Next, the sample and hold signal control signal SHS 344 is configured to transition to an off level starting at the ninth time T9. It should be understood that the ninth time T9 occurs after the seventh time T7 and the eighth time T8. In this example, the sample and hold signal control signal SHS 344 is configured to complete its transition to an off level at the tenth time T10 to turn off the second storage transistor 244. At this time, it should be understood that the sample and hold signal value is stored in the second storage transistor 244. In the depicted example, the sample and hold signal control signal SHS 344 transitions from an on level to an off level via slope control, such that the tenth time T10 occurs after the ninth time T9, and the off transition duration between the ninth time T9 and the tenth time T10 is greater than the on transition duration of the sample and hold signal control signal SHR 344 transitioning from an off level to an on level at the sixth time T6. In one example, the sample and hold signal control signal SHS 344 transitions from an on level to an off level between the ninth time T9 and the tenth time T10 via a slope control circuit that controls the slope of the falling voltage of the sample and hold signal control signal SHR 344.

[0041] Next, the reset signal RST 320 switches to the ON value, then the row selection signal RS_ROW 350 switches to the OFF value, and then the row selection signal GS 324 switches to the OFF value.

[0042] Figure 4 This diagram illustrates another example of a timing diagram showing signal values ​​in an example pixel circuit and a voltage domain global shutter readout circuit, according to the teachings of this disclosure. It should be understood that... Figure 4 The signal described in the text can be in Figure 2 The signals depicted in the pixel circuitry 204 and the global shutter readout circuitry 254 shown are additional examples, and similarly named and numbered elements described above are similarly coupled and function below. It should be further understood that... Figure 4 The sequence diagrams depicted in the text are... Figure 3 The sequence diagrams depicted in the text share similarities.

[0043] For example, Figure 4The following parameters are described during the readout of pixel circuit 204 by global shutter readout circuit 254: row selection signal GS 424, reset signal RST 420, transfer signal TX 416, pixel enable signal PIXEN 436, reset voltage VD 456, reset row control signal RST_ROW 430, sample and hold reset control signal SHR 440, sample and hold signal control signal SHS 444, and row selection row signal RS_ROW 450. As shown in the illustrated example, the readout of pixel circuit 204 by global shutter readout circuit 254 includes a global precharge period 458, followed by a rolling readout period 460, followed by a global discharge period 462, and followed by a global transfer period 464.

[0044] During the global precharge period 458, it should be noted that the row selection signal GS 424, the pixel enable signal PIXEN 436, the sample and hold reset control signal SHR 440, and the sample and hold signal control signal SHS 444 are all zero or off, and the reset voltage VD 456 is a constant voltage (e.g., AVDD). In the depicted example, during the global precharge period 458, the reset signal RST 420 is initially turned on, and then the transfer signal TX 416 transitions from off to on, at which point the photodiode 214 and the floating diffuser 218 are reset. Next, the reset signal RST 420 transitions to off, then the transfer signal TX 416 transitions to off, after which the reset signal RST 420 transitions back to on.

[0045] Next, during the rolling readout period 460, note that the line selection signal GS 424 and the transfer signal TX 416 are both zero or off, and the reset signal RST 420 is either on or off. As shown during the rolling readout period 460, the reset voltage VD 456 changes from a constant voltage (e.g., AVDD) to a lower voltage (e.g., Vblk) close to black level, and the reset line control signal RST_ROW 430 turns on, which in turn turns on the reset transistor 230 in the global shutter readout circuit 254. Next, the line selection signal RS_ROW 450 turns on, and the pixel enable signal PIXEN 436 turns on and then off. Next, the sample and hold reset control signal SHR 440 turns on and then off. Next, the pixel enable signal PIXEN 436 turns on again and then off, followed by the sample and hold signal control signal SHS 444, which then turns off.

[0046] Next, during global discharge phase 462, note that the row selection signal GS 424, transfer signal TX 416, reset row control signal RST_ROW 430, and row selection signal RS_ROW 450 are all zero or off, the reset signal RST 420 is one-OR on, and the voltage VD 456 is a constant voltage (e.g., AVDD). As shown during global discharge phase 462, the pixel enable signal PIXEN 436 is turned on, then the sample and hold reset control signal SHR 440 and the sample and hold signal control signal SHS 444 are both turned on, and then turned off. Next, the pixel enable signal PIXEN 436 is then turned off.

[0047] Next, as shown in global transfer period 464, the row selection signal GS 424 transitions to a -OR ON value, and the reset row control signal RST_ROW 430 increases from its previous zero or off value. In one example, the reset row control signal RST_ROW 430 increases to the black clamp value at the start of global transfer period 464. Next, the row selection signal RS_ROW 450 transitions to a -OR ON value. Next, the reset signal RST 420 transitions to a zero or off value.

[0048] Next, the pixel enable signal PIXEN 436 is configured to transition to an ON level at a first time T1 during the global transition period 464 to turn on the pixel enable transistor 236. As shown in the example, the sample and hold reset control signal SHR440 is also configured to transition to an ON level to turn on the first storage transistor 240 at the first time T1. Next, the pixel enable signal PIXEN 436 is configured to transition to an OFF level at a second time T2. As shown in the depicted example, the pixel enable signal PIXEN 436 is configured to transition to an OFF level at a third time T3 to turn off the pixel enable transistor 236.

[0049] In the depicted example, the pixel enable signal PIXEN 436 transitions from an on level to an off level via slope control, such that a third time T3 occurs after a second time T2, and the off transition duration between the second time T2 and the third time T3 is greater than the on transition duration of the pixel enable signal PIXEN 436 transitioning from an off level to an on level at the first time T1. In one example, the pixel enable signal PIXEN 436 transitioning from an on level to an off level via slope control between the second time T2 and the third time T3 can be achieved by a slope control circuit that controls the slope of the falling voltage of the pixel enable signal PIXEN 436.

[0050] Next, the sample-and-hold reset control signal SHR 440 is configured to transition to an off level at the beginning of the fourth time T4. It should be understood that the fourth time T4 occurs after the second time T2 and the third time T3. As illustrated in the depicted example, the sample-and-hold reset control signal SHR 440 is configured to complete its transition to an off level at the fifth time T5 to turn off the first storage transistor 240. At this time, the reset level is sampled and held in the first storage transistor 242. In the depicted example, the sample-and-hold reset control signal SHR 440 transitions from an on level to an off level by slope control, such that the fifth time T5 occurs after the fourth time T4, and the off transition duration between the fourth time T4 and the fifth time T5 is greater than the on transition duration of the sample-and-hold reset control signal SHR 440 transitioning from an off level to an on level at the first time T1. In one example, the sample and hold reset control signal SHR 440 transitions from an on level to an off level between a fourth time T4 and a fifth time T5 via slope control, which can be achieved by a slope control circuit that controls the slope of the falling voltage of the sample and hold reset control signal SHR 440.

[0051] Next, after the fifth time point T5, the transfer signal TX 416 transitions to the ON value. This transfers the image charge in photodiode 214 to the floating diffuser. In one example, the reset row control signal RST_ROW 430 transitions to the signal clamp value. Then, the transfer signal TX 416 transitions to the OFF value.

[0052] Next, after the transfer signal TX 416 transitions to an off value during the global transfer period 464, the pixel enable signal PIXEN 436 is configured to transition to an on level at the sixth time T6 to turn on the pixel enable transistor 236, and the sample and hold signal control signal SHS 444 is configured to transition to an on level at the sixth time T6 to turn on the second storage transistor 244. It should be understood that the sixth time T6 occurs after the fifth time T5 and after the transfer signal TX 416 transitions to an off value.

[0053] Next, the pixel enable signal PIXEN 436 is configured to transition to an off level at the beginning of the seventh time, and then the pixel enable signal PIXEN 436 is configured to complete the transition to an off level at the eighth time T8 to turn off the pixel enable transistor 236. In the depicted example, the pixel enable signal PIXEN 436 transitions from an on level to an off level by slope control, such that the eighth time T8 occurs after the seventh time T7, and the off transition duration between the seventh time T7 and the eighth time T8 is greater than the on transition duration of the pixel enable signal PIXEN 436 transitioning from an off level to an on level at the sixth time T6. In one example, the transition of the pixel enable signal PIXEN 436 from an on level to an off level between the seventh time T7 and the eighth time T8 by slope control can be implemented by a slope control circuit that controls the slope of the falling voltage of the pixel enable signal PIXEN 436.

[0054] Next, the sample and hold signal control signal SHS 444 is configured to transition to an off level starting at the ninth time T9. It should be understood that the ninth time T9 occurs after the seventh time T7 and the eighth time T8. In this example, the sample and hold signal control signal SHS 444 is configured to complete its transition to an off level at the tenth time T10 to turn off the second storage transistor 244. At this time, the signal level is sampled and held in the second storage capacitor 246. In the depicted example, the sample and hold signal control signal SHS 444 transitions from an on level to an off level via slope control, such that the tenth time T10 occurs after the ninth time T9, and the off transition duration between the ninth time T9 and the tenth time T10 is greater than the on transition duration of the sample and hold signal control signal SHR 444 transitioning from an off level to an on level at the sixth time T6. In one example, the sample and hold signal control signal SHS 444 transitions from an on level to an off level between the ninth time T9 and the tenth time T10 via slope control, which can be achieved by a slope control circuit that controls the slope of the falling voltage of the sample and hold signal control signal SHR 444.

[0055] Next, the reset signal RST 420 switches to the ON value, then the row selection signal RS_ROW 450 switches to the OFF value, and then the row selection signal GS 424 switches to the OFF value.

[0056] In the above Figures 2 to 4In the various examples described herein where the pixel enable signals PIXEN 336 / 436 are disabled before the sample-and-hold reset control signals SHR 340 / 440 and the sample-and-hold signal control signals SHS 344 / 444, it should be understood that the masking performance is substantially improved compared to conventional examples where the pixel enable signals PIXEN 336 / 436 are not disabled before the sample-and-hold reset control signals SHR 340 / 440 and the sample-and-hold signal control signals SHS 344 / 444. In the various examples, the improvement in masking performance is addressed by applying slope control at the time of the shutdown signal to resolve the coupling capacitance mismatch between the bias voltage Vb and the sample-and-hold reset control signals SHR 340 / 440 and the sample-and-hold signal control signals SHS 344 / 444 across different locations in the pixel array (e.g., from left to right).

[0057] For example, when the pixel enable signal PIXEN 336 / 346 is turned off before the sample-and-hold reset control signal SHR 340 / 440 and the sample-and-hold signal control signal SHS 344 / 444, the voltage of bit line 212 is first sampled at the floating diffuser 238 without any coupling mismatch. Subsequently, when the sample-and-hold reset control signal SHR 340 / 440 or the sample-and-hold signal control signal SHS 344 / 444 is turned off at the appropriate time, the voltage of floating diffuser 238 is finally sampled at the first storage capacitor 242 and the second storage capacitor 246 without the coupling mismatch effect from the sample-and-hold reset control signal SHR 340 / 440 and the sample-and-hold signal control signal SHS 344 / 444 to the bias voltage Vb, etc. Furthermore, the pixel enable signal PIXEN 336 / 436 is processed via... Figure 4 In the example of slope control off described in the text, the black level / reset and signal voltage have small variations from left to right and from top to bottom in the pixel array.

[0058] Additionally, it should be noted that fixed-mode noise is also present in the above-mentioned... Figures 2 to 4The examples described are improved. For instance, in an example where the pixel enable signal PIXEN 336 / 436 remains on during the global transfer period 364 / 464, the floating diffuser 238 in the global shutter readout circuit 254 thus maintains the output coupled to the source follower transistor 222 in the pixel circuit 204 via bit line 212 and row select transistor 224. In an example where the sample-and-hold reset control signal SHR 340 / 440 and / or the sample-and-hold signal control signal SHS 344 / 444 are slowly turned off with slope control, most of the mismatched electrons (e.g., from both coupling and charge injection) from the sample-and-hold reset (SHR) and sample-and-hold signal (SHS) will be absorbed by the source follower transistor 222 in the pixel circuit 204 during the global transfer. However, during the rolling readout periods 360 / 460, when the sample and hold reset control signal SHR 340 / 440 and / or the sample and hold signal control signal SHS 344 / 444 are turned on (at different times), the floating diffuser 238 couples to one of the first and second storage capacitors 242 or 246, thus injecting mismatched holes from SHR and SHS into the first and second storage capacitors 242 or 246 and the floating diffuser 238. This mismatch cannot be completely canceled out by mismatched electrons during the global transfer periods 364 / 464. Due to this inconsistent condition, a significant fixed-mode noise exists at the output 252 of the global shutter readout circuit 254.

[0059] However, in the above text Figures 2 to 4In the example described, the pixel enable signal PIXEN 336 / 436 is turned off before any sampling and holding operation using the sample and hold reset control signals 340 / 440 and / or the sample and hold signal control signals SHS 344 / 444. Therefore, the floating diffuser 238 is floating when the pixel enable signal PIXEN 336 / 436 is turned off, instead of being coupled to and absorbed by the source follower transistor 222. Consequently, most of the SHR and SHS mismatched electrons are instead sampled by the first and second storage capacitors 242 or 246. During the rolling readout period 360 / 460, mismatched holes in the SHR and SHS (caused by the Sampling and Holding Reset Control Signal SHR 340 / 440 and / or the Sampling and Holding Signal Control Signal SHS 344 / 444 being turned on) are injected into the first and second storage capacitors 242 or 246 and the floating diffuser 238, and are canceled out primarily by the mismatched electrons injected into the first and second storage capacitors 242 or 246 (caused by the Sampling and Holding Reset Control Signal SHR 340 / 440 and / or the Sampling and Holding Signal Control Signal SHS 344 / 444 being turned off) during the global transfer period 364. Therefore, it should be understood that, according to the teachings of the invention, the same floating condition of the floating diffuser 238 helps to significantly reduce fixed-mode noise at the output 252 of the global shutter readout circuit 254 when the pixel enable signal PIXEN 336 / 436 is turned off during the global transfer.

[0060] The above description of the illustrative examples of the invention (including those described in the abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention have been described herein for illustrative purposes, various modifications are possible within the scope of the invention, as will be recognized by those skilled in the art.

[0061] Based on the above detailed description, these modifications can be made to the invention. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention should be fully defined by the appended claims, and the appended claims should be interpreted according to the established principles of their interpretation.

Claims

1. A global shutter readout circuit, comprising: A pixel enable transistor has a first terminal coupled to a bit line from the pixel circuitry; A source follower transistor having a gate coupled to a second terminal of the pixel enable transistor, such that the pixel enable transistor is coupled between the bit line and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor is coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; A first storage capacitor coupled to the first storage transistor, wherein the first storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a first sampling and holding SH signal coupled to the gate of the first storage transistor; A second storage transistor is coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; and A second storage capacitor is coupled to the second storage transistor, wherein the second storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a second sampling and holding (SH) signal coupled to the gate of the second storage transistor. The pixel enable signal is configured to transition to an on level at a first time during a global transfer period to turn on the pixel enable transistor, and the first SH signal is configured to transition to the on level at the first time to turn on the first storage transistor. The pixel enable signal is configured to transition to an off level at a second time, and the pixel enable signal is configured to complete the transition to the off level at a third time to turn off the pixel enable transistor, wherein the second and third times occur after the first time. The first SH signal is configured to transition to the off level at a fourth time, wherein the fourth time occurs after the second and third times, wherein the first SH signal is configured to complete the transition to the off level at a fifth time to turn off the first storage transistor, wherein the first SH signal is configured to transition from the on level to the off level by slope control such that the fifth time occurs after the fourth time, and the off transition duration between the fourth and fifth times is greater than the on transition duration of the first SH signal transitioning from the off level to the on level at the first time.

2. The global shutter readout circuit according to claim 1, The pixel enable signal is configured to transition to the on-level at a sixth time to turn on the pixel enable transistor, and the second SH signal is configured to transition to the on-level at the sixth time to turn on the second storage transistor, wherein the sixth time occurs after the fifth time. The pixel enable signal is configured to transition to the off level at a seventh time, and the pixel enable signal is configured to complete the transition to the off level at an eighth time to turn off the pixel enable transistor, wherein the seventh and eighth times occur after the sixth time. The second SH signal is configured to begin transitioning to the off level at a ninth time, wherein the ninth time occurs after the seventh and eighth times, wherein the second SH signal is configured to complete the transition to the off level at a tenth time to turn off the second storage transistor, wherein the second SH signal is configured to transition from the on level to the off level by slope control such that the tenth time occurs after the ninth time, and the off transition duration between the ninth and tenth times is greater than the on transition duration of the second SH signal transitioning from the off level to the on level at the sixth time.

3. The global shutter readout circuit according to claim 2, Wherein there is substantially no delay between the second time and the third time when the pixel enable signal completes the transition from the on level to the off level. There is substantially no delay between the seventh time when the pixel enable signal completes the transition from the on level to the off level and the eighth time.

4. The global shutter readout circuit according to claim 2, The pixel enable signal is configured to transition from the on level to the off level via slope control, such that the off transition duration between the second and third times is greater than the on transition duration of the pixel enable signal transitioning from the off level to the on level during the first time. The pixel enable signal is configured to transition from the on level to the off level by slope control, such that the off transition duration between the seventh and eighth times is greater than the on transition duration of the pixel enable signal transitioning from the off level to the on level at the sixth time.

5. The global shutter readout circuit according to claim 2, further comprising: A reset transistor, which is coupled between the reset voltage and the bit line; and A row selection transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

6. The global shutter readout circuit of claim 5, further comprising a floating diffuser, wherein the second terminal of the pixel enable transistor, the gate of the source follower transistor, the first storage transistor, and the second storage transistor are coupled to the floating diffuser.

7. The global shutter readout circuit according to claim 6, wherein the first storage transistor and the first storage capacitor are coupled between the floating diffusion and the reference voltage, wherein the second storage transistor and the second storage capacitor are coupled between the floating diffusion and the reference voltage.

8. The global shutter readout circuit of claim 7, further comprising a bias transistor coupled between the first terminal of the pixel enable transistor and ground.

9. The global shutter readout circuit of claim 8, further comprising a common-source cascode transistor coupled between the first terminal of the pixel enable transistor and the bias transistor.

10. The global shutter readout circuit of claim 9, wherein the gate of the bias transistor is coupled to a first bias voltage, and wherein the gate of the cascode transistor is coupled to a second bias voltage.

11. The global shutter readout circuit of claim 6, wherein the floating diffuser is configured to float and decouple from the bit line in response to turning off the pixel enable transistor.

12. The global shutter readout circuit of claim 11, wherein the floating diffuser is configured to float between the fourth and fifth times and between the ninth and tenth times and to be decoupled from the bit line.

13. An imaging system comprising: A pixel array, which contains multiple pixel circuits; A control circuit system coupled to the pixel array to control the operation of the pixel array; and A readout circuit system coupled to the pixel array to read out image data from the pixel array, wherein the readout circuit system includes a plurality of global shutter readout circuits, wherein each global shutter readout circuit includes: a pixel enable transistor having a first terminal coupled to a bit line from one of the plurality of pixel circuits; A source follower transistor having a gate coupled to a second terminal of the pixel enable transistor, such that the pixel enable transistor is coupled between the bit line and the source follower transistor, wherein the first and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor is coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; A first storage capacitor coupled to the first storage transistor, wherein the first storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a first sampling and holding SH signal coupled to the gate of the first storage transistor; A second storage transistor, coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor; and A second storage capacitor is coupled to the second storage transistor, wherein the second storage capacitor and the gate of the source follower transistor are configured to be coupled together in response to a second sampling and holding (SH) signal coupled to the gate of the second storage transistor. The pixel enable signal is configured to transition to an on level at a first time during a global transfer period to turn on the pixel enable transistor, and the first SH signal is configured to transition to the on level at the first time to turn on the first storage transistor. The pixel enable signal is configured to transition to an off level at a second time, and the pixel enable signal is configured to complete the transition to the off level at a third time to turn off the pixel enable transistor, wherein the second and third times occur after the first time. The first SH signal is configured to transition to the off level at a fourth time, wherein the fourth time occurs after the second and third times, wherein the first SH signal is configured to complete the transition to the off level at a fifth time to turn off the first storage transistor, wherein the first SH signal is configured to transition from the on level to the off level by slope control such that the fifth time occurs after the fourth time, and the off transition duration between the fourth and fifth times is greater than the on transition duration of the first SH signal transitioning from the off level to the on level at the first time.

14. The imaging system according to claim 13, The pixel enable signal is configured to transition to the on-level at a sixth time to turn on the pixel enable transistor, and the second SH signal is configured to transition to the on-level at the sixth time to turn on the second storage transistor, wherein the sixth time occurs after the fifth time. The pixel enable signal is configured to transition to the off level at a seventh time, and the pixel enable signal is configured to complete the transition to the off level at an eighth time to turn off the pixel enable transistor, wherein the seventh and eighth times occur after the sixth time. The second SH signal is configured to begin transitioning to the off level at a ninth time, wherein the ninth time occurs after the seventh and eighth times, wherein the second SH signal is configured to complete the transition to the off level at a tenth time to turn off the second storage transistor, wherein the second SH signal is configured to transition from the on level to the off level by slope control such that the tenth time occurs after the ninth time, and the off transition duration between the ninth and tenth times is greater than the on transition duration of the second SH signal transitioning from the off level to the on level at the sixth time.

15. The imaging system according to claim 14, Wherein there is substantially no delay between the second time and the third time when the pixel enable signal completes the transition from the on level to the off level. There is substantially no delay between the seventh time when the pixel enable signal completes the transition from the on level to the off level and the eighth time.

16. The imaging system according to claim 14, The pixel enable signal is configured to transition from the on level to the off level via slope control, such that the off transition duration between the second and third times is greater than the on transition duration of the pixel enable signal transitioning from the off level to the on level during the first time. The pixel enable signal is configured to transition from the on level to the off level by slope control, such that the off transition duration between the seventh and eighth times is greater than the on transition duration of the pixel enable signal transitioning from the off level to the on level at the sixth time.

17. The imaging system of claim 14, wherein each global shutter readout circuit further comprises: A reset transistor, which is coupled between the reset voltage and the bit line; and A row selection transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

18. The imaging system of claim 17, wherein each global shutter readout circuit further includes a floating diffuser, wherein the second terminal of the pixel enable transistor, the gate of the source follower transistor, the first storage transistor, and the second storage transistor are coupled to the floating diffuser.

19. The imaging system of claim 18, wherein the first storage transistor and the first storage capacitor are coupled between the floating diffusion and the reference voltage, wherein the second storage transistor and the second storage capacitor are coupled between the floating diffusion and the reference voltage.

20. The imaging system of claim 19, wherein each global shutter readout circuit further includes a bias transistor coupled between the first terminal of the pixel enable transistor and ground.

21. The imaging system of claim 20, wherein each global shutter readout circuit further includes a common-source cascode transistor coupled between the first terminal of the pixel enable transistor and the bias transistor.

22. The imaging system of claim 21, wherein the gate of the bias transistor is coupled to a first bias voltage, and the gate of the cascode transistor is coupled to a second bias voltage.

23. The imaging system of claim 18, wherein the floating diffuser is configured to float and decouple from the bit line in response to turning off the pixel enable transistor.

24. The imaging system of claim 23, wherein the floating diffuser is configured to float between the fourth and fifth times and between the ninth and tenth times and to be decoupled from the bit line.

Images