Memory structure and method of manufacturing the same

Abstract

A memory structure is provided including a source / drain region on a substrate, a first dielectric layer overlying the source / drain region, a second dielectric layer on the first dielectric layer, and a contact contacting the source / drain region. The contact includes a first contact portion extending into the source / drain region, a second contact portion extending into the first dielectric layer, and a third contact portion extending into the second dielectric layer. A bottom surface of the first contact portion is lower than a top surface of the source / drain region. The second contact portion is between the first contact portion and the third contact portion. A distance between a sidewall of the first contact portion and a sidewall of the source / drain region is 30% to 60% of a width of the source / drain region. The multiple contact portions increase a contact area between the overall contact and the source / drain region, thereby reducing a resistance between the contact and the source / drain region, improving efficiency of the memory structure.

Description

Technical Field

[0001] This disclosure relates to memory structures and methods of manufacturing them, and in particular to the contacts of memory structures. Background Technology

[0002] Memory devices are used in a variety of electronic applications, such as dynamic random access memory (DRAM), static random access memory (SRAM), or similar. The memory industry continues to improve the integration density of multiple electronic components (e.g., transistors, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, thus allowing more components to be integrated into a given area. However, the reduced feature size also decreases the contact area between electronic components, which can potentially adversely affect the functionality of the memory device. Summary of the Invention

[0003] According to some embodiments of this disclosure, a memory structure includes source / drain regions on a substrate, a first dielectric layer covering the source / drain regions, a second dielectric layer on the first dielectric layer, and contacts contacting the source / drain regions. The contacts include a first contact portion extending into the source / drain regions, a second contact portion extending into the first dielectric layer, and a third contact portion extending into the second dielectric layer. The bottom surface of the first contact portion is lower than the top surface of the source / drain regions. The second contact portion is located between the first contact portion and the third contact portion. The distance between the sidewall of the first contact portion and the sidewall of the source / drain regions is 30% to 60% of the width of the source / drain regions.

[0004] In some embodiments, the bottom surface of the second contact portion is lower than the bottom surface of the first contact portion.

[0005] In some embodiments, the bottom surface of the second contact portion is coplanar with the bottom surface of the first contact portion.

[0006] In some embodiments, the bottom surface of the third contact portion is higher than the bottom surface of the first contact portion and the bottom surface of the second contact portion.

[0007] In some embodiments, the bottom surface of the third contact portion is coplanar with the top surface of the source / drain region.

[0008] In some embodiments, the interface between the second contact portion and the third contact portion is coplanar with the sidewall of the first dielectric layer.

[0009] In some embodiments, the width of the second contact portion is the same as the width of the first dielectric layer on the sidewall of the source / drain region.

[0010] In some embodiments, the width of the second contact portion is greater than the width of the first dielectric layer on the sidewall of the source / drain region.

[0011] In some embodiments, the first dielectric layer is an oxide layer and the second dielectric layer is a nitride layer.

[0012] According to some embodiments of this disclosure, a memory structure includes a substrate having a bit region and a cell region, a first source / drain region on the substrate in the bit region, a second source / drain region on the substrate in the cell region, a first dielectric layer covering the first source / drain region and the second source / drain region, a second dielectric layer on the first dielectric layer, a bit contact contacting the first source / drain region, and a cell contact contacting the second source / drain region. The bit contact includes a first bit contact portion extending into the first source / drain region, a second bit contact portion extending into the first dielectric layer on the sidewall of the first source / drain region, and a third bit contact portion extending into the second dielectric layer. The bottom surface of the first bit contact portion is lower than the top surface of the first source / drain region. The second bit contact portion is located between the first bit contact portion and the third bit contact portion. The distance between the sidewall of the first bit contact portion and another sidewall of the first source / drain region is 30% to 60% of the width of the first source / drain region.

[0013] In some embodiments, the cell contact includes a first cell contact portion extending into the second source / drain region, a second cell contact portion extending into the sidewall of the second source / drain region and the second source / drain region, and a third cell contact portion extending into the second dielectric layer. The bottom surface of the first cell contact portion is lower than the top surface of the second source / drain region. The second cell contact portion is located between the first cell contact portion and the third cell contact portion. The distance between the sidewall of the first cell contact portion and the other sidewall of the second source / drain region is 30% to 60% of the width of the second source / drain region.

[0014] In some embodiments, the bottom surface of the first unit contact portion is lower than the bottom surface of the first unit contact portion.

[0015] In some embodiments, the bottom surface of the second bit contact portion is coplanar with the bottom surface of the second unit contact portion.

[0016] In some embodiments, the bottom surface of the third bit contact portion is coplanar with the bottom surface of the third unit contact portion and the top surface of the first source / drain region.

[0017] In some embodiments, the width of the third bit contact portion is 30% to 60% of the distance between the first dielectric layer on the sidewall of the first source / drain region and the first dielectric layer on the sidewall of the second source / drain region.

[0018] In some embodiments, the width of the second unit contact portion is greater than the width of the second bit contact portion.

[0019] According to some embodiments of this disclosure, a method of manufacturing a memory structure includes the following steps: forming a first dielectric layer on a source / drain region and forming a second dielectric layer on the first dielectric layer; forming a mask layer on the second dielectric layer, wherein the mask layer includes a mask opening exposing the second dielectric layer, and the distance between the sidewall of the mask opening and the sidewall of the source / drain region is 30% to 60% of the width of the source / drain region; etching the second dielectric layer and the first dielectric layer through the mask opening to form a first opening, wherein the first opening exposes the top surface of the source / drain region and another sidewall; etching the source / drain region through the first opening to form a second opening; and filling the second opening with a conductive material to form a contact.

[0020] In some embodiments, the bottom surface of the second opening includes a first portion exposing the source / drain region, a second portion exposing the first dielectric layer, and a third portion exposing the second dielectric layer. The second portion is lower than the first portion, and the first portion is lower than the third portion.

[0021] In some embodiments, the second portion further exposes the source / drain regions.

[0022] In some embodiments, the bottom surface of the second opening includes a first portion exposing the source / drain region, a second portion exposing the first dielectric layer, and a third portion exposing the second dielectric layer. The second portion is coplanar with the first portion and is lower than the third portion. Attached Figure Description

[0023] The various aspects of this disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1 A cross-sectional view of a memory structure is shown based on a comparative example of this disclosure.

[0025] Figure 2A A cross-sectional view of a memory structure is shown according to an embodiment of the present disclosure.

[0026] Figure 2B Draw Figure 2A An enlarged view of the memory structure in the image.

[0027] Figure 3A A cross-sectional view of the memory structure is shown according to another embodiment of the present disclosure.

[0028] Figure 3B A magnified view of the memory structure in Figure 3A is shown.

[0029] Figures 4A to 4H Cross-sectional views of an intermediate stage of a method for manufacturing a memory structure are illustrated based on some embodiments of the present disclosure. Detailed Implementation

[0030] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, values, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one component or feature and another component or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0032] This disclosure provides a memory structure and a method for manufacturing the same. The memory structure includes a first dielectric layer covering source / drain regions, a second dielectric layer on the first dielectric layer, and contacts contacting the source / drain regions. A first contact portion of the contacts extends into the source / drain regions, a second contact portion extends into the first dielectric layer, and a third contact portion extends into the second dielectric layer. Because the sidewalls of the first contact portion are separated from the sidewalls of the source / drain regions by a certain distance, the contact area between the contacts and the source / drain regions is increased. Therefore, the resistance between the contacts and the source / drain regions is reduced, thereby improving the efficiency of the memory structure.

[0033] According to a comparative example of this disclosure, Figure 1A cross-sectional view of the memory structure 100 is shown. The memory structure 100 includes a substrate 110, a first source / drain region 124a and a second source / drain region 124b on the substrate 110, a first dielectric layer 130 covering the first source / drain region 124a and the second source / drain region 124b, a gate structure 150 above the substrate 110, a second dielectric layer 160 on the first dielectric layer 130 and the gate structure 150, a first contact 170 that contacts the first source / drain region 124a through the first dielectric layer 130, and a second contact 180 that contacts the second source / drain region 124b through the first dielectric layer 130.

[0034] Specifically, substrate 110 includes bit region 102 and cell region 104. Fin 120a protrudes from substrate 110 in bit region 102. Fin 120a includes a bottom 122a and a first source / drain region 124a on bottom 122a. In some embodiments, fin 120a includes the same bulk material as substrate 110, and the upper portion of fin 120a is doped to form the first source / drain region 124a. Similarly, fin 120b protrudes from substrate 110 in bit region 102. Fin 120b includes a bottom 122b and a second source / drain region 124b on bottom 122b.

[0035] In some embodiments, bit region 102 and cell region 104 can collectively form memory cells (or active regions) of memory structure 100. For example... Figure 1 As shown, the isolation structure 140 is adjacent to the cell region 104 to separate the cell region 104 from another memory cell (not shown). The first source / drain region 124a in the bit region 102 can serve as the drain region, while the second source / drain region 124b in the cell region 104 serves as the source region. Therefore, the first contact 170 can be called a drain contact or a bit contact, while the second contact 180 can be called a source contact or a cell contact. It is worth noting that the sidewalls of the first source / drain region 124a and the second source / drain region 124b are coplanar with the sidewalls of the first contact 170 and the second contact 180, respectively. In other words, the top surfaces of the first source / drain region 124a and the second source / drain region 124b are completely covered by the bottom surfaces of the first contact 170 and the second contact 180.

[0036] According to one embodiment of this disclosure, Figure 2A A cross-sectional view of memory structure 200 is shown. Figure 2B Draw Figure 2A An enlarged view of region R1 in memory structure 200. Memory structure 200 is similar to... Figure 1The memory structure 100 has a different contact design on the source / drain regions.

[0037] Specifically, the memory structure 200 includes a substrate 210 having a bit region 202 and a cell region 204, fins 220a on the substrate 210 in the bit region 202, and fins 220b on the substrate 210 in the cell region 204. A first source / drain region 224a is located on the bottom 222a of the fin 220a, and a second source / drain region 224b is located on the bottom 222b of the fin 220b. A first dielectric layer 230 covers the fins 220a, fins 220b, and substrate 210, such that the first source / drain region 224a and the second source / drain region 224b are covered by the first dielectric layer 230. An isolation structure 240 is adjacent to the cell region 204 to separate the cell region 204 from another memory cell (not shown). A gate structure 250 is located above the substrate 210, and a first dielectric layer 230 covering the first source / drain regions 224a and 224b is located above the gate structure 250. A second dielectric layer 260 is located on the gate structure 250 and covers the first dielectric layer 230 covering the first source / drain regions 224a and 224b. In some embodiments, the first dielectric layer 230 may include a material different from the second dielectric layer 260. For example, the first dielectric layer 230 may be an oxide layer, while the second dielectric layer 260 may be a nitride layer.

[0038] The first contact 270 (or bit contact) of the memory structure 200 passes through the first dielectric layer 230 and contacts the first source / drain region 224a. Specifically, the first contact 270 includes a first contact portion 270a, a second contact portion 270b adjacent to the first contact portion 270a, and a third contact portion 270c adjacent to the second contact portion 270b. In other words, the second contact portion 270b is located between the first contact portion 270a and the third contact portion 270c.

[0039] The first contact portion 270a extends into the first source / drain region 224a, such that the bottom surface of the first contact portion 270a is lower than the top surface of the first source / drain region 224a. The second contact portion 270b extends into the first dielectric layer 230 on the sidewall of the first source / drain region 224a. The bottom surface of the second contact portion 270b is also lower than the top surface of the first source / drain region 224a. The third contact portion 270c extends into the second dielectric layer 260.

[0040] like Figure 2BAs shown, the sidewall of the first contact portion 270a and the first source / drain region 224a are not in contact with each other by a distance D1. More specifically, the distance D1 between the sidewall of the first contact portion 270a and the sidewall of the first source / drain region 224a is 30% to 60% of the width W1 of the first source / drain region 224a. Therefore, both the bottom surface and the sidewall of the first contact portion 270a are in contact with the first source / drain region 224a.

[0041] and Figure 1 Compared to memory structure 100, the contact area between the first contact 270 and the first source / drain region 224a is greater than that of memory structure 100. Figure 1 The contact area between the first contact 170 and the first source / drain region 124a is reduced. This reduces the resistance between the first contact 270 and the first source / drain region 224a. This increases the current between the first source / drain region 224a and the second source / drain region 224b, thereby improving the efficiency of the memory structure 200. Furthermore, the design of the first contact 270 does not affect the relationship between the first source / drain region 224a and the gate structure 250, thus avoiding an increase in gate-induced drain leakage (GIDL) in the memory structure 200.

[0042] The second contact 280 (or cell contact) of the memory structure 200 passes through the first dielectric layer 230 and contacts the second source / drain region 224b. The second contact 280 includes a first contact portion 280a, a third contact portion 280c, and a second contact portion 280b between the first contact portion 280a and the third contact portion 280c.

[0043] The first contact portion 280a extends into the second source / drain region 224b, such that the bottom surface of the first contact portion 280a is lower than the top surface of the second source / drain region 224b. The second contact portion 280b extends into the first dielectric layer 230 on the sidewall of the second source / drain region 224b. Compared to the second contact portion 270b, the second contact portion 280b extends laterally into the second source / drain region 224b. The third contact portion 280c extends into the second dielectric layer 260.

[0044] Similar to the first contact 270, the sidewalls of the first contact portion 280a and the second source / drain region 224b are separated from each other by a distance, without contacting the sidewalls of the second contact 280. The distance between the sidewalls of the first contact portion 280a and the sidewalls of the second source / drain region 224b is 30% to 60% of the width of the second source / drain region 224b. Therefore, both the bottom surface and the sidewalls of the first contact portion 280a contact the second source / drain region 224b. Furthermore, the second contact portion 280b extends into the second source / drain region 224b, such that the bottom surface and the sidewalls of the second contact portion 280b also contact the second source / drain region 224b.

[0045] and Figure 1 Compared to memory structure 100, the contact area between the second contact 280 and the second source / drain region 224b is greater. Figure 1 The contact area between the second contact 180 and the second source / drain region 124b is reduced. Therefore, the resistance between the second contact 280 and the second source / drain region 224b can be reduced, thereby improving the efficiency of the memory structure 200.

[0046] refer to Figure 2A and Figure 2B The bottom surface positions of each contact portion can be appropriately arranged to increase the contact area between the contact and the source / drain regions. In some embodiments, the bottom surface of the third contact portion may be higher than the bottom surfaces of the first and second contact portions. Figure 2B As shown, when the bottom surface of the first contact portion 270a and the bottom surface of the second contact portion 270b are lower than the top surface of the first source / drain region 224a, the bottom surface of the third contact portion 270c can be coplanar with the top surface of the first source / drain region 224a. Similarly, when the bottom surface of the first contact portion 280a and the bottom surface of the second contact portion 280b are lower than the top surface of the second source / drain region 224b, the bottom surface of the third contact portion 280c can be coplanar with the top surface of the second source / drain region 224b.

[0047] In some embodiments, the bottom surface of the second contact portion may be coplanar with the bottom surface of the first contact portion. For example... Figure 2BAs shown, the distance H1 from the top surface of the first source / drain region 224a to the bottom surface of the second contact portion 270b can be the same as the distance H2 from the top surface of the first source / drain region 224a to the bottom surface of the first contact portion 270a. Therefore, the bottom surface of the second contact portion 270b is coplanar with the bottom surface of the first contact portion 270a. In some embodiments, the distance H1 can be in the range of 10 nm to 20 nm. If the distance H1 is less than 10 nm, the contact area between the first contact 270 and the first source / drain region 224a may not increase significantly. If the distance H1 is greater than 20 nm, it may cause gate-induced drain current degradation of the memory structure 200.

[0048] In some embodiments, the bottom surface of the second contact portion may be lower than the bottom surface of the first contact portion. For example... Figure 2B As shown, the distance H3 from the top surface of the second source / drain region 224b to the bottom surface of the second contact portion 280b can be greater than the distance H4 from the top surface of the second source / drain region 224b to the bottom surface of the first contact portion 280a. Therefore, the bottom surface of the second contact portion 280b is lower than the bottom surface of the first contact portion 280a. In some embodiments, the distance H3 can be in the range of 10 nm to 20 nm. If the distance H3 is less than 10 nm, the contact area between the second contact 280 and the second source / drain region 224b may not increase significantly. If the distance H1 is greater than 20 nm, it may cause gate-induced drain current degradation in the memory structure 200.

[0049] In some embodiments, due to the manufacturing process of the memory structure, the bottom surface position of the bit contact can correspond to the bottom surface position of the cell contact. For example, as Figure 2B As shown, the distance H1 from the top surface of the first source / drain region 224a to the bottom surface of the second contact portion 270b can be the same as the distance H3 from the top surface of the second source / drain region 224b to the bottom surface of the second contact portion 280b. Therefore, the bottom surface of the second contact portion 270b and the bottom surface of the second contact portion 280b are coplanar.

[0050] The distance H2 from the top surface of the first source / drain region 224a to the bottom surface of the first contact portion 270a can be greater than the distance H4 from the top surface of the second source / drain region 224b to the bottom surface of the first contact portion 280a. Therefore, the bottom surface of the first contact portion 270a is lower than the bottom surface of the first contact portion 280a. It is worth noting that the bottom surfaces of the third contact portion 270c, the third contact portion 280c, the top surfaces of the first source / drain region 224a and the second source / drain region 224b can be coplanar with each other.

[0051] According to another embodiment of this disclosure, Figure 3A A cross-sectional view of memory structure 300 is shown. Figure 3B Draw Figure 3A An enlarged view of region R1 of the memory structure 300. Most components of the memory structure 300 (e.g., the substrate 310 with bit region 302 and cell region 304, the fin 320a with bottom 322a, the fin 320b with bottom 322b, the first dielectric layer 330, the isolation structure 340, the gate structure 350, and the second dielectric layer 360) are similar to... Figure 2A and Figure 2B The corresponding components of memory structure 200 are described above, but the first contact 370 and the second contact 380 have different contact portion designs. Details of these similar components can be found in the description of memory structure 200 and will not be repeated here.

[0052] like Figure 3B As shown, the distance H1 from the top surface of the first source / drain region 324a to the bottom surface of the second contact portion 370b can be the same as the distance H3 from the top surface of the second source / drain region 324b to the bottom surface of the second contact portion 380b. The distance H2 from the top surface of the first source / drain region 324a to the bottom surface of the first contact portion 370a can be greater than the distance H4 from the top surface of the second source / drain region 324b to the bottom surface of the first contact portion 380a. In other words, the bottom surface of the first contact portion 370a is lower than the bottom surface of the first contact portion 380a. The bottom surfaces of the third contact portion 370c, the third contact portion 380c, the top surfaces of the first source / drain region 324a and the second source / drain region 324b can be coplanar with each other.

[0053] and Figure 2BCompared to memory structure 200, memory structure 300 can have a distance H1 greater than distance H2 and a distance H3 greater than distance H4. Therefore, the bottom surfaces of both the second contact portion 370b and the second contact portion 380b are lower than the bottom surfaces of the first contact portion 370a and the first contact portion 380a. Thus, both the first contact portion 370a and the second contact portion 370b contact the first source / drain region 324a, thereby increasing the contact area between the first contact 370a and the first source / drain region 324a and reducing resistance. Similarly, both the first contact portion 380a and the second contact portion 380b contact the second source / drain region 324b, thereby increasing the contact area between the second contact 380a and the second source / drain region 324b and reducing resistance.

[0054] Reference Figure 2A and Figure 2B In some embodiments, the widths of the respective contact portions can be appropriately arranged to increase the contact area between the contact and the source / drain regions. For example, the interface between the first contact portion 270a and the second contact portion 270b can be coplanar with the sidewall of the first source / drain region 224a, and the interface between the second contact portion 270b and the third contact portion 270c can be coplanar with the sidewall of the first dielectric layer 230 on the sidewall of the first source / drain region 224a. Therefore, the width of the second contact portion 270b is the same as the width of the first dielectric layer 230 on the sidewall of the first source / drain region 224a.

[0055] As another example, the interface between the second contact portion 280b and the third contact portion 280c may be coplanar with the sidewall of the first dielectric layer 230 on the sidewall of the second source / drain region 224b, with the second contact portion 280b extending laterally toward the second source / drain region 224b. Therefore, the width of the second contact portion 280b is greater than the width of the first dielectric layer 230 on the sidewall of the second source / drain region 224b. In some embodiments where the first contact 270 is a bit contact and the second contact 280 is a cell contact, the width of the second contact portion 280b may be greater than the width of the second contact portion 270b.

[0056] In some embodiments, the third contact portion may have a suitable width to avoid a conductive path between the first contact and the second source / drain region. For example, the sidewalls of the first dielectric layer 230 on the sidewall of the first source / drain region 224a and the sidewalls of the first dielectric layer 230 on the sidewall of the adjacent second source / drain region 224b are separated from each other by a distance D2. The width W2 of the third contact portion 270c may be 30% to 60% of the distance D2, thereby avoiding direct current transfer between the first contact 270 and the second source / drain region 224b. In some embodiments, the width of the third contact portion 270c may be the same as that of the third contact portion 280c.

[0057] According to some embodiments of this disclosure Figures 4A to 4H Draw Figures 2A to 2B A cross-sectional view of an intermediate stage in the manufacturing process of the memory structure 200. More specifically, the manufacturing process relates to the formation of contacts on the source / drain regions. Figures 4A to 4H A cross-sectional view of the manufactured memory structure 200 is shown as an example; however, Figures 4A to 4H The method shown is not limited to manufacturing memory structure 200. The method shown can be used to manufacture other memory structures within the scope of this disclosure, such as... Figure 3B The memory structure 300 is included. Furthermore, additional manufacturing steps may be performed between the multiple steps of the method, and descriptions of these additional manufacturing steps may be omitted for clarity. These additional steps may occur before, during, and / or after the method disclosed herein.

[0058] refer to Figure 4A A first source / drain region 224a and a second source / drain region 224b are provided. A first dielectric layer 230 is formed on the first source / drain region 224a and the second source / drain region 224b, such that the top surface and sidewalls of the first source / drain region 224a and the second source / drain region 224b are covered by the first dielectric layer 230. A second dielectric layer 260 is formed on the first dielectric layer 230. Figure 4A As shown, the top surface and sidewalls of the first dielectric layer 230 may be covered by the second dielectric layer 260.

[0059] A masking layer 400 is formed on the second dielectric layer 260. The masking layer 400 includes a masking opening 410 that exposes a portion of the second dielectric layer 260. The masking opening 410 is located above the first source / drain region 224a. Figure 4AAs shown, the masking opening 410 is not aligned with the first source / drain region 224a. Specifically, the sidewall of the masking opening 410, located directly above the first source / drain region 224a, is separated from the sidewall of the first source / drain region 224a by a distance D3. In some embodiments, the distance D3 may be 30% to 60% of the width W1 of the first source / drain region 224a.

[0060] Another sidewall of the shielding opening 410 is located directly above the second dielectric layer 260 between the first source / drain region 224a and the second source / drain region 224b. The other sidewall of the shielding opening 410 and the sidewall of the first dielectric layer 230 on the first source / drain region 224a are separated from each other by a distance D4. In some embodiments, the distance D4 can be 30% to 60% of the distance D2, where the distance D2 is the distance between the first dielectric layer 230 on the sidewall of the first source / drain region 224a and the first dielectric layer 230 on the sidewall of the more closely spaced second source / drain region 224b.

[0061] refer to Figure 4B The second dielectric layer 260 exposed by the mask opening 410 and the underlying first dielectric layer 230 are etched to form the opening 420. Specifically, the etching operation is performed through the mask opening 410. The etching operation stops on the top surface of the first source / drain region 224a. When the etching operation stops, the opening 420 exposes one of the top surface and sidewalls of the first source / drain region 224a.

[0062] The bottom surface of opening 420 includes a first portion 422 exposing the top surface of the first source / drain region 224a, a second portion 424 exposing the first dielectric layer 230 on the sidewalls of the first source / drain region 224a, and a third portion 426 exposing the second dielectric layer 260. The second portion 424 is located between the first portion 422 and the third portion 426. Figure 4B As shown, the second portion 424 is lower than the first portion 422 and the third portion 426, such that the opening 420 exposes the sidewall of the first source / drain region 224a. In some embodiments, the first portion 422 may be coplanar with the third portion 426, and the distance H1 between the top surface of the first source / drain region 224a and the top surface of the second portion 424 may be in the range of 10 nm to 20 nm.

[0063] In some embodiments, the etching operation performed on the second dielectric layer 260 and the first dielectric layer 230 may be an anisotropic etching process. In some embodiments, the etching operation performed on the second dielectric layer 260 and the first dielectric layer 230 may have higher selectivity for the first dielectric layer 230. Therefore, the first dielectric layer 230 on the sidewall of the first source / drain region 224a may be etched at a faster rate relative to the second dielectric layer 260 to form a second portion 424 below the third portion 426.

[0064] refer to Figure 4C The first source / drain region 224a exposed by the opening 420 is etched to form the opening 420'. Specifically, the etching operation is performed through the opening 420. The etching operation is selective for the first source / drain region 224a, so that the first dielectric layer 230 and the second dielectric layer 260 are not significantly etched. Therefore, the first source / drain region 224a is etched downward from the exposed portion of the top surface and laterally from the exposed portion of the sidewall to form the opening 420'.

[0065] The bottom surface of the opening 420' includes a first portion 422' exposing the first source / drain region 224a, a second portion 424' exposing the first dielectric layer 230, and a third portion 426' exposing the second dielectric layer 260. In some embodiments, such as Figure 4B As shown, the second portion 424' may be coplanar with the first portion 422', and the second portion 424' may be lower than the third portion 426'. In other words, the distance H2 between the top surface of the first source / drain region 224a and the top surface of the first portion 422' may be the same as the distance H1 in the range of 10 nm to 20 nm. In some other embodiments, the second portion 424' may be lower than the first portion 422', and the first portion 422' may be lower than the third portion 426'.

[0066] refer to Figure 4D Filled with conductive material Figure 4C An opening 420' is formed in the opening 420' to form a first contact 270. Specifically, a conductive material layer is formed in the opening 420' on the second dielectric layer 260. Next, a planarization process is performed on the conductive material layer to remove excess conductive material from the second dielectric layer 260. The remaining conductive material forms the first contact 270. The first contact 270 corresponds to... Figure 2B The first contact 270 in the middle, wherein the contact area between the first contact 270 and the first source / drain region 224a is increased.

[0067] The above operations can also be used to form the second contact 280. (See reference) Figures 4E to 4FA masking layer 450, including a masking opening 460, is formed on the second dielectric layer 260. The masking opening 460 is located above the second source / drain region 224b. The second dielectric layer 260 exposed by the masking opening 460 and the underlying first dielectric layer 230 are etched to form the opening 470. The opening 470 is similar to... Figure 4B The opening 420 in the middle includes a first portion 472 exposing the second source / drain region 224b, a second portion 474 exposing the first dielectric layer 230 on the sidewall of the second source / drain region 224b, and a third portion 476 exposing the second dielectric layer 260. Figures 4E to 4F For details of the steps shown, please refer to the information provided. Figures 4A to 4B The content described.

[0068] In some embodiments, the distance D3 between the sidewall of the shielding opening 460 located directly above the second source / drain region 224b and the sidewall of the second source / drain region 224b can be 30% to 60% of the width W1 of the second source / drain region 224b. In some embodiments, the distance between the other sidewall of the shielding opening 460 and the sidewall of the first dielectric layer 230 on the second source / drain region 224b can be Figure 4A The distance D4. In some embodiments, the distance H3 between the top surface of the second source / drain region 224b and the top surface of the second portion 474 can be in the range of 10 nm to 20 nm.

[0069] refer to Figure 4G The second source / drain region 224b exposed by the opening 470 is etched to form the opening 470'. Specifically, the etching operation is performed through the opening 470. The etching operation is selective for the second source / drain region 224b, so that the first dielectric layer 230 and the second dielectric layer 260 are not significantly etched. Therefore, the second source / drain region 224b is etched downward from the exposed portion of the top surface and laterally from the exposed portion of the sidewall to form the opening 470'.

[0070] The bottom surface of opening 470' includes a first portion 472' exposing the second source / drain region 224b, a second portion 474' exposing the first dielectric layer 230, and a third portion 476' exposing the second dielectric layer 260. In some embodiments, with Figure 4C Compared to the first source / drain region 224a, the second source / drain region 224b can be etched with less material. Therefore, the second portion 474' is lower than the first portion 472', and the first portion 472' is lower than the third portion 476'. In other words, the distance H4 between the top surface of the second source / drain region 224b and the top surface of the first portion 472' can be less than the distance H3. In some embodiments, the width of the second portion 474' can be greater than... Figure 4C The width of the second part 424' in the second part 474' is such that the second part 474' also exposes a portion of the second source / drain region 224b.

[0071] refer to Figure 4H Filled with conductive material Figure 4G The opening 470' in the middle forms the second contact 280. Figure 4H The steps shown are similar to those on Figure 4D The content described above. The formed second contact 280 corresponds to... Figure 2B The second contact 280 in the middle, wherein the contact area between the second contact 280 and the second source / drain region 224b is increased.

[0072] According to the embodiments of this disclosure, a memory structure includes a first dielectric layer covering a source / drain region, a second dielectric layer on the first dielectric layer, and contacts contacting the source / drain region. The contacts include a first contact portion extending into the source / drain region, a second contact portion extending into the first dielectric layer, and a third contact portion extending into the second dielectric layer. The distance between the sidewall of the first contact portion and the sidewall of the source / drain region is 30% to 60% of the width of the source / drain region. Furthermore, the manufacturing method can control the position of the bottom surface of the contact portion. Therefore, the bottom surface of the first contact portion, the sidewall of the first contact portion, and even the sidewall of the second contact portion contact the source / drain region. Thus, the contact area between the contact and the source / drain region is increased, thereby reducing contact resistance and improving the efficiency of the memory structure.

[0073] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0074] [Symbol Explanation]

[0075] 100: Memory Structure

[0076] 102: Bit region

[0077] 104: Cell Region

[0078] 110:Substrate

[0079] 120a: Fin

[0080] 120b: Fin

[0081] 122a: Bottom

[0082] 122b: Bottom

[0083] 124a: First source / drain region

[0084] 124b: Second source / drain region

[0085] 130: First dielectric layer

[0086] 140: Isolation Structure

[0087] 150: Gate structure

[0088] 160: Second dielectric layer

[0089] 170: First contact element

[0090] 180: Second contact element

[0091] 200: Memory Structure

[0092] 202: Bit region

[0093] 204: Cell Region

[0094] 210:Substrate

[0095] 220a: Fin

[0096] 220b: Fins

[0097] 222a: Bottom

[0098] 222b: Bottom

[0099] 224a: First source / drain region

[0100] 224b: Second source / drain region

[0101] 230: First dielectric layer

[0102] 240: Isolation Structure

[0103] 250: Gate structure

[0104] 260: Second dielectric layer

[0105] 270: First contact element

[0106] 270a: First contact part

[0107] 270b: Second contact part

[0108] 270c: Third contact part

[0109] 280: Second contact element

[0110] 280a: First contact part

[0111] 280b: Second contact part

[0112] 280c: Third contact part

[0113] 300: Memory Structure

[0114] 302: Bit region

[0115] 304: Cell Region

[0116] 310:Substrate

[0117] 320a: Fin

[0118] 320b: Fins

[0119] 322a: Bottom

[0120] 322b: Bottom

[0121] 324a: First source / drain region

[0122] 324b: Second source / drain region

[0123] 330: First dielectric layer

[0124] 340: Isolation Structure

[0125] 350: Gate structure

[0126] 360: Second dielectric layer

[0127] 370: First contact element

[0128] 370a: First contact part

[0129] 370b: Second contact part

[0130] 370c: Third contact part

[0131] 380: Second contact element

[0132] 380a: First contact part

[0133] 380b: Second contact part

[0134] 380c: Third contact part

[0135] 400: Mask layer

[0136] 410: Masking opening

[0137] 420,420': Opening

[0138] 422,422': Part 1

[0139] 424,424': Part Two

[0140] 426,426': Part Three

[0141] 450: Mask layer

[0142] 460: Masking opening

[0143] 470,470': Opening

[0144] 472,472': Part 1

[0145] 474,474': Part Two

[0146] 476,476': Part Three

[0147] D1, D2, D3, D4: Distance

[0148] H1, H2, H3, H4: Distance

[0149] R1: Region

[0150] W1, W2: Width.

Claims

1. A memory structure, characterized in that, include: The source / drain region is located on the substrate; The first dielectric layer covers the source / drain region; The second dielectric layer is located on the first dielectric layer; and A contact element that contacts the source / drain region, wherein the contact element includes: The first contact portion extends into the source / drain region, wherein the bottom surface of the first contact portion is lower than the top surface of the source / drain region; The second contact portion extends into the first dielectric layer, wherein the bottom surface of the second contact portion is lower than the bottom surface of the first contact portion; and The third contact portion extends into the second dielectric layer, wherein the second contact portion is located between the first contact portion and the third contact portion, and the distance between the sidewall of the first contact portion away from the second contact portion and the sidewall of the source / drain region away from the second contact portion is 30% to 60% of the width of the source / drain region.

2. The memory structure of claim 1, wherein the bottom surface of the third contact portion is higher than the bottom surface of the first contact portion and the bottom surface of the second contact portion.

3. The memory structure of claim 1, wherein the bottom surface of the third contact portion is coplanar with the top surface of the source / drain region.

4. The memory structure of claim 1, wherein the interface between the second contact portion and the third contact portion is coplanar with the sidewall of the first dielectric layer.

5. The memory structure of claim 4, wherein the width of the second contact portion is the same as the width of the first dielectric layer on the sidewall of the source / drain region.

6. The memory structure of claim 4, wherein the width of the second contact portion is greater than the width of the first dielectric layer on the sidewall of the source / drain region.

7. The memory structure of claim 1, wherein the first dielectric layer is an oxide layer and the second dielectric layer is a nitride layer.

8. A memory structure, characterized in that, include: The substrate includes bit regions and cell regions; The first source / drain region is located on the substrate in the bit region; The second source / drain region is located on the substrate in the cell region; A first dielectric layer covers the first source / drain region and the second source / drain region; The second dielectric layer is located on the first dielectric layer; A bit contact element contacts the first source / drain region, wherein the bit contact element includes: The first element contact portion extends into the first source / drain region, wherein the bottom surface of the first element contact portion is lower than the top surface of the first source / drain region; The second bit contact portion extends into the first dielectric layer on the first sidewall of the first source / drain region, wherein the bottom surface of the second bit contact portion is lower than the bottom surface of the first bit contact portion; and The third bit contact portion extends into the second dielectric layer, wherein the second bit contact portion is located between the first bit contact portion and the third bit contact portion, and the distance between the first sidewall of the first bit contact portion and the second sidewall of the first source / drain region is 30% to 60% of the width of the first source / drain region. The unit contact contacts the second source / drain region.

9. The memory structure of claim 8, wherein the cell contact comprises: The first unit contact portion extends into the second source / drain region, wherein the bottom surface of the first unit contact portion is lower than the top surface of the second source / drain region; The second unit contact portion extends into the first dielectric layer and the second source / drain region on the first sidewall of the second source / drain region; and The third unit contact portion extends into the second dielectric layer, wherein the second unit contact portion is located between the first unit contact portion and the third unit contact portion, and the distance between the first sidewall of the first unit contact portion and the second sidewall of the second source / drain region is 30% to 60% of the width of the second source / drain region.

10. The memory structure of claim 9, wherein the bottom surface of the first unit contact portion is lower than the bottom surface of the first unit contact portion.

11. The memory structure of claim 9, wherein the bottom surface of the second bit contact portion is coplanar with the bottom surface of the second cell contact portion.

12. The memory structure of claim 9, wherein the bottom surface of the third bit contact portion is coplanar with the bottom surface of the third cell contact portion and the top surface of the first source / drain region.

13. The memory structure of claim 9, wherein the width of the third bit contact portion is 30% to 60% of the distance between the first dielectric layer on the first sidewall of the first source / drain region and the first dielectric layer on the first sidewall of the second source / drain region.

14. The memory structure of claim 9, wherein the width of the second cell contact portion is greater than the width of the second bit contact portion.

15. A method for manufacturing a memory structure, characterized in that, include: A first dielectric layer is formed on the source / drain region and a second dielectric layer is formed on the first dielectric layer; A masking layer is formed on the second dielectric layer, wherein the masking layer includes a masking opening that exposes the second dielectric layer, and the distance between the sidewall of the masking opening near the source / drain region and the sidewall of the source / drain region is 30% to 60% of the width of the source / drain region. The second dielectric layer and the first dielectric layer are etched through the opening in the shield to form a first opening, wherein the first opening exposes the top surface of the source / drain region and the other sidewall; The source / drain region is etched through the first opening to form a second opening, wherein the bottom surface of the second opening includes a first portion exposing the source / drain region, a second portion exposing the first dielectric layer, and a third portion exposing the second dielectric layer, the second portion being lower than the first portion, and the first portion being lower than the third portion; and The second opening is filled with a conductive material to form a contact, and the bottom surface of the contact in the second part is lower than the bottom surface of the contact in the first part.

16. The method of claim 15, wherein the second portion further exposes the source / drain region.

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