A line length matching method, device and storage medium based on trunk wiring

Abstract

The present application discloses an automatic line length matching method, device and storage medium based on trunk wiring, comprising: initializing wiring resources for at least one signal line network of a differential pair logic structure in a circuit layout; grouping multiple pins in the at least one signal line network according to the length, width, metal layer, horizontal or vertical center line and direction of the wiring line of the pins to obtain multiple grouping results with different grouping numbers, and selecting the grouping result with the least number of groupings as the final grouping result of the at least one signal line network; generating a trunk wiring model of the at least one signal line network based on the final grouping result, the trunk wiring model including the differential pair logic structure and the wiring trunk; and connecting the pins in the trunk wiring model to the wiring trunk closest to the pins based on the principle of closest distance.

Description

Technical Field

[0001] The present application relates to the technical field of wiring design of very large scale integrated circuits (VLSI), and more specifically, to a line length matching method based on trunk wiring. Background Art

[0002] Differential logic is a common structure in analog circuits and requires a high degree of matching. Matching not only requires matching of components but also matching of signal lines is crucial.

[0003] Differential signaling is increasingly used in high-speed circuit design, such as USB, HDMI, PCI, and DDR4 / DDR5. The key advantages of differential lines carrying these signals include strong interference immunity, effective EMI suppression, and precise timing alignment. Because the signals transmitted via these lines operate at high frequencies, the lengths of the two differential lines must be closely matched. Length mismatches can generate common-mode noise and radiation, and severe mismatches can also cause jitter and unpredictable timing issues. For example, a 6.25Gbps differential signal has a symbol duration of only 160ps, while signals on microstrip lines in FR4 PCBs travel at approximately 180ps per inch. Therefore, a 50mil routing difference can result in approximately 9ps of timing skew. Therefore, a 50mil uncoupled length, acceptable for low-frequency differential routing, can cause timing issues in designs exceeding 5Gbps. Maintaining strict length matching is a paramount requirement for high-speed differential routing.

[0004] Differential pair routing is a technique that creates a balanced transmission system for differential signals (signals of equal and opposite phases) on a printed circuit board (PCB). Previous differential pair routing methods have focused on component matching while neglecting line matching. During layout design, it's common to find that signal line endpoints are blocked by other signal lines when connecting to each other, resulting in unequal signal line lengths. As manufacturing processes become increasingly precise, line matching is becoming increasingly important. To achieve optimal circuit matching, not only must component matching be ensured, but signal line matching must also be considered. Signal line length and width are the primary considerations for matching. Summary of the Invention

[0005] Technical problem to be solved by the invention

[0006] This application is completed in view of the above-mentioned problems. This application implements a method for automatically matching the length of differential logic signal line networks during the detailed wiring process of ultra-large-scale integrated circuits. It aims to solve the problem of matching the connection lengths of single signal line networks or multiple signal line networks, and uses an automated algorithm to match the lengths of qualified signal line networks, thereby improving matching performance, shortening the design and manufacturing cycle of chips, and saving costs.

[0007] According to the first aspect of the present application, an automatic line length matching method based on trunk wiring is provided, comprising: initializing wiring resources for at least one signal line network of a differential pair logic structure in a circuit layout; grouping multiple pins in the at least one signal line network according to the horizontal or vertical center line of the pins and the direction of the wiring line to obtain multiple grouping results with different grouping numbers, and selecting the grouping result with the least number of groupings as the final grouping result of the at least one signal line network; generating a trunk wiring model of the at least one signal line network based on the final grouping result, the trunk wiring model including a differential pair logic structure and a wiring trunk; and connecting the pins in the trunk wiring model to the wiring trunk closest to the pins based on the principle of closest distance.

[0008] In one implementation, the method further includes grouping the plurality of pins in the at least one signal line net based on the length, width, and metal layer of the pins in the at least one signal line net.

[0009] In one implementation, a group of pins obtained by grouping pins according to the horizontal center lines of the pins in the at least one signal line network are connected to the same wiring trunk, or a group of pins obtained by grouping pins according to the vertical center lines of the pins in the at least one signal line network are connected to the same wiring trunk.

[0010] In one implementation, it also includes: determining whether the topological structures of the pin groups of multiple signal line networks of the differential pair logic structure in the layout are the same; when it is determined that the topological structures of the pin groups of the multiple signal line networks are the same, merging different pin groups of the multiple signal line networks into one pin group, wherein the same topological structures of the pin groups of the multiple signal line networks refer to the same length, width, metal layer and horizontal line or vertical center line of the pin, as well as the same metal layer and direction of the wiring line.

[0011] In one implementation, based on the formula: Calculate multiple boundary values ​​of different wiring directions of a merged pin group, where n represents the number of pins in the merged pin group, path represents the connected signal line network, and via represents the through hole between the signal line network and the trunk. Set the boundary corresponding to the maximum boundary value among the calculated multiple boundary values ​​as the longest boundary, and extend each path of the merged pin group to the longest boundary.

[0012] According to a second aspect of the present application, an automatic line length matching device based on trunk wiring is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the automatic line length matching method based on trunk wiring is executed.

[0013] According to a third aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that when the computer program is run, the above-mentioned automatic line length matching method based on trunk wiring is executed.

[0014] Effects of the Invention

[0015] Through this application, an automated algorithm is used to match the lengths of qualified signal line networks, which can optimize wiring matching performance, effectively enhance the signal line network matching performance of the differential structure, shorten the design and manufacturing cycle of the chip, and save costs.

[0016] Other features and advantages of the present application will be set forth in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of an analog circuit including a differential pair logic structure (device) obtained according to an embodiment of the present application.

[0018] Figure 2 is a schematic diagram of a layout of an analog circuit according to an embodiment of the present application.

[0019] Figure 3 is a schematic diagram of a signal line network according to an embodiment of the present application.

[0020] Figure 4 Schematic diagram of the pin topology of the signal line network according to an embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of generating a wiring model by performing trunk wiring on each signal line network according to an embodiment of the present application.

[0022] Figure 6 It is a schematic diagram of single signal grouping according to an embodiment of the present application.

[0023] Figure 7 This is a schematic diagram of the trunk wiring of a single signal line network pin group according to the implementation method of the present application.

[0024] Figure 8 This is a schematic diagram of merging pin groups of different signal line networks with the same topology according to an embodiment of the present application.

[0025] Figure 9 This is a schematic diagram of extending the length of a wiring line to a boundary based on a calculated longest boundary value according to an embodiment of the present application.

[0026] Figure 10-12 This is a specific example of line length matching based on trunk wiring according to the embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0028] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0029] For ease of explanation, the terms commonly used in this application are first introduced.

[0030] Schematic: A diagram showing the principle of connection between components on a circuit board (e.g. Figure 1 shown).

[0031] Layout: This refers to the physical implementation of a schematic. Circuit design and chips are connected through the layout, and the layout is the concrete manifestation of the circuit. Specifically, the layout is a diagram of the actual component placement and wiring, created based on the schematic, for use in the production of actual circuit boards. Before the actual circuit board is manufactured, a schematic drawing must be created based on the schematic. The layout is then used for production, and components are installed to create the actual circuit board, commonly known as a printed circuit board (PCB).

[0032] Signal line net: It is composed of multiple pins. In the layout, the pins are usually rectangular strips with a metal layer.

[0033] Routing circuit connections: In a layout, this refers to connecting pins within the same signal net. For example, connecting different pins within a signal net. In this article, the pattern connecting different pins is called a path, and path length matching refers to matching the path lengths.

[0034] Trunk routing: refers to connecting the pins of a signal net to the trunk. The trunk is also a pin in the physical circuit. For example, trunk routing includes connecting pins a1, b1, and c1 of the signal net 1 to trunk d1. Note that pins between different signal nets cannot be connected, otherwise a short circuit will be formed, such as Figure 3 shown.

[0035] For differential pair logic structures in analog circuits, performing device and line matching can enhance anti-interference capabilities, strengthen current collection capabilities, and thus enhance circuit performance. The following details the automatic line length matching method based on trunk wiring in this application for differential pair logic structures.

[0036] The automatic line length matching method based on trunk wiring in this application specifically includes the following steps:

[0037] S1: Generate differential pair logic structure based on integrated circuit layout

[0038] Get the schematic diagram of the integrated circuit (such as Figure 1 The schematic diagram of the integrated circuit is converted into a layout using a device generation tool of an EDA (such as Cadence), and the layout and the attribute information of the layout are stored in a database or memory. The attribute information of the layout includes information such as the geometric figures, topological relationships, circuit structures, and hierarchies in the layout. Then, based on the layout and the attribute information of the layout, the device matching function of the EDA is used to perform device matching on the differential logic in the layout of the analog circuit to obtain a differential pair logic structure (such as Figure 2 shown).

[0039] In one implementation, a differential pair logic structure, such as an inverter, is obtained by performing device matching based on an integrated circuit layout. It is understood that the differential pair logic structure inverter obtained in the above manner is limited to an inverter, and any desired differential pair logic structure can be generated based on an integrated circuit layout.

[0040] S2: Initialize routing resources for at least one signal net of the differential pair logic structure in the layout

[0041] The process of initializing wiring resources includes automatically configuring wiring process data, such as design rules, wiring constraints, available wiring layers, vias and other basic data; obtaining signal line nets and wiring parameters, etc.

[0042] In one implementation, routing constraints include, for example, the width of the line, the spacing between different lines in the same signal line network (routing spacing); routing parameters include the position of the pin in the layout, the metal layer of the pin, the size of the pin, etc.

[0043] In one implementation, data such as process data, signal line nets, and wiring parameters are extracted based on a database or memory of a local computer.

[0044] In one implementation, the user inputs process data, signal line network, wiring parameters and other data through an input interface.

[0045] In one implementation, wiring resources including process data, signal line nets, and wiring parameters are obtained from a server. The server can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud storage, and network services.

[0046] like Figure 3 As shown in the figure, signal line net 1 is composed of multiple pins with metal layers, namely a1, b1, c1, and d1; signal line net 2 is composed of multiple pins with metal layers, namely a2, b2, c2, and d2. Among them, d1 and d2 are also called wiring trunks.

[0047] S3: After initializing the wiring resources in step S2, trunk wiring is performed on at least one signal line network and wiring data information is stored.

[0048] The wiring data information includes: the length, width, metal layer, horizontal or vertical center line of the wiring pin, the direction of the wiring line and the metal layer.

[0049] like Figure 4 As shown, in the stored wiring data information, the length and width of the pin refer to the length and width of the rectangular area occupied by the pin, respectively; the metal layer refers to the metal layer used in the rectangular area occupied by the pin, generally copper wire, tinned copper wire or tinned iron wire; the horizontal center line of the pin refers to the center line of the horizontal direction of the rectangular area occupied by the pin, and the vertical center line of the pin refers to the center line of the vertical direction of the rectangular area occupied by the pin.

[0050] Routing directions include four directions: North, South, West, and East. In one implementation, the center point of the intersection of the routing line and the rectangular area occupied by the pin is defined as the starting point, and the center point of the intersection of the routing line and the trunk is defined as the ending point. The routing direction is calculated according to the following rules: Let the starting point be bSpoint = (x0, y0), and the ending point be eSpoint = (x1, y1), where x0 and x1 represent the horizontal coordinates of the starting and ending points, respectively; y0 and y1 represent the vertical coordinates of the starting and ending points, respectively.

[0051] Set the horizontal coordinate of the starting point to be the same as that of the ending point, that is, bSpoint.x0 is equal to eSpoint.x1;

[0052] If bSpoint.y0<=eSpoint.y1, the direction of the routing line is north;

[0053] If bSpoint.y0>eSpoint.y1, the direction of the routing line is south;

[0054] Set the vertical coordinate of the starting point to be the same as the vertical coordinate of the ending point, that is, bSpoint.y0 is equal to eSpoint.y1;

[0055] If bSpoint.x0<=eSpoint.x1, the direction of the routing line is east;

[0056] If bSpoint.x0>eSpoint.x1, the direction of the routing line is west.

[0057] S4: Based on the wiring data information stored in step S3, length matching of the wiring lines of the signal line net is performed.

[0058] In one implementation, each signal line network is routed sequentially through step S3 to generate a routing model, such as Figure 5 As shown, the wiring model includes: (1) differential pair logic structure; (2) wiring trunk. As mentioned above, the differential pair logic structure is an analog circuit device generated by an EDA tool and matched, and the wiring trunk is a trunk generated by the EDA tool in the upper / lower channels of the matched differential pair logic structure.

[0059] Based on the above wiring model, the length matching of the wiring lines of the signal line network implemented in this application is mainly to connect the pins on the differential pair logic structure (device) and the trunks on the upper / lower channels so that the lengths of the connected wiring lines are matched.

[0060] In one implementation, the steps of the line length matching method for trunk cabling are as follows:

[0061] S31) Grouping the pins of the single signal line net, and performing trunk routing on the single signal line net by selecting the grouping result with the least number of groups according to the greedy algorithm.

[0062] In this application, the pins of a single signal line network are grouped based on their length, width, metal layer, and horizontal center line (or vertical center line).

[0063] In one implementation, if the length, width, metal layer, and horizontal center line (or vertical center line) of the pins of a single signal line net are all the same, they are grouped together.

[0064] like Figure 6 As shown, for example, for the first single signal line net 1, the pins in the first single signal line net 1 are divided into 4 groups based on their length, width, and metal layer, and grouped by the horizontal center line of the pins; the pins are divided into 8 groups based on their length, width, metal layer, and grouped by the vertical center line of the pins; and according to the greedy algorithm, the pins of the first single signal line net 1 are grouped by selecting the group with the smallest number of groups as the grouping condition. Here is a brief introduction to the basic idea of ​​the greedy algorithm: 1. Establish a mathematical model to describe the problem. 2. Divide the problem to be solved into several sub-problems. 3. Solve each sub-problem to obtain the local optimal solution of the sub-problem. 4. Combine the local optimal solutions of the sub-problems into a solution to the original problem.

[0065] Similarly, for other second single signal line nets net2, similar pin grouping processing is performed according to the above grouping rules.

[0066] As above, this application selects the result of grouping according to the horizontal center line of the pins based on the greedy algorithm ( Figure 6 , divided into 4 groups) to perform backbone wiring for the single signal line network.

[0067] During trunk wiring, the pins of the first single signal line net 1, which are grouped at least by the horizontal center lines of the pins, are connected to the same trunk to perform line length matching.

[0068] like Figure 7 As shown in the figure, the pins of single signal net 1 are divided into pin group 1 and pin group 2. Pin group 1 is connected to the upper trunk, and pin group 2 is connected to the lower trunk. The pin group is connected to the nearest trunk based on the distance between the pins and the trunk.

[0069] S32) Multi-signal line network grouping

[0070] For multiple signal line nets, the pin groups of different signal line nets are merged based on whether the pin group topology structure of each signal line net (pin length, width, metal layer, horizontal center line or vertical center line of the pin, metal layer and line direction of the wiring line) is the same.

[0071] The conditions for the same pin group topology structure of each signal line network are: the same pin group (that is, the length, width, metal layer and horizontal or vertical center line of the pin are the same), and the metal layer and direction of the wiring line are the same.

[0072] like Figure 8As shown, the pin group topology structures of the first single signal line net net1 and the second single signal line net net2 are the same, so the first pin group group1 of the first single signal line net net1 and the first pin group group1 of the second single signal line net net2 are merged into one pin group.

[0073] Based on the pin group after merging multiple single signal nets, the longest boundary value L of the merged pin group is calculated according to the wiring line direction, and the length of the line is extended to the boundary.

[0074] For the merged pin group, based on different line directions: North, South, West, East, use Calculate the longest boundary value L, where n represents the number of pins in the pin group, path represents the connected signal line net, and via represents the through hole between the signal line net and the trunk. For example, for a pin group with a line direction of north, via Calculate the boundary values, where yt represents the y coordinate of the area where the routing line and the via are located. Based on different routing directions, the calculated boundary values ​​are yt (North), yb (South), xr (East), and xl (West). Figure 9 In the example, the route extension direction is North and South. Based on the different routing directions, the longest boundary value L is selected from the calculated boundary values ​​yt(North), yb(South), xr(East), and xl(West), and the route length is extended to the boundary.

[0075] The following is based on Figure 10-12 , specifically describes the line length matching method based on trunk wiring in this application.

[0076] like Figure 10 After the initialization of the wiring resources is completed, there are two single signal line nets in the circuit layout: the first single signal line net net1 and the second single signal line net net2; the pins of the first single signal line net net1 are a1, b1, c1, d1, e1, and f1, and the pins of the second single signal line net net2 are a2, b2, c2, d2, e2, and f2; the trunk of the first single signal line net net1 is set to e1 and f1, and the trunk of the second single signal line net net2 is set to e2 and f2.

[0077] First, group the pin groups of the first single signal line net, net1, and the second single signal line net, net2. As mentioned above, this application can group the pins of different signal line nets based on the same length, width, metal layer, and horizontal or vertical centerline of the pins. The grouping results for the first single signal line net, net1, are: net1Group1 = {a1, b1}, net1Group2 = {c1, d1}; the grouping results for the second single signal line net, net2, are: net2Group1 = {a2, b2}, net2Group2 = {c2, d2}. The backbone of the first single signal line net, net1, is T1 = {e1, f1}, and the backbone of the second single signal line net, net2, is T2 = {e2, f2}.

[0078] Perform trunk wiring for the first single signal line net1 and the second single signal line net2 respectively, according to the principle of the shortest distance from the pin to the trunk, such as Figure 11 As shown in the figure, the pins in net1Group1 are connected to trunk e1, and the pins in net1Group2 are connected to trunk f1. The relevant information of the lines is recorded. Similarly, the pins in net2Group1 are connected to trunk e2, and the pins in net2Group2 are connected to trunk f2.

[0079] Grouping of multiple signal nets: Merge the pin groups of different signal nets based on whether their topological structures (length, width, metal layer, horizontal or vertical center line of the pins, metal layer and direction of the wiring lines) are the same. Figure 12 As can be seen, the pin lengths, widths, metal layers, horizontal centerlines of the pins, and metal layers and directions of the routing lines in net1Group1 and net2Group1 are the same, so they are grouped together as Group1. Similarly, net1Group2 and net2Group2 are grouped together as Group2.

[0080] Line length matching: According to the direction of the wiring line, calculate the longest boundary value L and extend it. Figure 12 As can be seen, the routing direction of group 1 is North, and the routing direction of group 2 is South. Therefore, the routing in group 1 extends upward to the longest boundary value, and the routing in group 2 extends downward to the boundary value.

[0081] This application's automatic line length matching method based on trunk routing first groups the pins of a single signal line net of a matching device (differential pair logic structure), ensuring that the lines are connected to the same trunk and that the topology is as similar as possible, thereby improving the matching of the signal line nets. Secondly, multiple signal line nets are further grouped based on the topology to ensure line matching between different signal line nets. Finally, the matching signal line nets are extended in a certain direction to enhance the matching of the differential pair logic structure. For a differential pair logic structure, the user only needs to enter one or more signal line nets, and the method described in this application automatically performs trunk routing and matches the line lengths of the signal line nets.

[0082] Through this application, an automated algorithm is used to match the lengths of qualified signal line networks, which can optimize wiring matching performance, effectively enhance the signal line network matching performance of the differential structure, shorten the design and manufacturing cycle of the chip, and save costs.

[0083] In a second aspect of the present application, an automatic line length matching device based on trunk wiring is also provided, comprising a memory and a processor. A computer program is stored in the memory, and when the computer program is executed by the processor, the method described above can be executed.

[0084] The processor described in this application may be a newly designed one or an improved one of the processing units of an existing processor. The types of existing processing units may include, but are not limited to, a central processing unit (CPU), a digital signal processing unit (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, and may also include a microprocessor or a processing unit of other conventional processors.

[0085] The memory of the automatic line length matching device based on trunk wiring can be used to store program instructions that can be executed by the processor (such as application programs, drivers, and even operating system program instructions). The processor used to execute the above method is configured to implement the above method by executing the computer program stored in the memory.

[0086] The present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above method are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0087] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An automatic line length matching method based on trunk wiring, characterized in that: include: Initializing routing resources for at least one signal net of a differential pair logic structure in a circuit layout; Grouping multiple pins in at least one signal line net according to horizontal or vertical center lines of the pins and directions of routing lines to obtain multiple grouping results with different numbers of groups, and selecting the grouping result with the least number of groups as the final grouping result of the at least one signal line net; generating a trunk wiring model of at least one signal line net based on the final grouping result, wherein the trunk wiring model includes a differential pair logic structure and a wiring trunk; as well as Based on the principle of closest distance, the pins in the trunk wiring model are respectively connected to the wiring trunk closest to the pins.

2. The automatic line length matching method based on trunk wiring according to claim 1, characterized in that: Also includes: The plurality of pins in the at least one signal line net are grouped based on the length, width, and metal layer of the pins in the at least one signal line net.

3. The automatic line length matching method based on trunk wiring according to claim 1, characterized in that: A group of pins obtained by grouping the pins according to the horizontal center lines of the pins in the at least one signal line network are connected to the same wiring trunk, or a group of pins obtained by grouping the pins according to the vertical center lines of the pins in the at least one signal line network are connected to the same wiring trunk.

4. The automatic line length matching method based on trunk wiring according to claim 1, characterized in that: Also includes: Determine whether the topological structures of the pin groups of multiple signal line networks of the differential pair logic structure in the circuit layout are the same. When it is determined that the topological structures are the same, merge the different pin groups of the multiple signal line networks into one pin group, wherein the topological structures of the pin groups of the multiple signal line networks are the same means that the length, width, metal layer and horizontal line or vertical center line of the pin, as well as the metal layer and direction of the wiring line are the same.

5. The automatic line length matching method based on trunk wiring according to claim 4, characterized in that: Based on the formula: Calculate multiple boundary values ​​of different wiring directions of a merged pin group, where n represents the number of pins in the merged pin group, path represents the connected signal line network, and via represents the through hole between the signal line network and the trunk. Set the boundary corresponding to the maximum boundary value among the multiple boundary values ​​as the longest boundary, and then extend each path of the merged pin group to the longest boundary.

6. An automatic line length matching device based on trunk wiring, characterized in that: The invention comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the automatic line length matching method based on backbone wiring according to any one of claims 1 to 5 is executed.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is run, the automatic line length matching method based on backbone wiring according to any one of claims 1 to 5 is executed.

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