A wiring method for quickly connecting MOS pins and input / output pins

Abstract

A wiring method for quickly connecting MOS pins and input / output pins includes the following steps: obtaining the center point coordinates of the input / output pins and the MOS pins, calculating the closest input / output pins and MOS pins; determining whether there is an overlapping area between the closest input / output pins and the MOS pins; if there is an overlapping area, using the center of the overlapping area as the wiring position, and connecting the closest input / output pins and the MOS pins through direct wiring according to a preset wiring layer and wiring width; if there is no overlapping area, connecting the closest input / output pins and the MOS pins through L-shaped wiring according to a preset wiring layer and wiring width. The present invention selects a direct connection or L-shaped wiring mode based on whether there is an overlapping area in the projections of the closest pair of I / O pins and MOS pins in the X and Y directions, thereby quickly completing the wiring of the specified unit and improving the efficiency of layout design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a wiring method for quickly connecting MOS pins and input / output pins. Background Art

[0002] Traditionally, integrated circuit layouts rely primarily on manual design. With the advancement of process nodes and the increase in design complexity, the scale of integrated circuit layouts has become increasingly large. If layouts are still designed purely by hand, it will consume a significant amount of time and effort, reducing design efficiency. To further improve layout design efficiency and allow engineers to focus more on creative design, computer-aided design technology is indispensable.

[0003] In some analog circuit layout design scenarios, I / O pins (input / output pins) need to connect to the various terminals (source, drain, and gate) of the surrounding MOS transistors. When routing, it is important to consider design rules and keep the routing as neat and aesthetically pleasing as possible.

[0004] Currently, MOS pins (MOS pins) and I / O pins (input / output pins) can only be routed manually. When multiple I / O cells and MOS cells are arranged in an array, a large number of MOS cells and I / O cells need to be routed. Manual routing is inefficient and requires a lot of time and effort. Summary of the Invention

[0005] In order to address the defects of the prior art, the purpose of the present invention is to provide a wiring method for quickly connecting MOS pins and input / output pins. According to whether there is an overlapping area in the projection of the closest pair of I / O Pins and MOS Pins in the X and Y directions, a direct connection or L-shaped wiring mode is selected, so that the wiring of the specified cell can be quickly completed with the help of EDA tools, saving time and improving layout design efficiency.

[0006] To achieve the above objectives, the present invention provides a wiring method for quickly connecting MOS pins and array I / O pins, comprising the following steps:

[0007] Get the center coordinates of the input / output pins and MOS pins, and calculate the closest input / output pins and MOS pins;

[0008] Determine whether there is an overlapping area between the input / output pin and the MOS pin that is closest to each other;

[0009] If there is an overlapping area, the center of the overlapping area is used as the wiring position, and a direct wiring is performed to connect the input / output pin and the MOS pin that are closest to each other according to the preset wiring layer and wiring width;

[0010] If there is no overlapping area, L-shaped wiring is performed to connect the input / output pin and the MOS pin that are closest to each other according to the preset wiring layer and wiring width.

[0011] Furthermore, the input / output pins or the MOS pins are arranged in an array.

[0012] Furthermore, the step of determining whether there is an overlapping area between the closest input / output pin and the MOS pin further includes: projecting the closest input / output pin pattern and the MOS pin pattern in the X direction and the Y direction, respectively, to determine whether there is an overlapping area between the MOS pin and the input / output pin.

[0013] Furthermore, if there is no overlapping area, the step of connecting the closest input / output pin and the MOS pin through L-shaped wiring according to a preset wiring layer and wiring width further includes:

[0014] Selecting the boundary closest to the MOS pin on the input / output pin pattern, and offsetting the boundary inward by half the wiring width as the first outlet position;

[0015] Determine the first outgoing line direction according to the relationship between the horizontal length and the vertical length of the input / output pin pattern;

[0016] Any position on the MOS pin pattern is used as the second outgoing line position, and a direction perpendicular to the first outgoing line direction is used as the second outgoing line direction;

[0017] According to the preset wiring layer and wiring width, a first wiring is performed from the first outlet position along the first outlet direction to the MOS pin, and a second wiring is performed from the second outlet position along the second outlet direction to the input / output pin. The first wiring is connected to the second wiring to form an L-shaped wiring pattern.

[0018] Furthermore, the step of determining the first outlet direction based on the size relationship between the horizontal length and the vertical length of the input / output pin pattern includes: comparing the horizontal length and the vertical length of the input / output pin pattern; if the horizontal length is greater than or equal to the vertical length, determining that the first outlet direction is the vertical direction; otherwise, determining that the first outlet direction is the horizontal direction.

[0019] Furthermore, the method further includes: determining whether the input / output pin and the MOS pin are perpendicular to each other; if so, taking the center of the MOS pin pattern as the second outlet position.

[0020] Furthermore, the step of selecting the boundary on the input / output pin pattern closest to the MOS pin includes: calculating the distance between the midpoint of each boundary on the input / output pin pattern and the center point of the MOS pin pattern, and selecting the boundary where the midpoint of the boundary with the smallest distance is located.

[0021] Furthermore, it also includes: after the wiring is completed, all objects connected by the wiring are obtained according to the connectivity relationship; it is determined whether all the objects belong to the pin graphics to be connected in this wiring or the physical graphic lines and logical path segments created during the wiring process. If any object does not belong, it is considered that a short circuit has occurred in the result of this wiring.

[0022] To achieve the above-mentioned objectives, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the steps of the wiring method for quickly connecting MOS pins and input / output pins as described above.

[0023] To achieve the above objectives, the present invention also provides a computer-readable storage medium, which stores at least one instruction, and the instruction is loaded and executed by a processor to implement the steps of the wiring method for quickly connecting MOS pins and input / output pins as described above.

[0024] The wiring method for quickly connecting MOS pins and input / output pins provided by the present invention has the following beneficial effects compared with the prior art:

[0025] By calculating the closest pair of input / output pins and MOS pins, and selecting the direct or L-shaped routing mode based on whether there is an overlapping area in the projection of the two in the X and Y directions, the connection is finally completed according to the direct or L-shaped routing rules. This method can simultaneously route multiple input / output pins and MOS pins in the current block (macro cell) area and supports user-defined routing layers and widths, improving layout design efficiency while also enhancing ease of use.

[0026] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0028] Figure 1 Flowchart of a wiring method for quickly connecting a MOS Pin and an I / O Pin according to an embodiment of the present invention;

[0029] Figure 2 Schematic diagram of the closest I / O Pin and MOS Pin according to an embodiment of the present invention;

[0030] Figure 3 Schematic diagram showing that there is no overlapping area between the projections of the I / O Pin and the MOS Pin in the X direction and the Y direction according to an embodiment of the present invention;

[0031] Figure 4 Schematic diagram showing overlapping areas of projections of I / O Pins and MOS Pins in the X and Y directions according to an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of direct connection wiring between I / O Pin and MOS Pin according to one embodiment of the present invention;

[0033] Figure 6 Schematic diagram of direct connection wiring between I / O Pin and MOS Pin according to another embodiment of the present invention;

[0034] Figure 7 Schematic diagram of L-shaped connection between I / O Pin and MOS Pin according to one embodiment of the present invention;

[0035] Figure 8 Schematic diagram of L-shaped connection between I / O Pin and MOS Pin according to another embodiment of the present invention;

[0036] Figure 9 Schematic diagram of L-shaped connection between I / O Pin and MOS Pin according to another embodiment of the present invention;

[0037] Figure 10 Schematic diagram of a MOS Pattern PR wiring window according to an embodiment of the present invention;

[0038] Figure 11 A schematic diagram of a wiring result for quickly connecting an array MOS Pin and an I / O Pin according to an embodiment of the present invention;

[0039] Figure 12 FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0041] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0042] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0043] It should be noted that the concepts of "first" and "second" may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0044] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more". "Plurality" should be understood as two or more.

[0045] In an embodiment of the present invention, a wiring method for quickly connecting a MOS pin (MOS Pin) and an input / output pin (I / OPin) is provided, comprising:

[0046] Find the nearest I / O pin and MOS pin for connection;

[0047] Choose direct wiring or L-shaped wiring based on whether there is an overlapping area between the nearest I / O pin and the MOS pin.

[0048] If there is an overlapping area, use the midpoint of the overlapping area as the routing point and directly connect the I / O pin and MOS pin.

[0049] If there is no overlapping area, a line will be routed from the MOS Pin using the user-set Width and Layer. The I / O Pin's line position will be offset inward by Width / 2 (Width is the user-set line width) from the closest boundary on the I / O Pin graphic to the MOS Pin. The line direction will be determined based on the relationship between the horizontal and vertical lengths of the I / O Pin, and L-shaped routing will be performed between the MOS Pin and the I / O Pin.

[0050] Figure 1 The following is a flow chart of a wiring method for quickly connecting MOS Pin and I / O Pin according to an embodiment of the present invention. Figure 1 The embodiments of the present invention will be described in detail.

[0051] In step 101, the closest I / O Pin and MOS Pin are calculated.

[0052] In this embodiment, the center point coordinates of the corresponding I / O Pin and MOS Pin are obtained according to the I / O Pin Name and MOS Pin Name input by the user, and the closest I / O Pin and MOS Pin are calculated based on the center point coordinates for connection.

[0053] Figure 2 Schematic diagram of the closest I / O Pin and MOS Pin according to an embodiment of the present invention, as shown in FIG. Figure 2 As shown, calculate the distance between pin 1 in the I / O Pin and pins 2 to 5 in the MOS Pin. Pin 1 and pin 2 are the closest I / O Pin and MOS Pin, and will be used for connection, that is, routing the nearest I / O Pin and MOS Pin.

[0054] In step 102 , it is determined whether there is an overlapping area between the projections of the closest I / O Pin and MOS Pin in the X direction and the Y direction.

[0055] In this embodiment, the pin pattern of the closest I / O pin or MOS pin is projected in the X-direction (or horizontal direction) and the Y-direction (or vertical direction) to see if there is any overlap with the other pin pattern after projection. (This can also be understood as extending the pin pattern and observing whether there is any overlap with the other pin pattern after projection).

[0056] Figure 3 Schematic diagram showing that there is no overlapping area between the projections of the I / O Pin and the MOS Pin in the X direction and the Y direction according to an embodiment of the present invention. Figure 3As shown in the figure, the I / O pin is projected horizontally and vertically, and the projection trajectory does not intersect with the MOS pin. That is, there is no overlapping area between the projections of the I / O pin and the MOS pin in the X direction and the Y direction. Figure 4 FIG. 1 is a schematic diagram showing an overlapping area of ​​the projections of the I / O Pin and the MOS Pin in the X direction and the Y direction according to an embodiment of the present invention. Figure 4 As shown, the MOS Pin is projected in the horizontal and vertical directions, and its projection in the vertical direction overlaps with the I / O Pin in area A, that is, the projections of the I / O Pin and the MOS Pin in the Y direction overlap.

[0057] In step 103, if there is an overlapping area, a direct connection is made to the I / O Pin and the MOSPin using the midpoint of the overlapping area as the outgoing line position.

[0058] In this embodiment, when the I / O Pin and the MOS Pin are projected in the X direction and the Y direction and it is determined whether there is an overlapping area between the two, the situation of the overlapping area may be different. Figure 4 If we use the projection of the I / O pin in the Y direction to judge, the overlapping area is located on the MOS pin, and the overlapping area is the MOS pin itself.

[0059] It should be noted that no matter whether the overlapping area is located on the I / O Pin pattern or the MOS Pin pattern, the direct wiring pattern made based on the center of the overlapping area is consistent. The following describes the direct wiring using the former overlapping area as an example.

[0060] Figure 5 FIG. 1 is a schematic diagram of direct connection wiring between I / O Pin and MOS Pin according to an embodiment of the present invention. Figure 5 As shown in the figure, there is an overlapping area between the I / O pin and the MOS pin (located on the I / O pin). The midpoint of the overlapping area is the outlet position, that is, the midpoint of the overlapping area is located on the center line of the outlet pattern. According to the routing layer (Layer) and routing width (Width) set by the user, a direct connection is made to the MOS pin to connect the I / O pin and the MOS pin.

[0061] Figure 6 FIG. 1 is a schematic diagram of direct connection wiring between I / O Pin and MOS Pin according to another embodiment of the present invention. Figure 6As shown, there is an overlap area between the I / O pin and the MOS pin (taking the overlap area on the I / O pin as an example). The horizontal width of this overlap area is L. The center of this overlap area is the lead-out point. If a direct connection is made between the I / O pin and the MOS pin, the distance between the center of the lead-out point and the left edge of the MOS pin graphic is L / 2, and the distance between the center of the lead-out point and the right edge of the I / O pin graphic is also L / 2.

[0062] In step 104 , if there is no overlapping area, L-shaped wiring is performed between the I / O pin and the MOS pin.

[0063] In this embodiment, the I / O pin and MOS pin do not overlap. The I / O pin's closest boundary to the MOS pin (the midpoint of this boundary is closest to the MOS pin) is selected and offset inward by Width / 2 (where Width is the user-set routing width) from this boundary as the I / O pin's exit position (i.e., where the centerline of the exit pattern passes). The exit direction is determined based on the relationship between the I / O pin's horizontal and vertical lengths. If the horizontal length of the I / O pin's graphic is greater than or equal to the vertical length, the exit direction from the I / O pin is vertical; otherwise, the exit direction is horizontal. The MOS pin exits according to the user-set Width and Layer, and the MOS pin's exit direction is perpendicular to the I / O pin's exit direction.

[0064] In step 105 , it is determined whether the I / O Pin and the MOS Pin without any overlapping area are perpendicular to each other.

[0065] In this embodiment, if the horizontal length (or width) of the pin pattern is greater than or equal to its vertical length (or height), the pin orientation is horizontal; otherwise, the pin orientation is vertical. By comparing the horizontal and vertical lengths of the I / O pin and the MOS pin, if they are the same, the I / O pin and the MOS pin have the same orientation, meaning they are parallel to each other; otherwise, they are perpendicular to each other.

[0066] In step 106 , if there is no overlapping area where the pin directions of the I / O pin and the MOS pin are not perpendicular, the line direction of the MOS pin is the same as the pin direction.

[0067] Furthermore, a center line of the MOS Pin's outgoing wire pattern in the outgoing wire direction coincides with a center line of the MOS Pin in the pin direction.

[0068] Figure 7 Schematic diagram of L-shaped connection between I / O Pin and MOS Pin according to one embodiment of the present invention. Figure 7As shown, the horizontal length of the I / O pin graphic is greater than its vertical length, and the horizontal length of the MOS pin is also greater than its vertical length. This means that the pins of the I / O and MOS pin graphics are both horizontal and not perpendicular to each other. In this case, the I / O pin's lead is oriented vertically, with the lead being located at a point on the I / O pin graphic closest to the MOS pin, indented by Width / 2. An L-shaped connection is made to the MOS pin. The MOS pin leads horizontally, using the user-defined Width and Layer settings. Its lead pattern connects to the I / O pin's lead pattern, forming an L-shaped connection.

[0069] Figure 8 FIG. 1 is a schematic diagram of an L-shaped connection between an I / O Pin and a MOS Pin according to another embodiment of the present invention. Figure 8 As shown, the horizontal length of the I / O pin is shorter than its vertical length, and the horizontal length of the MOS pin is also shorter than its vertical length. That is, the I / O pin and the MOS pin are both oriented vertically and parallel to each other. Therefore, the I / O pin's trace is located at a point inward by Width / 2 from the closest boundary of the I / O pin graphic to the MOS pin, extending horizontally toward the MOS pin. The MOS pin's trace is also oriented vertically, the same as the MOS pin's, and extends toward the I / O pin using the user-defined Width and Layer, forming an L-shaped trace between the I / O pin and the MOS pin.

[0070] In step 107 , if there is no overlapping area and the pin directions of the I / O pin and the MOS pin are perpendicular to each other, the line direction of the MOSPin is perpendicular to its pin direction, and its line position is the center of the MOS Pin pattern.

[0071] Figure 9 FIG. 1 is a schematic diagram of an L-shaped connection between an I / O Pin and a MOS Pin according to another embodiment of the present invention. Figure 9 As shown, the horizontal length of the I / O pin is greater than its vertical length (i.e., the I / O pin's pin orientation is horizontal), while the horizontal length of the MOS pin is less than its vertical length (i.e., the MOS pin's pin orientation is vertical). The I / O and MOS pins are perpendicular to each other. Therefore, when L-shaped routing is performed with the I / O pin's exit direction vertical and the exit position inward by Width / 2 from the edge of the I / O pin pattern closest to the MOS pin pattern, the MOS pin's exit direction is horizontal, and the centerline of the MOS pin's exit direction passes through the center of the MOS pin pattern.

[0072] The wiring method for quickly connecting MOS Pins and I / O Pins of the present invention is further explained below through an application example of the present invention.

[0073] Figure 10 Schematic diagram of Mos Pattern PR wiring window according to an embodiment of the present invention, refer to Figure 10 , set the connection parameters through the MosPattern PR wiring window, including selecting the MOS Pin and I / O Pin to be connected, setting the layer and line width, etc. The operation steps are as follows:

[0074] In step 201, open the Mos Pattern PR window in the ToolBox, click the Route button in the upper left corner of the pop-up Mos Pattern PR window to enter the routing setting interface;

[0075] In step 202, click the "+" sign in the lower right corner of the wiring setting interface to add a setting row, select the I / O Pin and MOS Pin to be connected in each row, and set the line layer and line width;

[0076] In step 203, click the Apply button in the lower right corner of the window to generate a path according to the wiring method for quickly connecting the MOS Pin and the I / O Pin as described above.

[0077] Figure 11 FIG. 1 is a schematic diagram of the wiring result of quickly connecting the array MOS Pin and the I / O Pin according to an embodiment of the present invention. Figure 11As shown, the projection of MOS Pin pattern 1102 in the Y direction overlaps with I / O Pin pattern 1101, and the projection of MOSPIn pattern 1104 in the X direction overlaps with I / O Pin pattern 1103. Direct wiring is used between I / O Pin pattern 1101 and MOSPIn pattern 1102, and between I / O Pin pattern 1103 and MOS Pin pattern 1104. There is no overlapping area between I / O Pin pattern 1105 and MOS Pin pattern 1106. They are perpendicular to each other. L-shaped wiring is used between I / O Pin pattern 1105 and MOS Pin pattern 1106, and the outlet position of MOS Pin pattern 1106 is located at the center of the pattern. I / O Pin pattern 1107 and MOS Pin pattern 1108 are parallel to each other and overlap, so direct wiring should be used. Since MOS Pin pattern 1108 coincides with the overlapping area, the center line of the direct wiring pattern just passes through the center of MOS Pin pattern 1108. The Pin patterns 1110 are parallel to each other but have no overlapping areas and are wired in an L-shaped manner.

[0078] The proposed method for quickly connecting MOS pins and I / O pins calculates the closest pair of I / O pins and MOS pins, selects a direct connection or L-shaped wiring mode based on whether there is an overlapping area between the two on the coordinate axis projection, and finally completes the connection according to the direct connection or L-shaped wiring principles provided by this method. It has the following advantages:

[0079] (1) The wiring results are neat and the style is unified;

[0080] (2) Supports user-defined wiring layers and widths, and is easy to use;

[0081] (3) This method can simultaneously complete the routing of multiple I / O Pins and MOS Pins in the current Block (macro cell) area, and can quickly complete the routing of MOS Pins and I / O Pins, thereby improving the efficiency of layout design;

[0082] (4) After routing, if a short circuit occurs with other routing objects or objects already in the layout, a pop-up window will be displayed to the user: After the routing is completed, all objects connected by this routing are obtained based on the connectivity relationship. If the obtained object does not belong to this routing, that is, it does not belong to the pin to be connected in this routing and the path (physical graphic line) and via (logical path) created during the routing process, then the result of this routing is considered to have a short circuit.

[0083] In an embodiment of the present invention, an electronic device is further provided. Figure 12FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 12 As shown, the electronic device of the present invention includes a processor 1201 and a memory 1202, wherein:

[0084] The memory 1202 stores a computer program. When the computer program is read and executed by the processor 1201 , the computer program executes the steps in the embodiment of the wiring method for quickly connecting MOS Pins and I / O Pins as described above.

[0085] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored. The computer program is configured to execute the steps of the wiring method embodiment for quickly connecting MOSPin and I / O Pin as described above when running.

[0086] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0087] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will be able to modify the technical solutions described in the foregoing embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A wiring method for quickly connecting MOS pins and input / output pins, comprising the following steps: Get the center coordinates of the input / output pins and MOS pins, and calculate the closest input / output pins and MOS pins; Determine whether there is an overlapping area between the input / output pin and the MOS pin that is closest to each other; If there is an overlapping area, the center of the overlapping area is used as the wiring position, and a direct wiring is performed to connect the input / output pin and the MOS pin that are closest to each other according to the preset wiring layer and wiring width; If there is no overlapping area, L-shaped wiring is performed to connect the input / output pin and the MOS pin that are closest to each other according to the preset wiring layer and wiring width; The step of determining whether there is an overlapping area between the closest input / output pin and the MOS pin further includes: projecting the closest input / output pin pattern and the MOS pin pattern in the X direction and the Y direction respectively to determine whether there is an overlapping area between the MOS pin and the input / output pin; If there is no overlapping area, the step of connecting the closest input / output pin and the MOS pin through L-shaped wiring according to a preset wiring layer and wiring width further includes: Selecting the boundary closest to the MOS pin on the input / output pin pattern, and offsetting the boundary inward by half the wiring width as the first outlet position; Determine the first outgoing line direction according to the relationship between the horizontal length and the vertical length of the input / output pin pattern; Any position on the MOS pin pattern is used as the second outgoing line position, and a direction perpendicular to the first outgoing line direction is used as the second outgoing line direction; According to the preset wiring layer and wiring width, a first wiring is performed from the first outlet position along the first outlet direction to the MOS pin, and a second wiring is performed from the second outlet position along the second outlet direction to the input / output pin. The first wiring is connected to the second wiring to form an L-shaped wiring pattern.

2. The wiring method for quickly connecting MOS pins and input / output pins according to claim 1, characterized in that: The input / output pins or the MOS pins are arranged in an array.

3. The wiring method for quickly connecting MOS pins and input / output pins according to claim 1, characterized in that: The step of determining the first outgoing line direction based on the relationship between the horizontal length and the vertical length of the input / output pin pattern includes: comparing the horizontal length and the vertical length of the input / output pin pattern; if the horizontal length is greater than or equal to the vertical length, determining that the first outgoing line direction is the vertical direction; otherwise, determining that the first outgoing line direction is the horizontal direction.

4. The wiring method for quickly connecting MOS pins and input / output pins according to claim 1, characterized in that: Also includes: It is determined whether the input / output pin and the MOS pin are perpendicular to each other. If they are perpendicular to each other, the center of the MOS pin pattern is used as the second outlet position.

5. The wiring method for quickly connecting MOS pins and input / output pins according to claim 1, characterized in that: The step of selecting the boundary closest to the MOS pin on the input / output pin pattern includes: calculating the distance between the midpoint of each boundary on the input / output pin pattern and the center point of the MOS pin pattern, and selecting the boundary where the midpoint of the boundary with the smallest distance is located.

6. The wiring method for quickly connecting MOS pins and input / output pins according to claim 1, characterized in that: Also includes: After the wiring is completed, all objects connected by the wiring are obtained based on the connectivity relationship; it is determined whether all the objects belong to the pin graphics to be connected in this wiring or the physical graphic lines and logical path segments created during the wiring process. If any object does not belong, it is considered that the result of this wiring has a short circuit.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is configured to execute the computer program stored in the memory to implement the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by the processor to implement the method according to any one of claims 1 to 6.

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