Synaptic array, computational circuit, and operation method for neural network learning

Abstract

The present invention discloses a synaptic array, an operation circuit, and an operation method for neural network learning, belonging to the field of neural network operation technology. The synaptic array comprises an upper and lower double-layer crossbar array structure. The upper crossbar array comprises upper basic units connected between word lines, bit lines, and word lines located on the upper layer. Each upper basic unit comprises a series-connected switch device and a fixed resistor. The lower crossbar array comprises lower basic units connected between word lines, bit lines, and word lines located on the lower layer. Each lower basic unit comprises a series-connected memristor and a transistor. Interconnect lines extend from the connection ends of the switch devices and the fixed resistors and are connected to the gates of the transistors. The conductance of each memristor is used to calculate weights. Based on the synaptic array of the present invention, neural network learning operations can be implemented without occupying a large amount of off-chip computing resources.

Description

Technical Field

[0001] The present invention belongs to the field of neural network computing technology, and more specifically, relates to a synaptic array, computing circuit and operating method for neural network learning. Background Art

[0002] An artificial neural network (ANN) utilizes a structure similar to the synaptic connections in the brain. It mimics the behavioral characteristics of animal neural networks and is a mathematical model for distributed, parallel information processing. Among the many machine learning algorithms, ANNs are widely applicable and highly robust. These networks rely on the complexity of the system to adjust the interconnections between its numerous nodes to achieve their goal of processing information.

[0003] A neural network consists of an input layer, several hidden layers, and an output layer. Each layer contains a large number of neurons, and neurons in adjacent layers are connected by synapses. Synapses are the most numerous processing elements in a neural network, and synaptic weights are important parameters for neural network training and updating. Numerous synaptic devices have been reported, including magnetic memory, phase-change memory, and memristors. Memristors are particularly promising candidates due to their non-volatility, ease of integration, low power consumption, and ability to store multiple bits of data. Furthermore, the simulated memory function of memristors is similar to that of biological synapses: their conductance can be continuously altered by applying a relatively large voltage bias, but remains constant with a small or no bias.

[0004] Supervised learning of neural networks is a very complex process, which includes steps such as forward propagation, backpropagation, and weight updating. Currently, when building hardware circuits for neural network learning operations, the synaptic arrays used are mostly single-layer structures, that is, single-layer crossbar arrays, such as CN109460817B - A convolutional neural network on-chip learning system based on non-volatile memory, which uses a single-layer crossbar array based on memristors as synaptic weights. Although this synaptic array has a simple structure, it requires a large amount of off-chip computing resources to perform error calculations and weight update calculations during the backpropagation and weight updating of supervised learning. As a result, neural network training requires a large amount of computing resources, a large amount of calculation, slow operation speed, and high power consumption. Summary of the Invention

[0005] In response to the above-mentioned defects or improvement needs of the prior art, the present invention provides a synaptic array, an operation circuit and an operation method of a neural network, the purpose of which is to achieve efficient operation of neural network learning and reduce operation power consumption.

[0006] To achieve the above objectives, according to one aspect of the present invention, a synaptic array for neural network learning is provided, characterized in that it includes:

[0007] An upper crossbar array includes N word lines sWL, M bit lines sBL, and upper basic units connected between any word line sWL and any bit line sBL, each upper basic unit including a switch device and a fixed resistor connected in series;

[0008] A lower crossbar array includes N word lines WL, M bit lines BL, and lower basic units connected between any word line WL and any bit line BL, each lower basic unit including a memristor and a transistor connected in series;

[0009] Each upper layer basic unit is connected to each lower layer basic unit in a one-to-one correspondence, and the connection method is: an interconnection line is drawn from the connection end of the switch device and the fixed resistor of the upper layer basic unit and connected to the gate of the transistor of the corresponding lower layer basic unit;

[0010] The conductance value of each memristor is used to calculate the weight between the connected word line WL and the bit line BL. During the forward propagation process, each word line WL is used to receive the emission signal of the neuron, and the bit line BL outputs the multiplication result of the emission signal and the weight matrix. The weight matrix is ​​all the weights of the synaptic array.

[0011] In one embodiment, the switching device is a threshold conversion device, a transistor or a diode.

[0012] In one embodiment, all bit lines are parallel to each other, all word lines are parallel to each other, and the word lines and bit lines intersect.

[0013] In one embodiment, the memristor is a conductive filament memristor or a phase change memory.

[0014] According to another aspect of the present invention, an operation circuit for neural network learning is provided, comprising a storage module and a synaptic array, an integration module, and a threshold comparison module located between every two adjacent layers of the neural network, wherein:

[0015] The synaptic array is the synaptic array for neural network learning. The number of bit lines BL of the previous synaptic array is the same as the number of word lines WL of the next synaptic array. The synaptic array F between the kth layer and the k+1th layer is k The word line WL receives the release signal ε of the kth layer k After that, the release signal ε is output through the bit line BL k With the weight matrix w k.k+1 The multiplication result, weight matrix w k.k+1 Synaptic array F k All weights of

[0016] The integration module is used to linearly integrate the multiplication results of the corresponding weight matrices to obtain the membrane potential y of the k+1th layerk+1 (t);

[0017] The threshold comparison module is used to compare the membrane potential y k+1 (t) and the corresponding threshold V th For comparison, when y k+1 (t)>V th When the k+1th layer sends a signal ε to the next layer k+1 ; Otherwise, no signal is issued;

[0018] The storage module is used to record the signal release time of each layer.

[0019] In one embodiment, an error calculation module is further included, which is used to calculate the error value of the output layer based on the actual output information of the output layer and the target output information.

[0020] According to another aspect of the present invention, a method for operating an arithmetic circuit for neural network learning is provided, wherein the method operates based on the arithmetic circuit for neural network learning to implement forward propagation operation and back propagation operation, wherein:

[0021] The operations to implement the forward propagation operation include:

[0022] Apply voltage to the word line sWL and the bit line sBL to ensure that all the switching devices in the upper layer are turned on, so that all the transistors in the lower layer are turned on;

[0023] The training data is input into the word line WL of the synaptic array F1 as the unit step signal emitted by the first layer until the signal is output at the output layer; the storage module is used to record the signal emission time of each layer to complete the forward propagation operation of the current round;

[0024] The operations to implement the backpropagation operation include:

[0025] Calculate the error value δ of the output layer in the current round o , so that the error value of the output layer δ o Back propagation is performed layer by layer to obtain the error value of each layer. The operation of obtaining the error value of the kth layer includes:

[0026] presynaptic signal and postsynaptic signaling One of the two is applied to the synaptic array F k The word line sWL and the other one applied to the synapse array F k bit line sBL; presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1Relative relationship of presynaptic signal and postsynaptic signaling The voltage difference can open the synaptic array F k Switching devices in;

[0027] The error value δ of the k+1th layer k+1 After scaling -β times, the input synaptic array F k The bit line BL, β is the set scaling factor, and the synaptic array F is obtained. k The word line WL outputs data as the error value δ k .

[0028] In one embodiment, a weight update operation is also included, for any synaptic array F k The weight update operation includes:

[0029] The first and second stages are divided into synaptic array F k The word line WL applies a presynaptic signal and applies a postsynaptic signal to the bit line BL Presynaptic signaling at each stage and postsynaptic signaling The polarity of the same type of signal in the two phases is opposite; in each phase, the presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1 The relative relationship between

[0030] According to the error value δ of the k+1th layer k+1 Synaptic Array F k Different refresh signals are applied to the bit line sBL and word line sWL, including:

[0031] When δ k+1 =0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned off in both the first and second phases;

[0032] When δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned off in one phase and turned on in the other phase. During the period when the transistor is turned on, the presynaptic signal overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease;

[0033] When δ k+1<0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned on in one phase and turned off in the other phase, and during the period when the transistor is turned on, the presynaptic signal of the time overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

[0034] In one embodiment, in implementing the synaptic array F k In the weight update operation,

[0035] In two stages, the synaptic array F k The word line WL applies a presynaptic signal and applies a postsynaptic signal to the bit line BL include:

[0036] In the first stage, the synaptic array F k The word line WL is applied as a positive presynaptic signal A negative postsynaptic signal is applied to the bit line BL.

[0037] In the second stage, the synaptic array F k The word line WL is applied as a negative presynaptic signal A positive postsynaptic signal is applied to the bit line BL.

[0038] According to the error value δ of the k+1th layer k+1 Synaptic Array F k Different signals are applied to the corresponding bit lines sBL and word lines sWL, including:

[0039] When δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistors are turned off in the first phase and turned on in the second phase. In the second phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease;

[0040] When δ k+1 <0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned on in the first phase and turned off in the second phase. In the first phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

[0041] In one embodiment,

[0042] When δ k+1=0, the corresponding bit line sBL and word line sWL are both low level;

[0043] When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a low level in the first stage and a high level in the second stage;

[0044] When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a high level in the first stage and a low level in the second stage.

[0045] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0046] This invention proposes a novel synaptic array comprising a double-layer crossbar array structure: the upper layer comprises word lines (SWLs), bit lines (SBLs), switches, and fixed resistors; the lower layer comprises word lines (WLs), bit lines (BLs), memristors, and transistors. Compared to traditional synaptic arrays, the present invention incorporates an upper crossbar array. By adjusting the potential difference between the word lines and bit lines in the upper crossbar array, the switching state of each switch device can be controlled, thereby controlling the on / off state of the memristor branches in the lower layer. In other words, each memristor can be controlled from two dimensions. The first dimension is the control of the lower word line and bit line, which can also adjust the voltage difference applied to the two ends of the memristor. This voltage difference determines the degree of adjustment of the memristor's conductance value; the second dimension is the control of the upper word line and bit line. In fact, the upper word line and bit line are used to control the switching device, and then control whether the lower memristor branch is turned on, thereby determining whether the error can be reversely propagated, whether the memristor can perform conductivity modulation, and controlling the duration of conductivity modulation, thereby realizing on-chip learning operations of neural networks without occupying a large amount of off-chip computing resources, improving computing speed and reducing power consumption.

[0047] Furthermore, the present invention is based on an operating method of an arithmetic circuit for neural network learning, which relies on the design of a synaptic array. The synaptic array comprises an upper crossbar array with switching devices and fixed resistors as basic units and a lower crossbar array with memristors and transistors as basic units, forming a double-layer crossbar array. The corresponding basic units in the two crossbar arrays are connected by wires; the double-layer crossbar array can realize the forward propagation, reverse propagation and weight update processes of the neural network. In the forward process, the input signal is applied to the word line of the lower crossbar array, and vector-matrix multiplication is performed layer by layer with the memristor matrix in the lower crossbar array from the input end to the output end. In the reverse propagation process, the error signal is applied to the bit line of the lower crossbar array, and vector-matrix multiplication is performed layer by layer with the transpose of the memristor matrix from the output end to the input end, and the switching device controls whether the error signal can be reversely propagated. During the weight update process, voltages are applied to the wordlines and bitlines of the underlying crossbar array based on the pulse time-dependent plasticity to change the memristor conductance in parallel. Error signals at each layer are then used to control the conduction state of the switching devices, thereby controlling the on / off state of the transistors to determine whether the voltages on the wordlines and bitlines of the underlying crossbar array can change the memristor conductance. The proposed method for operating an arithmetic circuit for neural network learning, based on the design of a synaptic array, can efficiently implement on-chip training of time-encoded spiking neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic structural diagram of a synapse array according to an embodiment;

[0049] Figure 2 Schematic diagram of a neural network structure according to an embodiment;

[0050] Figure 3 Schematic diagram of a computing circuit framework for neural network learning according to one embodiment;

[0051] FIG4( a ) is a schematic diagram of a forward propagation operation according to an embodiment;

[0052] FIG4( b ) is a schematic diagram of signal changes during the forward propagation process according to an embodiment;

[0053] FIG5( a ) is a schematic diagram of an error back propagation operation according to an embodiment;

[0054] FIG5( b ) is a schematic diagram of signal changes when the pre-synaptic signal and the post-synaptic signal overlap in time during error back propagation according to an embodiment;

[0055] FIG5( c ) is a schematic diagram of signal changes when the pre-synaptic signal and the post-synaptic signal have no temporal overlap during error back propagation according to an embodiment;

[0056] FIG6( a ) is a schematic diagram of a weight update operation according to an embodiment;

[0057] FIG6( b ) is a schematic diagram of signal changes when the error signal is greater than 0 during the weight update process according to an embodiment;

[0058] FIG6( c ) is a schematic diagram of signal changes when the error signal is equal to 0 during the weight update process according to an embodiment;

[0059] FIG6( d ) is a schematic diagram of signal changes when the error signal is less than 0 during the weight update process according to an embodiment. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0061] Example 1

[0062] The present invention relates to a synaptic array for neural network learning.

[0063] like Figure 1 The synapse array shown is a double-layer crossbar array structure, specifically including:

[0064] The upper crossbar array includes upper-layer word lines (sWL), bit lines (sBL), and upper-layer basic units connected between any word line (sWL) and any bit line (sBL). Each upper-layer basic unit includes a series-connected switch and a fixed resistor. The lower-layer crossbar array includes lower-layer word lines (WL), bit lines (BL), and lower-layer basic units connected between any word line (WL) and any bit line (BL). Each lower-layer basic unit includes a series-connected memristor and a transistor. The number of upper-layer word lines (sWL) and lower-layer word lines (WL) is the same, and the number of upper-layer bit lines (sBL) and lower-layer bit lines (BL) is the same. Each upper-layer basic unit is connected to each lower-layer basic unit on a one-to-one basis. The connection relationship is that interconnect lines extend from the connection ends of the switch and fixed resistor of the upper-layer basic unit to the gate of the transistor of the corresponding lower-layer basic unit. The conductance of each memristor is used to calculate the weight between the connected word line and bit line. The word line (WL) is used to receive the firing signal of the neuron, and the bit line (BL) outputs the product of the firing signal and the weight matrix.

[0065] It should be noted that there is no strict distinction between word lines and bit lines. For any basic cell, one end is connected to a word line and the other end is connected to a bit line. In a specific embodiment, all bit lines are parallel to each other, all word lines are parallel to each other, and word lines and bit lines intersect. In the same layer, a corresponding basic cell is located at the intersection of any word line and any bit line. The word lines and bit lines can be used to index the corresponding basic cell and apply targeted signals.

[0066] Specifically, the synaptic array consists of two layers of crossbar arrays: a switch and a fixed resistor in series, and a memristor and a transistor in series. The two ends of each unit are connected to the word and bit lines of the crossbar array. Interconnect lines extend from the switches and fixed resistors in the upper crossbar array to the gates of the corresponding transistors in the lower crossbar array.

[0067] It is understood that the switching device has the characteristic that when the voltage difference across the switching device is greater than its threshold, the switching device is turned on. Specifically, the switching device is a threshold conversion device, a transistor, or a diode, wherein the transistor is turned on when its gate-source voltage is greater than its threshold voltage.

[0068] A fixed resistor is connected to the switching device to control the voltage divider at the junction between the fixed resistor and the switching device. The interconnect wire between the fixed resistor and the switching device is connected to the transistor gate, so the voltage divider is the transistor gate voltage. When the voltage divider is greater than the transistor threshold voltage, the transistor turns on; when the voltage divider is less than the transistor threshold voltage, the transistor turns off. The resistance of the fixed resistor is determined by the threshold voltage of the switching device and the threshold voltage of the transistor.

[0069] A memristor is connected to a transistor, and its stored conductance value is associated with the synaptic weights used in neural network calculations. For example, the stored conductance value can be used directly as the synaptic weight value, or the corresponding synaptic weight value can be obtained based on the functional relationship between the conductance value and the synaptic weight value. When the transistor is in the on state, the signal can pass through the memristor, modulating its conductance value; when the transistor is in the off state, the signal cannot pass through the memristor, and its conductance value remains unchanged. Memristors include non-volatile memories such as conductive filament memristors and phase change memories.

[0070] Take the implementation of a 2*2 synaptic array as an example, that is, the number of neurons in the previous layer is 2, the number of neurons in the next layer is also 2, and there is a synaptic connection between each neuron in the previous layer and each neuron in the next layer, thus forming a 2*2 weight matrix. The element a in the weight matrix is ijIt can be the synaptic weight between the i-th neuron in the previous layer and the j-th neuron in the next layer. The training of the neural network is to continuously update the synaptic weights and finally determine the appropriate value. In this embodiment, the number of word lines WL of the crossbar array in the lower layer of the synaptic array is the same as the number of neurons in the previous layer, which is 2, and is recorded as WL1 and WL2 respectively. The number of bit lines BL of the crossbar array in the lower layer of the synaptic array is the same as the number of neurons in the next layer, which is 2, and is recorded as BL1 and BL2 respectively. The number of word lines sWL of the upper layer crossbar array is the same as the number of word lines WL of the lower layer crossbar array, which is 2, and is recorded as sWL1 and sWL2 respectively. The number of bit lines sBL of the upper layer crossbar array is the same as the number of word lines BL of the lower layer crossbar array, which is 2, and is recorded as sBL1 and sBL2 respectively.

[0071] Compared to traditional synaptic arrays, the synaptic array of the present invention adds an upper crossbar array. That is, each memristor can be controlled in two dimensions. The first dimension is the control of the lower-layer word lines and bit lines, which can also adjust the voltage difference applied to the two ends of the memristor, which determines the degree of adjustment of the memristor's conductance. The second dimension is the control of the upper-layer word lines and bit lines. In fact, the upper-layer word lines and bit lines control the switching devices, and then control whether the lower-layer memristor branch is conductive, thereby determining whether the memristor can perform conductance modulation and controlling the duration of conductance modulation. Based on this synaptic array, when forward propagation is performed, the transmitted signal is weighted and summed through the memristors. When reverse propagation is performed, the error signal at the output can be directly propagated back through the synaptic array, and combined with the on-off state of the upper-layer switching devices, the synaptic array can be directly used to calculate the error at each layer. When updating the weights, the conductance of the memristor is modulated according to the error value by controlling the signals of the upper and lower word lines and bit lines. Therefore, based on the synaptic array of the present invention, its double-layer crossbar array can realize the forward propagation, backpropagation and weight update processes of neural network supervised learning without occupying a large amount of off-chip computing resources, thereby realizing efficient computing of neural network supervised learning and reducing computing power consumption.

[0072] Example 2

[0073] The present invention also relates to an operation circuit for neural network learning, comprising a storage module and a synaptic array located between every two adjacent layers of the neural network, an integration module and a threshold comparison module, wherein the synaptic array is the synaptic array introduced above.

[0074] For any two adjacent layers, the synaptic array F between layer k and layer k+1 k The word line WL receives the release signal ε of the kth layer k After that, the release signal ε is output through the bit line BL k With the weight matrix w k.k+1The multiplication result, weight matrix w k.k+1 Synaptic array F k All weights of .

[0075] The integration module is used to linearly integrate the multiplication results of the corresponding weight matrices to obtain the membrane potential y of the k+1th layer k+1 (t).

[0076] The threshold comparison module is used to compare the membrane potential y k+1 (t) and the corresponding threshold V th For comparison, when y k+1 (t)>V th When the k+1th layer sends a signal ε to the next layer k+1 ; Otherwise, no signal is issued.

[0077] The storage module is used to record the signal release time of each layer.

[0078] Since each result output by the bit line BL of the previous synapse array will be used as the input signal of each word line WL of the next synapse array after processing, the number of bit lines BL of the previous synapse array is the same as the number of word lines WL of the next synapse array.

[0079] Let’s take a simple example to illustrate: Figure 2 The figure shows a simplified neural network structure diagram, which has only three layers, namely input layer i, hidden layer h, and output layer o. The input layer i has 4 neurons, the hidden layer h has 5 neurons, and the output layer o has 3 neurons. Figure 3 Figure 1 shows a schematic diagram of the corresponding arithmetic circuit framework, which includes two synaptic arrays, namely two double-layer crossbar arrays, located between the input layer i and the hidden layer h, and between the hidden layer h and the output layer o, respectively. The first double-layer crossbar array has four word lines (WL) and five bit lines (BL) and five bit lines (sBL). The second double-layer crossbar array has five word lines (WL) and five sWL, and three bit lines (BL) and three bit lines (sBL).

[0080] In one embodiment, the operation circuit further includes an error calculation module, which is used to calculate the error value of the output layer according to the actual output information of the output layer and the target output information.

[0081] In one embodiment, the operation circuit further includes a manipulation module for manipulating the signals of the synaptic array according to a set algorithm to implement forward propagation operation, backpropagation operation and weight update operation.

[0082] Example 3

[0083] The present invention also relates to an operating method of an operation circuit for neural network learning, which operates based on the operation circuit introduced above to realize forward propagation operation, backpropagation operation and weight update operation in time-coded pulse neural network supervised learning.

[0084] Spiking Neural Networks (SNNs) are third-generation neural networks. Unlike second-generation neural networks, which use analog value coding, they use pulses for encoding, transmitting information within the neural network. This makes them a more biomimetic neural network model, better simulating the workings of the human brain. Spiking neural networks can be further subdivided into two different coding schemes: rate coding and timing coding. Timing coding uses the timing of pulses to encode information. Compared to rate coding, it exploits information unique to spiking neural networks compared to analog neural networks: the timing of pulses. This is a key advantage of spiking neural networks as third-generation neural networks. Because each pulse contains timing information, timing-coded spiking neural networks typically require very few pulses, or even a single pulse, to transmit a large amount of information between layers, making them an ideal choice for spiking neural networks. However, in the currently widely used field of supervised learning, timing-coded spiking neural networks lack hardware-friendly training methods. Compared to analog neural networks, their computational requirements on a time scale dictate the high computational complexity and power consumption of traditional digital system processing units (such as CPUs and GPUs). On the other hand, some of the unique learning rules of spiking neural networks, such as the Hebb rule and spike temporal plasticity dependence (STDP), are very efficient and convenient when operated on some new types of memories (including memristors and phase-change memories). Circuits built on these new memories can serve as a good carrier for spiking neural networks. However, such algorithms can only be used for unsupervised learning and have limited application scenarios.

[0085] This embodiment implements supervised learning of a time-coded spiking neural network based on the arithmetic circuit introduced above, wherein the input emission signal is a unit step signal.

[0086] The specific implementation of the pulse neural network operation includes forward propagation operation, back propagation operation and weight update operation:

[0087] The forward propagation operation of any two adjacent layers in the spiking neural network includes:

[0088] The kth layer emits a unit step signal ε(tt k ) and the weight matrix w from the kth layer to the k+1th layer k.k+1 After multiplication, linear integration is performed to obtain the membrane potential y of the k+1th layerk+1 (t);

[0089] The membrane potential y k+1 (t) and the corresponding threshold V th For comparison, when y k+1 (t)>V th When the k+1th layer sends a unit step signal ε(tt k+1 ) and record the signal release time t of the k+1th layer k+1 ; Otherwise, no signal is issued;

[0090] When the data is forward propagated to the output layer, the backpropagation operation is performed, including:

[0091] The error value δ of the output layer is calculated based on the actual output pulse time of the output layer and the target pulse output time. o , the error value δ of the output layer o Back propagation layer by layer, the error value δ of the k+1th layer k+1 The error value δ with the kth layer k The relationship satisfies:

[0092]

[0093] After obtaining the error values ​​of each layer, perform the weight update operation to obtain the update amount Δw of each weight matrix k.k+1 , superimpose the original weight matrix w k.k+1 , and get the corresponding updated weight matrix:

[0094] The weight matrix update amount Δw is calculated using the following formula: k.k+1 :

[0095] Δw k.k+1 = -ηReLU(t k+1 -t k )·sgn(δ k+1 )

[0096]

[0097] In the formula, ReLU(t k+1 -t k ) is the value of ε(tt k ) after integration at t k+1 The value of the moment.

[0098] Based on the arithmetic circuit described above, the operation process of the arithmetic operation is described in detail below.

[0099] The operations to implement the forward propagation operation include:

[0100] Upper layer operation:

[0101] A voltage is applied to the word lines sWL and bit lines sBL to ensure that all switches in the upper layer are turned on, thereby turning on all transistors in the lower layer. In other words, during the forward process, a certain voltage is applied to the word lines and bit lines of the upper crossbar array to keep the switches in the on state, thereby keeping the transistors in the lower crossbar array in the on state.

[0102] Lower level operation:

[0103] The training data is input into the word line WL of the synaptic array F1 as the unit step signal emitted by the first layer until a pulse is output at the output layer; a storage module is used to record the signal emission time of each layer to complete the forward propagation operation of the current round.

[0104] Specifically, if Figure 4(a) and 4(b) As shown, in the forward propagation process, the data (the figure takes the firing data of two neurons as an example, one of which has a firing time of t k1 , the other one is issued at time t k2 , t k ={t k1 ,t k2}) is input into the word line WL of the lower crossbar array, and after passing through the synaptic array (weight matrix), a weighted superposition current signal is obtained on the bit line BL. This operation corresponds to the vector-matrix multiplication operation in the neural network operation. The current signal on the bit line is integrated into the membrane potential of the neuron by the integration module, and then the membrane potential is compared with the corresponding threshold by the threshold comparison module. When the membrane potential is at time t k+1 When the threshold of the corresponding neuron is exceeded, the threshold comparison module sends a unit step signal to the next layer, which is input to the word line WL of the synaptic array in the next layer. This pulse propagates deeper into the network. During the forward propagation process, the pulse emission time of each neuron is recorded by the storage module by monitoring the rising edge of the signal.

[0105] In the lower-level operation, the signal processing caused mainly includes the following processes:

[0106] 1. Weight calculation process: Data is input into the word line WL of the lower crossbar array. After passing through the synaptic array (weight matrix), a weighted superposition current signal is obtained on the bit line BL. This operation corresponds to the vector-matrix multiplication operation in the neural network operation.

[0107] Taking the 2*2 synaptic array in Example 1 as an example, the process of transmitting the signal emitted by the previous layer of neurons to the next layer of neurons through the synaptic array is as follows:

[0108] Transistors T11 to T22 remain on, and the emission signal of the neurons in the previous layer (U WL1 ,U WL2) is input into the word lines (WL1, WL2) of the crossbar array under the synaptic array. Each neuron is connected to a word line and emits a signal U WL1 Input word line WL1, emit signal U WL2 The input word line WL2 passes through the memristors M11 and M21. According to Ohm's law and Kirchhoff's law, the weighted sum current is obtained on BL1, that is, I BL1 =U WL1 ×G 11 +U WL2 ×G 21 , where I BL1 To get the weighted sum current on BL1, G 11 and G 21 is the conductance of M11 and M21. Similarly, the weighted sum of currents is obtained on BL2, i.e., I BL2 =U WL1 ×G 12 +U WL2 ×G 22 , where I BL1 To get the weighted sum current on BL1, G 12 and G 22 is the conductance value of M12 and M22. Thus, the weighted summation of the emission signals of the neurons in the previous layer is realized, completing the key step of multiplying the emission signal and the weight matrix in the forward propagation.

[0109] 2. Membrane potential calculation process: The current signal on the bit line is integrated into the membrane potential of the neuron by the integration module.

[0110] For each layer, the kth layer emits a unit step signal ε(tt k ) and the weight matrix w from the kth layer to the k+1th layer k.k+1 The multiplication result is ε(tt k )*w k.k+1 The membrane potential y of the k+1th layer of neurons is obtained by integrating the integral module of the operation circuit k+1 (t):

[0111]

[0112] Among them, ε(tt k ) is the unit step function,

[0113]

[0114] t k The time when the signal is released at the kth layer.

[0115] In this embodiment, the emission signal is set to a unit step signal, and the membrane potential y k+1(t) increases linearly, and the membrane potential can also be equivalently expressed as:

[0116] y k+1 (t) = w k.k+1 *x k (t)

[0117] x k (t) = αReLU(tt k )

[0118] ReLU() is the Rectified Linear Unit function, and α is a constant coefficient.

[0119] 3. Threshold comparison process: The membrane potential is compared with the corresponding threshold by the threshold comparison module. When the membrane potential exceeds the threshold of the corresponding neuron, the threshold comparison module sends a unit step signal to the next layer and inputs it to the word line WL of the synaptic array of the next layer. At the same time, the storage module is used to record the signal issuance time of the current layer.

[0120] When the membrane potential y k+1 (t) at t k+1 When the time is greater than the threshold, the k+1th layer neuron is at t k+1 Send pulses to the next layer at any time, that is, t k+1 =where(y k+1 (t)≥V th ), where V th is the neuron threshold voltage.

[0121] The forward propagation process of the neural network propagates forward layer by layer according to this rule until a signal is emitted at the output layer, completing the forward propagation of this round, and then performing backpropagation.

[0122] The operations to implement the backpropagation operation include:

[0123] Calculate the error value δ of the output layer in the current round o , so that the error value of the output layer δ o Back propagate layer by layer to obtain the error value of each layer.

[0124] When the data is forward propagated to the output layer, the actual output pulse time is obtained and target pulse output time Compared with combining the loss function L to calculate the loss of the network and thus obtain the error value of the output layer, the error value of the output layer of the neural network can be directly calculated using existing methods.

[0125] In this embodiment, the output layer error value δ o The calculation formula is as follows:

[0126]

[0127] The operations for obtaining the error value of the k-th layer include:

[0128] Upper level operation: presynaptic signal and postsynaptic signaling One of the two is applied to the synaptic array F k The word line sWL and the other one applied to the synapse array F k bit line sBL; presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1 Relative relationship of presynaptic signal and postsynaptic signaling The voltage difference can open the synaptic array F k The switching device in.

[0129] Lower layer operation; the error value δ of the k+1th layer k+1 After scaling -β times, the input synaptic array F k The bit line BL, β is the set scaling factor, and the synaptic array F is obtained. k The word line WL outputs data as the error value δ k .

[0130] In the back propagation process, when the forward propagation reaches the last layer of the neural network, the actual output time is obtained, the error value between the actual output time and the target output time is calculated, and the error value is scaled and input into the bit line BL of the crossbar array in the lower layer. During the duration of the error signal, the presynaptic signal and postsynaptic signaling The presynaptic signal is determined by the input and output time of each crossbar array recorded by the storage module during the forward propagation process. pre The postsynaptic signal is released at t post At the end of the time point, the voltage is applied to the word line sWL and the bit line sBL of the upper crossbar array. pre and t post The relative time relationship between the kth layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1The relative relationship is the same, and the relative relationship includes the time interval and the time before and after. When the two signals overlap in time, the voltage difference generated during the overlapping time falls on the switch device and the custom resistor. At this time, the voltage across the switch device is greater than its threshold voltage, and the switch device is turned on; when the two signals do not overlap in time, the voltage across the switch device is less than its threshold voltage, and the switch device is turned off. When the switch device is turned on, the transistor gate voltage is greater than its threshold voltage, the transistor is turned on, and the error signal and the memristor array in the lower crossbar array are weighted summed. The error signal of the previous layer is obtained on the word line, and then it is input into the lower bit line of the previous crossbar array. Similarly, the error of each layer is obtained. When the switch device is turned off, the error signal of the previous layer is all 0.

[0131] Take the error signal on BL1, the presynaptic signal on sWL1 and the postsynaptic signal on sBL1 as an example. Figure 5(a) and 5(b) As shown, the presynaptic signal is at t pre The postsynaptic signal is released at t post The time point ends when the two signals overlap in time, that is, t pre to t post During the overlap time, the voltage difference generated falls on the switch device S11 and the custom resistor R11. The voltage across S11 is greater than its threshold voltage, S11 turns on, and the gate voltage of transistor T11 increases accordingly. T11 turns on, and the error signal passes through M11 and merges with the error signal passing through M12 to form the error signal propagating forward on WL1, that is, I WL1 =U BL1 ×G M11 +U BL2 ×G M12 , where G M11 , G M12 is the conductivity value of M11 and M12, U BL1 and U BL2 is the error signal on BL1 and BL2, I WL1 is the weighted summation error signal on WL1, which is the error of the previous layer. As shown in Figure 5(c), when the two signals have no temporal overlap, the voltage across the switch device is less than its threshold voltage, the switch device is turned off, the transistor is turned off, and the error signal cannot pass through the memristor, meaning the error signal is zero.

[0132] In fact, the error calculation formula implemented by the above reverse operation is:

[0133]

[0134] Where β is the set scaling factor, is the weight matrix w k.k+1 The transpose of .

[0135] When t k+1 >t k When ε(t k+1 -t k )=1, the error δ of the k+1th layer k+1 After scaling by -β times, the input synaptic array is Multiply them together to get the error δ of the kth layer k ;

[0136] When t k+1 ≤t k When ε(t k+1 -t k )=0, then δ k =0.

[0137] After completing the back-propagation operation and obtaining the error values ​​of each layer, the synaptic weight update operation is continued.

[0138] For any synaptic array F k The weight update operation includes:

[0139] Lower layer operation: divided into the first and second stages to the synaptic array F k The word line WL applies a presynaptic signal and applies a postsynaptic signal to the bit line BL Presynaptic signaling at each stage and postsynaptic signaling The polarity of the same type of signal in the two phases is opposite; in each phase, the presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1 relative relationship.

[0140] Specifically, during the weight update process, the applied signal waveform can be divided into two stages.

[0141] In the first stage, the presynaptic signal is pre The postsynaptic signal is released at t postAt the end of the time point, the voltage drop generated at both ends of the memristor during the overlap time is applied to the word line and bit line of the lower crossbar array, causing its conductance to increase or decrease linearly. In the second stage, the relative value of the release time of the presynaptic signal and the end time of the postsynaptic signal remain the same as in the first stage, but the polarity is opposite to that of the first stage, and the conductance of the memristor decreases or increases linearly. If the first stage causes the conductance to increase linearly, the second stage causes the conductance to decrease linearly. If the first stage causes the conductance to decrease linearly, the second stage causes the conductance to increase linearly. If there is no overlap time, the presynaptic signal at t pre and postsynaptic signaling at t post It cannot act on both ends of the memristor at the same time, and the voltage difference is not enough to modulate the conductance.

[0142] Upper layer operation: According to the error value δ of the k+1th layer k+1 Synaptic Array F k Different update signals are applied to the bit line sBL and word line sWL:

[0143] When δ k+1 =0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned off in both the first and second phases;

[0144] When δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned off in one phase and turned on in the other phase. During the period when the transistor is turned on, the presynaptic signal overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease;

[0145] When δ k+1 <0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned on in one phase and turned off in the other phase, and during the period when the transistor is turned on, the presynaptic signal of the time overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

[0146] Specifically, during the weight update process, the update signal for each double-layer crossbar array is determined by the error value acquired by the bit lines in the lower crossbar array during backpropagation. The update signal is applied to the bit lines and word lines of the upper crossbar array to control the state of the corresponding transistors, and thus control whether the memristor branch is conductive, that is, whether the two ends of the memristor can receive the modulation signal (presynaptic signal and postsynaptic signal) applied by the lower word lines and bit lines. When the transistor is turned on, during the time the transistor is on, the voltage difference between the overlapping parts of the presynaptic signal and the postsynaptic signal can change the conductance of the memristor; during the time the transistor is off, the conductance of the memristor cannot be changed by the presynaptic and postsynaptic signals.

[0147] When the error signal is positive, the update signal applied to the upper bit line and word line can turn on the transistor during the period when the modulated conductance value decreases, so that the presynaptic signal s′ overlaps with the time during the transistor opening period. tpre and postsynaptic signal s′ tpost The voltage drop across the memristor causes its conductance to gradually decrease.

[0148] When the error signal is positive, the update signal applied to the upper bit line and word line cannot turn on the transistor, and the conductance value of the memristor is not modulated.

[0149] When the error signal is negative, the update signal applied to the upper bit line and word line can turn on the transistor during the phase of increasing the modulated conductance value to overlap the presynaptic signal during the period when the transistor is turned on. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

[0150] It can be understood that, in specific operations, the conductance can be modulated to increase in the first stage and to decrease in the second stage, or the conductance can be modulated to decrease in the first stage and to increase in the second stage.

[0151] Take the case where the conductance is increased in the first stage and decreased in the second stage as an example. k The word line WL is applied as a positive presynaptic signal A negative postsynaptic signal is applied to the bit line BL. When the error signal δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistors are turned off in the first phase and turned on in the second phase. In the second phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease. k+1<0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned on in the first phase and turned off in the second phase. In the first phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

[0152] Furthermore, in one embodiment,

[0153] When δ k+1 =0, the corresponding bit line sBL and word line sWL are both at low level. Specifically, they can both be grounded.

[0154] When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a low level in the first stage and a high level in the second stage. For example, the word line sWL can be grounded, and a signal that jumps from a low level to a high level is applied to the bit line sBL.

[0155] When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a high level in the first stage and a low level in the second stage. For example, the word line sWL can be grounded, and a signal that jumps from a high level to a low level is applied to the bit line sBL.

[0156] like Figures 6(a) to 6(d) As shown, a specific example is used to illustrate that during the weight update, sWL1 is grounded and the error update signal on sBL1 is used.

[0157] As shown in Figure 6(b), when δ k+1 >0, the error update signal is a zero signal in the first stage, the transistor cannot be turned on, and the conductance remains unchanged. The second stage is a square wave with an amplitude greater than zero, which turns on the transistor. At this time, if the presynaptic signal and the postsynaptic signal overlap in time, the conductance linearity decreases. If there is no time overlap, the conductance remains unchanged.

[0158] As shown in Figure 6(c), when δ k+1 =0, the error update signal is zero in both the first and second stages, the transistor cannot be turned on, and the conductance remains unchanged.

[0159] As shown in Figure 6(d), when δ k+1 <0, the error update signal is a square wave with an amplitude greater than zero in the first stage, which turns on the transistor. At this time, if the pre-synaptic signal and the post-synaptic signal overlap in time, the conductance linearly increases. If there is no time overlap, the conductance remains unchanged. The second stage is a zero signal, the transistor cannot be turned on, and the conductance remains unchanged.

[0160] The effect of this operation is that when the error update signal is greater than zero, the conductance value that the original pulse-contact plasticity should change is updated; when the error update signal is less than zero, the conductance value that the original pulse-contact plasticity should change is updated in the opposite direction.

[0161] The calculation formula of the weight update increment corresponding to this process is:

[0162] Δw k.k+1 = -ηReLU(t k+1 -t k )·sgn(δ k+1 )

[0163]

[0164] In the formula, ReLU(t k+1 -t k ) is the value of ε(tt k ) after integration at t k+1 The value of the moment.

[0165] In summary, the present invention is based on the operation method of the operation circuit for neural network learning, which relies on the design of the synaptic array. The synaptic array is composed of an upper crossbar array with switching devices and fixed resistors as basic units and a lower crossbar array with memristors and transistors as basic units, forming a double-layer crossbar array. The corresponding basic units in the two crossbar arrays are connected by wires; the double-layer crossbar array can realize the forward propagation, reverse propagation and weight update process of the pulse neural network. In the forward process, the input signal is applied to the word line of the lower crossbar array, and the vector matrix multiplication operation is performed layer by layer with the memristor matrix in the lower crossbar array from the input end to the output end. In the reverse propagation process, the error signal is applied to the bit line in the lower crossbar array, and the vector matrix multiplication operation is performed layer by layer with the transpose of the memristor matrix from the output end to the input end, and the switch device controls whether the error signal can be reversely propagated. During the weight update process, voltages are applied to the wordlines and bitlines of the underlying crossbar array based on pulse time-dependent plasticity to change the memristor conductance in parallel. Error signals at each layer are used to control the conduction state of the switching devices, thereby controlling the on / off state of the transistors to determine whether the voltages on the wordlines and bitlines of the underlying crossbar array can change the memristor conductance. The proposed operating method for an arithmetic circuit for neural network learning, based on a synaptic array design, can efficiently implement operations using a novel non-volatile memory.

[0166] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A synaptic array for neural network learning, characterized in that: include: An upper crossbar array includes N word lines sWL, M bit lines sBL, and upper basic units connected between any word line sWL and any bit line sBL, each upper basic unit including a switch device and a fixed resistor connected in series; A lower crossbar array includes N word lines WL, M bit lines BL, and lower basic units connected between any word line WL and any bit line BL, each lower basic unit including a memristor and a transistor connected in series; Each upper layer basic unit is connected to each lower layer basic unit in a one-to-one correspondence, and the connection method is: an interconnection line is drawn from the connection end of the switch device and the fixed resistor of the upper layer basic unit and connected to the gate of the transistor of the corresponding lower layer basic unit; The conductance value of each memristor is used to calculate the weight between the connected word line WL and the bit line BL. During the forward propagation process, each word line WL is used to receive the emission signal of the neuron, and the bit line BL outputs the multiplication result of the emission signal and the weight matrix. The weight matrix is ​​all the weights of the synaptic array.

2. The synaptic array for neural network learning according to claim 1, wherein: The switching device is a threshold conversion device, a transistor or a diode.

3. The synaptic array for neural network learning according to claim 1, wherein: All bit lines are parallel to each other, all word lines are parallel to each other, and the word lines and bit lines intersect.

4. The synaptic array for neural network learning according to claim 1, wherein The memristor is a conductive filament memristor or a phase change memory.

5. An arithmetic circuit for neural network learning, characterized in that: It includes a storage module and a synaptic array, an integration module and a threshold comparison module that are connected in sequence between every two adjacent layers of the neural network, wherein: The synaptic array is a synaptic array for neural network learning according to any one of claims 1 to 4, wherein the number of bit lines BL of the previous synaptic array is the same as the number of word lines WL of the next synaptic array; the synaptic arrays F between the kth layer and the k+1th layer are k The word line WL receives the release signal ε of the kth layer k Afterwards, through the synaptic array F k The bit line BL outputs the release signal ε to the integration module k With the weight matrix w k.k+1 The multiplication result, weight matrix w k.k+1 Synaptic array F k All weights of The integration module is used to perform linear integration on the received multiplication result to obtain the membrane potential y of the k+1th layer k+1 (t); The threshold comparison module is used to compare the membrane potential y k+1 (t) and the corresponding threshold V th For comparison, when y k+1 (t)>V th When the k+1th layer sends a signal ε to the k+2th layer k+1 ; Otherwise, no signal is issued; The storage module is used to record the signal release time of each layer.

6. The computing circuit for neural network learning according to claim 5, wherein: It also includes an error calculation module for calculating the error value of the output layer based on the actual output information and target output information of the output layer of the neural network.

7. A method for operating an arithmetic circuit for neural network learning, characterized in that: Implementing the forward propagation operation and the back propagation operation of the operation circuit for neural network learning according to claim 5 or 6, wherein: The operations to implement the forward propagation operation include: Apply voltage to the word line sWL and the bit line sBL to ensure that all the switching devices in the upper layer are turned on, so that all the transistors in the lower layer are turned on; The training data is input into the word line WL of the synaptic array F1 as the unit step signal emitted by the first layer until the signal is output at the output layer; the signal emission time of each layer is recorded using the storage module to complete the forward propagation operation of the current round; The operations to implement the backpropagation operation include: Calculate the error value δ of the output layer in the current round o , so that the error value of the output layer δ o Back propagation is performed layer by layer to obtain the error value of each layer. The operation of obtaining the error value of the kth layer includes: presynaptic signal and postsynaptic signaling One of the two is applied to the synaptic array F k The word line sWL and the other one applied to the synapse array F k bit line sBL; presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1 Relative relationship of presynaptic signal and postsynaptic signaling The voltage difference can open the synaptic array F k Switching devices in; The error value δ of the k+1th layer k+1 After scaling -β times, the input synaptic array F k The bit line BL, β is the set scaling factor, and the synaptic array F is obtained. k The word line WL outputs data as the error value δ k .

8. The method for operating a computing circuit for neural network learning according to claim 7, wherein: It also includes weight update operations, for any synaptic array F k The weight update operation includes: The first and second stages are divided into synaptic array F k The word line WL applies a presynaptic signal and applies a postsynaptic signal to the bit line BL Presynaptic signaling at each stage and postsynaptic signaling The polarity of the same type of signal in the two phases is opposite; in each phase, the presynaptic signal The onset time of postsynaptic signal The relative relationship of the end time is consistent with the k-th layer signal release time t recorded during the forward propagation k and the signal release time t of the k+1th layer k+1 The relative relationship between According to the error value δ of the k+1th layer k+1 Synaptic Array F k Different refresh signals are applied to the bit line sBL and word line sWL, including: When δ k+1 =0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned off in both the first and second phases; When δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned off in one phase and turned on in the other phase. During the period when the transistor is turned on, the presynaptic signal overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease; When δ k+1 <0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistor is turned on in one phase and turned off in the other phase, and during the period when the transistor is turned on, the presynaptic signal of the time overlaps and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

9. The method for operating an arithmetic circuit for neural network learning according to claim 8, wherein: In implementing the synaptic array F k In the weight update operation, In two stages, the synaptic array F k The word line WL applies a presynaptic signal and applies a postsynaptic signal to the bit line BL include: In the first stage, the synaptic array F k The word line WL is applied as a positive presynaptic signal A negative postsynaptic signal is applied to the bit line BL. In the second stage, the synaptic array F k The word line WL is applied as a negative presynaptic signal A positive postsynaptic signal is applied to the bit line BL. According to the error value δ of the k+1th layer k+1 Synaptic Array F k Different signals are applied to the corresponding bit lines sBL and word lines sWL, including: When δ k+1 >0, the update signals applied to the corresponding bit line sBL and word line sWL ensure that the corresponding transistors are turned off in the first phase and turned on in the second phase. In the second phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually decrease; When δ k+1 <0, the update signals applied to the corresponding bit lines sBL and word lines sWL ensure that the corresponding transistors are turned on in the first phase and turned off in the second phase. In the first phase, the presynaptic signals overlap in time. and postsynaptic signaling The voltage drop across the memristor causes its conductance to gradually increase.

10. The method for operating an arithmetic circuit for neural network learning according to claim 9, wherein: When δ k+1 =0, the corresponding bit line sBL and word line sWL are both low level; When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a low level in the first stage and a high level in the second stage; When δ k+1 >0, one of the corresponding bit line sBL and word line sWL is at a low level, and the other is at a high level in the first stage and a low level in the second stage.

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