A power semiconductor module packaging structure and packaging process and packaging device

Abstract

The embodiment of the present invention provides a power semiconductor module packaging structure and its packaging process and packaging device. The packaging process processes a packaging base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged; uses a target plastic packaging material to plasticize the packaging base to form a first plastic packaging layer on the target heat sink; performs metal sputtering on the first plastic packaging layer to form a metal layer, and electroplating on the metal layer according to a preset substrate pattern to form a circuit layer; electrically bonds the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire; and uses a target plastic packaging material to plasticize the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire to obtain a packaged finished product. Since the first plastic packaging layer is also formed by the target plastic packaging material, when the power semiconductor generates heat, the deformation of the first plastic packaging layer and the plastic packaging layer wrapping the power semiconductor are consistent, and the situation of inconsistent deformation between the traditional plastic packaging layer and the substrate will not occur.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a power semiconductor module packaging structure and a packaging process and a packaging device thereof. Background Art

[0002] The power MOS module is a MOS tube that is potted into a module according to a certain functional combination. The power MOS module usually needs to be used in conjunction with other external devices. The power MOS module is widely used in various switching power supplies, controllers and other related equipment. It is an important part of high-power power electronic systems. However, the heat generated by the power MOS module is also large. If the heat of the MOS tube chip is not dissipated in time, it will seriously affect the working performance of the power MOS module.

[0003] In order to dissipate heat for the power MOS module, the existing packaging process of the power MOS module generally uses a ceramic copper-clad substrate, which is fixed on the heat dissipation base plate by welding and applying thermal conductive paste. The packaging materials include a shell, silicone or epoxy molding compound.

[0004] The existing packaging process causes mismatched stress in the packaging structure of the power MOS module due to inconsistent deformation of the ceramic copper-clad substrate, packaging materials, and heat sink when heated. Over time, the power MOS module is prone to deformation cracks or even breakage. Summary of the invention

[0005] The embodiments of the present invention provide a power semiconductor module packaging structure and a packaging process and a packaging device thereof, thereby solving the technical problem that the existing power semiconductor packaging structure is unevenly deformed by heat, and is prone to cracks that affect its service life.

[0006] In a first aspect, the present invention provides a power semiconductor module packaging process through an embodiment of the present invention, comprising: processing a packaging base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged; performing a plastic packaging process on the packaging base using a target plastic packaging material to form a first plastic packaging layer on the target heat sink; performing metal sputtering on the first plastic packaging layer to form a metal layer, and electroplating on the metal layer according to a preset substrate pattern to form a circuit layer; electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire; and performing a plastic packaging process on the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire using the target plastic packaging material to obtain a packaged product.

[0007] As an optional implementation, the step of processing a package base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged includes:

[0008] Determining a target packaging area on the target heat sink based on the preset layout parameters;

[0009] Processing the packaging base on a target heat sink located in the target packaging area;

[0010] Wherein, the package base includes a plurality of bumps.

[0011] As an optional implementation manner, before performing metal sputtering on the first plastic encapsulation layer to form a metal layer, the method further includes:

[0012] A plurality of grooves are processed on the first plastic packaging layer.

[0013] As an optional implementation manner, the step of performing metal sputtering on the first plastic encapsulation layer to form a metal layer includes:

[0014] A metal sputtering process is performed in each of the grooves to form a metal layer in each of the grooves.

[0015] As an optional implementation manner, before electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire, the method further includes:

[0016] Sintering metallic silver on the circuit layer in the area where the power semiconductor to be packaged is to be fixed to form a sintered silver layer;

[0017] The other side of the power semiconductor to be packaged is fixedly connected to the sintered silver layer.

[0018] As an optional implementation, the packaging process further includes:

[0019] A metal sheet is formed on the top surface of the power semiconductor to be packaged, and the metal sheet is electrically bonded to the circuit layer through the metal wire.

[0020] In a second aspect, the present invention provides a power semiconductor module packaging device through an embodiment of the present invention, including:

[0021] A substrate processing unit, used for processing a package base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged;

[0022] The substrate processing unit is further used to perform a plastic packaging process on the packaging base using a target plastic packaging material to form a first plastic packaging layer on the target heat dissipation plate;

[0023] A circuit printing unit, configured to perform metal sputtering on the first plastic packaging layer to form a metal layer, and perform electroplating on the metal layer according to a preset substrate pattern to form a circuit layer;

[0024] A chip bonding unit, used for electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire;

[0025] The plastic encapsulation unit is used to perform plastic encapsulation processing on the metal layer, the circuit layer, the power semiconductor to be packaged and the metal bonding using the target plastic encapsulation material to obtain a packaged product.

[0026] In a third aspect, the present invention provides a power semiconductor module packaging device through an embodiment of the present invention, comprising a memory, a processor, and a code stored in the memory and executable on the processor, wherein when the processor executes the code, any one of the implementations in the first aspect is implemented.

[0027] In a fourth aspect, the present invention provides a computer-readable storage medium through an embodiment of the present invention, on which a computer program is stored, and when the program is executed by a processor, any implementation method in the first aspect is implemented.

[0028] In a fifth aspect, the present invention provides a power semiconductor module packaging structure through an embodiment of the present invention, comprising a metal sheet, a power semiconductor, a circuit layer, a first plastic sealing layer and a target heat sink stacked in sequence from top to bottom, wherein the metal sheet, the power semiconductor, the circuit layer and the first plastic sealing layer are all plastic-sealed in a second plastic sealing layer;

[0029] The first plastic encapsulation layer and the second plastic encapsulation layer are both formed based on a target plastic encapsulation material;

[0030] The top surface of the power semiconductor is electrically bonded to the circuit layer through the metal sheet, and the other surface of the power semiconductor is fixedly connected to the circuit layer;

[0031] The first plastic sealing layer is embedded and fixedly connected with the target heat dissipation plate.

[0032] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0033] First, based on the preset layout parameters of the power semiconductor to be packaged, a package base is processed on the target heat sink, and then the package base is plastic-sealed using the target plastic-sealing material to form a first plastic-sealing layer on the target heat sink, and then metal sputtering is performed on the first plastic-sealing layer to form a metal layer, and electroplating is performed on the metal layer according to the preset substrate pattern to form a circuit layer, and after the top surface of the power semiconductor to be packaged is electrically bonded to the circuit layer through a metal wire, the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire are plastic-sealed using the target plastic-sealing material to obtain a packaged product. Since the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire are all plastic-sealed in the target plastic-sealing material, the first plastic-sealing layer is also formed by the target plastic-sealing material. This makes the deformation of the first plastic-sealing layer and the plastic-sealing layer that wraps the power semiconductor consistent during the heating process of the power semiconductor, and the situation of inconsistent deformation between the traditional plastic-sealing layer and the substrate will not occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A flowchart of a power semiconductor module packaging process according to an embodiment of the present invention;

[0036] Figure 2 A cross-sectional view of a power semiconductor module packaging structure in an embodiment of the present invention;

[0037] Figure 3 A cross-sectional view of an existing mid-power semiconductor module packaging structure;

[0038] Figure 4 A schematic diagram of a power semiconductor module packaging device structure according to an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of a power semiconductor module packaging device structure according to an embodiment of the present invention;

[0040] Figure 6 Schematic diagram of a computer-readable storage medium structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The embodiments of the present invention provide a power semiconductor module packaging structure and a packaging process and a packaging device thereof, thereby solving the technical problem that the existing power semiconductor packaging structure is unevenly deformed by heat, and is prone to cracks that affect its service life.

[0042] The technical solution provided by the embodiment of the present invention is to solve the above technical problems, and the overall idea is as follows:

[0043] First, based on the preset layout parameters of the power semiconductor to be packaged, a package base is processed on the target heat sink, and then the package base is plastic-sealed with the target plastic-sealing material to form a first plastic-sealing layer on the target heat sink. Metal sputtering is performed on the first plastic-sealing layer to form a metal layer, and electroplating is performed on the metal layer according to the preset substrate pattern to form a circuit layer. After the top surface of the power semiconductor to be packaged is electrically bonded to the circuit layer through a metal wire, the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire are plastic-sealed with the target plastic-sealing material to obtain a packaged finished product.

[0044] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0045] First of all, the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0047] In the first aspect, the present invention provides a power semiconductor module packaging process through an embodiment of the present invention, which can be applied to the packaging of MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) power semiconductor modules to be packaged, such as silicon carbide (SiC), gallium nitride (GaN), and aluminum nitride (AlN).

[0048] Please see Figure 1 As shown, the power semiconductor module packaging process may include the following steps:

[0049] Step S101: processing a package base on a target heat sink based on preset layout parameters of a power semiconductor to be packaged.

[0050] Specifically, the preset layout parameters of the power semiconductors to be packaged may include: the number of power semiconductors to be packaged that are packaged on the same target heat sink, and the arrangement of the power semiconductors to be packaged on the same target heat sink. For example, the preset layout parameters may be that the number of power semiconductors to be packaged is 9, and the power semiconductors to be packaged are arranged in a square 3×3 form on the target heat sink.

[0051] For details, see Figure 2 As shown, a target packaging area can be determined on the target heat sink 100 based on preset layout parameters, and a packaging base 101 can be processed on the target heat sink 100 located in the target packaging area, wherein the packaging base 101 includes multiple bumps, such as multiple cylinders or multiple prisms.

[0052] In the specific implementation process, the target heat sink 100 can be made of metal such as copper, nickel, silver or gold, and the target heat sink 100 is made of the same material as the package base 101. In addition to being composed of a plurality of bumps, the package base 101 can also be embossed according to a preset pattern, or grooved according to a preset pattern.

[0053] The preset graphics and preset patterns can be set according to the actual application scenario. The package base 101 can effectively increase the contact area and bonding force of the subsequent process by increasing the surface area of ​​the target package area. It should be noted that the material of the bump package base 101 is consistent with the material of the target heat sink 100.

[0054] Step S102 : using a target plastic packaging material to perform plastic packaging on the package base 101 to form a first plastic packaging layer on the target heat dissipation plate 100 .

[0055] Specifically, the target molding material may include epoxy resin. Figure 2 As shown, the package base 101 needs to be completely encapsulated in the target encapsulation material, so as to form a first encapsulation layer 200 in the target encapsulation area of ​​the target heat dissipation plate 100 .

[0056] Step S103: performing metal sputtering on the first plastic packaging layer 200 to form a metal layer, and performing electroplating on the metal layer according to a preset substrate pattern to form a circuit layer.

[0057] Before executing step S103 , a plurality of grooves 201 may be processed on the first plastic encapsulation layer 200 to provide a larger contact area for subsequent metal sputtering, thereby increasing the contact area between the metal layer and the first plastic encapsulation layer 200 and thus increasing the bonding force between the metal layer and the first plastic encapsulation layer 200 .

[0058] Regarding how to form the metal layer, specifically, metal sputtering is performed in each groove 201 to form a metal layer in each groove 201. Figure 2 As shown, metal sputtering cannot be performed directly on the surface of the first plastic packaging layer 200. A metal sputtering process is required to first make a very thin metal layer on the surface of the first plastic packaging layer 200, so that the next process can directly electroplate the circuit layer 300 on the metal layer, making the metal stack more compact and the circuit layer 300 not easy to fall off.

[0059] The preset substrate pattern includes the pin output of a single power semiconductor to be packaged and electrical connections such as grounding. Of course, the preset substrate pattern also includes some non-polar areas. Electroplating is performed on the surface of the first plastic encapsulation layer 200 according to the preset substrate pattern, and different substrate patterns are drawn according to the polarity of the power semiconductor chip. The blank area between the circuit layers 300 is used to separate different polarities.

[0060] It should be noted that the first plastic packaging layer 200 and the circuit layer 300 can be used as a substrate of a power semiconductor.

[0061] Step S104: electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer 300 through metal wires.

[0062] As an optional implementation, in order to better fix the packaged power semiconductor, please continue to refer to Figure 2 As shown, before executing step S104 , metallic silver may be sintered on the circuit layer 300 in the area where the power semiconductor to be packaged is to be fixed, so as to form a sintered silver layer 400 .

[0063] The top surface of the power semiconductor 500 to be packaged is electrically bonded to the circuit layer 300 via a metal wire, and the other surface of the power semiconductor 500 to be packaged is fixedly connected to the sintered silver layer 400 .

[0064] In order to make it easier to bond the top surface of the power semiconductor 500 to be packaged with the circuit layer 300, a metal sheet 600 may be formed on the top surface of the power semiconductor 500 to be packaged, and the metal sheet 600 is electrically bonded to the circuit layer 300 through a metal wire 700. The metal wire 700 may be a copper wire or a gold wire.

[0065] The metal sheet 600 can be attached to the top surface of the power semiconductor 500 to be packaged by hot pressing, and the metal sheet 600 is pressed and sintered after hot pressing. The metal sheet 600 can include a copper sheet, a silver sheet or a gold sheet. The power semiconductor 500 to be packaged can also be fixed on the sintered silver layer 400 by hot pressing.

[0066] After forming a metal sheet 600 on the top surface of the power semiconductor 500 to be packaged and electrically bonding the metal sheet 600 to the circuit layer 300 through the metal wire 700 , the terminals and polarity pins may be welded, pressed or sintered.

[0067] Step S105: using a target plastic packaging material to perform plastic packaging processing on the metal layer, the circuit layer 300, the power semiconductor 500 to be packaged, and the metal wire 700 to obtain a packaged product.

[0068] In the specific implementation process, the metal layer, the circuit layer 300, the power semiconductor to be packaged 500, the metal sheet 600, the metal wire 700 and the sintered silver layer 400 are all plastic-encapsulated in the target plastic encapsulation material to complete the packaging of the power semiconductor. Since the first plastic encapsulation layer 200 is also formed by the target plastic encapsulation material, when the power semiconductor is heated, the deformation of the first plastic encapsulation layer 200 and the plastic encapsulation layer that wraps the power semiconductor are consistent, and the situation of inconsistent deformation between the traditional plastic encapsulation layer and the substrate will not occur.

[0069] Looking at the power semiconductor module packaging structure in the prior art, see Figure 3 As shown, a ceramic copper clad substrate 301 is used, and the ceramic copper clad substrate 301 is fixed on the heat dissipation base plate 302 by welding / thermal conductive paste, etc. The plastic packaging material uses a shell + silicone or epoxy plastic packaging material. When the power semiconductor generates heat, the upper and lower deformations of the ceramic copper clad substrate are inconsistent, resulting in a low stress matching degree of the ceramic copper clad substrate.

[0070] In the embodiment of the present invention, a ceramic copper-clad laminate is not used, and a first plastic encapsulation layer 200 is used instead of a traditional substrate. The first plastic encapsulation layer 200 and the plastic encapsulation process in step S105 both use a target plastic encapsulation material, so that the thermal expansion coefficient is consistent, thereby solving the problem of stratification caused by inconsistent stress deformation, avoiding the risk of hidden cracks caused by stress mismatch in traditional ceramics, and improving the yield and reliability of the overall package.

[0071] Since the embodiment of the present invention does not use a ceramic copper-clad plate, the heat dissipation thickness between the power semiconductor chip and the heat dissipation plate is directly omitted, and the thickness of the copper cladding and the metal solder layer / thermal paste is also omitted, and the thickness of the heat dissipation layer is directly reduced by 50%.

[0072] The embodiment of the present invention does not use a ceramic copper-clad plate but uses a plastic packaging process, thereby effectively reducing the packaging cost of the power semiconductor module.

[0073] In the second aspect, based on the same inventive concept, the present invention provides a power semiconductor module packaging device through an embodiment of the present invention, which can be applied to the packaging of MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) power semiconductor 500 modules to be packaged, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), etc. Figure 4 As shown, the power semiconductor module packaging device may include:

[0074] The substrate processing unit 401 is used to process a packaging base 101 on a target heat sink 100 based on preset layout parameters of the power semiconductor 500 to be packaged.

[0075] The substrate processing unit 401 is further used to perform a plastic packaging process on the packaging base 101 using a target plastic packaging material to form a first plastic packaging layer 200 on the target heat dissipation plate 100 .

[0076] The circuit printing unit 402 is used to perform metal sputtering on the first plastic packaging layer 200 to form a metal layer, and perform electroplating on the metal layer according to a preset substrate pattern to form a circuit layer 300 .

[0077] The chip bonding unit 403 is used to electrically bond the top surface of the power semiconductor 500 to be packaged to the circuit layer 300 through the metal wire 700 .

[0078] The plastic encapsulation unit 404 is used to perform plastic encapsulation processing on the metal layer, the circuit layer 300, the power semiconductor 500 to be packaged, and the metal bonding using a target plastic encapsulation material to obtain a packaged product.

[0079] Since the power semiconductor module packaging device introduced in this embodiment is an electronic device used to implement the power semiconductor module packaging process in the embodiment of the present invention, based on the power semiconductor module packaging process introduced in the embodiment of the present invention, those skilled in the art can understand the specific implementation of the electronic device of the present embodiment and its various variations, so how the electronic device implements the method in the embodiment of the present invention is not described in detail here. As long as those skilled in the art implement the electronic device used in the power semiconductor module packaging process in the embodiment of the present invention, they all fall within the scope of protection of the present invention.

[0080] In a third aspect, based on the same inventive concept, an embodiment of the present invention provides a power semiconductor module packaging device. Figure 5As shown, the power semiconductor module packaging device provided by the embodiment of the present invention includes: a memory 501, a processor 502, and a code stored in the memory and executable on the processor 502. When executing the code, the processor 502 implements any implementation method of the power semiconductor module packaging process described above.

[0081] Among them, Figure 5 In the embodiment of the present invention, a bus architecture (represented by bus 5000) is shown, bus 5000 may include any number of interconnected buses and bridges, bus 5000 links various circuits including one or more processors represented by processor 502 and memory represented by memory 501. Bus 5000 may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. Bus interface 505 provides an interface between bus 5000 and receiver 503 and transmitter 504. Receiver 503 and transmitter 504 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 502 is responsible for managing bus 5000 and general processing, while memory 501 may be used to store data used by processor 502 when performing operations.

[0082] Fourthly, Figure 6 As shown, based on the same inventive concept, the present invention provides a computer-readable storage medium 800 through an embodiment of the present invention, on which a computer program 801 is stored. When the computer program 801 is executed by a processor, any implementation method of the power semiconductor module packaging process described above is implemented.

[0083] In a fifth aspect, the present invention provides a power semiconductor module packaging structure through an embodiment of the present invention, referring to Figure 2 As shown, the power semiconductor module packaging structure includes a metal sheet 600, a power semiconductor 500, a circuit layer 300, a first plastic sealing layer 200 and a target heat sink 100 stacked in sequence from top to bottom, wherein the metal sheet 600, the power semiconductor 500, the circuit layer 300 and the first plastic sealing layer 200 are all plastic-sealed in the second plastic sealing layer 900.

[0084] The first plastic encapsulation layer 200 and the second plastic encapsulation layer 900 are both formed based on the target plastic encapsulation material. The top surface of the power semiconductor 500 is electrically bonded to the circuit layer 300 through the metal sheet 600, and the other side of the power semiconductor 500 is fixedly connected to the circuit layer 300. The first plastic encapsulation layer 200 is embedded and fixedly connected to the target heat sink 100.

[0085] The technical solutions in the above embodiments of the present invention have at least the following technical effects or advantages:

[0086] Since the metal layer, the circuit layer 300, the power semiconductor to be packaged 500 and the metal wire 700 are all encapsulated in the target encapsulation material, and the first encapsulation layer 200 is also formed by the target encapsulation material, the first encapsulation layer 200 and the encapsulation layer encapsulating the power semiconductor will deform in the same way during the heating process of the power semiconductor, and the conventional situation of inconsistency between the encapsulation layer and the substrate will not occur.

[0087] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable code.

[0088] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer instructions. These computer instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0089] These computer instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0090] These computer instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0091] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0092] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A power semiconductor module packaging process, characterized in that: include: Based on the preset layout parameters of the power semiconductor to be packaged, a package base is processed on the target heat sink; The method of processing a package base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged includes: determining a target package area on the target heat sink based on the preset layout parameters; processing the package base on the target heat sink located in the target package area; wherein the package base includes a plurality of bumps; Using a target plastic packaging material to perform plastic packaging on the packaging base to form a first plastic packaging layer on the target heat dissipation plate; Performing metal sputtering on the first plastic encapsulation layer to form a metal layer, and performing electroplating on the metal layer according to a preset substrate pattern to form a circuit layer; before performing metal sputtering on the first plastic encapsulation layer to form a metal layer, it also includes: processing a plurality of grooves on the first plastic encapsulation layer; performing metal sputtering on the first plastic encapsulation layer to form a metal layer, including: performing metal sputtering treatment in each of the grooves to form a metal layer in each of the grooves; Electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire; Using the target plastic packaging material to perform plastic packaging on the metal layer, the circuit layer, the power semiconductor to be packaged, and the metal wire to obtain a packaged product; The first molding layer 200 and the second molding layer 900 are both formed based on a target molding material.

2. The power semiconductor module packaging process according to claim 1, characterized in that: Before electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire, the method further includes: Sintering metallic silver on the circuit layer in the area where the power semiconductor to be packaged is to be fixed to form a sintered silver layer; The other side of the power semiconductor to be packaged is fixedly connected to the sintered silver layer.

3. The power semiconductor module packaging process according to claim 2, characterized in that: Also includes: A metal sheet is formed on the top surface of the power semiconductor to be packaged, and the metal sheet is electrically bonded to the circuit layer through the metal wire.

4. A power semiconductor module packaging device, characterized in that: include: A substrate processing unit, used for processing a package base on a target heat sink based on preset layout parameters of the power semiconductor to be packaged; The substrate processing unit is further used to perform a plastic packaging process on the packaging base using a target plastic packaging material to form a first plastic packaging layer on the target heat dissipation plate; A circuit printing unit, configured to perform metal sputtering on the first plastic packaging layer to form a metal layer, and perform electroplating on the metal layer according to a preset substrate pattern to form a circuit layer; A chip bonding unit, used for electrically bonding the top surface of the power semiconductor to be packaged to the circuit layer through a metal wire; The plastic encapsulation unit is used to perform plastic encapsulation processing on the metal layer, the circuit layer, the power semiconductor to be packaged and the metal bonding using the target plastic encapsulation material to obtain a packaged product.

5. A power semiconductor module packaging device, comprising a memory, a processor, and a code stored in the memory and executable on the processor, characterized in that: When the processor executes the code, the process described in any one of claims 1 to 3 is implemented.

6. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the process according to any one of claims 1 to 3 is implemented.

7. A power semiconductor module packaging structure, characterized in that: It comprises a metal sheet, a power semiconductor, a circuit layer, a first plastic sealing layer and a target heat sink stacked in sequence from top to bottom, wherein the metal sheet, the power semiconductor, the circuit layer and the first plastic sealing layer are all plastic-sealed in a second plastic sealing layer; The first plastic encapsulation layer and the second plastic encapsulation layer are both formed based on a target plastic encapsulation material; The top surface of the power semiconductor is electrically bonded to the circuit layer through the metal sheet, and the other surface of the power semiconductor is fixedly connected to the circuit layer; The first plastic sealing layer is embedded and fixedly connected with the target heat dissipation plate.

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