Modulators, fractional frequency synthesizers, RF transceivers and electronic products

Abstract

The present invention provides a modulator, a fractional frequency synthesizer, a radio frequency transceiver and an electronic product, comprising: a multi-stage cascade modulation module obtains a digital frequency division ratio signal based on an integer frequency division ratio and a fractional frequency division ratio; a jitter module, used to generate a pseudo-random sequence; a high-pass filter module, filtering the pseudo-random sequence; an addition module, adding the output signal of the multi-stage cascade modulation module and the output signal of the high-pass filter module to obtain an output sequence; wherein the probability distribution range of the integral quantization error corresponding to the output sequence is greater than the probability distribution range of the integral quantization error corresponding to the digital frequency division ratio signal generated by the multi-stage cascade modulation module. The present invention adds additional random jitter to the output signal of the multi-stage cascade modulation module, greatly increases the randomness of the modulator output sequence, expands the probability distribution range of the output signal of the multi-stage cascade modulation module, improves the immunity to loop nonlinearity, and thus achieves the effect of improving the fractional spurious performance.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a modulator, a fractional frequency synthesizer, a radio frequency transceiver and an electronic product. Background Art

[0002] Fractional frequency synthesizer plays a vital role in the field of wireless communications, and its performance directly affects the quality of wireless communications.

[0003] At present, fractional frequency synthesizers all use multi-mode dividers, and the instantaneous division ratio of the multi-mode divider is controlled by the Delta-Sigma modulator (DSM) to achieve the fractional frequency division function. Fractional spurs are inevitably introduced in this process. In order to solve the problem of fractional spurs, the conventional solution is to disrupt the periodicity of the output sequence and ensure the randomization of the DSM output sequence. However, due to the existence of the nonlinearity of the phase-locked loop, even if the DSM output does not contain a periodic component, that is, the DSM itself does not have fractional spurs, after the nonlinear deterioration, there will still be fractional spurs at the output of the phase-locked loop. The traditional DSM cannot effectively suppress the fractional spurs introduced by the loop nonlinearity.

[0004] Therefore, how to achieve a better suppression effect on the fractional spurious introduced by the nonlinearity of the phase-locked loop has become one of the problems that technical personnel in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a modulator, a fractional-frequency synthesizer, a radio frequency transceiver and an electronic product, which can solve the fractional spurious problem introduced by the loop nonlinearity of the fractional-frequency synthesizer in the prior art while ensuring that there is no periodic component in the output of the modulator.

[0007] To achieve the above object and other related objects, the present invention provides a modulator, the modulator at least comprising:

[0008] Multi-stage cascade modulation module, dithering module, high-pass filtering module and adding module;

[0009] The multi-stage cascade modulation module receives an integer frequency division ratio and a fractional frequency division ratio, and obtains a digital frequency division ratio signal based on the integer frequency division ratio and the fractional frequency division ratio;

[0010] The jitter module is used to generate a pseudo-random sequence, and the pseudo-random sequence includes values ​​1 and -1;

[0011] The high-pass filter module is connected to the output end of the jitter module to filter the pseudo-random sequence output by the jitter module;

[0012] The adding module is connected to the output ends of the multi-stage cascade modulation module and the high-pass filtering module, and adds the output signal of the multi-stage cascade modulation module and the output signal of the high-pass filtering module to obtain an output sequence;

[0013] The probability distribution range of the integrated quantization error corresponding to the output sequence is greater than the probability distribution range of the integrated quantization error corresponding to the digital frequency division ratio signal.

[0014] Optionally, the multi-stage cascade modulation module is a Delta-Sigma modulation structure of a MASH 1-1-1 topology.

[0015] Optionally, the high-pass filtering module includes at least 2nd-order filtering.

[0016] Optionally, the high-pass filtering module includes a first-order filtering unit, a second-order filtering unit, a third-order filtering unit and a two-choice unit;

[0017] The first-order filtering unit, the second-order filtering unit and the third-order filtering unit are cascaded in sequence, and the first-order filtering unit receives the pseudo-random sequence;

[0018] The input end of the two-select-one unit is respectively connected to the output end of the second-order filter unit and the third-order filter unit, and outputs the output signal of the second-order filter unit or the output signal of the third-order filter unit based on the filter order selection signal.

[0019] To achieve the above-mentioned object and other related objects, the present invention provides a fractional-frequency synthesizer, which comprises at least: a phase-locked loop circuit of a charge pump structure and the above-mentioned modulator;

[0020] The modulator receives the frequency division signal of the phase-locked loop circuit and is used to generate an output sequence, and the output sequence serves as the frequency division control signal of the phase-locked loop circuit.

[0021] Optionally, the phase-locked loop circuit includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a multi-mode frequency divider;

[0022] The frequency detector receives the reference clock signal and is connected to the output end of the multi-mode frequency divider to output the phase difference between the reference clock signal and the frequency division signal;

[0023] The charge pump is connected to the output end of the frequency detector and phase detector to convert the phase difference into a current signal;

[0024] The loop filter is connected to the output end of the charge pump to filter the output signal of the charge pump;

[0025] The voltage-controlled oscillator is connected to the output end of the loop filter, and generates an oscillation signal of a corresponding frequency based on the output signal of the loop filter;

[0026] The multi-mode frequency divider is connected to the output end of the voltage-controlled oscillator, and performs fractional frequency division on the oscillation signal based on the frequency division control signal to obtain the frequency division signal.

[0027] Optionally, the phase-locked loop circuit further includes a frequency divider, which is connected to the output end of the voltage-controlled oscillator and outputs the oscillation signal after frequency division.

[0028] To achieve the above object and other related objects, the present invention further provides a radio frequency receiver, the radio frequency receiver at least comprising:

[0029] A low noise amplifier, a down-conversion mixer and a fractional frequency synthesizer as described above;

[0030] The low noise amplifier receives the radio frequency signal and performs amplification processing;

[0031] The fractional frequency synthesizer is used to provide a local oscillator signal;

[0032] The down-conversion mixer is connected to the output ends of the low noise amplifier and the fractional frequency synthesizer to convert the radio frequency signal into an intermediate frequency signal.

[0033] To achieve the above-mentioned object and other related objects, the present invention further provides a radio frequency transmitter, the radio frequency transmitter at least comprising:

[0034] Up-conversion mixers, power amplifiers and the above fractional frequency synthesizers;

[0035] The fractional frequency synthesizer is used to provide a local oscillator signal;

[0036] The up-conversion mixer is connected to the output end of the fractional frequency synthesizer, receives an intermediate frequency signal, and converts the intermediate frequency signal into a radio frequency signal;

[0037] The power amplifier is connected to the output end of the up-conversion mixer to amplify the radio frequency signal.

[0038] To achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned fractional-frequency synthesizer.

[0039] As described above, the modulator, fractional frequency synthesizer, radio frequency transceiver and electronic product of the present invention have the following features:

[0040] Beneficial effects:

[0041] The modulator, fractional frequency synthesizer, radio frequency transceiver and electronic product of the present invention significantly increase the randomness of the modulator output sequence by adding additional random jitter to the output signal of the multi-stage cascade modulation module, thereby achieving a strong effect of breaking up the potential periodicity of the output sequence; by expanding the probability distribution range of the output signal of the multi-stage cascade modulation module, the PNN waveform when nonlinearity exists is changed, thereby reducing the energy of the periodic component in the nonlinear noise and improving the optimization effect of fractional spurious suppression. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Shown is a schematic structural diagram of the modulator of the present invention.

[0043] Figure 2 Shown is a schematic structural diagram of the fractional-frequency synthesizer of the present invention.

[0044] Figure 3 Schematic diagram showing the probability distribution of the integrated quantization error for a multi-stage cascade modulation module.

[0045] Figure 4 It is a schematic diagram showing the probability distribution of the integrated quantization error of the modulator of the present invention at the second-order filtering gear.

[0046] Figure 5 It is a schematic diagram showing the probability distribution of the integrated quantization error of the modulator of the present invention under the third-order filtering gear.

[0047] Figure 6 It shows a schematic diagram comparing the PNN waveforms of a multi-stage cascade modulation module and the modulator of the present invention at a 2nd order filtering gear and a 3rd order filtering gear.

[0048] Figure 7 Schematic diagram of fractional spurious energy shown as a multi-stage cascaded modulation module.

[0049] Figure 8 It is a schematic diagram showing the fractional spurious energy of the modulator of the present invention at the 2nd order filtering gear.

[0050] Fig. 9 It is a schematic diagram showing the fractional spurious energy of the modulator of the present invention at the 3rd order filtering gear.

[0051] Component number description

[0052] 1 Fractional Frequency Synthesizer

[0053] 11 Modulator

[0054] 111 Multi-level cascade modulation module

[0055] 112 Jitter Module

[0056] 113 High-pass filter module

[0057] 113a First-order filter unit

[0058] 113b Second order filter unit

[0059] 113c Third-order filter unit

[0060] 113d Two-choice unit

[0061] 114 Addition module

[0062] 12 Phase and frequency detector

[0063] 13. Charge Pump

[0064] 14 Loop Filter

[0065] 15 Voltage Controlled Oscillator

[0066] 16 Multimode Crossover

[0067] 17 Crossover

[0068] 18 Crystal Oscillator DETAILED DESCRIPTION

[0069] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0071] The decimal spurs introduced by loop nonlinearity can be analyzed using periodic nonlinear noise (PNN). PNN represents the time domain waveform of the periodic component of nonlinear noise. The frequency of the PNN waveform is the frequency deviation corresponding to the decimal spurs, and the swing of the PNN waveform reflects the amplitude of the decimal spurs. The formula of PNN is as follows:

[0072]

[0073] Among them, τ k (n) is the k tracks of the integrated quantization error t[n] output by the modulator (Delta-Sigma modulator), are k trajectories after nonlinear degradation, P(τ k (n)) is the value of the nth sampling point t[n] is τ k The calculated PNN waveform is equivalent to the periodic component extracted from t[n]. When there is no periodic component, that is, no fractional spurious, the PNN waveform will not fluctuate over time and will remain constant.

[0074] PNN is related to the type of loop nonlinearity and the probability distribution of the integral quantization error t[n] in the modulator. For specific loop nonlinearity, the amplitude of the PNN periodic fluctuation can be changed by changing the probability distribution, thereby suppressing the periodic component and thus suppressing the fractional spurs introduced by the nonlinearity.

[0075] For a charge-pump based PLL (CPPLL), the nonlinearity of the loop mainly comes from the mismatch of the charge pump current. The current mismatch of the charge pump can be approximated by a piecewise linear (PWL) type nonlinear model. The PWL nonlinearity can be expressed as:

[0076]

[0077] Among them, t NL [n] is the integrated quantization error after nonlinear degradation, and ε is the mismatch coefficient.

[0078] The present invention aims at the PWL loop nonlinear model, reduces the amplitude of the periodic component in the nonlinear noise by changing the probability distribution mode of the integral quantization error of the Delta-Sigma modulator, and achieves a better spurious suppression effect on the decimal spurious introduced by the PWL nonlinearity.

[0079] like Figure 1 As shown, the present invention provides a modulator 11. Specifically, the modulator 11 is a Delta-Sigma modulator. The modulator 11 includes:

[0080] A multi-stage cascade modulation module 111 , a dithering module 112 , a high-pass filtering module 113 and an adding module 114 .

[0081] like Figure 1 As shown, the multi-stage cascade modulation module 111 receives an integer frequency division ratio and a fractional frequency division ratio, and obtains a digital frequency division ratio signal based on the integer frequency division ratio and the fractional frequency division ratio.

[0082] Specifically, in this embodiment, the multi-stage cascade modulation module 111 adopts the Delta-Sigma modulation structure of the MASH 1-1-1 topology, and the multi-stage cascade modulation module 111 converts the fractional frequency division ratio into a control word, and adds it to the control word corresponding to the integer frequency division ratio to obtain the digital frequency division ratio signal; the digital frequency division ratio signal is a digital signal, which reflects the integer frequency division ratio and the fractional frequency division ratio based on the signal average value within multiple cycles. In actual use, any circuit structure that can convert the integer frequency division ratio and the fractional frequency division ratio into a digital frequency division ratio signal is applicable to the present invention, and the number of cascade stages and the specific circuit structure can be configured as needed, and are not limited to this embodiment.

[0083] like Figure 1 As shown, the jitter module 112 is used to generate a pseudo-random sequence;

[0084] Specifically, the jitter module 112 generates a pseudo-random sequence with values ​​of 1 and -1 through a PRBS (Pseudo-Random Binary Sequence), and the average value of the pseudo-random sequence is 0.

[0085] like Figure 1 As shown, the high-pass filter module 113 is connected to the output end of the dither module 112 to filter the pseudo-random sequence output by the dither module 112 .

[0086] Specifically, the pseudo-random sequence output by the jitter module 112 will eventually be added to the output signal of the modulator 11, so the pseudo-random sequence will contribute additional quantization noise to the output of the modulator 11. The high-pass filter module 113 is used to perform high-pass filtering on the quantization noise of the pseudo-random sequence, pushing the quantization noise to high frequency so that it can be subsequently filtered out by the low-pass characteristics of the filter in the phase-locked loop. In order to achieve better quantization noise performance, the high-pass filter module 113 includes at least 2nd order filtering; in this example, the high-pass filter module 113 is set to a configuration with optional 2nd order and 3rd order filtering. As an example, Figure 1As shown, the high-pass filter module 113 includes a first-order filter unit 113a, a second-order filter unit 113b, a third-order filter unit 113c and a two-choice unit 113d. The first-order filter unit 113a, the second-order filter unit 113b and the third-order filter unit 113c are cascaded in sequence (i.e., the output end of the first-order filter unit 113a is connected to the input end of the second-order filter unit 113b, and the output end of the second-order filter unit 113b is connected to the input end of the third-order filter unit 113c), and the first-order filter unit 113a receives the pseudo-random sequence and transmits it to the second-order filter unit 113b and the third-order filter unit 113c in sequence for high-pass filtering. The input end of the two-select-one unit 113d is connected to the output end of the second-order filter unit 113b and the output end of the third-order filter unit 113c, respectively, and outputs the output signal of the second-order filter unit 113b or the output signal of the third-order filter unit 113c based on the filter order selection signal; when the filter order selection signal is in the first state, the output signal of the second-order filter unit 113b is selected and output to achieve 2nd order filtering, and when the filter order selection signal is in the second state, the output signal of the third-order filter unit 113c is selected and output to achieve 3rd order filtering. Among them, any circuit structure that can achieve high-pass filtering is applicable to each order filter unit of the present invention, and the specific structure is not repeated here one by one.

[0087] like Figure 1 As shown, the addition module 114 is connected to the output ends of the multi-stage cascade modulation module 111 and the high-pass filtering module 113, and adds the output signal of the multi-stage cascade modulation module 111 and the output signal of the high-pass filtering module 113 to obtain an output sequence (i.e., the output signal of the modulator 11).

[0088] Specifically, the addition module 114 implements the addition function. From the perspective of breaking up the periodicity, additional random jitter is added to the output signal of the multi-stage cascade modulation module 111. Since the average value of the additional random jitter is 0, it does not affect the fractional average value of the output sequence. At the same time, it can greatly increase the randomness of the output sequence, thereby achieving a strong breaking-up effect on the potential periodicity of the output sequence. From the perspective of PNN, adding additional random jitter actually completes the expansion of the probability distribution of the output signal of the multi-stage cascade modulation module 111 by convolving the two-part probability distribution (that is, the probability distribution range of the integral quantization error corresponding to the output sequence is greater than the probability distribution range of the integral quantization error corresponding to the digital division ratio signal), thereby changing the PNN waveform, and then changing the energy of the periodic component in the nonlinear noise to achieve the suppression of fractional spurs.

[0089] like Figure 2 As shown, the present invention further provides a fractional-frequency synthesizer 1, which comprises: a phase-locked loop circuit with a charge pump structure and the modulator 11.

[0090] like Figure 2 As shown, the modulator 11 receives the frequency division signal of the phase-locked loop circuit and is used to generate an output sequence, and the output sequence serves as the frequency division control signal of the phase-locked loop circuit.

[0091] Specifically, in this embodiment, the frequency division signal is used as the clock signal of the modulator 11, and the modulator 11 works based on the frequency division signal and generates an output sequence with an expanded probability distribution according to the integer frequency division ratio and the fractional frequency division ratio. The specific structure and principle are as described above, and will not be described here one by one.

[0092] like Figure 2 As shown, the phase-locked loop circuit generates a stable oscillation signal based on the output sequence provided by the modulator 11.

[0093] Specifically, in this embodiment, the phase-locked loop circuit includes a frequency detector 12, a charge pump 13, a loop filter 14, a voltage-controlled oscillator 15 and a multi-mode frequency divider 16. The frequency detector 12 receives a reference clock signal, is connected to the output end of the multi-mode frequency divider 16, and outputs the phase difference between the reference clock signal and the frequency-divided signal; the frequency detector 12 can detect both frequency and phase, and can obtain accurate phase difference information. The reference clock signal can be provided by a crystal oscillator 18. The charge pump 13 is connected to the output end of the frequency detector 12 to convert the phase difference into a current signal; as an example, the charge pump 13 includes a charging branch and a discharging branch, and the charging and discharging are controlled by the output signal of the frequency detector 12. The loop filter 14 is connected to the output end of the charge pump 13 to filter the output signal of the charge pump 13; the loop filter 14 can filter out high-frequency noise, including high-frequency noise in the loop and high-frequency noise output by the high-pass filter module 113. The voltage controlled oscillator 15 is connected to the output end of the loop filter 14, and generates an oscillation signal of a corresponding frequency based on the output signal of the loop filter 14; the frequency of the oscillation signal is related to the output signal of the loop filter 14. The multi-mode frequency divider 16 is connected to the output end of the voltage controlled oscillator 15, and performs fractional frequency division on the oscillation signal based on the frequency division control signal to obtain the frequency division signal; the multi-mode frequency divider 16 can adopt any circuit structure in the prior art that can realize multi-mode frequency division, which will not be described in detail here.

[0094] Specifically, as another implementation of the present invention, the phase-locked loop circuit further includes a frequency divider 17, which is connected to the output end of the voltage-controlled oscillator 15 and outputs the oscillation signal after frequency division. In this embodiment, the frequency divider 17 is an integer frequency divider, which is used to divide the oscillation signal output by the voltage-controlled oscillator 15 and apply it to the occasion where it is needed.

[0095] It should be noted that any phase-locked loop circuit with a charge pump structure is applicable to the present invention and is not limited to this embodiment.

[0096] like Figure 3 to Figure 5 As shown, the probability distribution of the modulator integral quantization error is analyzed. Figure 3 is a probability distribution diagram of the integrated quantization error of the multi-stage cascade modulation module 111 (i.e., the traditional Delta-Sigma modulator), the corresponding probability distribution range of the integrated quantization error is between -2 and 2, and the probability is more concentrated in the middle area; Figure 4 The probability distribution diagram of the integrated quantization error of the modulator of the present invention under the second-order filtering gear, and the corresponding probability distribution range of the integrated quantization error is between -4 and 4; Figure 5 The figure is a probability distribution diagram of the integral quantization error of the modulator of the present invention under the 3rd order filtering gear, and the corresponding probability distribution range of the integral quantization error is between -6 and 6; it can be seen that the modulator of the present invention expands the range of the probability distribution and disperses the probability distribution to both sides, and the expansion effect is more obvious as the filtering order increases.

[0097] like Figure 6 As shown, the PNN waveform is analyzed and the amplitude of the periodic component of the nonlinear noise of the multi-stage cascade modulation module 111 is the highest; the amplitude of the periodic component of the nonlinear noise of the modulator of the present invention is significantly weakened, and the higher the filtering order, the stronger the suppression effect of the periodic component.

[0098] like Figure 7 to Figure 9As shown, the fractional spurs introduced by the PWL nonlinearity are analyzed. The output power spectrum density of the multi-stage cascade modulation module 111 under the deterioration of the piecewise linear nonlinear model has very strong fractional spurs; the fractional spur suppression of the modulator of the present invention is obvious, and the higher the filter order, the stronger the fractional spur suppression effect. Specifically, when directly simulating the power spectrum density PSD, due to the influence of noise, the fractional spurs will be submerged by the noise, and the amplitude of the fractional spurs at this time cannot be correctly obtained. In order to facilitate the quantification of the spurious suppression effect, in addition to directly simulating the modulator output by PSD (lines in the figure), the energy of the fractional spurs is also predicted by performing PSD on the periodic component PNN of the nonlinear noise (triangles in the figure), and the predicted spurious energy can maintain a high degree of consistency with the PSD simulation results. According to the simulation data obtained by the prediction method, the fractional spurious energy of the multi-stage cascade modulation module 111 is -11dB (corresponding to the horizontal coordinate 10 -3 ),like Figure 7 As shown; the modulator of the present invention has a fractional stray energy of -17dB (corresponding to the horizontal axis 10 -3 ),like Figure 8 As shown, the fractional stray energy of the modulator of the present invention in the third-order filtering gear is -22dB (corresponding to the horizontal axis 10 -3 ), the decimal spurious suppression effect of more than 10dB can be achieved. At this time, the decimal spurious energy obtained by direct simulation is so low that it is submerged by the noise (abscissa 10 -3 The lines at the bottom have no raised peaks).

[0099] The present invention also provides a radio frequency receiver, which at least includes: a low noise amplifier, a down-conversion mixer and the fractional-frequency synthesizer 1; the low noise amplifier receives a radio frequency signal and performs amplification processing; the fractional-frequency synthesizer 1 is used to provide a local oscillator signal; the down-conversion mixer is connected to the output ends of the low noise amplifier and the fractional-frequency synthesizer 1, and is used to convert the radio frequency signal into an intermediate frequency signal to facilitate subsequent circuit processing.

[0100] The present invention also provides a radio frequency transmitter, which at least includes: an up-conversion mixer, a power amplifier and the fractional-frequency frequency synthesizer 1; the fractional-frequency frequency synthesizer 1 is used to provide a local oscillator signal; the up-conversion mixer is connected to the output end of the fractional-frequency frequency synthesizer 1, and receives an intermediate frequency signal and converts the intermediate frequency signal into a radio frequency signal; the power amplifier is connected to the output end of the up-conversion mixer, amplifies the radio frequency signal, and then transmits it through an antenna.

[0101] It should be noted that the RF receiver and the RF transmitter may share the same fractional-number frequency synthesizer 1 to form a RF transceiver.

[0102] The present invention also provides an electronic product, which at least comprises: the fractional frequency synthesizer 1, the hourly frequency synthesizer 1 is used to provide an oscillation signal of a required frequency. The electronic product can also be configured with corresponding functional modules according to actual needs, which will not be described one by one here.

[0103] The modulator of the present invention achieves a better suppression effect on the decimal spurs introduced by the loop nonlinearity, and the purity of the frequency spectrum output by the frequency synthesizer is greatly improved.

[0104] In summary, the present invention provides a modulator, a fractional frequency synthesizer, a radio frequency transceiver and an electronic product, comprising: a multi-stage cascade modulation module, a jitter module, a high-pass filter module and an addition module; the multi-stage cascade modulation module receives an integer frequency division ratio and a fractional frequency division ratio, and obtains a digital frequency division ratio signal based on the integer frequency division ratio and the fractional frequency division ratio; the jitter module is used to generate a pseudo-random sequence, and the pseudo-random sequence includes numerical values ​​1 and -1; the high-pass filter module is connected to the output end of the jitter module, and filters the pseudo-random sequence output by the jitter module; the addition module is connected to the output ends of the multi-stage cascade modulation module and the high-pass filter module, and adds the output signal of the multi-stage cascade modulation module with the output signal of the high-pass filter module to obtain an output sequence; wherein the probability distribution range of the integrated quantization error corresponding to the output sequence is greater than the probability distribution range of the integrated quantization error corresponding to the digital frequency division ratio signal output by the multi-stage cascade modulation module. The modulator, fractional frequency synthesizer, radio frequency transceiver and electronic product of the present invention add additional random jitter to the output signal of the multi-stage cascade modulation module, greatly increase the randomness of the modulator output sequence, and achieve a strong effect of breaking up the potential periodicity of the output sequence; by expanding the probability distribution range of the output signal of the multi-stage cascade modulation module, changing the PNN waveform, and then changing the energy of the periodic component in the nonlinear noise, the immunity to loop nonlinearity is improved, and then the effect of improving the fractional spurious performance is achieved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A modulator, characterized in that: The modulator comprises at least: Multi-stage cascade modulation module, dithering module, high-pass filtering module and adding module; The multi-stage cascade modulation module receives an integer frequency division ratio and a fractional frequency division ratio, and obtains a digital frequency division ratio signal based on the integer frequency division ratio and the fractional frequency division ratio; The jitter module is used to generate a pseudo-random sequence, the pseudo-random sequence includes values ​​1 and -1, and the average value of the pseudo-random sequence is 0; The high-pass filter module is connected to the output end of the dither module to filter the pseudo-random sequence output by the dither module; the high-pass filter module includes a first-order filter unit, a second-order filter unit, a third-order filter unit and a two-choice unit; the first-order filter unit, the second-order filter unit and the third-order filter unit are cascaded in sequence, and the first-order filter unit receives the pseudo-random sequence; the input end of the two-choice unit is respectively connected to the output end of the second-order filter unit and the third-order filter unit, and the output signal of the second-order filter unit or the output signal of the third-order filter unit is output based on the filter order selection signal; The adding module is connected to the output ends of the multi-stage cascade modulation module and the high-pass filtering module, and adds the output signal of the multi-stage cascade modulation module and the output signal of the high-pass filtering module to obtain an output sequence; The probability distribution range of the integrated quantization error corresponding to the output sequence is greater than the probability distribution range of the integrated quantization error corresponding to the digital frequency division ratio signal generated by the multi-stage cascade modulation module.

2. The modulator according to claim 1, characterized in that: The multi-stage cascade modulation module is a Delta-Sigma modulation structure of MASH 1-1-1 topology.

3. The modulator according to claim 1, characterized in that: The high-pass filtering module includes at least a second-order filter.

4. A fractional frequency synthesizer, characterized in that: The fractional frequency synthesizer comprises at least: a phase-locked loop circuit with a charge pump structure and a modulator as claimed in any one of claims 1 to 3; The modulator receives the frequency division signal of the phase-locked loop circuit and is used to generate an output sequence, and the output sequence serves as the frequency division control signal of the phase-locked loop circuit.

5. The fractional frequency synthesizer according to claim 4, characterized in that: The phase-locked loop circuit includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a multi-mode frequency divider; The frequency detector receives the reference clock signal and is connected to the output end of the multi-mode frequency divider to output the phase difference between the reference clock signal and the frequency division signal; The charge pump is connected to the output end of the frequency detector and phase detector to convert the phase difference into a current signal; The loop filter is connected to the output end of the charge pump to filter the output signal of the charge pump; The voltage-controlled oscillator is connected to the output end of the loop filter, and generates an oscillation signal of a corresponding frequency based on the output signal of the loop filter; The multi-mode frequency divider is connected to the output end of the voltage-controlled oscillator, and performs fractional frequency division on the oscillation signal based on the frequency division control signal to obtain the frequency division signal.

6. The fractional frequency synthesizer according to claim 5, characterized in that: The phase-locked loop circuit also includes a frequency divider, which is connected to the output end of the voltage-controlled oscillator and outputs the oscillation signal after frequency division.

7. A radio frequency receiver, characterized in that: The radio frequency receiver at least comprises: A low noise amplifier, a down-conversion mixer and a fractional frequency synthesizer as claimed in any one of claims 4 to 6; The low noise amplifier receives the radio frequency signal and performs amplification processing; The fractional frequency synthesizer is used to provide a local oscillator signal; The down-conversion mixer is connected to the output ends of the low noise amplifier and the fractional frequency synthesizer to convert the radio frequency signal into an intermediate frequency signal.

8. A radio frequency transmitter, characterized in that: The radio frequency transmitter at least comprises: An up-conversion mixer, a power amplifier and a fractional frequency synthesizer as claimed in any one of claims 4 to 6; The fractional frequency synthesizer is used to provide a local oscillator signal; The up-conversion mixer is connected to the output end of the fractional frequency synthesizer, receives an intermediate frequency signal, and converts the intermediate frequency signal into a radio frequency signal; The power amplifier is connected to the output end of the up-conversion mixer to amplify the radio frequency signal.

9. An electronic product, characterized in that: The electronic product at least includes: the fractional-frequency synthesizer as described in any one of claims 4-6.

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