Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate with a first surface; arranging a plurality of transistors on the first surface in a first preset pattern; arranging a plurality of transistor contact structures in one-to-one correspondence with the transistors, the bottom of each transistor contact structure being in contact with a transistor, the bottom of each transistor contact structure being arranged in the first preset pattern, and the top of each transistor contact structure being arranged in a regular hexagon; arranging a plurality of storage elements in one-to-one correspondence with the transistor contact structures, the bottom of each storage element being in contact with the top of a transistor contact structure, and the storage elements being arranged in a regular hexagon; and arranging a plurality of storage contact structures in one-to-one correspondence with the storage elements, the bottom of each storage contact structure being in contact with the top of a storage element, the bottom of each storage contact structure being arranged in a regular hexagon, the top of each storage contact structure being arranged in a second preset pattern, and the second preset pattern being different from the first preset pattern. The process difficulty and production cost are reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Non-volatile memory features high-speed read / write, low power consumption, radiation resistance, and long data retention time, making it irreplaceable in fields with high reliability requirements, such as aerospace.

[0003] With the development of semiconductor technology, the capacity requirements for non-volatile memories (NVRs) are becoming increasingly stringent. To improve the capacity of NVRs, it is necessary to densely arrange memory elements. However, since memory elements are located between transistors and bit line structures, changing the arrangement of memory elements requires corresponding adjustments to the positions of transistors and the shape of the bit line structures. This increases the production cost and process difficulty of NVRs. How to achieve dense arrangement of memory elements without changing the positions of transistors and the shape of the bit line structures has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a semiconductor structure and its fabrication method, which can optimize the semiconductor structure fabrication process and achieve the goal of influencing the position of transistors and the shape of bit line structures by the arrangement of memory elements.

[0005] A semiconductor structure, comprising: The substrate has a first surface; Several transistors are located on the first surface, and the transistors are arranged according to a first preset pattern; A number of transistor contact structures are provided, each corresponding to a transistor. The bottom of the transistor contact structure is in contact with the transistor. The bottom of the transistor contact structure is arranged according to the first preset pattern, and the top of the transistor contact structure is arranged in a regular hexagonal pattern. Several storage elements correspond one-to-one with transistor contact structures. The bottom of the storage element contacts the top of the transistor contact structure. The storage elements are arranged in a regular hexagonal pattern, with each storage element located at the vertex and center of the regular hexagon. Several storage contact structures correspond one-to-one with storage elements. The bottom of the storage contact structure contacts the top of the storage element. The bottom of the storage contact structure is arranged in a regular hexagonal pattern, and the top of the storage contact structure is arranged in a second preset pattern. The second preset pattern is different from the first preset pattern. The bottom and top of the transistor contact structure are positioned opposite each other, as are the bottom and top of the storage contact structure.

[0006] In one embodiment, the first preset pattern arrangement includes a regular hexagon, with each transistor located at the vertex and center of the regular hexagon.

[0007] In one embodiment, the area of ​​the top of the transistor contact structure is equal to the area of ​​the bottom of the transistor contact structure.

[0008] In one embodiment, the second preset graphic includes a multi-row, multi-column arrangement array.

[0009] In one embodiment, the area of ​​the bottom of the storage contact structure is larger than the area of ​​the top of the storage contact structure.

[0010] In one embodiment, the first preset graphic includes a multi-row, multi-column arrangement array.

[0011] In one embodiment, the area of ​​the top of the transistor contact structure is smaller than the area of ​​the bottom of the transistor contact structure.

[0012] In one embodiment, the second preset shape includes a regular hexagon, and the storage contact structure is located at the vertex and center of the regular hexagon.

[0013] In one embodiment, the area of ​​the top of the storage contact structure is equal to the area of ​​the bottom of the storage contact structure.

[0014] In one embodiment, the transistor contact structure includes: The first lead-out structure has its bottom being the bottom of the transistor contact structure; The bottom of the second lead-out structure is in contact with the top of the first lead-out structure, and the top of the second lead-out structure is the top of the transistor contact structure. The bottom and top of the first lead-out structure are positioned opposite each other, and the bottom and top of the second lead-out structure are positioned opposite each other.

[0015] In one embodiment, the area of ​​the bottom of the second lead-out structure is not less than the area of ​​the top of the first lead-out structure.

[0016] In one embodiment, the semiconductor structure further includes: The word line structure is in contact with the gate region of the transistor; The source line structure is in contact with the source region of the transistor; In this configuration, the drain region of the transistor is in contact with the bottom of the transistor contact structure.

[0017] In one embodiment, the storage element includes a phase change storage element, a ferroelectric storage element, a magnetoresistive storage element, a resistive switching storage element, or a phase change storage element.

[0018] In one embodiment, the semiconductor structure further includes: Several bit line structures, each bit line structure being in contact with the top of a storage contact structure located in the same column.

[0019] In one embodiment, the semiconductor structure further includes: Several bit line structures, each bit line structure is in contact with the top of two adjacent columns of storage contact structures.

[0020] This application also provides a method for fabricating a semiconductor structure, including: Provide a substrate having a first surface; A plurality of transistors are formed on the first surface, and the transistors are arranged according to a first preset pattern; Transistor contact structures are formed on each transistor. The bottom of the transistor contact structure is in contact with the transistor. The bottom of the transistor contact structure is arranged according to a first preset pattern, and the top of the transistor contact structure is arranged in a regular hexagonal pattern. Storage elements are formed on the top of each transistor contact structure. The storage elements are arranged in a regular hexagon, with each storage element located at the vertex and center of the regular hexagon. Storage contact structures are formed on the top of each storage element. The bottom of the storage contact structures is arranged in a regular hexagonal pattern, and the top of the storage contact structures is arranged in a second preset pattern, which is different from the first preset pattern. The bottom and top of the transistor contact structure are positioned opposite each other, as are the bottom and top of the storage contact structure.

[0021] In one embodiment, the first preset pattern includes a regular hexagon, with each transistor located at the vertex and center of the regular hexagon; The area of ​​the top of the transistor contact structure is equal to the area of ​​the bottom of the transistor contact structure.

[0022] In one embodiment, the second preset graphic includes a multi-row, multi-column array; The area at the bottom of the storage contact structure is larger than the area at the top of the storage contact structure.

[0023] In one embodiment, the first preset graphic includes a multi-row, multi-column array; The area at the top of the transistor contact structure is smaller than the area at the bottom of the transistor contact structure.

[0024] In one embodiment, the second preset shape includes a regular hexagon, and the storage contact structure is located at the vertex and center of the regular hexagon.

[0025] The aforementioned semiconductor structure includes a plurality of transistors located on a first surface, the transistors being arranged according to a first preset pattern; a plurality of transistor contact structures corresponding one-to-one with the transistors, the bottom of the transistor contact structure contacting the transistors, the bottom of the transistor contact structure being arranged according to the first preset pattern, and the top of the transistor contact structure being arranged in a regular hexagonal pattern; a plurality of memory elements corresponding one-to-one with the transistor contact structures, the bottom of the memory elements contacting the top of the transistor contact structures, the memory elements being arranged in a regular hexagonal pattern, each memory element located at a vertex and a center position of the regular hexagon; a plurality of memory contact structures corresponding one-to-one with the memory elements, the bottom of the memory contact structures contacting the top of the memory elements, the bottom of the memory contact structures being arranged in a regular hexagonal pattern, and the top of the memory contact structures being arranged according to a second preset pattern, the second preset pattern being different from the first preset pattern; wherein, the bottom and top of the transistor contact structures are positioned opposite each other, and the bottom and top of the memory contact structures are positioned opposite each other. By setting a transistor contact structure with the bottom arranged in the first preset pattern and the top arranged in a regular hexagon, and a storage contact structure with the bottom arranged in a regular hexagon and the top arranged in the second preset pattern, the fabrication of the transistor, storage element and the device structure above the storage element is realized without changing the position or shape of the device structure above the storage element, thereby reducing the process difficulty and production cost.

[0026] The above-described method for fabricating a semiconductor structure provides a substrate having a first surface; a plurality of transistors are formed on the first surface, the transistors being arranged according to a first preset pattern; a transistor contact structure is formed on each transistor, the bottom of the transistor contact structure being in contact with the transistor, the bottom of the transistor contact structure being arranged according to the first preset pattern, and the top of the transistor contact structure being arranged in a regular hexagonal pattern; a memory element is formed on the top of each transistor contact structure, the memory element being arranged in a regular hexagonal pattern, with each memory element located at a vertex and a center of the regular hexagon; a memory contact structure is formed on the top of each memory element, the bottom of the memory contact structure being arranged in a regular hexagonal pattern, and the top of the memory contact structure being arranged according to a second preset pattern, the second preset pattern being different from the first preset pattern; wherein, the bottom and top of the transistor contact structure are positioned opposite each other, and the bottom and top of the memory contact structure are positioned opposite each other. By setting a transistor contact structure with the bottom arranged in the first preset pattern and the top arranged in a regular hexagon between the transistor and the memory element, and setting a memory contact structure with the bottom arranged in a regular hexagon and the top arranged in the second preset pattern on the top of the memory element, the fabrication of the transistor, the memory element and the device structure above the memory element is realized without changing the position or shape of the device structure above the transistor and the memory element, thereby reducing the process difficulty and production cost. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure in the first embodiment; Figure 2 This is a top view of the transistor contact structure in a semiconductor structure after the transistor contact structure has been formed in one embodiment. Figure 3 This is a top view of a semiconductor structure in one embodiment; Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure in the second embodiment; Figure 5 This is a cross-sectional schematic diagram of a storage element in one embodiment; Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment; Figure 7 This is a flowchart illustrating step S106 in one embodiment; Figure 8 This is a schematic cross-sectional view of the semiconductor structure after forming a transistor contact mask layer in one embodiment; Figure 9 for Figure 8 A cross-sectional schematic diagram of the semiconductor structure after the transistor contact structure is formed in one corresponding embodiment; Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after the memory element is formed in one corresponding embodiment; Figure 11 for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after forming the bit line mask layer in one corresponding embodiment; Figure 12 for Figure 11 A cross-sectional schematic diagram of the semiconductor structure after the bit line structure is formed in one corresponding embodiment.

[0029] Explanation of reference numerals in the attached figures: 100, Substrate; 102, Transistor; 104, Transistor Contact Structure; 106, Storage Element; 108, Storage Contact Structure; 110, Word Line Structure; 112, Source Line Structure; 114, Bit Line Structure; 202, First Lead-Out Structure; 204, Second Lead-Out Structure; 206, Bottom Electrode; 208, Metal Layer; 210, Phase Change Material Layer; 212, Top Electrode; 214, Interlayer Dielectric Layer; 216, Protective Layer; 302, First Contact Structure; 304, First Conductive Thin Film; 306, Transistor Contact Mask Layer; 308, First Dielectric Layer; 310, Second Dielectric Layer; 312, Storage Contact Trench; 314, Third Dielectric Layer; 316, Bit Line Structure Layer; 318, Bit Line Mask Layer; 320, Fourth Dielectric Layer. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type. Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly. When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items. After semiconductor technology reached the 22nm node, flash memory technology, which relies on floating gates to store charge, encountered difficulties in shrinking its size. At this time, phase-change random access memory (PCRAM) technology has been widely used due to its significant advantages over flash memory technology in many aspects, such as cell area, read / write speed, read / write cycles, and data retention time.

[0033] To ensure data accuracy while increasing the integration density of storage elements in PCRAM, a dense arrangement of these elements is crucial. However, since the storage elements are located between transistors and bit line structures, changing the arrangement of these elements requires corresponding adjustments to the positions of the transistors and the shape of the bit line structures, which increases the manufacturing cost and process complexity of PCRAM.

[0034] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure in the first embodiment. See [link / reference]. Figure 1 In this embodiment, a semiconductor structure is provided, including: a substrate 100, a plurality of transistors 102, a plurality of transistor contact structures 104, a plurality of memory elements 106, and a plurality of memory contact structures 108; the substrate 100 has a first surface, the transistors 102 are located on the first surface, and each transistor 102 is arranged according to a first preset pattern, that is, each transistor 102 is arranged on the first surface of the substrate 100 according to the first preset pattern; the transistor contact structures 104 are located between the transistors 102 and the memory elements 106, and are in contact with the transistors 102 and the memory elements 106 respectively, that is, the bottom of the transistor contact structure 104 is in contact with the transistors 102, and the top of the transistor contact structure 104 is in contact with the memory elements 106, the transistor contact structures 104 correspond one-to-one with the transistors 102, the bottom of the transistor contact structure 104 is arranged according to the first preset pattern, and the top of the transistor contact structure 104 is arranged according to the first preset pattern. The storage elements 106 are arranged in a regular hexagonal pattern; each storage element 106 corresponds to a transistor contact structure 104, and the storage elements 106 are arranged in a regular hexagonal pattern, with each storage element 106 located at the vertex and center of the regular hexagon; each storage contact structure 108 corresponds to a storage element 106, with the bottom of the storage contact structure 108 contacting the top of the storage element 106, the bottom of the storage contact structure 108 arranged in a regular hexagonal pattern, and the top of the storage contact structure 108 arranged in a second preset pattern, which is different from the first preset pattern; wherein, the bottom and top of the transistor contact structure 104 are arranged opposite each other, and the bottom and top of the storage contact structure 108 are arranged opposite each other, that is, the bottom and top of the transistor contact structure 104 are arranged parallel to each other, and the bottom and top of the storage contact structure 108 are arranged parallel to each other.

[0035] The aforementioned semiconductor structure includes a plurality of transistors 102 located on a first surface, the transistors 102 being arranged in a first preset pattern; a plurality of transistor contact structures 104 corresponding one-to-one with the transistors 102, the bottom of the transistor contact structure 104 contacting the transistors 102, the bottom of the transistor contact structure 104 being arranged in the first preset pattern, and the top of the transistor contact structure 104 being arranged in a regular hexagonal pattern; and a plurality of storage elements 106 corresponding one-to-one with the transistor contact structures 104, the bottom of the storage element 106 contacting the top of the transistor contact structure 104, and the storage elements 106 being arranged in a regular hexagonal pattern. The storage elements 106 are arranged in a hexagonal pattern, with each element 106 located at the vertex and center of the hexagon. Several storage contact structures 108 correspond one-to-one with each storage element 106. The bottom of each storage contact structure 108 contacts the top of the storage element 106. The bottom of the storage contact structures 108 is arranged in a hexagonal pattern, while the top of each storage contact structure 108 is arranged in a second preset pattern, which differs from the first preset pattern. The bottom and top of transistor contact structures 104 and storage contact structures 108 are also arranged opposite each other. By setting transistor contact structures 104 with bottoms arranged in the first preset pattern and tops arranged in a hexagonal pattern, and storage contact structures 108 with bottoms arranged in a hexagonal pattern and tops arranged in the second preset pattern, the fabrication of transistors 102, storage elements 106, and the device structures above storage elements 106 is achieved without changing the position or shape of the structures, thus reducing the complexity of the process and production costs.

[0036] Figure 2 This is a top view of the transistor contact structure 104 in a semiconductor structure after the transistor contact structure 104 has been formed in one embodiment, as shown below. Figure 2 As shown, in one embodiment, the first preset pattern arrangement includes a regular hexagon, with each transistor 102 located at the vertex and center of the regular hexagon. In this case, the transistor contact structure 104 is a columnar structure above the transistor 102, and the top and bottom of the transistor contact structure 104 are projected onto the first surface in a perpendicular manner.

[0037] In one embodiment, the area of ​​the top of the transistor contact structure 104 is equal to the area of ​​the bottom of the transistor contact structure 104.

[0038] Figure 3 This is a top view schematic diagram of a semiconductor structure in one embodiment, such as... Figure 3 As shown, in one embodiment, the second preset graphic includes a multi-row, multi-column arrangement array.

[0039] In one embodiment, the area of ​​the bottom of the storage contact structure 108 is larger than the area of ​​the top of the storage contact structure 108.

[0040] In one embodiment, the area of ​​the bottom of the storage contact structure 108 is larger than the area of ​​the top of the storage element 106. In other embodiments, the area of ​​the bottom of the storage contact structure 108 is less than or equal to the area of ​​the top of the storage element 106. This arrangement allows for close contact between the storage contact structure 108 and the storage element 106 while avoiding damage to the storage element 106 during the formation of the storage contact structure 108.

[0041] In one embodiment, the material of the storage contact structure 108 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0042] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure in the second embodiment, as shown below. Figure 4 As shown, in one embodiment, the first preset graphic includes a multi-row, multi-column arrangement array.

[0043] In one embodiment, the area of ​​the top of the transistor contact structure 104 is smaller than the area of ​​the bottom of the transistor contact structure 104.

[0044] Continue to refer to Figure 4 In one embodiment, the second preset shape includes a regular hexagon, and the storage contact structure 108 is located at the vertex and center of the regular hexagon.

[0045] In one embodiment, the area of ​​the top of the storage contact structure 108 is equal to the area of ​​the bottom of the storage contact structure 108.

[0046] Continue to refer to Figure 1 , Figure 4In one embodiment, the transistor contact structure 104 includes: a first lead-out structure 202 and a second lead-out structure 204; the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 104, and the first lead-out structure 202 is used to lead out the transistor 102; exemplaryly, the bottom of the first lead-out structure 202 is connected to the drain region of the transistor 102, and is used to lead out the drain region of the transistor 102. Typically, the area of ​​the bottom of the first lead-out structure 202 is equal to the area of ​​the drain region of the transistor 102; the bottom of the second lead-out structure 204 is in contact with the top of the first lead-out structure 202, and the top of the second lead-out structure 204 is the top of the transistor contact structure 104; wherein, the bottom and top of the first lead-out structure 202 are arranged opposite to each other, and the bottom and top of the second lead-out structure 204 are arranged opposite to each other. At this time, the bottom of the first lead-out structure 202 is arranged according to a first preset pattern, and the top of the second lead-out structure 204 is arranged in a regular hexagonal pattern.

[0047] In one embodiment, the area of ​​the bottom of the second lead-out structure 204 is not less than the area of ​​the top of the first lead-out structure 202.

[0048] In one embodiment, the portion of the first lead-out structure 202 near the bottom of the second lead-out structure 204 is a trapezoidal structure.

[0049] In one embodiment, the materials of the first lead-out structure 202 and the second lead-out structure 204 include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, at least one of the storage contact structure 108, the first lead-out structure 202, and the second lead-out structure 204 may be made of a different material than others; for example, the material of the first lead-out structure 202 may be different from the materials of the storage contact structure 108 and the second lead-out structure 204. In practical applications, the same material may also be selected to prepare the storage contact structure 108, the first lead-out structure 202, and the second lead-out structure 204 as needed.

[0050] In one embodiment, the storage element 106 includes a phase change storage element, a ferroelectric storage element, a magnetoresistive storage element, a resistive switching storage element, or a phase change storage element.

[0051] Figure 5 This is a cross-sectional schematic diagram of the storage element 106 in one embodiment. For example... Figure 5As shown, in this embodiment, the storage element 106 is a phase-change storage element. The phase-change storage element includes a bottom electrode 206, a metal layer 208, a phase-change material layer 210, and a top electrode 212. The bottom electrode 206 is in contact with the upper surface of the transistor contact structure 104. The metal layer 208 is located on the upper surface of the bottom electrode 206, and the phase-change material layer 210 is located on the upper surface of the metal layer 208. According to the applied voltage or current pulse signal with different widths and heights, a reversible phase transition occurs between the crystalline state (low-resistance state) and the amorphous state (high-resistance state), thereby realizing the writing ("1") and erasing ("0") operations of information. The top electrode layer is located on the upper surface of the phase-change material layer 210. For example, the material of the phase-change material layer 210 includes chalcogenide materials, synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5.

[0052] In one embodiment, the materials of the bottom electrode 206, metal layer 208, and top electrode 212 include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, at least one structure of the bottom electrode 206, metal layer 208, and top electrode 212 may be made of a different material than the others; for example, the material of the top electrode 212 may be different from the materials of the bottom electrode 206 and metal layer 208. In practical applications, the same materials may be selected to prepare the bottom electrode 206, metal layer 208, and top electrode 212 as needed.

[0053] The basic storage principle of Phase Change Random Access Memory (PCRAM) is to apply voltage or current pulse signals of different widths and heights between the bottom electrode 206 and the top electrode 212 of the storage element 106, causing a physical phase change in the phase change material layer 210. Specifically, the phase change material layer 210 undergoes a reversible phase transition between a crystalline state (low-resistance state) and an amorphous state (high-resistance state), thereby enabling the writing ("1") and erasing ("0") operations of information. The mutual conversion process includes two processes: amorphization from crystalline to amorphous and crystallization from amorphous to crystalline. The former is called the amorphization process, and the latter is called the crystallization process. Information is then read out by measuring and comparing the resistance difference between the two physical phase states. This non-destructive reading process ensures accurate reading of the information stored in the device cell. The phase change material layer 210 has a resistivity difference of several orders of magnitude between its crystalline and amorphous states, which gives it a high noise margin, sufficient to distinguish between the "0" state and the "1" state.

[0054] In one embodiment, the phase change memory element further includes an interlayer dielectric layer 214 located between the bottom electrode 206 and the top electrode 212. A through trench is formed in the interlayer dielectric layer 214, and a metal layer 208 and a phase change material layer 210 are sequentially filled in the trench. Exemplarily, the material of the interlayer dielectric layer 214 includes oxides and oxynitrides, such as silicon dioxide or silicon nitride. Exemplarily, the width of the trench along the X direction is not less than 10 nanometers and not more than 20 nanometers.

[0055] Continue to refer to Figure 5 In other embodiments, the phase change memory element further includes a protective layer 216 covering the sidewall of the bottom electrode 206 and extending along the sidewall of the bottom electrode 206 to cover the sidewall of the top electrode 212. Exemplarily, the protective layer 216 is made of silicon nitride.

[0056] Continue to refer to Figure 1 , Figure 4 In one embodiment, the semiconductor structure further includes: a plurality of word line structures 110 and a plurality of source line structures 112; the word line structures 110 are in contact with the gate region of the transistor 102, i.e., connected to the gate region of the transistor 102, and the source line structures 112 are in contact with the source region of the transistor 102, i.e. connected to the source region of the transistor 102; wherein, the drain region of the transistor 102 is in contact with the bottom of the transistor contact structure 104.

[0057] like Figure 1 , Figure 3 As shown, in one embodiment, the semiconductor structure further includes a plurality of bit line structures 114, each bit line structure 114 being in contact with the top of a memory contact structure 108 located in the same column, and the bit line structure 114 being a straight line. For example, the length of the bit line structure 114 along the X direction is not less than the length of the top of the memory contact structure 108 along the X direction, and the X direction intersects the extending direction of the bit line structure 114.

[0058] like Figure 4 As shown, in one embodiment, the semiconductor structure further includes: a plurality of bit line structures 114, any bit line structure 114 being in contact with the top of two adjacent columns of memory contact structures 108, the bit line structure 114 being a broken line and being in contact with and connected to the two adjacent columns of memory contact structures 108.

[0059] Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment, as shown below. Figure 6 As shown, in this embodiment, a method for fabricating a semiconductor structure is provided, comprising: S102 provides a substrate having a first surface.

[0060] S104, a plurality of transistors arranged in a first preset pattern are formed on the first surface.

[0061] like Figure 1 As shown, a plurality of transistors 102 are formed on the first surface of the substrate 100, and each transistor 102 is arranged on the first surface of the substrate 100 according to a first preset pattern.

[0062] S106, transistor contact structures are formed on each transistor respectively.

[0063] Transistor contact structures 104 are formed on each transistor 102. The bottom of the transistor contact structure 104 is in contact with the transistor 102. The bottom of the transistor contact structure 104 is arranged according to a first preset pattern, and the top of the transistor contact structure 104 is arranged in a regular hexagonal pattern. The bottom and top of the transistor contact structure 104 are arranged opposite to each other, that is, the bottom and top of the transistor contact structure 104 are arranged parallel to each other.

[0064] S108, storage elements are formed on the top of each transistor contact structure.

[0065] Storage elements 106 are formed on the top of each transistor contact structure 104. Each storage element 106 corresponds to a transistor contact structure 104. The storage elements 106 are arranged in a regular hexagonal pattern, with each storage element 106 located at the vertex and center of the regular hexagon.

[0066] S110, a storage contact structure is formed on the top of each storage element, with the top arranged according to a second preset pattern.

[0067] Storage contact structures 108 are formed on the top of each storage element 106. The bottom of the storage contact structure 108 is arranged in a regular hexagonal pattern, and the top of the storage contact structure 108 is arranged in a second preset pattern, which is different from the first preset pattern. The bottom and top of the storage contact structure 108 are arranged opposite to each other, that is, the bottom and top of the storage contact structure 108 are arranged parallel to each other.

[0068] The method for fabricating the above-described semiconductor structure includes providing a substrate 100 having a first surface; forming a plurality of transistors 102 on the first surface, the transistors 102 being arranged according to a first preset pattern; forming transistor contact structures 104 on each transistor 102, the bottom of the transistor contact structure 104 being in contact with the transistor 102, the bottom of the transistor contact structure 104 being arranged according to the first preset pattern, and the top of the transistor contact structure 104 being arranged in a regular hexagonal pattern; and forming a storage element 106 on the top of each transistor contact structure 104. The storage elements 106 are arranged in a regular hexagonal pattern, with each storage element 106 located at the vertex and center of the regular hexagon. Storage contact structures 108 are formed on the top of each storage element 106. The bottom of the storage contact structure 108 is arranged in a regular hexagonal pattern, and the top of the storage contact structure 108 is arranged in a second preset pattern, which is different from the first preset pattern. The bottom and top of the transistor contact structure 104 are positioned opposite each other, and the bottom and top of the storage contact structure 108 are positioned opposite each other. By setting a transistor contact structure 104 with its bottom arranged in the first preset pattern and its top arranged in a regular hexagonal pattern between the transistor 102 and the storage element 106, and setting a storage contact structure 108 with its bottom arranged in a regular hexagonal pattern and its top arranged in the second preset pattern on the top of the storage element 106, the fabrication of the transistor 102, the storage element 106 and the device structure above the storage element 106 is realized without changing the position or shape of the device structure above the transistor 102 and the storage element 106, thereby reducing the difficulty of the process and the production cost.

[0069] like Figure 2 As shown, in one embodiment, the first preset pattern includes a regular hexagon, with each transistor 102 located at the vertex and center of the regular hexagon. At this time, the transistor contact structure 104 is a columnar structure above the transistor 102, and the top and bottom of the transistor contact structure 104 are projected onto the first surface.

[0070] In one embodiment, the area of ​​the top of the transistor contact structure 104 is equal to the area of ​​the bottom of the transistor contact structure 104.

[0071] like Figure 3 As shown, in one embodiment, the second preset graphic includes a multi-row, multi-column arrangement array.

[0072] In one embodiment, the area of ​​the bottom of the storage contact structure 108 is larger than the area of ​​the top of the storage contact structure 108.

[0073] In one embodiment, the area of ​​the bottom of the storage contact structure 108 is larger than the area of ​​the top of the storage element 106. In other embodiments, the area of ​​the bottom of the storage contact structure 108 is less than or equal to the area of ​​the top of the storage element 106. This arrangement allows for close contact between the storage contact structure 108 and the storage element 106 while avoiding damage to the storage element 106 during the formation of the storage contact structure 108.

[0074] In one embodiment, the material of the storage contact structure 108 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0075] like Figure 4 As shown, in one embodiment, the first preset graphic includes a multi-row, multi-column arrangement array.

[0076] In one embodiment, the area of ​​the top of the transistor contact structure 104 is smaller than the area of ​​the bottom of the transistor contact structure 104.

[0077] Continue to refer to Figure 4 In one embodiment, the second preset shape includes a regular hexagon, and the storage contact structure 108 is located at the vertex and center of the regular hexagon.

[0078] In one embodiment, the area of ​​the top of the storage contact structure 108 is equal to the area of ​​the bottom of the storage contact structure 108.

[0079] Figure 7 This is a flowchart illustrating step S106 in one embodiment, as shown below. Figure 1 , Figure 4 , Figure 7 As shown, in one embodiment, the transistor contact structure 104 includes: a first lead-out structure 202 and a second lead-out structure 204; step S106 includes: S202, a first lead-out structure is formed on each transistor, and the bottom of the first lead-out structure is in contact with the transistor.

[0080] Specifically, the bottom of the first lead-out structure 202 is in contact with the transistor 102 for leading out the transistor 102; for example, the bottom of the first lead-out structure 202 is connected to the drain region of the transistor 102 for leading out the drain region of the transistor 102, and typically, the area of ​​the bottom of the first lead-out structure 202 is equal to the area of ​​the drain region of the transistor 102.

[0081] S204, a second lead-out structure is formed on top of the first lead-out structure, and the top of the second lead-out structure is in contact with the bottom of the storage element.

[0082] Specifically, the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 104, and the top of the second lead-out structure 204 is the top of the transistor contact structure 104. The bottom and top of the first lead-out structure 202 are positioned opposite each other, and the bottom and top of the second lead-out structure 204 are also positioned opposite each other. At this time, the bottom of the first lead-out structure 202 is arranged according to a first preset pattern, and the top of the second lead-out structure 204 is arranged in a regular hexagonal pattern. When the first preset pattern is a regular hexagon, both the bottom of the first lead-out structure 202 and the top of the second lead-out structure 204 are arranged in a regular hexagonal pattern.

[0083] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after forming the transistor contact mask layer in one embodiment. Figure 9 for Figure 8 A cross-sectional schematic diagram of the semiconductor structure after the transistor contact structure is formed in one corresponding embodiment.

[0084] like Figure 8 , Figure 9 As shown, the first preset pattern is a multi-row, multi-column array. In the first step, a first contact structure 302, a first conductive film 304, and a transistor contact mask layer 306 are sequentially formed on the substrate 100 on which the transistor 102 is formed. The first contact structure 302 is connected to the drain region of the transistor 102. A first dielectric layer 308 with its upper surface flush with the upper surface of the first contact structure 302 is filled between adjacent first contact structures 302. The first conductive film 304 is located on the upper surface of the first contact structure 302, and the transistor contact mask layer 306 is located on the first conductive film 304, thus defining the shape and position of the transistor contact structure 104. The second step involves firstly removing a portion of the first conductive film 304, a portion of the first contact structure 302, and a portion of the first dielectric layer 308 using an etching process, using the transistor contact mask layer 306 as a mask. This yields a first lead-out structure 202 composed of the remaining first contact structure 302 and a second lead-out structure 204 composed of the remaining first conductive film 304. It is understood that in some embodiments, the etching process only removes the first conductive film 304 and the first contact structure 302 not covered by the transistor contact mask layer 306, forming the second lead-out structure 204 and the first lead-out structure 202. Next, a second dielectric layer 310 with an upper surface flush with the upper surface of the second lead-out structure 204 is filled between adjacent second lead-out structures 204.

[0085] In one embodiment, the area of ​​the bottom of the second lead-out structure 204 is not less than the area of ​​the top of the first lead-out structure 202.

[0086] In one embodiment, the portion of the first lead-out structure 202 near the bottom of the second lead-out structure 204 is a trapezoidal structure.

[0087] In one embodiment, the materials of the first lead-out structure 202 and the second lead-out structure 204 include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, at least one of the storage contact structure 108, the first lead-out structure 202, and the second lead-out structure 204 may be made of a different material than others; for example, the material of the first lead-out structure 202 may be different from the materials of the storage contact structure 108 and the second lead-out structure 204. In practical applications, the same material may also be selected to prepare the storage contact structure 108, the first lead-out structure 202, and the second lead-out structure 204 as needed.

[0088] In one embodiment, the storage element 106 includes a phase change storage element, a ferroelectric storage element, a magnetoresistive storage element, a resistive switching storage element, or a phase change storage element.

[0089] like Figure 1 , Figure 3 As shown, in one embodiment, the method for fabricating the semiconductor structure further includes: forming a plurality of bit line structures 114 on the memory contact structure, wherein any bit line structure 114 contacts the top of a memory contact structure 108 located in the same column, and the bit line structure 114 is a straight line. For example, the length of the bit line structure 114 along the X direction is not less than the length of the top of the memory contact structure 108 along the X direction, and the X direction intersects the extension direction of the bit line structure 114.

[0090] like Figure 4 As shown, in one embodiment, the method for fabricating the semiconductor structure further includes: forming a plurality of bit line structures 114 on the storage contact structure 108, wherein any bit line structure 114 is in contact with the top of two adjacent columns of storage contact structures 108, the bit line structure 114 is a broken line, and is in contact with and connected to the two adjacent columns of storage contact structures 108.

[0091] Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after the memory element is formed in one corresponding embodiment; Figure 11 for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after forming the bit line mask layer 318 in one corresponding embodiment; Figure 12 for Figure 11A cross-sectional view of the semiconductor structure after the bit line structure 114 is formed in one corresponding embodiment. (See attached diagram.) Figure 10 , Figure 11 , Figure 12As shown, in the third step, a memory element 106 is formed on each of the second lead-out structures 204. Taking the memory element 106 as a phase change memory element, the steps for forming the memory element 106 are as follows: First, a bottom electrode structure is formed on the upper surface of the second lead-out structure 204 by a deposition process, such as physical vapor deposition. Second, a planar interlayer dielectric structure is formed on the upper surface of the bottom electrode structure by a common deposition process and planarization process. Third, a trench penetrating the interlayer dielectric structure is formed in the interlayer dielectric structure by a photolithography etching process, resulting in an interlayer dielectric layer 214 composed of the remaining interlayer dielectric structure. For example, the material of the interlayer dielectric structure includes oxides, oxynitrides, such as silicon dioxide and silicon nitride. The width of the trench along the X direction is not less than 10 nanometers and not more than 20 nanometers. Next, a metal material structure with its upper surface higher than the interlayer dielectric layer 214 is filled into the trench, and excess metal material structures located on the surface of the interlayer dielectric layer 214 and in the trench are etched away to obtain a metal layer 208 composed of the remaining metal material structure. Exemplarily, the upper surface of the metal layer 208 is lower than the upper surface of the interlayer dielectric layer 214. Then, a phase change material layer 210 is formed in the trench by deposition (e.g., ALD process) and etching processes. Exemplarily, the upper surface of the phase change material layer 210 is flush with the upper surface of the interlayer dielectric layer 214. The material of the phase change material layer 210 includes chalcogenide materials, germanium-, antimony-, and tellurium-containing synthetic materials (GST), such as Ge2Sb2Te5. Finally, a top electrode 212 is formed on the upper surface of the phase change material layer 210, and the width of the top electrode 212 along the X direction is not less than the width of the trench along the X direction. Then, a protective structure, such as a silicon nitride structure, is formed on the sidewalls of the bottom electrode 206 and the top electrode 212. This protective structure extends along the sidewalls of the bottom electrode 206 and covers the upper surface of the top electrode 212. Next, a third dielectric structure is formed on the substrate 100, filling the space between adjacent bottom electrodes 206, with the upper surface of the third dielectric structure higher than the upper surface of the protective structure. Then, the protective structure and the third dielectric structure directly above the top electrode 212 are removed by photolithography and etching processes, resulting in a storage contact trench 312 above the top electrode 212, a protective layer 216 composed of the remaining protective structure, and a third dielectric layer 314 composed of the remaining third dielectric structure. Fourth, a storage contact structure 108 is formed in the storage contact trench 312, with its upper surface flush with the upper surface of the third dielectric layer 314. Fifth, a bit line structure layer 316 is formed on the upper surface of the third dielectric layer 314. Step 6: A bit line mask layer 318 is formed on the bit line structure layer 316. The bit line mask layer 318 defines the shape and position of the bit line structure 114. Step 7: Using the bit line mask layer 318 as a mask, a portion of the bit line structure layer 316 is removed by an etching process to obtain the bit line structure 114 composed of the remaining bit line structure layer 316.Step 8: A fourth dielectric layer 320 with its upper surface flush with the bit line structure 114 is formed between adjacent bit line structures 114. For example, the materials of the first dielectric layer 308, the second dielectric layer 310, the third dielectric layer 314 and the fourth dielectric layer 320 include silicon dioxide, silicon oxynitride and silicon nitride.

[0092] In one embodiment, the materials of the bottom electrode 206, metal layer 208, and top electrode 212 include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, at least one structure of the bottom electrode 206, metal layer 208, and top electrode 212 may be made of a different material than the others; for example, the material of the top electrode 212 may be different from the materials of the bottom electrode 206 and metal layer 208. In practical applications, the same materials may be selected to prepare the bottom electrode 206, metal layer 208, and top electrode 212 as needed.

[0093] The basic storage principle of Phase Change Random Access Memory (PCRAM) is to apply voltage or current pulse signals of different widths and heights between the bottom electrode 206 and the top electrode 212 of the storage element 106, causing a physical phase change in the phase change material layer 210. Specifically, the phase change material layer 210 undergoes a reversible phase transition between a crystalline state (low-resistance state) and an amorphous state (high-resistance state), thereby enabling the writing ("1") and erasing ("0") operations of information. The mutual conversion process includes two processes: amorphization from crystalline to amorphous and crystallization from amorphous to crystalline. The former is called the amorphization process, and the latter is called the crystallization process. Information is then read out by measuring and comparing the resistance difference between the two physical phase states. This non-destructive reading process ensures accurate reading of the information stored in the device cell. The phase change material layer 210 has a resistivity difference of several orders of magnitude between its crystalline and amorphous states, which gives it a high noise margin, sufficient to distinguish between the "0" state and the "1" state.

[0094] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate has a first surface; A plurality of transistors are located on the first surface, and the transistors are arranged in a first preset pattern; A plurality of transistor contact structures are provided, each corresponding to a transistor. The bottom of each transistor contact structure is in contact with the transistor. The bottom of each transistor contact structure is arranged according to the first preset pattern, and the top of each transistor contact structure is arranged in a regular hexagonal pattern. A plurality of storage elements are provided, each corresponding to a transistor contact structure. The bottom of each storage element is in contact with the top of the transistor contact structure. The storage elements are arranged in a regular hexagonal pattern, with each storage element located at a vertex and a center of the regular hexagon. A plurality of storage contact structures are provided, each corresponding to a storage element. The bottom of each storage contact structure contacts the top of the storage element. The bottom of each storage contact structure is arranged in a regular hexagonal pattern, and the top of each storage contact structure is arranged in a second preset pattern, which is different from the first preset pattern. The bottom and top of the transistor contact structure are arranged opposite to each other, and the bottom and top of the storage contact structure are arranged opposite to each other.

2. The semiconductor structure according to claim 1, characterized in that, The first preset graphic arrangement includes a regular hexagon, with each transistor located at the vertex and center of the regular hexagon.

3. The semiconductor structure according to claim 2, characterized in that, The area of ​​the top of the transistor contact structure is equal to the area of ​​the bottom of the transistor contact structure.

4. The semiconductor structure according to claim 2, characterized in that, The second preset graphic includes a multi-row, multi-column arrangement array.

5. The semiconductor structure according to claim 4, characterized in that, The area of ​​the bottom of the storage contact structure is larger than the area of ​​the top of the storage contact structure.

6. The semiconductor structure according to claim 1, characterized in that, The first preset graphic includes a multi-row, multi-column arrangement array.

7. The semiconductor structure according to claim 6, characterized in that, The area of ​​the top of the transistor contact structure is smaller than the area of ​​the bottom of the transistor contact structure.

8. The semiconductor structure according to claim 6, characterized in that, The second preset shape includes a regular hexagon, and the storage contact structure is located at the vertex and center of the regular hexagon.

9. The semiconductor structure according to claim 8, characterized in that, The area of ​​the top of the storage contact structure is equal to the area of ​​the bottom of the storage contact structure.

10. The semiconductor structure according to claim 1, characterized in that, The transistor contact structure includes: The first lead-out structure, the bottom of which is the bottom of the transistor contact structure; The second lead-out structure has its bottom contacting the top of the first lead-out structure, and the top of the second lead-out structure is the top of the transistor contact structure; The bottom and top of the first lead-out structure are positioned opposite each other, and the bottom and top of the second lead-out structure are positioned opposite each other.

11. The semiconductor structure according to claim 10, characterized in that, The area of ​​the bottom of the second lead-out structure is not less than the area of ​​the top of the first lead-out structure.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: The word line structure is in contact with the gate region of the transistor; The source line structure is in contact with the source region of the transistor; The drain region of the transistor is in contact with the bottom of the transistor contact structure.

13. The semiconductor structure according to claim 1, characterized in that, The storage element includes a phase change storage element, a ferroelectric storage element, a magnetoresistive storage element, a resistive switching storage element, or a phase change storage element.

14. The semiconductor structure according to claim 4, characterized in that, Also includes: A plurality of bit line structures, wherein any one of the bit line structures is in contact with the top of the storage contact structure located in the same column.

15. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: A plurality of bit line structures, wherein any one of the bit line structures is in contact with the top of two adjacent columns of the storage contact structures.

16. A method for fabricating a semiconductor structure, Other features include: A substrate is provided, the substrate having a first surface; A plurality of transistors are formed on the first surface, and the transistors are arranged in a first preset pattern. Transistor contact structures are formed on each of the transistors, with the bottom of the transistor contact structure in contact with the transistor. The bottom of the transistor contact structure is arranged according to the first preset pattern, and the top of the transistor contact structure is arranged in a regular hexagonal pattern. Storage elements are formed on the top of each transistor contact structure, and the storage elements are arranged in a regular hexagon, with each storage element located at the vertex and center of the regular hexagon; Storage contact structures are formed on the top of each of the storage elements. The bottom of the storage contact structures is arranged in a regular hexagonal pattern, and the top of the storage contact structures is arranged in a second preset pattern, which is different from the first preset pattern. The bottom and top of the transistor contact structure are arranged opposite to each other, and the bottom and top of the storage contact structure are arranged opposite to each other.

17. The preparation method according to claim 16, characterized in that, The first preset shape includes a regular hexagon, with each transistor located at the vertex and center of the regular hexagon; The area of ​​the top of the transistor contact structure is equal to the area of ​​the bottom of the transistor contact structure.

18. The preparation method according to claim 17, characterized in that, The second preset graphic includes a multi-row, multi-column arrangement array; The area of ​​the bottom of the storage contact structure is larger than the area of ​​the top of the storage contact structure.

19. The preparation method according to claim 16, characterized in that, The first preset graphic includes a multi-row, multi-column arrangement array; The area of ​​the top of the transistor contact structure is smaller than the area of ​​the bottom of the transistor contact structure.

20. The preparation method according to claim 19, characterized in that, The second preset shape includes a regular hexagon, and the storage contact structure is located at the vertex and center of the regular hexagon.

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