Line hammer mitigation using victim cache

Abstract

This application relates to row hammer attack mitigation using a victim cache. Row hammer attacks exploit unexpected and undesirable side effects of memory devices, where memory cells interact electrically with each other through leaky charge and may alter the contents of nearby memory lines not addressed in the original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to a cache line of the cache. The least recently used cache line of the cache is written to the victim cache.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically to apparatus, systems, and methods for line hammer mitigation using victim cache. Background Technology

[0002] Memory devices are typically provided as internal components of computers or other electronic systems, in semiconductors, or integrated circuits. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, erroneous data), and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied, and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of the computing or other electronic system. A controller may be used to manage the transfer of data, commands, and / or instructions between the host computer and the memory device. Summary of the Invention

[0004] One aspect of this disclosure provides a method for row hammer mitigation, wherein the method includes: writing data to a cache line of a first cache; and writing a least recently used cache line from the first cache to a cache line of a second cache, wherein writing the least recently used cache line from the first cache to the second cache is performed as part of a row hammer mitigation operation.

[0005] Another aspect of this disclosure provides an apparatus for row hammering mitigation, wherein the apparatus includes: a controller; a first cache coupled to the controller, the first cache being configured to operate according to a least recently used (LRU) scheme; a second cache coupled to the controller, the second cache being configured to operate according to an LRU scheme; and a memory device coupled to the first cache or the second cache via at least one memory channel, wherein the controller is configured to: control the writing of data to a cache line of the first cache; and control the writing of the least recently used cache line of the first cache to the second cache as part of the row hammering mitigation operation.

[0006] Another aspect of this disclosure provides a system for row hammer mitigation, wherein the system includes: a memory controller including: a central controller; a first cache including a first number of cache lines residing on the central controller; a second cache including a second number of cache lines residing on the central controller; and a memory device coupled to the memory controller, wherein the memory controller is configured to: write data to the first cache according to the Compute High-Speed ​​Link (CXL) protocol; and write the least recently used cache line of the first cache to the second cache as part of a row hammer mitigation operation. Attached Figure Description

[0007] Figure 1 The illustration presents a functional block diagram of a computing system comprising a controller for mitigating line hammer blows using a victim cache, according to several embodiments of the present disclosure.

[0008] Figure 2 The illustration presents a functional block diagram in the form of a controller for line hammer mitigation using a victim cache, according to several embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart corresponding to an example method for line hammer mitigation using a victim cache, according to an embodiment of this disclosure.

[0010] Figure 4 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0011] This document describes systems, apparatus, and methods related to row hammer mitigation using a victim cache. In one instance, a method for row hammer mitigation using a victim cache includes writing data to a cache line in a first cache and writing the least recently used cache line from the first cache to a cache line in a second cache. As described in more detail herein, writing the least recently used cache line from the first cache to the second cache may be performed as part of a row hammer mitigation operation.

[0012] A line hammer attack typically refers to a security vulnerability that exploits unexpected and undesirable side effects, where memory cells interact electrically with each other through leaking charge, potentially altering the contents of nearby memory rows that are not addressed in the original memory access. As memory devices tend to incorporate denser integrated circuits and physically smaller memory cells, these cells may contain less charge than in previous generations of memory devices, potentially leading to lower operational noise margins, an increased rate of electromagnetic interaction between memory cells, and a greater likelihood of data loss. Therefore, strategies for detecting, preventing, and / or correcting the adverse effects associated with line hammer attacks are becoming increasingly important.

[0013] Some methods attempt to mitigate row hammer attacks by refreshing memory cells at a higher rate than traditionally used rates (e.g., by using a refresh rate of less than 64 milliseconds (ms). However, this approach often results in higher power consumption and increased processing overhead compared to methods that do not change the refresh rate of memory cells.

[0014] Other methods may implement counter-based identification of frequently accessed memory rows and seek to proactively refresh adjacent rows based on counter values ​​indicating a potential row hammer attack is occurring. While these methods generally do not suffer from the power consumption and increased processing overhead inherent in the simpler methods described above, they may require additional circuitry to increment counters, memory counters, and / or analysis counters to determine whether to proactively refresh adjacent rows.

[0015] To address these and other shortcomings, the embodiments described herein involve adding a second cache (e.g., a "victim cache"), where entries from the first cache are written to the second cache after being written to the first cache. In some embodiments, the first and / or second caches operate according to a Least Recently Used (LRU) caching policy, wherein the least recently used cache line from the first and / or second cache is evicted first, followed by the second least recently used cache line from the first and / or second cache, and so on. As used herein, a "least recently used cache line" generally refers to a cache line (e.g., a set of cells or an address) in a cache that has remained in the same state relative to other cache lines in the cache since it was accessed, read, or written. Therefore, a least recently used cache line may be a cache line within a cache or a portion of a cache that has remained in the same state relative to other cache lines in the cache or a portion of the cache for the longest possible time period or duration.

[0016] By evicting cache lines from the first cache to the second cache according to the LRU cache policy, the amount of time spent storing any given cache line is increased, thereby reducing the frequency of accessing (e.g., "hitting") cache lines when attempting a line hammer attack. This, in turn, mitigates the effectiveness of attempted line hammer attacks without changing the refresh rate of memory cells and / or without using counters to determine the access frequency of cache lines in the first and / or second caches.

[0017] Furthermore, the embodiments described herein may further allow the latency associated with the first cache and / or the second cache to be matched with the latency of the channel coupling the memory device to the first cache and / or the second cache. For example, the latency associated with the first cache and / or the second cache may be significantly smaller than the latency associated with the channel coupling the memory device to the first cache and / or the second cache. Therefore, by matching the latency of the first cache and / or the second cache with the latency associated with the channel coupling the memory device to the first cache and / or the second cache, the amount of time spent storing any given cache line is increased, thereby reducing the frequency at which cache lines can be “hit” in an attempt to perform a line hammer attack.

[0018] Furthermore, the embodiments described herein allow operation to mitigate line hammer attacks without commands and / or signaling from circuitry outside the first and / or second caches, or at least without commands and / or signaling from circuitry outside the controller (e.g., central controller) on which the first and / or second caches are deployed. This eliminates the need to detect line hammer attacks compared to other methods, thus mitigating them. Additionally, this reduces the amount of data traffic (e.g., signaling and / or command traffic) inherent in some line hammer attack mitigation methods, thereby improving the overall functionality of the computing device in which embodiments of this disclosure operate.

[0019] In some embodiments, the first cache and / or the second cache may reside on a memory controller deployed in a memory system, which may be a compute high-speed link (CXL) compliant memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to enhance next-generation data center performance. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost.

[0020] As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on" a first cache and / or a second cache means that the hardware circuitry including the first cache and / or the second cache is physically located on the memory controller. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0021] With the increasing use of accelerators to supplement CPUs to support emerging applications such as artificial intelligence and machine learning, CXL is designed as an industry-open standard interface for high-speed communications. Built on the Peripheral Component Interconnect High Speed ​​(PCIe) infrastructure, CXL technology utilizes PCIe physical and electrical interfaces to provide high-level protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host and accelerator to share memory), and coherence interfaces. As will be understood, the interfaces described herein operating according to the CXL protocol allow for data transfer rates of at least 32 gigabits per second between certain components of the memory system described herein.

[0022] Figure 1This illustration presents a functional block diagram of a computing system 101, comprising a controller 100 for line hammer mitigation using a victim cache, according to several embodiments of the present disclosure. The computing system 101 may include a memory controller 100, which includes a front-end portion 104, a central controller portion 110, and a back-end portion 119. The computing system 101 may include a host 103 and memory devices 126, 128.

[0023] In some embodiments, memory controller 100 may manage non-volatile memory devices. For example, memory device 126 and / or memory device 128 may be non-volatile (e.g., persistent) memory devices. An example of a non-volatile memory device is a NAND memory device (also known as flash memory). A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0024] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. Various types of cells exist, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC). For example, an SLC may store one bit of information and have two logical states.

[0025] Other examples of non-volatile memory devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs), etc.

[0026] The embodiments are not limited thereto; however, in some embodiments, the memory controller 100 may manage a DRAM memory device 126 having a first tRAS and a FeRAM memory device 128 having a second tRAS. In some embodiments, the tRAS of the FeRAM memory device 128 is different from the tRAS of the DRAM memory device. In some embodiments, the DRAM memory device may include other features different from those of the FeRAM memory device. For example, the DRAM memory device and the FeRAM memory device may differ in the number of memory banks, the type of command encoding, refresh commands, refresh timing, or combinations thereof. Furthermore, in some embodiments, instead of managing both the DRAM memory device 126 and the FeRAM memory device 128, the memory controller 100 may be configured to manage only the DRAM memory device 126 or only the FeRAM memory device 128.

[0027] The memory controller 100 may have a front-end portion 104 including an interface for coupling the memory controller 100 to a host 103 via input / output (I / O) channels 102-1, 102-2, ..., 102-N (individually or collectively referred to as I / O channels 102), and circuitry for managing the I / O channels 102. In some embodiments, eight (8) I / O channels 102 may be present, and in other embodiments, sixteen (16) I / O channels 102 may be present. In some embodiments, multiple I / O channels 102 may be configured as a single port.

[0028] The memory controller 101 may include a central controller section 110 that can control the performance of memory operations in response to a request received from the host 103. Memory operations may be memory operations that read data from memory devices 126, 128 or operations that write data to memory devices 126, 128. In some embodiments, the central controller section 110 may control the writing of substantially multiple data pages substantially simultaneously in response to a request received from the host 103.

[0029] The central controller section 110 may include one or more caches (e.g., in this document, in...). Figure 2The cache 212 and / or victim cache 214 described herein are used to store performance-related data related to memory operations, and / or security components are used to encrypt the data before it is stored in memory device 126, memory device 128, and / or one or more caches. Examples of security components may include, but are not limited to, software and circuitry configured to implement data encryption, data hashing, data masking, and data tokenization. In some embodiments, in response to a request received from host 103, data from host 103 may be stored in cache lines of the cache and / or cache lines of the victim cache, as described herein. Data in the cache and / or victim cache may be written to memory devices 126, 128 at a certain point in time. In some embodiments, data may be encrypted using Advanced Encryption Standard (AES) encryption before it is stored in the cache and / or victim cache.

[0030] The central controller section 110 may include an error correction code (ECC) encoding circuitry for ECC encoding of data (e.g., as described herein). Figure 2 The ECC encoding circuit system 216 described herein, and the ECC decoding circuit system for ECC decoding of data (e.g., as described herein) Figure 2 The ECC decoding circuitry system 218 described herein. As used herein, the term "ECC encoding" can refer to encoding data by adding redundant bits. Generally, encoding can also be non-systematic. Therefore, an encoder can typically map a k-bit data vector from a codeword consisting of n (>k) bits without explicit separation between the original data and the parity bits. As used herein, the term "ECC decoding" can refer to examining ECC-encoded data to check for any errors in the data. Generally, ECC not only detects errors but also corrects subsets of the errors it can detect. The ECC encoding circuitry system can encode data to be written to memory devices 126 and 128. In some embodiments, errors detected in the data can be corrected immediately after detection. The ECC decoding circuitry system can decode data that has previously been ECC-encoded.

[0031] In some embodiments, the memory controller 100 may include a back-end portion 119, which includes a media controller and a physical (PHY) layer coupling the memory controller 100 to a plurality of memory banks. As used herein, the term “PHY layer” generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data over a physical data transmission medium. In some embodiments, the physical data transmission medium may be a plurality of channels 125-1, 125-2. As used herein, the term “memory bank” generally refers to a plurality of memory chips (e.g., memory dies) that can be accessed simultaneously. In some embodiments, channel 125 may have a sixteen (16)-bit data bus. If there are four 16-bit memory chips connected to channel 125, each memory chip may correspond to a memory bank. In these embodiments, there may be four (4) memory banks. In some embodiments, the four memory chips may be eight (8)-bit memory chips instead of 16-bit memory chips. In these embodiments, two memory chips can be combined to form a 16-bit channel, resulting in four memory chips forming two memory banks. Read and write commands may not be executed simultaneously in different memory banks because they can use a data channel shared in the multi-bank memory topology. In some embodiments, the page size of a first type of memory device (e.g., memory device 126) may be larger than the page size of a second type of memory device (e.g., memory device 128).

[0032] In some embodiments, the memory controller 100 may include a management unit 134 for initializing, configuring, and / or monitoring features of the memory controller 100. The management unit 134 may include an I / O bus for managing out-of-band data and / or commands, a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring features of the memory controller 100, and a management unit memory for storing data associated with initializing, configuring, and / or monitoring features of the memory controller 100. As used herein, the term "out-of-band data and / or commands" generally refers to data and / or commands transmitted via a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a transmission medium different from the transmission medium used to transmit data within the network.

[0033] Figure 2This illustration presents a functional block diagram in the form of a memory controller 200 for line hammer mitigation using a victim cache, according to several embodiments of the present disclosure. The memory controller 200 is configured to manage first-type memory devices (e.g., memory devices 226-1, ..., 226-N, which may be individually or collectively referred to as first-type memory devices 226) and second-type memory devices (e.g., memory devices 228-1, ..., 228-N, which may be individually or collectively referred to as second-type memory devices 228).

[0034] like Figure 2 As shown, the front-end portion 204 may include an interface 206 comprising a plurality of I / O channels 202-1, 202-2, ..., 202-N (individually referred to or collectively referred to as I / O channels 202), and a circuitry 208 for managing the interface 206. The interface 206 may be a Peripheral Component Interconnect High Speed ​​(PCIe) 5.0 interface coupled to the I / O channels 202. In some embodiments, the memory controller 200 may receive access requests involving at least one of cache 212, victim cache 214, memory device 226, and / or memory device 228 via the PCIe 5.0 interface 206 according to the CXL protocol. The interface 206 may receive access requests from the host (e.g., ...) via the I / O channels 202. Figure 1 The host 103 shown receives data. The interface management circuitry 208 can use the CXL protocol to manage the interface 206.

[0035] Central controller section 210 can be configured to initiate the execution of operations to mitigate line hammer attacks. For example, central controller section 210 may include cache 212 for storing data associated with the execution of memory operations, and victim cache 214 for storing cache lines evicted from cache 212. As used herein, the term "victim cache" generally refers to a hardware cache designed to reduce conflict misses and improve hit latency in direct-mapped caches. It is used at the refill path of a Level 1 cache (e.g., cache 212) such that cache lines evicted from cache 212 are cached in victim cache 214.

[0036] In some embodiments, data is written to cache 212, wherein the data is organized according to a least recently used (LRU) caching policy. Compared to some methods of writing evicted cache lines to memory device 226 and / or memory device 228, in the embodiments herein, when a least recently used cache line is evicted from cache 212, it is written to a victim cache 214. It should be noted that the victim cache 214 may also be organized according to an LRU caching policy.

[0037] By utilizing the LRU caching policy to write cache lines evicted from cache 212 to victim cache 214, the amount of time it takes to write data to cache lines in cache 212 and / or victim cache 214 is increased, thereby providing mitigation for line hammer attacks. In other words, since many conventional line hammer attacks are used by rapidly and repeatedly accessing (e.g., "hitting") memory locations storing data, moving data (e.g., cache lines) from cache 212 to victim cache 214 according to the LRU caching policy reduces the likelihood of a successful line hammer attack.

[0038] In some embodiments, cache 212 may be a set-associative cache containing multiple cache lines; however, embodiments are not limited thereto, and in some embodiments, cache 212 may be a direct-mapped cache containing multiple cache lines. In contrast, victim cache 214 may be a fully associative cache containing multiple cache lines. However, generally, victim cache 214 contains fewer cache lines than cache 212.

[0039] In some embodiments, the cache line size of cache 212 and / or cache 214 may be equal to or greater than the memory controller 200 access granularity (64 bytes). For example, each cache line may contain 256 bytes of data. In some embodiments, each cache line may include 512 bytes of data, but embodiments are not limited thereto. Generally, the size of read and write requests in a CXL memory system may be 64 bytes. Therefore, in some embodiments, data entries in cache 212 may have 64 bytes of data. Each cache line may include 256 bytes. Therefore, multiple 64-byte requests may be stored in each cache line. In response to a request from the host, memory controller 200 may write 256 bytes of data to cache 212, which may later be written to victim cache 214, as described herein. In some embodiments, 256 bytes of data may be written to cache 212 and / or victim cache 214 in 64-byte blocks, but embodiments are not limited thereto.

[0040] In a non-limiting instance, the device (e.g., Figure 1The memory system 101 described herein includes a controller, such as a central controller 210. A first cache (e.g., cache 212) and a second cache (e.g., victim cache 214) may be coupled to the controller 210. As described herein, the first cache and / or the second cache may operate according to an LRU scheme. That is, the first cache (e.g., cache 212) and / or the second cache (e.g., victim cache 214) may utilize an LRU caching strategy.

[0041] Memory devices (e.g., memory devices 226 and / or 228) are coupled to a first cache and / or a second cache via at least one memory channel (e.g., at least one memory channel of channel 225). In this example, a controller (e.g., central controller 210) can control the writing of data to cache lines in the first cache and control the writing of least recently used cache lines from the first cache to the second cache as part of a line hammer mitigation operation, as described herein. In some embodiments, such as Figure 2 As shown, the first cache and the second cache reside on the central controller section 210 of the memory controller 200.

[0042] As mentioned above, the first cache may be larger than the second cache. For example, the second cache may contain at least 256 cache lines, and the first cache may contain at least twice as many cache lines as the second cache (e.g., 512 cache lines or more). Embodiments are not limited to this; however, it is assumed that the first cache contains a larger number of cache lines than the second cache. An embodiment is envisioned where the first cache contains 256 cache lines and the second cache contains 128 cache lines. Similarly, an embodiment is envisioned where the first cache contains 2,048 cache lines and the second cache contains 256 cache lines. Therefore, it should be understood that the number of cache lines associated with the first and second caches is arbitrary, except that the second cache typically contains fewer cache lines than the first cache.

[0043] In addition, such as Figure 2 As shown, in some embodiments, the first cache is physically different from the second cache. For example, in some embodiments, the first cache and the second cache are deployed as separate integrated circuit components (e.g., substrate, ASIC, FPGA, etc.) communicatively coupled to each other. As another example, in some embodiments, the first cache and the second cache are independently addressable and / or accessible by a controller.

[0044] As described above, the controller may be the central controller portion 210 of the memory controller 200, configured to operate according to a computation high-speed link protocol. Therefore, in some embodiments, the controller may be configured to write data to the first cache at a rate of at least 32 gigabits per second. Embodiments are not limited thereto; however, in some embodiments, the controller may be configured to match the latency of the second cache to the latency of at least one memory channel 225 coupling the first cache or the second cache, or both, to the memory devices 226, 228. In such embodiments, the latency between the first cache and / or the second cache can be reduced to extend the amount of time between potential memory accesses, thereby further reducing the likelihood of a successful hammer attack.

[0045] Continuing with this non-limiting example, the first cache may be a direct-mapped cache or a set-associative cache, as described above, while the second cache may be a fully associative cache. Due to the cost (e.g., power consumption, bandwidth, physical space, etc.) of providing a fully associative cache throughout the memory controller 200, various aspects of this disclosure specify that the second cache (e.g., victim cache 214) is a fully associative cache, while the first cache (e.g., cache 212) is a direct-mapped cache or a set-associative cache. By providing a fully associative victim cache in conjunction with a direct-mapped cache or a set-associative cache, line hammer attacks can be mitigated, as described herein.

[0046] In some embodiments, the controller may determine not to write the least recently used cache line from the second cache to the memory device and write the least recently used cache line from the second cache back to the second cache. For example, if it is determined that the least recently used cache line will not be evicted from memory, the least recently used cache line may be maintained in the second cache, flushed, or rewritten to the second cache such that it becomes the most recently used cache line of the second cache.

[0047] In another non-limiting instance, the system (e.g., Figure 1The memory system 101 described herein includes: a memory controller 200, which includes a central controller 210; a first cache (e.g., cache 212), the first cache including a first number of cache lines residing on the central controller 210. The system further includes a second cache (e.g., victim cache 214), the second cache including a second number of cache lines residing on the central controller 210. As discussed herein, the first cache may be a direct-mapped cache or a set-associative cache, while the second cache may be a fully associative cache. Furthermore, in some embodiments, the second cache includes fewer cache lines than the first cache. In this example, the memory controller 200 may be further coupled to a memory device (e.g., as described herein). Figure 1 and 2 (One or more of the memory devices 126, 226 and / or one of the memory devices 128, 228 described herein).

[0048] The memory controller 200 and / or the central controller 210 can enable data to be written to a first cache according to the Compute High-Speed ​​Link (CXL) protocol. For example, the memory controller 200 and / or the central controller 210 can be configured to write data to the first cache at a rate of at least 32 gigabits per second. In some embodiments, the memory controller 200 and / or the central controller 210 can enable the least recently used cache lines of the first cache to be written to a second cache as part of a line hammer mitigation operation. In some embodiments, the first cache and / or the second cache can operate according to a least recently used (LRU) cache policy to write (e.g., evict) the least recently used cache lines of the first cache to the second cache, and / or write the least recently used cache lines of the second cache to different locations within the system.

[0049] For example, in some embodiments, the memory controller 200 and / or the central controller 210 may determine not to write the least recently used cache line from the second cache to the memory device, and write the least recently used cache line from the second cache to the first cache or the second cache.

[0050] In some embodiments, the memory controller 200 and / or the central controller 210 may utilize an instruction-level parallelism (ILP) scheme to write data to a first cache and / or a second cache. Embodiments are not limited thereto; however, in some embodiments, the memory controller 200 and / or the central controller 210 may utilize a memory-level parallelism (MLP) scheme to write data to a first cache and / or a second cache. As used herein, the terms “instruction-level parallelism” or “ILP” generally refer to the parallel or simultaneous execution of a series of instructions in a memory system or a computing system where a memory system is deployed. ILP is generally distinct from “concurrency” because ILP typically operates on a single thread of a process executed by the computing system. Furthermore, as used herein, the terms “memory-level parallelism” or “MLP” generally refer to the ability to suspend multiple memory operations simultaneously in a memory system or a computing system where a memory system is deployed, particularly cache misses and / or translation back cover (TLB) misses.

[0051] Continuing with this non-limiting example, the memory controller 210 may perform operations to match the latency of the second cache with the latency of the memory channel (e.g., channel 225) that couples the memory controller 210 to the memory device. For example, as described herein, the latency between the first cache and / or the second cache may be reduced to extend the amount of time between potential memory accesses, thereby further reducing the effectiveness of potential hammer attacks.

[0052] like Figure 2 As shown, the central controller portion 210 may include a security component 214 to encrypt data before it is stored in memory device 226 and / or memory device 228, and to decrypt data before it is passed to cache 212. Data may be passed from cache 212 and / or from victim cache 214 to memory device 226 and / or memory device 228. As previously described, security component 214 may encrypt data using AES encryption. In some embodiments, security component 214 may encrypt data written to memory device 228, but may not encrypt data written to memory device 226. Data written to memory device 228 may be encrypted because memory device 228 may have security vulnerabilities that memory device 226 does not have. When security component 214 is not used, for example when data is written to memory device 226, the security component may be bypassed. In some embodiments, security component 214 may be enabled or disabled. For example, when memory is written to a persistent memory device such as memory device 228, security component 214 can be enabled.

[0053] like Figure 2As shown, the central controller section 210 may include an error correction code (ECC) circuitry for ECC encoding and decoding of data. In some embodiments, the memory controller 210 may implement low-power chip kill (LPCK) error correction. As used herein, the term "chip kill" generally refers to protecting the memory system (e.g., Figure 1 The memory system 101 shown is a form of error correction that protects against failure of any single memory chip and multi-bit errors in any part of a single memory chip. In some embodiments, the LPCK circuitry can increase data stability and correct errors in the data. One method of chip-hunting protection is an on-the-fly correction implementation. On-the-fly correction can form multiple codewords from the four (4)-bit symbols of each of a plurality of memory dies. For example, if there are eleven (11) dies, each containing four separate bit symbols, with each bit symbol containing four bits, the eleven dies can form four codewords, each codeword having eleven separate bit symbols, comprising a total of forty-four (44) bits.

[0054] In some embodiments, a first codeword may include the first bit symbol of each die, a second codeword may include the second bit symbol of each die, a third codeword may include the third bit symbol of each die, and a fourth codeword may include the fourth bit symbol of each die. In other words, the eight data bit symbols and three parity bit symbols of the codeword may be stored in eleven (11) dies. Eight (8) of the eleven dies may contain data bit symbols, and the remaining three (3) of the eleven dies may contain parity bit symbols. Adding three parity bit symbols allows the central controller section 210 to correct up to one symbol error and detect up to two symbol errors in each codeword. If only two (2) parity bits are added instead of three parity bit symbols, the central controller section 210 may correct up to one symbol error but detect only one symbol error. In some embodiments, the data bit symbols and parity bit symbols may be written to or read from the eleven dies simultaneously by the ECC encoding circuitry system 216 and the ECC decoding circuitry system 218. If every bit symbol in the die fails, only the bit symbols from the die in the codeword will fail. This allows the memory contents to be reconstructed even if a die fails completely.

[0055] like Figure 2As shown, the memory controller 200 may include a back-end portion 219, which includes: a media controller portion 220, which includes a plurality of media controllers; and a physical (PHY) layer portion 222, which includes a plurality of PHY layers 224-1, 224-2, 224-N, ..., 224-(N+1) (individually or collectively referred to as PHY layers 224). In some embodiments, the back-end portion 219 is configured to couple the PHY layer portion 222 to a plurality of memory banks 230-1, ..., 230-N (individually or collectively referred to as memory banks 230) of a first memory device 226 and a plurality of memory banks 232-1, ..., 232-M (individually or collectively referred to as memory banks 232) of a second memory device 228-1, ..., 228-N (individually or collectively referred to as second memory device 228). The media controller 220 may include open page policies and close page policies. As used herein, the term "open page policy" generally refers to a policy that allows a memory controller (e.g., media controller 220) to open a memory page for a specific amount of time after performing a read or write operation. As used herein, the term "close page policy" generally refers to a policy that ensures a memory page is closed immediately after performing a read or write operation. In some embodiments, the FeRAM memory device 228 may implement a close page policy, with the additional requirement that the tRAS and other timings of the FeRAM memory device 228 differ from those of DRAM.

[0056] In embodiments using LPCK error correction, the media controller portion 220 may be a single media controller 220. When implementing LPCK error correction, multiple channels 225-1, 225-2, 225-N, ..., 225-(N+1) (individually referred to or collectively as multiple channels 225) may be driven simultaneously to write data to DRAM memory device 226 and / or FeRAM memory device 228. In some embodiments, instead of using a single media controller 220, multiple media controllers may be used to drive multiple channels 225 in the LPCK architecture. When multiple media controllers are used to drive channels 225 simultaneously, the media controllers are utilized substantially simultaneously.

[0057] As used herein, the term "substantially" means that a feature does not need to be absolute, but is close enough to achieve the advantages of the feature. For example, "substantially synchronous" is not limited to operations performed in absolute synchronization and can include timing intended to be simultaneous but which may not be precisely synchronized due to manufacturing limitations. For example, media controllers utilized "substantially simultaneously" may not start or end precisely at the same time due to read / write latency that can be manifested by various interfaces (e.g., LPDDR5 and PCIe). For example, multiple memory controllers can be used such that they write data to the memory device at the same time regardless of whether one media controller starts or terminates before the others.

[0058] Each of the multiple media controllers can receive the same commands and addresses, and essentially drive multiple channels 225 simultaneously. By using the same commands and addresses for the multiple media controllers, each of the multiple media controllers can perform the same memory operations on the same multiple memory cells using multiple channels 225.

[0059] Backend portion 222 may include multiple PHY layers 224 and a media controller portion 220 configured to drive channels 225 that couple the PHY layers 224 to memory banks 230, 232. In some embodiments, memory banks 230, 232 may be DRAM memory banks 230 and / or FeRAM memory banks 232. In some embodiments, memory controller 200 may be coupled to memory banks 230, 232 via channels 225 coupled to backend portion 219, and each of the channels 225 is coupled to four (4) memory banks 230, 232.

[0060] The memory controller 200 may include a management unit 234 configured to initialize, configure, and / or monitor features of the memory controller 200. In some embodiments, the management unit 234 includes an I / O bus 238 for managing out-of-band data and / or commands, a management unit controller 240 for executing instructions associated with initializing, configuring, and / or monitoring features of the memory controller 200, and a management unit memory 242 for storing code and / or data associated with managing and / or monitoring features of the memory controller 200. The endpoints of the management unit 234 may be exposed to a host system (e.g., Figure 1 The host 103 shown in the diagram manages data. In some embodiments, features monitored by the management unit 234 may include the voltage supplied to the memory controller 200 or the temperature measured by an external sensor, or both. Furthermore, the management unit 234 may include an Advanced High Performance Bus (AHB) interconnect 236 to couple different components of the management unit 234.

[0061] As stated above, I / O bus 238 can be configured to transmit out-of-band data and / or commands. In some embodiments, I / O bus 238 may be a system management bus (SMBus). As used herein, the term "SMBus" generally refers to a single-ended simple two-wire bus for lightweight communication purposes. Furthermore, management unit 234 may include circuitry for managing in-band data. As used herein, the term "in-band data" generally refers to data transmitted via a primary transmission medium within a network, such as a local area network (LAN).

[0062] Management unit 234 may include management unit controller 240. In some embodiments, management unit controller 240 may be a controller that meets the Joint Test Action Group (JTAG) standard and is based on an internal integrated circuit (I... 2 C or I 3 C) Controllers for protocol and auxiliary I / O circuitry system operation. As used herein, the term "JTAG" generally refers to the industry standard used for verifying designs and testing printed circuit boards after manufacturing. As used herein, the term "I..." 2 "C" typically refers to a serial protocol used for two-wire interfaces to connect low-speed devices such as microcontrollers, I / O interfaces, and other similar peripherals in embedded systems. In some embodiments, an auxiliary I / O circuitry system may couple the management unit 234 to the memory controller 200. Furthermore, firmware for operating the management unit may be stored in the management unit memory 242. In some embodiments, the management unit memory 242 may be flash memory, such as flash NOR memory or other persistent flash memory devices.

[0063] Figure 3 This is a flowchart corresponding to an example method 350 for line hammer mitigation using a victim cache, according to several embodiments of the present disclosure. Method 350 can be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0064] At operation 352, method 350 includes writing data to a cache line in a first cache. The first cache may be similar to the cache line described herein. Figure 2The cache 212 described herein. Therefore, in some embodiments, method 350 may include writing data to a cache line of the first cache according to the Compute High-Speed ​​Link (CXL) protocol, as described herein.

[0065] At operation 354, method 350 involves writing a cache line from the first cache to a cache line in the second cache. The second cache may be similar to the one described in this document. Figure 2 The victim cache 214 is described herein. As described herein, the first cache may include a greater number of cache lines than the second cache. In some embodiments, the least recently used cache line is written from the first cache to the second cache as part of a line hammer mitigation operation.

[0066] As described herein, in some embodiments, the first cache is a direct-mapped cache or a set-associative cache, and the second cache is a fully associative cache. Furthermore, as described herein, the first and second caches can each operate according to a Least Recently Used (LRU) caching policy. As discussed above, operating the first and / or second caches according to an LRU caching policy ensures that cache lines evicted from the first and / or second caches are accessed less frequently compared to other cache lines in the first and / or second caches, thereby facilitating improved line hammer attack mitigation.

[0067] Method 350 may further include coupling the latency of the second cache to the latency of the first cache and / or the second cache to a memory device (e.g., as described herein). Figure 1 and 2 Delay matching of the channels of the memory devices 126, 226 and / or 128, 228 described herein. In some embodiments, the channels may be similar to those described herein. Figure 1 and 2 One of channels 125 and 225 described herein. By matching the latency of the second cache to the latency of the channel coupling the first cache and / or the second cache to the memory device, at least improved row hammer mitigation can be provided, because increasing the latency of the first cache and / or the second cache can further increase the amount of time available to perform row hammer attacks, such as cache strikes. Furthermore, because the latency of the channel coupling the first cache and / or the second cache to the memory device can represent a bottleneck in data access (e.g., a bottleneck when retrieving data from the memory device), users of the computing system described herein are unlikely to experience any perceptible latency in data access when implementing embodiments of this disclosure.

[0068] Method 350 may further include determining not to write the least recently used cache line from the second cache to a memory device coupled to the first cache or the second cache or both, and writing the least recently used cache line from the second cache back to the second cache.

[0069] Figure 4 This is a block diagram of an example computer system 600 in which embodiments of this disclosure may operate. For example, Figure 4 An example machine is described as the computer system 400, within which an instruction set for causing the machine to perform any or more of the methods discussed herein is executable. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or the memory subsystem 413 may be used to perform the operation of the line hammer mitigation component 413 (e.g., to perform the operation of the line hammer mitigation component 413). Figure 1 Central controller 110 and / or Figure 2 (Operation of the central controller 210). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0070] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0071] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0072] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communication via network 420.

[0073] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) on which one or more instruction sets 426 or software embodying any one or more methods or functions described herein are stored. Instructions 426 may also reside wholly or at least partially in main memory 404 and / or processing device 402 during execution by computer system 400, the main memory 404 and processing device 402 also constituting machine-readable storage medium. Machine-readable storage medium 424, data storage system 418, and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0074] In one embodiment, instruction 426 includes instructions for implementing a hammer strike mitigation component 413 (e.g., Figure 1 Central controller 110 and / or Figure 2 The central controller 210 and / or its constituent components provide functional instructions. Although the machine-readable storage medium 424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0075] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0076] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that control and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or similar data represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0077] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each media coupled to a computer system bus.

[0078] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices for performing the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0079] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0080] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

[0081] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” may include both singular and plural referents. Additionally, “a plurality,” “at least one,” and “one or more” (e.g., a plurality of cache lines) may refer to one or more cache lines; however, “a plurality” is intended to refer to more than one of these.

[0082] Furthermore, the words “may” and “can” are used throughout this application in a permissive sense (i.e., having the potential to be) rather than in a mandatory sense (i.e., must). The term “comprising” and its derivatives mean “including but not limited to”. Depending on the context, the term “coupled / coupling” means a physical, direct or indirect connection or access to and movement (transmission) of commands and / or data.

Claims

1. A method comprising: Write the data to the cache line of the first cache; Line hammer mitigation is performed by writing the least recently used cache line from the first cache to the second cache. Determine not to write the least recently used cache line from the second cache to a memory device coupled to the first cache or the second cache or both; and Write the least recently used cache line from the second cache back to the second cache.

2. The method according to claim 1, wherein: The first cache is a set-associative cache, and The second cache is a fully associative cache.

3. The method according to claim 1, wherein the first cache and the second cache each operate according to the least recently used (LRU) cache policy.

4. The method according to claim 1, further comprising writing the data into the cache line of the first cache according to the Compute High-Speed ​​Link (CXL) protocol.

5. The method of claim 1, wherein the first cache comprises a greater number of cache lines than the second cache.

6. An apparatus comprising: Controller; A first cache, coupled to the controller, is configured to operate according to a Least Recently Used (LRU) scheme. A second cache, coupled to the controller, is configured to operate according to an LRU scheme; and A memory device coupled to the first cache or the second cache via at least one memory channel, wherein the controller is configured to: Control the writing of data to the cache line of the first cache; The control writes the least recently used cache line from the first cache to the second cache to perform a line hammering mitigation operation; Determine not to write the least recently used cache line from the second cache to the memory device; and The control writes the least recently used cache line from the second cache back to the second cache.

7. The device of claim 6, wherein the controller includes a central controller portion of a memory controller configured to operate according to a computation high-speed link protocol.

8. The device of claim 7, wherein the first cache and the second cache reside on the central controller portion of the memory controller.

9. The device of claim 6, wherein the second cache comprises at least 256 cache lines, and wherein the first cache comprises at least twice the number of cache lines as the second cache.

10. The device according to claim 6, wherein: The first cache is a set-associative cache, and The second cache is a fully associative cache.

11. The device of claim 6, wherein the first cache is physically different from the second cache.

12. A system comprising: The memory controller includes: Central controller; A first cache includes a first number of cache lines residing on the central controller; The second cache includes a second number of cache lines residing on the central controller; and A memory device coupled to the memory controller, wherein the memory controller is configured to: The data is written to the first cache according to the high-speed computing link CXL protocol; To perform a row hammering mitigation operation, the row hammering mitigation operation includes writing the least recently used cache line of the first cache to the second cache; Determine not to write the least recently used cache line from the second cache to the memory device; and Write the least recently used cache line from the second cache back to the second cache.

13. The system according to claim 12, wherein: The first cache is a set-associative cache, and The second cache is a fully associative cache.

14. The system of claim 12, wherein the first cache or the second cache or both are configured to operate according to a least recently used cache policy.

15. The system of claim 12, wherein the second cache comprises fewer cache lines than the first cache.

16. The system of claim 12, wherein the memory controller is configured to utilize an instruction-level parallelism scheme to write the data to the first cache.

17. The system of claim 12, wherein the memory controller is configured to write the data to the first cache at a rate of at least 32 gigabits per second.

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