Display substrate, display device, and method for manufacturing display substrate

Abstract

A display substrate and a display device are provided. The display substrate includes a plurality of pixel units disposed on a substrate, a first conductive layer disposed on the substrate, a buffer layer disposed on a side of the first conductive layer away from the substrate, a semiconductor layer disposed on a side of the buffer layer away from the substrate, a first insulating layer disposed on a side of the semiconductor layer away from the substrate, and a second conductive layer disposed on a side of the first insulating layer away from the substrate. The display substrate further includes at least one conductive via penetrating at least the first insulating layer and at least one conductive plug electrically connecting the second conductive layer and the first conductive layer through the at least one conductive plug. The first conductive layer includes a first conductive sub-layer and a second conductive sub-layer, a projection of the first conductive sub-layer on the substrate at least partially overlaps a projection of the at least one conductive via on the substrate, and a thickness of the first conductive sub-layer along a third direction is greater than a thickness of the second conductive sub-layer along the third direction.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display substrate, a display device, and a method for manufacturing the display substrate. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have advantages such as active light emission, good temperature characteristics, low power consumption, fast response, and flexibility, and are gradually becoming one of the mainstream display technologies, with increasingly widespread applications in display devices such as mobile phones, computers, and televisions. Ensuring the transmittance of the light-emitting area is one of the important research topics in the backplane design of OLED display panels.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising:

[0005] Substrate;

[0006] A plurality of pixel units disposed on the substrate are arranged in an array along a first direction and a second direction. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The first direction and the second direction intersect.

[0007] The first conductive layer disposed on the substrate;

[0008] A buffer layer disposed on the side of the first conductive layer away from the substrate.

[0009] A semiconductor layer disposed on the side of the buffer layer away from the substrate;

[0010] A first insulating layer disposed on the side of the semiconductor layer away from the substrate; and

[0011] A second conductive layer is disposed on the side of the first insulating layer away from the substrate.

[0012] The pixel driving circuit includes at least one transistor and a storage capacitor. The at least one transistor includes a source and a drain. The storage capacitor includes a first capacitor electrode and a second capacitor electrode disposed opposite to each other. One of the first capacitor electrode and the second capacitor electrode is located in the first conductive layer. The source and drain of the at least one transistor are located in the second conductive layer.

[0013] The display substrate includes a first conductive portion located in the first conductive layer and a second conductive portion located in the second conductive layer, wherein the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap.

[0014] The display substrate further includes at least one conductive via and at least one conductive plug located in the at least one conductive via, wherein the at least one conductive via penetrates at least the first insulating layer, and the second conductive portion is electrically connected to the first conductive portion through the at least one conductive plug; and

[0015] The first conductive portion includes a first conductive sub-portion and a second conductive sub-portion. The orthographic projection of the first conductive sub-portion on the substrate at least partially overlaps with the orthographic projection of the at least one conductive via on the substrate. The thickness of the first conductive sub-portion along a third direction is greater than the thickness of the second conductive sub-portion along a third direction, wherein the third direction is perpendicular to the plane defined by the first direction and the second direction.

[0016] According to some exemplary embodiments, the first conductive part includes a first top surface remote from the substrate, and the second conductive part includes a second top surface remote from the substrate, wherein the first top surface is further away from the substrate in the third direction than the second top surface.

[0017] According to some exemplary embodiments, the first conductive sub-part includes a protrusion that protrudes toward the at least one conductive via relative to a second top surface of the second conductive sub-part, and the at least one conductive plug contacts at least a portion of the first top surface of the first conductive sub-part.

[0018] According to some exemplary embodiments, the buffer layer exposes at least a portion of the first conductive part; and / or, the buffer layer covers the second conductive part.

[0019] According to some exemplary embodiments, the buffer layer includes a third top surface away from the substrate, and the first top surface of the first conductive portion is substantially flush with a portion of the third top surface adjacent to the first conductive portion.

[0020] According to some exemplary embodiments, the protrusion includes a first side and a second side, the first side and the second side being located on opposite sides of the first top surface, the first top surface connecting the first side and the second side; and the buffer layer contacts and covers the second top surface, the first side and the second side of the second conductive portion.

[0021] According to some exemplary embodiments, the first conductive part includes a first bottom surface near the substrate, and the second conductive part includes a second bottom surface near the substrate, the first bottom surface and the second bottom surface being substantially flush in the third direction.

[0022] According to some exemplary embodiments, the second conductive portion includes a third bottom surface near the substrate; at a location adjacent to the at least one conductive via, the third bottom surface of the second conductive portion and the second top surface of the second conductive portion are spaced apart by a first distance in a third direction, and the depth of the at least one conductive via in the third direction is less than the first distance.

[0023] According to some exemplary embodiments, the first conductive portion includes a first conductive connection portion located in the first conductive layer, at least a portion of the first conductive connection portion serving as the second capacitor electrode; the second conductive portion includes a first conductive transition portion located in the second conductive layer; and the orthographic projection of the first conductive transition portion on the substrate falls within the orthographic projection of the first conductive connection portion on the substrate.

[0024] According to some exemplary embodiments, the at least one conductive via includes a first conductive via, the at least one conductive plug includes a first conductive plug, the first conductive plug being located in the first conductive via; the orthographic projection of the first conductive adapter on the substrate at least partially overlaps with the orthographic projection of the first conductive via on the substrate; and the orthographic projection of a portion of the first conductive via on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the first conductive connection on the substrate, one end of the first conductive plug being electrically connected to the first sub-conductive portion of the first conductive connection, and the other end of the first conductive plug being electrically connected to the first conductive adapter.

[0025] According to some exemplary embodiments, the at least one transistor includes a driving transistor, the driving transistor including a channel region; the display substrate further includes a first semiconductor portion located in the semiconductor layer, the first semiconductor portion including a first source region, a first drain region and a channel region of the driving transistor, the first source region and the first drain region being located on opposite sides of the channel region of the driving transistor; the orthographic projection of the first conductive via on the substrate at least partially overlaps with the orthographic projection of one of the first source region and the first drain region on the substrate; and one of the first source region and the first drain region is electrically connected to the first conductive transition portion through the first conductive via.

[0026] According to some exemplary embodiments, the first conductive portion includes a second conductive connection portion located in the first conductive layer, the display substrate further includes a sensing signal line, the second conductive connection portion is electrically connected to the sensing signal line; the second conductive portion includes a second conductive transition portion located in the second conductive layer; and the orthographic projection of the second conductive transition portion on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the substrate.

[0027] According to some exemplary embodiments, the at least one conductive via includes a second conductive via, the at least one conductive plug includes a second conductive plug, the second conductive plug being located in the second conductive via; the orthographic projection of the second conductive adapter on the substrate at least partially overlaps with the orthographic projection of the second conductive via on the substrate; and the orthographic projection of a portion of the second conductive via on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the second conductive connection on the substrate, one end of the second conductive plug being electrically connected to the first sub-conductive portion of the second conductive connection, and the other end of the second conductive plug being electrically connected to the second conductive adapter.

[0028] According to some exemplary embodiments, the at least one transistor includes a sensing transistor, the sensing transistor including a channel region; the display substrate further includes a third semiconductor portion located in the semiconductor layer, the third semiconductor portion including a third source region, a third drain region and a channel region of the sensing transistor, the third source region and the third drain region being located on opposite sides of the channel region of the sensing transistor; the orthographic projection of the second conductive via on the substrate at least partially overlaps with the orthographic projection of one of the third source region and the third drain region on the substrate; and one of the third source region and the third drain region is electrically connected to the second conductive transition portion through the second conductive via.

[0029] According to some exemplary embodiments, the first conductive portion includes a third conductive connection portion located in the first conductive layer; the second conductive portion includes a third conductive transition portion located in the second conductive layer, the display substrate includes a first power signal line located in the second conductive layer, the third conductive connection portion is a part of the first power signal line; and the orthographic projection of the third conductive transition portion on the substrate at least partially overlaps with the orthographic projection of the third conductive connection portion on the substrate.

[0030] According to some exemplary embodiments, the at least one conductive via includes a third conductive via, the at least one conductive plug includes a third conductive plug, and the third conductive plug is located in the third conductive via; the orthographic projection of the first power signal line on the substrate at least partially overlaps with the orthographic projection of the third conductive via on the substrate; and the third conductive connection includes two first sub-conductive portions, the orthographic projection of the third conductive via on the substrate at least partially overlaps with the orthographic projection of one of the two first sub-conductive portions of the third conductive connection on the substrate, one end of the third conductive plug is electrically connected to one of the two first sub-conductive portions of the third conductive connection, and the other end of the third conductive plug is electrically connected to the first power signal line.

[0031] According to some exemplary embodiments, the second conductive portion further includes a fourth conductive transition portion located in the second conductive layer; and the orthographic projection of the fourth conductive transition portion on the substrate at least partially overlaps with the orthographic projection of the third conductive connection portion on the substrate.

[0032] According to some exemplary embodiments, the at least one conductive via includes a fourth conductive via, the at least one conductive plug includes a fourth conductive plug, the fourth conductive plug being located in the fourth conductive via; the orthographic projection of the fourth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the fourth conductive via on the substrate; and the orthographic projection of the fourth conductive via on the substrate at least partially overlaps with the orthographic projection of the other of the two first sub-conductive portions of the third conductive connection on the substrate, one end of the fourth conductive plug being electrically connected to the other of the two first sub-conductive portions of the third conductive connection, and the other end of the fourth conductive plug being electrically connected to the fourth conductive adapter.

[0033] According to some exemplary embodiments, the first conductive portion includes a fourth conductive connection portion located in the first conductive layer; the second conductive portion includes a fifth conductive transition portion located in the second conductive layer; and the orthographic projection of the fifth conductive transition portion on the substrate at least partially overlaps with the orthographic projection of the fourth conductive connection portion on the substrate.

[0034] According to some exemplary embodiments, the at least one conductive via includes a fifth conductive via, the at least one conductive plug includes a fifth conductive plug, the fifth conductive plug being located in the fifth conductive via; the orthographic projection of the fifth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the fifth conductive via on the substrate; and the orthographic projection of the fifth conductive via on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the fourth conductive connection on the substrate, one end of the fifth conductive plug being electrically connected to the first sub-conductive portion of the fourth conductive connection, and the other end of the fifth conductive plug being electrically connected to the fifth conductive adapter.

[0035] According to some exemplary embodiments, the orthographic projection of the fifth conductive via on the substrate at least partially overlaps with the orthographic projection of the other of the third source region and the third drain region on the substrate; and the other of the third source region and the third drain region is electrically connected to the fifth conductive transition portion through the fifth conductive via.

[0036] In another aspect, a display device is provided, the display device comprising the display substrate as described above.

[0037] In another aspect, a method for manufacturing a display substrate is provided, the method comprising:

[0038] A first conductive material layer is formed on the substrate.

[0039] The first conductive material layer is patterned using a halftone mask process to form a first conductive layer including a first conductive portion, wherein the first conductive portion includes a first conductive sub-part and a second conductive sub-part;

[0040] A buffer material layer is formed on the side of the first conductive layer away from the substrate.

[0041] The buffer material layer is patterned using a masking process to form a buffer layer;

[0042] A semiconductor material layer is formed on the side of the buffer layer away from the substrate.

[0043] The semiconductor material layer is patterned using a mask process to form a semiconductor layer;

[0044] A first insulating material layer is formed on the side of the semiconductor layer away from the substrate.

[0045] The first insulating material layer is patterned using a mask process to form a first insulating layer including at least one conductive via, wherein the at least one conductive via penetrates at least the first insulating layer;

[0046] A second conductive material layer is formed on the side of the first insulating layer away from the substrate, wherein at least a portion of the second conductive material layer is formed in the at least one conductive via to form at least one conductive plug located in the at least one conductive via; and

[0047] The second conductive material layer is patterned using a mask process to form a second conductive layer including a second conductive portion, wherein the orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the second conductive portion is electrically connected to the first conductive portion through the at least one conductive plug.

[0048] Wherein, the orthographic projection of the first conductive part on the substrate at least partially overlaps with the orthographic projection of the at least one conductive via on the substrate, the thickness of the first conductive part along a third direction is greater than the thickness of the second conductive part along a third direction, wherein the third direction is perpendicular to the surface of the substrate near the first conductive layer. Attached Figure Description

[0049] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0050] Figure 1 This is a plan view of a display substrate according to an embodiment of the present disclosure.

[0051] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixel circuit of a single sub-pixel of the display substrate.

[0052] Figures 3 to 13 These are partial plan views of at least one film layer of a display substrate according to some exemplary embodiments of the present disclosure, wherein, Figure 3 A partial plan view of the fourth conductive layer of the display substrate is schematically shown. Figure 4 A partial plan view of the first conductive layer of the display substrate is schematically shown. Figure 5 A partial plan view schematically illustrating the combination of the first and fourth conductive layers of the display substrate is shown. Figure 6 A partial plan view of the semiconductor layer of the display substrate is schematically shown. Figure 7 A partial plan view schematically illustrating the combination of the fourth conductive layer, the first conductive layer, and the semiconductor layer of the display substrate is shown. Figure 8 A partial plan view of the third conductive layer of the display substrate is schematically shown. Figure 9A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, and the third conductive layer of the display substrate. Figure 10 A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, and the first insulating layer of the display substrate. Figure 11 A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, and the second insulating layer of the display substrate. Figure 12 A partial plan view of the second conductive layer of the display substrate is schematically shown. Figure 13 A partial plan view schematically illustrates a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, the second insulating layer, and the second conductive layer of the display substrate.

[0053] Figure 14 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 13 The cross-sectional view taken from line AA' in the diagram.

[0054] Figures 15A to 15D These are display substrates along some exemplary embodiments according to this disclosure. Figure 4 The cross-sectional view taken from lines BB', CC', DD', and EE'.

[0055] Figures 16A to 16D These are display substrates along some exemplary embodiments according to this disclosure. Figure 13 The cross-sectional view taken from lines FF', GG', HH', and II' shows only the electrical connection between the first and second conductive layers, while omitting other components.

[0056] Figure 17 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 13 The cross-sectional view taken from line JJ' in the diagram.

[0057] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0058] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0059] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0060] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0061] It should be understood that when an element or layer is said to be "formed on" another element or layer, that element or layer can be formed directly or indirectly on the other element or layer. That is, for example, intermediate elements or intermediate layers can exist. Conversely, when an element or layer is said to be "directly formed on" another element or layer, there are no intermediate elements or intermediate layers. Other terms used to describe relationships between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.).

[0062] In this document, the directional terms "first direction" and "second direction" are used to describe different directions of pixel arrangement, such as the horizontal and vertical directions of pixel arrangement. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0063] In this document, unless otherwise specified, the expression "located on the same layer" generally means that the first and second components can use the same materials and can be formed by the same patterning process. The expression "A and B are connected as one piece" means that component A and component B are formed as one piece, that is, they usually include the same materials and form a structurally continuous integral component.

[0064] The transistors used in the embodiments of this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. Since the source and drain of the TFTs used here are symmetrical, their sources and drains can be interchanged. The following examples primarily describe the case of a P-type TFT used as the driving transistor; other transistors may be of the same or different type as the driving transistor depending on the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type TFT.

[0065] Some exemplary embodiments of this disclosure provide a display substrate, the display substrate comprising: a substrate; a plurality of pixel units disposed on the substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one pixel unit including a plurality of sub-pixels, at least one sub-pixel including a light-emitting element and a pixel driving circuit for driving the light-emitting element; a semiconductor layer disposed on the substrate; a first conductive layer disposed on the semiconductor layer near the substrate; a second conductive layer disposed on the semiconductor layer away from the substrate; and a pixel defining layer disposed on the second conductive layer away from the substrate, the pixel defining layer including a plurality of openings for defining light-emitting regions of the plurality of sub-pixels, wherein... The pixel driving circuit includes a sensing transistor, a storage capacitor, and capacitor traces. The sensing transistor includes a source and a drain. The storage capacitor includes a first capacitor electrode and a second capacitor electrode disposed opposite to each other. The capacitor traces are used to electrically connect one of the source and drain of the sensing transistor to the second capacitor electrode. The source and drain of the sensing transistor are located in a second conductive layer, and the second capacitor electrode and the capacitor traces are both located in a first conductive layer. The capacitor traces include a main body portion extending along a second direction. For the same sub-pixel, the orthographic projection of the main body portion of the capacitor trace of the pixel driving circuit of the sub-pixel on the substrate is spaced apart from the orthographic projection of the light-emitting area of ​​the sub-pixel on the substrate. In embodiments of this disclosure, by placing most of the capacitor trace (e.g., the main body portion of the capacitor trace) outside the light-emitting area of ​​the sub-pixel, its blocking effect on the light emitted from the light-emitting area can be reduced, thereby improving the light transmittance of the light-emitting area. In this way, the display quality of the display substrate can be improved without affecting the driving of the sensing transistor.

[0066] Figure 1 This is a plan view of a display substrate according to an embodiment of the present disclosure. Figure 14 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a more specific structure of the display substrate. (See reference 1) Figure 1 and Figure 14 According to embodiments of the present disclosure, the display substrate may include a substrate 100, a pixel unit PX disposed on the substrate 100, a driving unit DRU disposed on the substrate 100, and a trace PL electrically connecting the pixel unit PX and the driving unit DRU, wherein the driving unit DRU is used to drive the pixel unit PX.

[0067] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units PX are disposed to display images. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel units PX are disposed, that is, an area where no images are displayed. A driving unit DRU for driving the pixel units PX and some traces PL connecting the pixel units PX to the driving unit DRU may be disposed in the non-display area NA. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel can be determined based on the width of the non-display area NA.

[0068] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the display area AA is set as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0069] A non-display area NA may be disposed on at least one side of the display area AA. In embodiments of this disclosure, the non-display area NA may surround the outer periphery of the display area AA. In embodiments of this disclosure, the non-display area NA may include a lateral portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0070] Pixel units (PX) are disposed within the display area (AA). A pixel unit (PX) is the smallest unit used to display an image, and multiple units can be configured. For example, a pixel unit (PX) may include a light-emitting device that emits white light and / or colored light.

[0071] Pixel units PX can be configured in multiples, arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units PX, and pixel units PX can be arranged in various forms. For example, pixel units PX can be arranged such that the direction inclined relative to the first direction X and the first direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0072] A pixel unit PX can include multiple sub-pixels. For example, a pixel unit PX can include three sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. As another example, a pixel unit PX can include four sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. For instance, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, the third sub-pixel SP3 can be a blue sub-pixel, and the fourth sub-pixel SP4 can be a white sub-pixel.

[0073] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the first sub-pixel SP1 may include a first light-emitting element located in the first light-emitting area SPA1 and a first pixel driving circuit SPC1 for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element located in the second light-emitting area SPA2 and a second pixel driving circuit SPC2 for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element located in the third light-emitting area SPA3 and a third pixel driving circuit SPC3 for driving the third light-emitting element, and the third light-emitting element may emit blue light; the fourth sub-pixel SP4 may include a fourth light-emitting element located in the fourth light-emitting area SPA4 and a fourth pixel driving circuit SPC4 for driving the fourth light-emitting element.

[0074] The light-emitting region of a subpixel can be the area where the light-emitting element of the subpixel is located. For example, in an OLED display substrate, the light-emitting element of a subpixel may include a first electrode (e.g., an anode), a light-emitting material layer, and a second electrode (e.g., a cathode) stacked together. Thus, the light-emitting region of the subpixel can be the area corresponding to the portion of the light-emitting material layer sandwiched between the anode and cathode. As another example, in an OLED display substrate, the display substrate may include a pixel defining layer disposed on a substrate 100, the pixel defining layer including multiple openings corresponding to multiple subpixels, the multiple openings respectively defining the light-emitting regions of the multiple subpixels.

[0075] Subpixels also include non-light-emitting areas; for example, a portion of the pixel driving circuitry of a subpixel may be located within the non-light-emitting area. The aperture ratio of a subpixel is determined by the ratio of the area of ​​its light-emitting area to the total area of ​​that subpixel (the sum of the areas of its light-emitting and non-light-emitting areas).

[0076] The light-emitting devices (e.g., the luminescent layer, or EL layer) of an OLED may lack uniformity during fabrication. For example, when fabricating the EL layer using a vapor deposition process, limitations of the process can lead to inconsistencies in the EL layers of different sub-pixels, resulting in uneven brightness or color among different sub-pixels. Furthermore, with prolonged use, the EL layer undergoes varying degrees of aging, also causing inconsistencies in the EL layers of different sub-pixels, leading to uneven brightness or color among different sub-pixels. In embodiments of this disclosure, the display substrate may further include an OSC (Optical System Coefficient) photosensitive circuit, which can sense the actual light emitted by the pixel unit. Thus, in embodiments of this disclosure, the display substrate can perform optical compensation on the sub-pixels within each pixel unit based on the actual light emitted by the pixel unit sensed by the OSC, thereby improving the uniformity of light emission from the display substrate.

[0077] For example, in some exemplary embodiments of this disclosure, each pixel unit PX is provided with a light metering circuit OSC. Each light metering circuit OSC senses the light actually emitted by the pixel unit PX it is located in.

[0078] For example, in embodiments of this disclosure, at least two pixel units PX can share a single photosensitive circuit OSC. Within the same column of pixel units, two pixel units PX located in adjacent rows can share a single photosensitive circuit OSC. This eliminates the need for a separate photosensitive circuit for each pixel unit PX, reducing the number of photosensitive circuits and thus increasing the aperture ratio.

[0079] When the display substrate is in a display state, the photosensitive circuit OSC can sense the light actually emitted by the two adjacent pixel units. For example, the photosensitive circuit OSC may include at least a photoelectric conversion element. Thus, the photosensitive circuit OSC can be configured to: sense the light actually emitted by the two adjacent pixel units; and send a sensing electrical signal based on the sensed light.

[0080] For example, refer to Figure 1 The photosensitive circuit OSC can send the sensed electrical signal to an external circuit, such as the control IC of a display device. The control IC can control the control signals sent to the pixel unit PX according to the sensed electrical signal, for example, it can control the data signals (i.e., data signals) sent to the pixel driving circuit of each sub-pixel. Under the control of the data signals, each sub-pixel emits light accordingly.

[0081] exist Figure 1 In the illustrated embodiment, sub-pixels SP1, SP2, SP3, and SP4 are arranged side by side, and each sub-pixel SP1, SP2, SP3, and SP4 may have its own data line DL.

[0082] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixel circuit of a single sub-pixel of the display substrate. Figure 2 The pixel driving circuit shown can be any one of the pixel driving circuits SPC1, SPC2, SPC3, and SPC4 described above. (Refer to...) Figure 2 The pixel driving circuit may include multiple components such as a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. This pixel driving circuit can be referred to as a 3T1C structure.

[0083] It should be noted that the pixel driving circuit included in the display substrate according to the embodiments of the present disclosure is described here using the 3T1C structure as an example. However, the pixel driving circuit included in the display substrate according to the embodiments of the present disclosure is not limited to the 3T1C structure.

[0084] Continue to refer to Figure 2 The gate g2 of switching transistor T2 is electrically connected to the first scan signal line GL1, the first electrode of switching transistor T2 is electrically connected to the data line DL, and the second electrode of switching transistor T2 is electrically connected to the gate g1 of driving transistor T1. For example, the second electrode of switching transistor T2 and the gate g1 of driving transistor T1 can both be electrically connected to node GN. Switching transistor T2 is used to control the writing of voltage signals from data line DL to the pixel driving circuit.

[0085] It should be noted that each transistor may include an active layer, a gate, a first electrode (e.g., a source), and a second electrode (e.g., a drain). For example, the switching transistor T2 includes a gate g2 and an active layer ACT2; the driving transistor T1 includes a gate g1 and an active layer ACT1; and the sensing transistor T3 includes a gate g3 and an active layer ACT3. In embodiments of this disclosure, the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in a conductive layer disposed in the semiconductor layer away from the substrate.

[0086] It should be noted that in this article, the first electrode of a transistor can refer to one of the source (e.g., s1, s2, s3) and drain (e.g., d1, d2, d3) of the transistor, and the second electrode of a transistor can refer to the other of the source (e.g., s1, s2, s3) and drain (e.g., d1, d2, d3) of the transistor.

[0087] The gate g1 of the driving transistor T1 is electrically connected to node GN. The first electrode of the driving transistor T1 is electrically connected to a first power supply signal (e.g., a high voltage level signal VDD). The second electrode of the driving transistor T1 can be electrically connected to the anode of the light-emitting element OLED, thereby generating a driving current based on the voltage signal to drive the light-emitting element OLED to emit light. For example, the light-emitting element OLED can be an organic light-emitting diode (OLED).

[0088] The two ends of the storage capacitor Cst are electrically connected to the gate g1 and drain d1 of the driving transistor T1, respectively, for storing the voltage signal input from the data line DL. For example, one end of the storage capacitor Cst is electrically connected to node GN, and the other end is electrically connected to node SN. For example, the storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2. The first capacitor electrode Cst1 of the storage capacitor Cst, the second electrode (e.g., drain d2) of the switching transistor T2, and the gate g1 of the driving transistor T1 are all electrically connected to node GN, and the second capacitor electrode Cst2 of the storage capacitor Cst, the second electrode (e.g., drain d1) of the driving transistor T1, and the anode of the light-emitting element OLED are all electrically connected to node SN.

[0089] The gate g3 of sensing transistor T3 is electrically connected to the second scan signal line GL2, the first electrode (e.g., source s3) of sensing transistor T3 is electrically connected to the sensing signal line SL, and the second electrode (e.g., drain d3) of sensing transistor T3 is electrically connected to node SN. That is, the second capacitor electrode Cst2 of storage capacitor Cst, the second electrode (e.g., drain d1) of driving transistor T1, the anode of light-emitting element OLED, and the second electrode (e.g., drain d3) of sensing transistor T3 are all electrically connected to node SN.

[0090] The anode of the OLED is electrically connected to node SN, and the cathode is electrically connected to a second power supply signal (e.g., a low-voltage level signal VSS). Both level signals VDD and VSS are DC voltage signals used to provide the necessary voltage to drive the OLED to emit light.

[0091] Figure 14 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure. Figures 3 to 14 These are partial plan views of at least one film layer of a display substrate according to some exemplary embodiments of the present disclosure, wherein, Figure 3 A partial plan view of the fourth conductive layer of the display substrate is schematically shown. Figure 4 A partial plan view of the first conductive layer of the display substrate is schematically shown. Figure 5 A partial plan view schematically illustrating the combination of the first and fourth conductive layers of the display substrate is shown. Figure 6 A partial plan view of the semiconductor layer of the display substrate is schematically shown. Figure 7 A partial plan view schematically illustrating the combination of the fourth conductive layer, the first conductive layer, and the semiconductor layer of the display substrate is shown. Figure 8 A partial plan view of the third conductive layer of the display substrate is schematically shown. Figure 9 A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, and the third conductive layer of the display substrate. Figure 10 A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, and the first insulating layer of the display substrate. Figure 11 A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, and the second insulating layer of the display substrate. Figure 12 A partial plan view of the second conductive layer of the display substrate is schematically shown. Figure 13 A partial plan view schematically illustrates a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, the second insulating layer, and the second conductive layer of the display substrate. Figure 14 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 13 The cross-sectional view taken from line AA' in the diagram. Figures 15A to 15D These are display substrates along some exemplary embodiments according to this disclosure. Figure 4 The cross-sectional view taken from lines BB', CC', DD', and EE'. Figures 16A to 16D These are display substrates along some exemplary embodiments according to this disclosure. Figure 13 The cross-sectional view taken from lines FF', GG', HH', and II' shows only the electrical connection between the first and second conductive layers, while omitting other components. Figure 17 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 13 The cross-sectional view taken from line JJ' in the diagram.

[0092] Combined with reference Figures 3 to 17 The display substrate may include multiple conductive layers, a semiconductor layer, and multiple insulating layers. For ease of description, the multiple conductive layers are respectively described as a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

[0093] The display substrate may include: a substrate 100, a fourth conductive layer 40 disposed on the substrate 100, a third insulating layer IDL3 disposed on the side of the fourth conductive layer 40 away from the substrate 100, a first conductive layer 10 disposed on the side of the third insulating layer IDL3 away from the substrate 100, a buffer layer BFL disposed on the side of the first conductive layer 10 away from the substrate 100, a semiconductor layer ACT disposed on the side of the buffer layer BFL away from the substrate 100, a gate insulating layer GIL disposed on the side of the semiconductor layer ACT away from the substrate 100, and a third conductive layer 30 disposed on the side of the gate insulating layer GIL away from the substrate 100. A first insulating layer IDL1 is disposed on the side of the third conductive layer 30 away from the substrate 100; a second conductive layer 20 is disposed on the side of the first insulating layer IDL1 away from the substrate 100; a second insulating layer IDL2 is disposed on the side of the second conductive layer 20 away from the substrate 100; a first electrode layer 300 is disposed on the side of the second insulating layer IDL2 away from the substrate 100; a pixel defining layer PDL is disposed on the side of the first electrode layer 300 away from the substrate 100; a light-emitting material layer EL is disposed on the side of the pixel defining layer PDL away from the substrate 100; and a second electrode layer 600 is disposed on the side of the light-emitting material layer EL away from the substrate 100.

[0094] It should be noted that each of the above-mentioned insulating layers may include a single-layer structure or a stacked structure composed of multiple insulating layers. For example, the second insulating layer IDL2 may include at least one passivation layer and at least one planarization layer. The specific structure of the insulating layers is not particularly limited in the embodiments disclosed herein.

[0095] Reference Figure 3 The diagram schematically illustrates a partial plan view of the fourth conductive layer 40. The material of the fourth conductive layer 40 may include a transparent conductive material, such as indium tin oxide (ITO). For example, the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst may be located in the first conductive layer 10. In embodiments of this disclosure, the display substrate may further include capacitor traces 5 for electrically connecting the storage capacitor Cst to the sensing transistor T3. Specifically, the capacitor traces 5 may be used to electrically connect the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst to one of the source s3 and drain d3 of the sensing transistor T3. Figure 3As shown, the capacitor trace 5 may include a first connecting portion 51, a second connecting portion 53, and a capacitor trace body portion 52. The capacitor trace body portion 52 extends along a second direction Y and is located between the first connecting portion 51 and the second connecting portion 53. The first connecting portion 51 is connected to either the first capacitor electrode Cst1 or the second capacitor electrode Cst2, and the second connecting portion 53 is electrically connected to one of the source s3 and drain d3 of the sensing transistor T (which will be described in detail below).

[0096] In some exemplary embodiments of this disclosure, for the same sub-pixel, the first capacitor electrode Cst1 or the second capacitor electrode Cst2 and the capacitor trace 5 are formed as a continuously extending integral structure. For example, as Figure 3 The diagram schematically illustrates a partial planar view of the fourth conductive layer 40, comprising four sub-pixels located within the same pixel unit. For each sub-pixel, the first capacitor electrode Cst1 or the second capacitor electrode Cst2 has a relatively large block pattern, and the capacitor trace 5 has a relatively large aspect ratio strip pattern. The block pattern and the strip pattern are connected to each other, thereby forming a continuously extending integral structure. This facilitates the formation of the second capacitor electrode and capacitor trace located on the same layer using the same patterning process.

[0097] It should be noted that, unless otherwise specified, the term "continuously extending integral structure" in this document means that at least two components located on the same layer extend continuously without any break in the middle, that is, at least two of the at least two components that are close to each other are connected to each other.

[0098] For the same sub-pixel, the orthographic projection of the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the pixel driving circuit of the sub-pixel on the substrate 100 at least partially overlaps with the orthographic projection of the light-emitting area of ​​the sub-pixel on the substrate 100.

[0099] Combined with reference Figure 4 and Figure 5 The material of the first conductive layer 10 may include a light-shielding material, such as a metal. In embodiments of this disclosure, the display substrate may further include a first conductive connection portion 11, a second conductive connection portion 12, a third conductive connection portion 13, and a fourth conductive connection portion 14 located in the first conductive layer 10. For the same sub-pixel, the first conductive connection portion 11, the second conductive connection portion 12, the third conductive connection portion 13, and the fourth conductive connection portion 14 are spaced apart.

[0100] For the same sub-pixel, the orthographic projection of the first conductive connection portion 11 on the substrate 100 at least partially overlaps with the orthographic projection of the first capacitor electrode Cst1 or the second capacitor electrode Cst2 located in the fourth conductive layer 40 on the substrate 100. The orthographic projection of the fourth conductive connection portion 14 on the substrate 100 at least partially overlaps with the orthographic projection of the capacitor trace 5 on the substrate 100. For example, the orthographic projection of the fourth conductive connection portion 14 on the substrate 100 at least partially overlaps with the orthographic projection of the second connection portion 53 of the capacitor trace 5 on the substrate 100. The orthographic projection of each of the second conductive connection portions 12 and the third conductive connection portions 13 on the substrate 100 does not overlap with the orthographic projection of each of the second capacitor electrode Cst2 and the capacitor trace 5 on the substrate 100.

[0101] In embodiments of this disclosure, the display substrate includes a first conductive portion located in the first conductive layer 10. The first conductive portion may include at least one of a first conductive connection portion 11, a second conductive connection portion 12, a third conductive connection portion 13, and a fourth conductive connection portion 14. The structure of the first conductive portion will be further described below with reference to the accompanying drawings.

[0102] It should be noted that, in the embodiments of this disclosure, the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst can be located in the first conductive layer 10. For example, at least a portion of the first conductive connection portion 11 can be used as the first capacitor electrode Cst1 or the second capacitor electrode Cst2.

[0103] Reference Figure 6 The diagram schematically shows a partial planar view of the semiconductor layer ACT. (Refer to...) Figure 7 The diagram schematically illustrates a partial plan view of the fourth conductive layer 40, the first conductive layer 10, and the semiconductor layer ACT. In embodiments of this disclosure, the semiconductor layer ACT may comprise various types of semiconductor materials, such as amorphous silicon semiconductor materials, polycrystalline silicon semiconductor materials, and metal-oxide semiconductor materials. (See reference...) Figure 6 and Figure 7 In embodiments of this disclosure, the display substrate may further include a first semiconductor portion 301, a second semiconductor portion 302, and a third semiconductor portion 303 located in the semiconductor layer ACT. The first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst may be located in the semiconductor layer ACT.

[0104] It should be noted that, referring to Figure 15 and... Figure 17In embodiments of this disclosure, one of the first capacitor electrode Cst1 and the second capacitor electrode Cst2 of the storage capacitor Cst may be located in the first conductive layer 10, for example, it may be at least a portion of the first conductive connection portion 11. The other of the first capacitor electrode Cst1 and the second capacitor electrode Cst2 of the storage capacitor Cst may be located in at least one of the fourth conductive layer 40 and the semiconductor layer ACT. For example, the other of the first capacitor electrode Cst1 and the second capacitor electrode Cst2 may include a block pattern portion in the fourth conductive layer 40, or the other of the first capacitor electrode Cst1 and the second capacitor electrode Cst2 may include a conductor-treated portion in the semiconductor layer ACT, or the other of the first capacitor electrode Cst1 and the second capacitor electrode Cst2 may simultaneously include a block pattern portion in the fourth conductive layer 40 and a conductor-treated portion in the semiconductor layer ACT (for example, it may be a doped semiconductor portion).

[0105] For the same sub-pixel, the orthographic projection of the first capacitor electrode Cst1 of the storage capacitor Cst on the substrate 100 at least partially overlaps with the orthographic projection of the second capacitor electrode Cst2 of the storage capacitor Cst on the substrate 100. Thus, the first capacitor electrode Cst1 and the second capacitor electrode Cst2 are arranged opposite to each other to form the storage capacitor Cst.

[0106] For example, the first semiconductor section 301 corresponds to the driving transistor T1. The first semiconductor section 301 may include a source region 301s, a drain region 301d, and a channel region 301c. The channel region 301c is the channel region of the driving transistor T1, and the source region 301s and the drain region 301d correspond to the source s1 and drain d1 of the driving transistor T1, respectively. It should be understood that the channel region may have semiconductor characteristics, and the source region and the drain region may be semiconductor sections that have undergone conductor treatment, for example, they may be semiconductor sections that have undergone doping treatment.

[0107] For example, the second semiconductor section 302 corresponds to the switching transistor T2. The second semiconductor section 302 may include a source region 302s, a drain region 302d, and a channel region 302c. The channel region 302c is the channel region of the switching transistor T2. The source region 302s and the drain region 302d correspond to the source s2 and drain d2 of the switching transistor T2, respectively.

[0108] For example, the third semiconductor section 303 corresponds to the sensing transistor T3. The third semiconductor section 303 may include a source region 303s, a drain region 303d, and a channel region 303c. The channel region 303c is the channel region of the sensing transistor T3. The source region 303s and the drain region 303d correspond to the source s3 and drain d3 of the sensing transistor T3, respectively.

[0109] In some exemplary embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the first semiconductor portion 301 on the substrate 100 at least partially overlaps with the orthographic projection of the first conductive connection portion 11 on the substrate 100, and the orthographic projection of the first semiconductor portion 301 on the substrate 100 at least partially overlaps with the orthographic projection of the first capacitor electrode Cst1 or the second capacitor electrode Cst2 on the substrate 100. For example, for the same sub-pixel, the orthographic projection of the first semiconductor portion 301 on the substrate 100 falls within the orthographic projection of the first conductive connection portion 11 on the substrate 100, and the orthographic projection of the first semiconductor portion 301 on the substrate 100 falls within the orthographic projection of the first capacitor electrode Cst1 or the second capacitor electrode Cst2 on the substrate 100.

[0110] In some exemplary embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive connection portion 12 on the substrate 100, and the orthographic projection of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive connection portion 14 on the substrate 100. For example, for the same sub-pixel, the orthographic projection of one end of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive connection portion 12 on the substrate 100, and the orthographic projection of the other end of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive connection portion 14 on the substrate 100.

[0111] Reference Figure 8 The diagram schematically shows a partial plan view of the third conductive layer 30. (Refer to...) Figure 9 The diagram schematically illustrates a partial plan view of the fourth conductive layer 40, the first conductive layer 10, the semiconductor layer ACT, and the third conductive layer 30. In embodiments of this disclosure, the third conductive layer 30 may comprise various types of gate materials. (See reference 1) Figure 8 and Figure 9 In embodiments of this disclosure, the display substrate may further include a first gate conductor portion 31, a second gate conductor portion 32, a first auxiliary trace 33, a second auxiliary trace 34, and a third auxiliary trace 35 located in the third conductive layer 30. The display substrate may also include a first scan signal line GL1 and a second scan signal line GL2 for supplying gate scan signals, both of which are located in the third conductive layer 30.

[0112] For example, the first gate conductor portion 31 corresponds to the driving transistor T1, and the orthographic projection of the first gate conductor portion 31 on the substrate 100 at least partially overlaps with the orthographic projection of the first semiconductor portion 301 (e.g., the channel region 301c of the driving transistor T1) on the substrate 100. The portion of the first gate conductor portion 31 that overlaps with the channel region 301c of the driving transistor T1 forms the gate g1 of the driving transistor T1.

[0113] For example, the first scan signal line GL1 corresponds to the switching transistor T2, and the orthographic projection of the first scan signal line GL1 on the substrate 100 at least partially overlaps with the orthographic projection of the second semiconductor portion 302 (e.g., the channel region 302c of the switching transistor T2) on the substrate 100. The portion of the first scan signal line GL1 overlapping with the channel region 302c of the switching transistor T2 forms the gate g2 of the switching transistor T2. For example, the first scan signal line GL1 includes a protrusion extending along the second direction Y, which is the aforementioned second gate conductor portion 32. In the embodiments of this disclosure, the first scan signal line GL1 is located below the channel region 302c of the switching transistor T2 in the second direction Y, and the second gate conductor portion 32 of the first scan signal line GL1 extends upward toward the channel region 302c of the switching transistor T2.

[0114] For example, the second scan signal line GL2 corresponds to the sensing transistor T3, and the orthographic projection of the second scan signal line GL2 on the substrate 100 at least partially overlaps with the orthographic projection of the third semiconductor portion 303 (e.g., the channel region 303c of the sensing transistor T3) on the substrate 100. The portion of the second scan signal line GL2 that overlaps with the channel region 303c of the sensing transistor T3 forms the gate g3 of the sensing transistor T3.

[0115] In the embodiments of this disclosure, the first scan signal line GL1 and the second scan signal line GL2 extend substantially along the first direction X, and the first auxiliary trace 33, the second auxiliary trace 34 and the third auxiliary trace 35 extend substantially along the second direction Y.

[0116] In embodiments of this disclosure, a first scan signal line GL1 and a second scan signal line GL2 for supplying gate scan signals to the pixel driving circuit of the same row of sub-pixels are respectively located on both sides of the light-emitting area of ​​the same row of sub-pixels in the second direction Y. For example, in the illustrated embodiment, the first scan signal line GL1 and the second scan signal line GL2 for supplying gate scan signals to the pixel driving circuit of the same row of sub-pixels are respectively located above and below the light-emitting area of ​​the same row of sub-pixels in the second direction Y.

[0117] Figure 10A partial plan view schematically illustrates the combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, and the first insulating layer of the display substrate. Figure 10 The diagram schematically shows some vias located in the first insulating layer IDL1.

[0118] Reference Figure 10 The display substrate may include a first conductive via VH1 penetrating the first insulating layer IDL1. The first conductive via VH1 exposes a portion of the first conductive connection portion 11. The first conductive via VH1 exposes at least a portion of the first conductive sub-port 1101 of the first conductive connection portion 11. The first conductive via VH1 exposes the first source region 301s or the first drain region 301d of the driving transistor T1.

[0119] The display substrate may include a second conductive via VH2 penetrating the first insulating layer IDL1. The second conductive via VH2 exposes a portion of the second conductive connection portion 12. The second conductive via VH2 exposes at least a portion of the first conductive sub-port 1101 of the second conductive connection portion 12. The second conductive via VH2 exposes the third source region 303s or the third drain region 303d of the sensing transistor T3.

[0120] The display substrate may include a third conductive via VH3 penetrating the first insulating layer IDL1. The third conductive via VH3 exposes a portion of the third conductive connection portion 13. The third conductive via VH3 exposes at least a portion of the first conductive sub-portion 1101 of the third conductive connection portion 13.

[0121] The display substrate may include a fourth conductive via VH4 penetrating the first insulating layer IDL1. The fourth conductive via VH4 exposes another portion of the third conductive connection portion 13. The fourth conductive via VH4 exposes at least a portion of the first conductive sub-portion 1101 of the fourth conductive via VH4.

[0122] The display substrate may include a fifth conductive via VH5 penetrating the first insulating layer IDL1. The fifth conductive via VH5 exposes a portion of the fourth conductive connection portion 14. The fifth conductive via VH5 exposes at least a portion of the first conductive sub-port 1101 of the fifth conductive via VH5. The fifth conductive via VH5 exposes the third drain region 303d or the third source region 303s of the sensing transistor T3.

[0123] Reference Figure 11 The diagram schematically shows a partial plan view of the second conductive layer 20. (Refer to...) Figure 12The diagram schematically illustrates a partial plan view of the fourth conductive layer 40, the first conductive layer 10, the semiconductor layer ACT, the third conductive layer 30, the first insulating layer IDL1, and the second conductive layer 20. In embodiments of this disclosure, the second conductive layer 20 may comprise various types of source / drain materials. (See reference...) Figure 11 and Figure 12 In embodiments of this disclosure, the display substrate may further include a first power signal line VDD, a data line DL, a sensing signal line SL, a first conductive transition portion 21, a second conductive transition portion 22, a third conductive transition portion 23, a fourth conductive transition portion 24, a fifth conductive transition portion 25, and a sixth conductive transition portion 26 located in the second conductive layer 20. For the same sub-pixel, the first power signal line VDD, the data line DL, the sensing signal line SL, the first conductive transition portion 21, the second conductive transition portion 22, the fourth conductive transition portion 24, the fifth conductive transition portion 25, and the sixth conductive transition portion 26 are spaced apart from each other. The third conductive transition portion 23 is a part of the first power signal line VDD.

[0124] Combined with reference Figures 3 to 17 The display substrate includes a first conductive portion 110 located in the first conductive layer 10 and a second conductive portion 120 located in the second conductive layer 20. The orthographic projection of the first conductive portion 110 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive portion 120 on the substrate 100.

[0125] For example, the first conductive portion 110 may be at least one of the first conductive connection portion 11, the second conductive connection portion 12, the third conductive connection portion 13, and the fourth conductive connection portion 14 described above. The second conductive portion 120 may be at least one of the first conductive transition portion 21, the second conductive transition portion 22, the third conductive transition portion 23, the fourth conductive transition portion 24, and the fifth conductive transition portion 25 described above.

[0126] The display substrate further includes at least one conductive via VH, which penetrates at least the first insulating layer IDL1. For example, the at least one conductive via VH can be at least one of the first conductive via VH1, the second conductive via VH2, the third conductive via VH3, the fourth conductive via VH4, and the fifth conductive via VH5.

[0127] The display substrate may further include at least one conductive plug 1110 located in the at least one conductive via VH, and the second conductive portion 120 is electrically connected to the first conductive portion 110 through the at least one conductive plug 1110. The term "conductive plug" will be further described below in conjunction with the accompanying drawings.

[0128] Reference Figure 14The first conductive portion 110 may include a first conductive sub-portion 1101 and a second conductive sub-portion 1102. The orthographic projection of the first conductive sub-portion 1101 on the substrate at least partially overlaps with the orthographic projection of the at least one conductive via VH on the substrate. The thickness of the first conductive sub-portion 1101 along a third direction Z is greater than the thickness of the second conductive sub-portion 1102 along a third direction Z, wherein the third direction Z is perpendicular to the plane defined by the first direction X and the second direction Y. That is, the first conductive sub-portion is the portion of the first conductive portion corresponding to the conductive via, and the second conductive sub-portion is the other portion of the first conductive portion excluding the first conductive sub-portion. In embodiments of this disclosure, the thickness of the first conductive sub-portion is greater than the thickness of the second conductive sub-portion.

[0129] The first conductive part 1101 includes a first top surface 1101T that is away from the substrate 100, and the second conductive part 1102 includes a second top surface 1102T that is away from the substrate 100. The first top surface 1101T is further away from the substrate 100 in the third direction Z than the second top surface 1102T.

[0130] Continue to refer to Figure 14 The first conductive sub-part 1101 includes a protrusion that protrudes toward the at least one conductive via VH relative to the second top surface 1102T of the second conductive sub-part, and the at least one conductive plug 1110 contacts at least a portion of the first top surface 1101T of the first conductive sub-part.

[0131] The buffer layer BFL exposes at least a portion of the first conductive sub-part 1101. The buffer layer BFL covers the second conductive sub-part 1102. Specifically, the buffer layer BFL includes a third top surface BFLT away from the substrate 100, and the first top surface 1101T of the first conductive sub-part 1101 is substantially flush with the portion of the third top surface BFLT adjacent to the first conductive sub-part 1101.

[0132] It should be noted that, unless otherwise specified, the term "substantially flush" in this document means that the two objects being compared are at the same height in the third direction Z, or in other words, are on the same horizontal plane; or, that the two objects being compared have a certain height difference in the third direction Z, but this height difference is within ±5 of the thickness of the main body component to which the two objects belong. For example, here, "substantially flush" of the first top surface 1101T and the third top surface BFLT can include: the first top surface 1101T and the third top surface BFLT are at the same height in the third direction Z, or the height difference between the first top surface 1101T and the third top surface BFLT is within ±5 of the thickness of the first conductive part 110 or the buffer layer BFL itself.

[0133] Continue to refer to Figure 14 The protrusion includes a first side surface 11011 and a second side surface 11012, which are located on opposite sides of the first top surface 1101T. The first top surface 1101T connects the first side surface 11011 and the second side surface 11012. The buffer layer BFL contacts and covers the first side surface 11011, the second side surface 11012, and the second top surface 1102T of the second conductive portion.

[0134] The first conductive portion 1101 includes a first bottom surface 1101B near the substrate 100, and the second conductive portion 1102 includes a second bottom surface 1102B near the substrate 100. The first bottom surface 1101B and the second bottom surface 1102B are substantially flush in the third direction Z. For example, here, the first bottom surface 1101B and the second bottom surface 1102B being substantially flush can include: the first bottom surface 1101B and the second bottom surface 1102B being at the same height in the third direction Z, or the height difference between the first bottom surface 1101B and the second bottom surface 1102B being within ±5 of the thickness of the first conductive portion 110 or the buffer layer BFL itself.

[0135] Continue to refer to Figure 14 The second conductive portion 120 includes a third bottom surface 120B near the substrate 100; at a position adjacent to the at least one conductive via VH, the third bottom surface 120B of the second conductive portion and the second top surface 1102T of the second conductive sub-portion 1102 are spaced apart by a first distance H1 along the third direction Z, and the depth H2 of the at least one conductive via VH along the third direction Z is less than the first distance H1.

[0136] Reference Figures 1 to 17 In some embodiments, the first conductive portion 110 may include a first conductive connection portion 11 located in the first conductive layer 10. That is, the first conductive connection portion 11 may include a first conductive sub-portion 1101 and a second conductive sub-portion 1102. The thickness of the first conductive sub-portion 1101 along the third direction Z of the first conductive connection portion 11 is greater than the thickness of the second conductive sub-portion 1102 along the third direction Z of the first conductive connection portion 11.

[0137] It should be noted that since the first conductive connection portion 11 is a specific embodiment of the first conductive portion 110 described above, the above description of the first conductive portion can be applied to the first conductive connection portion 11 here. For the specific structure of the first conductive connection portion 11, especially its cross-sectional structure, please refer to the description above.

[0138] The second conductive portion 120 may include a first conductive transition portion 21 located in the second conductive layer 20. The orthographic projection of the first conductive transition portion 21 on the substrate falls within the orthographic projection of the first conductive connection portion 11 on the substrate.

[0139] In this embodiment, the at least one conductive via VH includes a first conductive via VH1, and the at least one conductive plug 1110 includes a first conductive plug 111, the first conductive plug 111 being located within the first conductive via VH1. The orthographic projection of the first conductive adapter 21 on the substrate at least partially overlaps with the orthographic projection of the first conductive via VH1 on the substrate. For example, the orthographic projection of the first conductive adapter 21 on the substrate 100 may cover the orthographic projection of the first conductive via VH1 on the substrate 100. A portion of the orthographic projection of the first conductive via VH1 on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion 1101 of the first conductive connection 11 on the substrate, one end of the first conductive plug 111 being electrically connected to the first sub-conductive portion 1101 of the first conductive connection 11, and the other end of the first conductive plug 11 being electrically connected to the first conductive adapter 21.

[0140] The orthographic projection of the first conductive via VH1 on the substrate at least partially overlaps with the orthographic projection of one of the first source region 301s and the first drain region 301d on the substrate. One of the first source region 301s and the first drain region 301d is electrically connected to the first conductive transition portion 21 through the first conductive via VH1.

[0141] Through the first conductive connection part 11, the first conductive via VH1 and the first conductive transition part 21, the electrical connection between the source s1 or drain d1 of the driving transistor T1 and the first capacitor electrode Cst1 or the second capacitor electrode Cst2 can be realized.

[0142] In some embodiments, the first conductive portion 110 may include a second conductive connection portion 12 located in the first conductive layer 10. For example, a second conductive connection portion 11 may include two first conductive sub-parts 1101 and one second conductive sub-part 1102. The thickness of the first conductive sub-parts 1101 of the second conductive connection portion 12 along the third direction Z is greater than the thickness of the second conductive sub-parts 1102 of the second conductive connection portion 12 along the third direction Z.

[0143] It should be noted that since the second conductive connection portion 12 is a specific embodiment of the first conductive portion 110 described above, the above description of the first conductive portion can be applied to the second conductive connection portion 12 here. For the specific structure of the second conductive connection portion 12, especially its cross-sectional structure, please refer to the description above.

[0144] In embodiments of this disclosure, the second conductive connection portion 12 is electrically connected to the sensing signal line SL.

[0145] The orthographic projection of the second conductive adapter 22 on the substrate overlaps at least partially with the orthographic projection of the second conductive connection 12 on the substrate.

[0146] The at least one conductive via VH includes a second conductive via VH2, and the at least one conductive plug 1110 includes a second conductive plug 112, the second conductive plug 112 being located in the second conductive via VH2.

[0147] The orthographic projection of the second conductive adapter 22 on the substrate at least partially overlaps with the orthographic projection of the second conductive via VH2 on the substrate.

[0148] A portion of the second conductive via VH2 has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion 1101 of the second conductive connection portion 12 on the substrate. One end of the second conductive plug 112 is electrically connected to the first sub-conductive portion 1101 of the second conductive connection portion 12, and the other end of the second conductive plug 112 is electrically connected to the second conductive adapter portion 22.

[0149] The orthographic projection of the second conductive via VH2 onto the substrate at least partially overlaps with the orthographic projection of one of the third source region 303s and the third drain region 303d onto the substrate. One of the third source region 303s and the third drain region 303d is electrically connected to the second conductive transition portion 22 through the second conductive via VH2.

[0150] In some embodiments, the first conductive portion 110 may include a third conductive connection portion 13 located in the first conductive layer 10. For example, a third conductive connection portion 13 may include two first conductive sub-parts 1101 and one second conductive sub-part 1102. The thickness of the first conductive sub-parts 1101 of the third conductive connection portion 13 along the third direction Z is greater than the thickness of the second conductive sub-parts 1102 of the third conductive connection portion 13 along the third direction Z.

[0151] It should be noted that since the third conductive connection portion 13 is a specific embodiment of the first conductive portion 110 described above, the above description of the first conductive portion can be applied to the third conductive connection portion 13 here. For the specific structure of the third conductive connection portion 13, especially its cross-sectional structure, please refer to the description above.

[0152] In embodiments of this disclosure, the third conductive connection portion 23 is a part of the first power signal line VDD. The orthographic projection of the third conductive connection portion 23 on the substrate at least partially overlaps with the orthographic projection of the third conductive connection portion 13 on the substrate.

[0153] The at least one conductive via VH includes a third conductive via VH3, and the at least one conductive plug 1110 includes a third conductive plug 113, the third conductive plug 113 being located in the third conductive via VH3.

[0154] The orthographic projection of the first power signal line VDD on the substrate at least partially overlaps with the orthographic projection of the third conductive via VH3 on the substrate.

[0155] The third conductive connection portion 13 includes two first sub-conductive portions 1101. The orthographic projection of the third conductive via VH3 on the substrate at least partially overlaps with the orthographic projection of one of the two first sub-conductive portions 1101 of the third conductive connection portion 13 on the substrate. One end of the third conductive plug 113 is electrically connected to one of the two first sub-conductive portions 1101 of the third conductive connection portion 13, and the other end of the third conductive plug 113 is electrically connected to the first power signal line VDD.

[0156] The orthographic projection of the fourth conductive adapter 24 on the substrate at least partially overlaps with the orthographic projection of the third conductive connection 13 on the substrate.

[0157] The at least one conductive via VH includes a fourth conductive via VH4, and the at least one conductive plug 1110 includes a fourth conductive plug 114, the fourth conductive plug 114 being located in the fourth conductive via VH4.

[0158] The orthographic projection of the fourth conductive adapter 24 on the substrate at least partially overlaps with the orthographic projection of the fourth conductive via VH4 on the substrate.

[0159] The orthographic projection of the fourth conductive via VH4 on the substrate at least partially overlaps with the orthographic projection of the other of the two first sub-conductive portions 1101 of the third conductive connection portion 13 on the substrate. One end of the fourth conductive plug 114 is electrically connected to the other of the two first sub-conductive portions 1101 of the third conductive connection portion 13, and the other end of the fourth conductive plug 114 is electrically connected to the fourth conductive adapter portion 24.

[0160] In some embodiments, the first conductive portion 110 may include a fourth conductive connection portion 14 located in the first conductive layer 10. For example, a fourth conductive connection portion 14 may include a first conductive sub-portion 1101 and a second conductive sub-portion 1102. The thickness of the first conductive sub-portion 1101 along the third direction Z of the fourth conductive connection portion 14 is greater than the thickness of the second conductive sub-portion 1102 along the third direction Z of the fourth conductive connection portion 14.

[0161] It should be noted that since the fourth conductive connection portion 14 is a specific embodiment of the first conductive portion 110 described above, the above description of the first conductive portion can be applied to the fourth conductive connection portion 14 here. For the specific structure of the fourth conductive connection portion 14, especially its cross-sectional structure, please refer to the description above.

[0162] In embodiments of this disclosure, the orthographic projection of the fifth conductive adapter 25 on the substrate at least partially overlaps with the orthographic projection of the fourth conductive connection 14 on the substrate.

[0163] The at least one conductive via VH includes a fifth conductive via VH5, and the at least one conductive plug 1110 includes a fifth conductive plug 115, the fifth conductive plug 115 being located in the fifth conductive via VH5.

[0164] The orthographic projection of the fifth conductive adapter 25 on the substrate at least partially overlaps with the orthographic projection of the fifth conductive via VH5 on the substrate.

[0165] The orthographic projection of the fifth conductive via VH5 on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion 1101 of the fourth conductive connection portion 14 on the substrate. One end of the fifth conductive plug 115 is electrically connected to the first sub-conductive portion 1101 of the fourth conductive connection portion 14, and the other end of the fifth conductive plug 115 is electrically connected to the fifth conductive adapter portion 25.

[0166] The orthographic projection of the fifth conductive via VH5 onto the substrate at least partially overlaps with the orthographic projection of the other of the third source region 303s and the third drain region 303d onto the substrate. The other of the third source region 303s and the third drain region 303d is electrically connected to the fifth conductive transition portion 25 through the fifth conductive via VH5.

[0167] In embodiments of this disclosure, the orthographic projection of the fifth conductive transition portion 25 on the substrate 100 at least partially overlaps with the orthographic projection of the fifth conductive via VH5 on the substrate 100. For example, the orthographic projection of the fifth conductive transition portion 25 on the substrate 100 may cover the orthographic projection of the fifth conductive via VH5 on the substrate 100. Through this transition conductive structure of the fourth conductive connection portion 14, the fifth conductive via VH5, and the fifth conductive transition portion 25, an electrical connection can be achieved between the source s3 or drain d3 of the sensing transistor T3 and the capacitor trace 5.

[0168] In the embodiments of this disclosure, the orthographic projection of the sixth conductive transition portion 26 on the substrate 100 at least partially overlaps with the orthographic projection of the seventh via VH7 on the substrate 100. For example, the orthographic projection of the sixth conductive transition portion 26 on the substrate 100 may cover the orthographic projection of the seventh via VH7 on the substrate 100. Through such a transition conductive structure as the seventh via VH7 and the sixth conductive transition portion 26, an electrical connection can be achieved between the gate g1 of the driving transistor T1 and the second capacitor electrode Cst2 or the first capacitor electrode Cst1.

[0169] For example, the first power signal line VDD can be electrically connected to the source region s1 or the drain region d1 of the driving transistor T1 through the eighth via VH8.

[0170] For example, in embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the data line DL on the substrate 100 at least partially overlaps with the orthographic projection of the first auxiliary trace 33 on the substrate 100; for example, the orthographic projection of the data line DL on the substrate 100 covers the orthographic projection of the first auxiliary trace 33 on the substrate 100. The data line DL can be electrically connected to the first auxiliary trace 33 through a tenth via VH10. For example, multiple tenth vias VH10 can be arranged at intervals along the second direction Y, and the data line DL can be electrically connected to the first auxiliary trace 33 through multiple spaced-apart tenth vias VH10. In this way, the contact area between the data line DL and the first auxiliary trace 33 can be increased, thereby reducing the contact resistance and lowering the voltage drop on the data line DL.

[0171] In the embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the first auxiliary trace 33, which is electrically connected to the data line for supplying data signals to the pixel driving circuit of the sub-pixel, on the substrate 100 is spaced apart from the orthographic projection of the capacitor trace body 52 of the pixel driving circuit of the sub-pixel on the substrate 100.

[0172] For example, in embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the sensing signal line SL on the substrate 100 at least partially overlaps with the orthographic projection of the second auxiliary trace 34 on the substrate 100. For instance, the orthographic projection of the sensing signal line SL on the substrate 100 covers the orthographic projection of the second auxiliary trace 34 on the substrate 100. The sensing signal line SL can be electrically connected to the second auxiliary trace 34 through an eleventh via VH11. For example, multiple eleventh vias VH11 can be spaced apart along the second direction Y, and the sensing signal line SL can be electrically connected to the first auxiliary trace 33 through multiple spaced-apart eleventh vias VH11. In this way, the contact area between the sensing signal line SL and the second auxiliary trace 34 can be increased, thereby reducing the contact resistance and lowering the voltage drop on the sensing signal line SL.

[0173] For example, in embodiments of this disclosure, for the same sub-pixel, the orthographic projection of the first power signal line VDD on the substrate 100 at least partially overlaps with the orthographic projection of the third auxiliary trace 35 on the substrate 100. For instance, the orthographic projection of the first power signal line VDD on the substrate 100 covers the orthographic projection of the third auxiliary trace 35 on the substrate 100. The first power signal line VDD can be electrically connected to the third auxiliary trace 35 through a twelfth via VH12. For example, multiple twelfth vias VH12 can be spaced apart along the second direction Y, and the first power signal line VDD can be electrically connected to the first auxiliary trace 33 through multiple spaced-apart twelfth vias VH12. In this way, the contact area between the first power signal line VDD and the first auxiliary trace 33 can be increased, thereby reducing the contact resistance and lowering the voltage drop on the first power signal line VDD.

[0174] For example, the data line DL can be electrically connected to the source region s2 or the drain region d2 of the switching transistor T2 through the ninth via VH9.

[0175] In embodiments of this disclosure, two data lines DL are provided between two adjacent sub-pixels in the same row. For example, the two adjacent sub-pixels in the same row include a first sub-pixel SP1 and a second sub-pixel SP2, and the two data lines include a first data line DL1 and a second data line DL2.

[0176] The first data line DL1 is used to supply data signals to the first sub-pixel SP1. The orthographic projection of the main body of the data line DL1, which is used to supply data signals to the pixel driving circuit of the first sub-pixel, on the substrate is spaced apart from the orthographic projection of the capacitor trace main body 52 of the pixel driving circuit of the first sub-pixel on the substrate.

[0177] The second data line DL2 is used to supply data signals to the second sub-pixel SP2. The orthographic projection of the main body of the data line DL2, which is used to supply data signals to the pixel driving circuit of the second sub-pixel, on the substrate is spaced apart from the orthographic projection of the capacitor trace main body 52 of the pixel driving circuit of the second sub-pixel on the substrate.

[0178] For example, the sensing signal line SL includes a first portion SL1 extending along a second direction Y and a second portion SL2 extending along a first direction X. In the first direction X, the second sub-pixel SP2 is adjacent to the sensing signal line SL, and the first sub-pixel SP1 is located on the side of the second sub-pixel SP2 away from the sensing signal line SL.

[0179] For example, one end of the second conductive connection portion 12 is electrically connected to another of the source s3 and drain d3 of the sensing transistor T3 of the pixel driving circuit of the first sub-pixel SP1 through the second conductive via VH2, and the other end of the second conductive connection portion 12 is electrically connected to another of the source s3 and drain d3 of the sensing transistor T3 of the pixel driving circuit of the second sub-pixel SP2 through the sixth via VH6.

[0180] The second portion SL2 of the sensing signal line is electrically connected via the sixth via VH6 to the other end of the second conductive connection portion 12 and to another of the source s3 and drain d3 of the sensing transistor T3 in the pixel driving circuit of the second sub-pixel SP2. In this way, the sensing signal supplied by the sensing signal line SL can be transmitted to each sub-pixel of a pixel unit.

[0181] For example, the first power signal line VDD is located on the side of the first sub-pixel SP1 away from the second sub-pixel SP2. The first power signal line VDD can be electrically connected to the source s1 or drain d1 of the driving transistor T1 through the third conductive via VH3, the third conductive connection part 13, the fourth conductive via VH4, and the fourth conductive transition part 24.

[0182] In embodiments of this disclosure, reference is made to Figure 14 and Figure 17 The pixel delimiting layer (PDL) includes multiple openings 80 for defining the light-emitting areas SPA1, SPA2, SPA3, and SPA4 of multiple sub-pixels.

[0183] Embodiments of this disclosure also provide a display device, which may include the aforementioned display substrate. The display device may include, but is not limited to, any product or component with display functionality, such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0184] While some embodiments of the general concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, The display substrate includes: Substrate; A plurality of pixel units disposed on the substrate are arranged in an array along a first direction and a second direction. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The first direction and the second direction intersect. The first conductive layer disposed on the substrate; A buffer layer disposed on the side of the first conductive layer away from the substrate; A semiconductor layer disposed on the side of the buffer layer away from the substrate; A first insulating layer disposed on the side of the semiconductor layer away from the substrate; and The second conductive layer is disposed on the side of the first insulating layer away from the substrate. The pixel driving circuit includes at least one transistor and a storage capacitor. The at least one transistor includes a source and a drain. The storage capacitor includes a first capacitor electrode and a second capacitor electrode disposed opposite to each other. One of the first capacitor electrode and the second capacitor electrode is located in the first conductive layer. The source and drain of the at least one transistor are located in the second conductive layer. The display substrate includes a first conductive portion located in the first conductive layer and a second conductive portion located in the second conductive layer, wherein the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. The display substrate further includes at least one conductive via and at least one conductive plug located in the at least one conductive via, wherein the at least one conductive via penetrates at least the first insulating layer, and the second conductive portion is electrically connected to the first conductive portion through the at least one conductive plug; and The first conductive portion includes a first conductive sub-portion and a second conductive sub-portion. The orthographic projection of the first conductive sub-portion on the substrate at least partially overlaps with the orthographic projection of the at least one conductive via on the substrate. The thickness of the first conductive sub-portion along a third direction is greater than the thickness of the second conductive sub-portion along a third direction, wherein the third direction is perpendicular to the plane defined by the first direction and the second direction. The display substrate further includes a fourth conductive layer, which is located between the substrate and the first conductive layer. The first conductive portion includes a first conductive connection portion located in the first conductive layer, and at least a portion of the first conductive connection portion serves as the first capacitor electrode or the second capacitor electrode; The other of the first capacitor electrode and the second capacitor electrode is located in the fourth conductive layer and the semiconductor layer, and the orthographic projection of the first capacitor electrode on the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode on the substrate; The at least one transistor includes a driving transistor, the driving transistor including a channel region; The display substrate further includes a first semiconductor portion located in the semiconductor layer, the first semiconductor portion including a first source region, a first drain region and a channel region of the driving transistor; The orthographic projection of the first semiconductor portion on the substrate is located within the orthographic projection of the first conductive connection portion on the substrate, and the orthographic projection of the first semiconductor portion on the substrate at least partially overlaps with the orthographic projection of the fourth conductive layer on the substrate.

2. The display substrate according to claim 1, wherein, The first conductive part includes a first top surface away from the substrate, and the second conductive part includes a second top surface away from the substrate, wherein the first top surface is further away from the substrate in the third direction than the second top surface.

3. The display substrate according to claim 2, wherein, The first conductive part includes a protrusion that protrudes toward the at least one conductive via relative to the second top surface of the second conductive part, and the at least one conductive plug contacts at least a portion of the first top surface of the first conductive part.

4. The display substrate according to any one of claims 1-3, wherein, The buffer layer exposes at least a portion of the first conductive part; and / or, the buffer layer covers the second conductive part.

5. The display substrate according to claim 3, wherein, The buffer layer includes a third top surface away from the substrate, and the first top surface of the first conductive part is substantially flush with the portion of the third top surface adjacent to the first conductive part.

6. The display substrate according to claim 5, wherein, The protrusion includes a first side surface and a second side surface, the first side surface and the second side surface being located on opposite sides of the first top surface, and the first top surface connecting the first side surface and the second side surface; and The buffer layer contacts and covers the second top surface, the first side surface, and the second side surface of the second conductive portion.

7. The display substrate according to claim 5, wherein, The first conductive part includes a first bottom surface near the substrate, and the second conductive part includes a second bottom surface near the substrate. The first bottom surface and the second bottom surface are substantially flush in the third direction.

8. The display substrate according to claim 7, wherein, The second conductive portion includes a third bottom surface near the substrate; at a location adjacent to the at least one conductive via, the third bottom surface of the second conductive portion and the second top surface of the second conductive portion are spaced apart by a first distance along a third direction, and the depth of the at least one conductive via along the third direction is less than the first distance.

9. The display substrate according to any one of claims 1-3, wherein, The second conductive portion includes a first conductive transition portion located in the second conductive layer; as well as The orthographic projection of the first conductive adapter on the substrate falls within the orthographic projection of the first conductive connection on the substrate.

10. The display substrate according to claim 9, wherein, The at least one conductive via includes a first conductive via, and the at least one conductive plug includes a first conductive plug, wherein the first conductive plug is located in the first conductive via; The orthographic projection of the first conductive adapter on the substrate at least partially overlaps with the orthographic projection of the first conductive via on the substrate. as well as A portion of the first conductive via's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the first conductive connection on the substrate. One end of the first conductive plug is electrically connected to the first sub-conductive portion of the first conductive connection, and the other end of the first conductive plug is electrically connected to the first conductive adapter.

11. The display substrate according to claim 10, wherein, The first source region and the first drain region are located on both sides of the channel region of the driving transistor; The orthographic projection of the first conductive via on the substrate at least partially overlaps with the orthographic projection of one of the first source region and the first drain region on the substrate. as well as One of the first source region and the first drain region is electrically connected to the first conductive transition portion through the first conductive via.

12. The display substrate according to claim 11, wherein, The first conductive portion includes a second conductive connection portion located in the first conductive layer, and the display substrate further includes a sensing signal line, wherein the second conductive connection portion is electrically connected to the sensing signal line; The second conductive portion includes a second conductive transition portion located in the second conductive layer; as well as The orthographic projection of the second conductive adapter on the substrate at least partially overlaps with the orthographic projection of the second conductive connection on the substrate.

13. The display substrate according to claim 12, wherein, The at least one conductive via includes a second conductive via, and the at least one conductive plug includes a second conductive plug, wherein the second conductive plug is located in the second conductive via; The orthographic projection of the second conductive adapter on the substrate at least partially overlaps with the orthographic projection of the second conductive via on the substrate. as well as A portion of the second conductive via's orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the second conductive connection on the substrate. One end of the second conductive plug is electrically connected to the first sub-conductive portion of the second conductive connection, and the other end of the second conductive plug is electrically connected to the second conductive adapter.

14. The display substrate according to claim 13, wherein, The at least one transistor includes a sensing transistor, the sensing transistor including a channel region; The display substrate further includes a third semiconductor portion located in the semiconductor layer. The third semiconductor portion includes a third source region, a third drain region, and a channel region of the sensing transistor. The third source region and the third drain region are located on both sides of the channel region of the sensing transistor, respectively. The orthogonal projection of the second conductive via on the substrate at least partially overlaps with the orthogonal projection of one of the third source region and the third drain region on the substrate. as well as One of the third source region and the third drain region is electrically connected to the second conductive transition portion through the second conductive via.

15. The display substrate according to claim 14, wherein, The first conductive portion includes a third conductive connection portion located in the first conductive layer; The second conductive portion includes a third conductive transition portion located in the second conductive layer, and the display substrate includes a first power signal line located in the second conductive layer, wherein the third conductive connection portion is a part of the first power signal line; as well as The orthographic projection of the third conductive adapter on the substrate at least partially overlaps with the orthographic projection of the third conductive connection on the substrate.

16. The display substrate according to claim 15, wherein, The at least one conductive via includes a third conductive via, and the at least one conductive plug includes a third conductive plug, the third conductive plug being located in the third conductive via; The orthographic projection of the first power signal line on the substrate at least partially overlaps with the orthographic projection of the third conductive via on the substrate. as well as The third conductive connection includes two first sub-conductive parts. The orthographic projection of the third conductive via on the substrate at least partially overlaps with the orthographic projection of one of the two first sub-conductive parts of the third conductive connection on the substrate. One end of the third conductive plug is electrically connected to one of the two first sub-conductive parts of the third conductive connection, and the other end of the third conductive plug is electrically connected to the first power signal line.

17. The display substrate according to claim 16, wherein, The second conductive portion further includes a fourth conductive transition portion located in the second conductive layer; as well as The orthographic projection of the fourth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the third conductive connection on the substrate.

18. The display substrate according to claim 17, wherein, The at least one conductive via includes a fourth conductive via, and the at least one conductive plug includes a fourth conductive plug, the fourth conductive plug being located in the fourth conductive via; The orthographic projection of the fourth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the fourth conductive via on the substrate. as well as The orthographic projection of the fourth conductive via on the substrate at least partially overlaps with the orthographic projection of the other of the two first sub-conductive portions of the third conductive connection portion on the substrate. One end of the fourth conductive plug is electrically connected to the other of the two first sub-conductive portions of the third conductive connection portion, and the other end of the fourth conductive plug is electrically connected to the fourth conductive adapter portion.

19. The display substrate according to claim 18, wherein, The first conductive portion includes a fourth conductive connection portion located in the first conductive layer; The second conductive portion includes a fifth conductive transition portion located in the second conductive layer; as well as The orthographic projection of the fifth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the fourth conductive connection on the substrate.

20. The display substrate according to claim 19, wherein, The at least one conductive via includes a fifth conductive via, and the at least one conductive plug includes a fifth conductive plug, the fifth conductive plug being located in the fifth conductive via; The orthographic projection of the fifth conductive adapter on the substrate at least partially overlaps with the orthographic projection of the fifth conductive via on the substrate. as well as The orthographic projection of the fifth conductive via on the substrate at least partially overlaps with the orthographic projection of the first sub-conductive portion of the fourth conductive connection on the substrate. One end of the fifth conductive plug is electrically connected to the first sub-conductive portion of the fourth conductive connection, and the other end of the fifth conductive plug is electrically connected to the fifth conductive adapter.

21. The display substrate according to claim 20, wherein, The orthographic projection of the fifth conductive via on the substrate at least partially overlaps with the orthographic projection of another of the third source region and the third drain region on the substrate. as well as The third source region and the third drain region are electrically connected to the fifth conductive transition section through the fifth conductive via.

22. A display device, characterized in that, The display device includes a display substrate according to any one of claims 1 to 21.

23. A method for manufacturing a display substrate, characterized in that, The method includes: A fourth conductive layer is formed on the substrate. A first conductive material layer is formed on the side of the fourth conductive layer away from the substrate. The first conductive material layer is patterned using a halftone mask process to form a first conductive layer including a first conductive portion. One of the first capacitor electrode and the second capacitor electrode is located in the first conductive layer. The first conductive portion includes a first conductive sub-part and a second conductive sub-part. The first conductive portion also includes a first conductive connection portion located in the first conductive layer. At least a portion of the first conductive connection portion serves as the first capacitor electrode or the second capacitor electrode. A buffer material layer is formed on the side of the first conductive layer away from the substrate. The buffer material layer is patterned using a masking process to form a buffer layer; A semiconductor material layer is formed on the side of the buffer layer away from the substrate. The semiconductor material layer is patterned using a mask process to form a semiconductor layer. The semiconductor layer includes a first semiconductor portion, which includes a first source region, a first drain region, and a channel region for driving transistors. The orthographic projection of the first semiconductor portion on the substrate is located within the orthographic projection of the first conductive connection portion on the substrate. The orthographic projection of the first semiconductor portion on the substrate at least partially overlaps with the orthographic projection of the fourth conductive layer on the substrate. The other of the first capacitor electrode and the second capacitor electrode is located in the fourth conductive layer and the semiconductor layer. The orthographic projection of the first capacitor electrode on the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode on the substrate. A first insulating material layer is formed on the side of the semiconductor layer away from the substrate. The first insulating material layer is patterned using a mask process to form a first insulating layer including at least one conductive via, wherein the at least one conductive via penetrates at least the first insulating layer; A second conductive material layer is formed on the side of the first insulating layer away from the substrate, wherein at least a portion of the second conductive material layer is formed in the at least one conductive via to form at least one conductive plug located in the at least one conductive via; and The second conductive material layer is patterned using a mask process to form a second conductive layer including a second conductive portion, wherein the orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the second conductive portion is electrically connected to the first conductive portion through the at least one conductive plug. Wherein, the orthographic projection of the first conductive part on the substrate at least partially overlaps with the orthographic projection of the at least one conductive via on the substrate, the thickness of the first conductive part along a third direction is greater than the thickness of the second conductive part along a third direction, wherein the third direction is perpendicular to the surface of the substrate near the first conductive layer.

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