A method, apparatus, device and storage medium for operating command processing

Abstract

The application relates to the technical field of solid state disks, and discloses an operation command processing method, device, equipment and storage medium. The method comprises the following steps: starting a hardware accelerator of an SSD master to obtain starting bit identifiers of all operation commands; when it is determined that the starting bit identifiers are not zero, a bit field corresponding to the starting bit identifier with the lowest bit of 1 is found from a register of the SSD master; the bit field is used for indicating the storage position of a target operation command to be executed; configuration information corresponding to the target operation command is read through the bit field; the target operation command is executed according to the configuration information, and the starting bit identifier is changed to zero when the execution is completed, until the starting bit identifiers of all operation commands are zero. According to the application, the bit field corresponding to the starting bit identifier with the lowest bit of 1 is found from the register to locate the next operation command to be executed, so that the operation command can be quickly located, and power consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of solid-state drive technology, and in particular to an operation command processing method, apparatus, device and storage medium. Background Technology

[0002] SSD (Solid State Disk) is a type of permanent storage device. Due to its advantages, such as fast read and write speeds, light weight, low power consumption, and small size, which are not found in traditional mechanical hard drives, SSD devices have been widely used in the market.

[0003] In existing technologies, SSD controllers use numerous command packets to perform read and write operations on the NAND controller. However, these multiple read / write commands are not necessarily contiguous within the storage space, and are typically executed sequentially. After executing one command, the system searches for and executes the next valid command. In extreme cases, such as when cmd0 becomes valid until cmdN becomes valid, there might be N-1 invalid cmd commands in between. Searching sequentially would take at least N-1 clock cycles. This results in significant latency, which noticeably impacts overall system performance. Summary of the Invention

[0004] In view of this, in order to solve the problems existing in the prior art, this application provides an operation command processing method, apparatus, device and storage medium.

[0005] Firstly, this application provides an operation command processing method, including:

[0006] Start the hardware accelerator of the SSD controller to obtain the boot bit identifier of all operation commands;

[0007] When it is determined that the boot bit identifier is not zero, the bit field corresponding to the boot bit identifier with the least significant bit set to 1 is retrieved from the register of the SSD controller; wherein, the bit field is used to indicate the storage location of the target operation command to be executed;

[0008] The configuration information corresponding to the target operation command is read through the bit field;

[0009] According to the configuration information, the target operation command is executed, and upon completion of execution, the start bit flag is changed to zero until the start bit flag of all the operation commands is zero.

[0010] In an optional implementation, before starting the hardware accelerator of the SSD controller to obtain the boot bit identifier of all operation commands, the method further includes:

[0011] Invert the initial start bit flags of all the operation commands bit by bit to obtain the start bit flag inverse code;

[0012] Perform carry processing on the inverse code of the start bit identifier to obtain the complement code of the start bit identifier;

[0013] After performing a bitwise AND operation on the initial start bit identifier and the two's complement of the start bit identifier, the start bit identifier is obtained, and all the start bit identifiers are combined into a register.

[0014] In an optional implementation, before starting the hardware accelerator of the SSD controller to obtain the boot bit identifier of all operation commands, the method further includes:

[0015] The command information corresponding to all the operation commands is divided according to functional attributes to obtain static information and dynamic information; wherein, each operation command contains multiple bits of command information;

[0016] The static information is stored in a static random access memory, and the dynamic information is stored in a trigger memory.

[0017] In an optional implementation, reading the configuration information corresponding to the target operation command includes:

[0018] The static information corresponding to the target operation command is read from the static random access memory, and the dynamic information corresponding to the target operation command is read from the trigger memory.

[0019] In an optional implementation, the method further includes: if the start bit identifier of the operation command is zero, then the operation command processing flow is terminated.

[0020] In an optional implementation, if the target operation command is used to instruct reading target data from flash memory, after executing the target operation command according to the configuration information, the method further includes:

[0021] The target data is read from the flash memory of the SSD controller using the target operation command.

[0022] The target data is stored in the corresponding cache, and a data read completion message is sent to the control chip of the SSD controller.

[0023] In an optional implementation, after storing the target data in the corresponding cache and sending data read completion information to the SSD controller's control chip, the method further includes:

[0024] The target data is read from the cache and transmitted to the peripheral controller.

[0025] Secondly, this application provides an operation command processing apparatus, comprising:

[0026] The acquisition module is used to start the hardware accelerator of the SSD controller to obtain the start bit identifier of all operation commands;

[0027] The lookup module is used to find the bit field corresponding to the boot bit identifier whose least significant bit is 1 from the register of the SSD controller when it is determined that the boot bit identifier is not zero; wherein, the bit field is used to indicate the storage location of the target operation command to be executed;

[0028] The reading module is used to read the configuration information corresponding to the target operation command through the bit field;

[0029] The processing module is used to execute the target operation command according to the configuration information, and change the start bit identifier to zero when the execution is completed, until the start bit identifier of all the operation commands is zero.

[0030] Thirdly, this application provides a computer device, the computer device including a solid-state drive and at least one processor, the solid-state drive storing a computer program, and the processor executing the computer program to implement the aforementioned operation command processing method.

[0031] Fourthly, this application provides a computer-readable storage medium storing a computer program, which, when executed, implements the aforementioned operation command processing method.

[0032] The embodiments of this application have the following beneficial effects:

[0033] This application provides an operation command processing method, which includes: activating the hardware accelerator of an SSD controller to obtain the startup bit identifiers of all operation commands; when the startup bit identifier is determined to be non-zero, searching the register of the SSD controller to obtain the bit field corresponding to the startup bit identifier whose least significant bit is 1; wherein the bit field is used to indicate the storage location of the target operation command to be executed; reading the configuration information corresponding to the target operation command through the bit field; executing the target operation command according to the configuration information, and changing the startup bit identifier to zero upon completion of execution, until the startup bit identifiers of all operation commands are zero. This application provides a method for quickly locating the next operation command to be executed by searching the register of the SSD controller to obtain the bit field corresponding to the startup bit identifier whose least significant bit is 1, thereby reducing power consumption. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. In the various drawings, similar components are numbered similarly.

[0035] Figure 1 A schematic diagram of the SSD controller structure is shown;

[0036] Figure 2 This diagram illustrates the first type of data transfer process on an SSD controller.

[0037] Figure 3 This diagram illustrates the second type of data transfer process on the SSD controller.

[0038] Figure 4 A schematic diagram of the hardware accelerator structure is shown;

[0039] Figure 5 A schematic diagram of the startup command module is shown;

[0040] Figure 6 A schematic diagram illustrating the sequential execution process of operation commands is shown;

[0041] Figure 7 A schematic diagram of the first embodiment of the operation command processing method in this application is shown;

[0042] Figure 8 A schematic diagram of a second embodiment of the operation command processing method in this application is shown;

[0043] Figure 9 A schematic diagram of a third embodiment of the operation command processing method in this application is shown;

[0044] Figure 10 A schematic diagram of a fourth embodiment of the operation command processing method in this application is shown;

[0045] Figure 11 A schematic diagram of the operation command processing device in an embodiment of this application is shown. Detailed Implementation

[0046] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0047] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0048] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0049] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0051] SATA (Serial Advanced Technology Accessory): is a computer bus interface used to connect host bus adapters to high-capacity storage devices such as optical drives and hard drives.

[0052] like Figure 1As shown, the SSD controller 100 and flash memory 300 (i.e., NAND FLASH) can be integrated into a single SSD device (i.e., solid-state drive). The SSD controller 100 mainly includes a control chip 110 (i.e., CPU), a front-end interface control module 120 (including the physical layer chip SATA_PHY and the control terminal SATA_CTRL), dynamic random access memory (i.e., DRAM) / static random access memory 140 (i.e., SRAM), and a back-end interface control module 130 (i.e., NAND_FLASH_CTRL). The CPU is responsible for the overall operation of the controller, realizing data read and write transmission; SATA_PHY, SATA_CTRL, etc., are the front-end interface control module 120 of the controller, used for data communication with the external host interface specified by the protocol; DRAM / SRAM is used for caching internal data of the controller; NAND_FLASH_CTRL is used to control the read and write of NAND FLASH. Currently, in addition to SATA, the mainstream front-end interfaces in the market also include interfaces such as PCIe. This embodiment uses SATA as the front-end interface for illustration.

[0053] like Figure 2 As shown, ① the peripheral controller 200 (i.e., SATA_HOST, such as a PC) sends a read data command to the SSD main controller 100 (the front-end interface control module 120 performs protocol processing and initial data parsing); ② the front-end interface control module 120 notifies the control chip 110 to process the read data command through interrupt or status information; ③ after parsing, the control chip 110 configures the back-end interface control module 130 to read the corresponding target data from the flash memory 300; ④ according to the configuration of the control chip 110, the back-end interface control module 130 sends the synchronous and asynchronous mode standard (i.e., ONFI / Toggle) based on the flash memory 300 to the flash memory 300. The following steps are described: ⑤ The flash memory 300 returns the read target data; ⑥ The back-end interface control module 130 stores the read target data into the dynamic random access memory / static random access memory according to the storage address configured by the control chip 110; ⑦ The back-end interface control module 130 notifies the control chip 110 to complete the data reading; ⑧ The control chip 110 configures SATA_CTRL; ⑨ SATA_CTRL starts reading data from the dynamic random access memory (i.e., DRAM) / static random access memory (SRAM) 140; ⑩ The front-end interface control module 120 transmits the read data to the peripheral controller 200 via a cable (i.e., SATA cable). The process of the peripheral controller 200 writing data to the SSD main controller 100 is similar and will not be described in detail in this embodiment.

[0054] In the above process, the transmission of front-end and back-end data relies entirely on the control chip 110. In mainstream application scenarios of SSD controller 100, such as handling large-volume data transmission, it will consume a lot of the processing time of the control chip 110, which is not conducive to the SSD controller 100 performing other operations. This results in a large data transmission delay, which greatly affects the effective bandwidth of the controller's data transmission, resulting in low data read and write throughput and low efficiency of the entire product.

[0055] like Figure 3 As shown, hardware acceleration is typically designed between the front-end interface and the back-end interface to offload the load of the control chip 110 on moving the target data.

[0056] like Figure 4 As shown, the ATM (Automatic Transfer Module) module is the hardware accelerator 150. To offload the data transfer load from the control chip 110, the hardware accelerator 150 needs to store the operation commands (cmd) configured by the control chip 110. Typically, there are many operation commands (dozens or hundreds). Each operation command also contains a lot of configuration information (tens or more bits), covering front-end SATA, back-end NFI, SRAM / DRAM operations, process status control, etc. Specifically, the startup command module 151 (CMD ENTRY) stores the operation commands configured by the control chip 110. The serial input / output interface control module 152 (SATA IO CTRL) interacts with the front-end SATA CTRL, controlling its data reading and writing. The flash input / output control module 153 (NAND FLASH IO CTRL) interacts with the back-end NAND CTRL, controlling its data reading and writing. The finite state machine 154 (FSM) controls the overall operation of the hardware accelerator 150, completing data transmission according to the relevant operation commands from the startup command module 151. Memory control module 155 (i.e. RAM CTRL): Interacts with SRAM / DRAM buffer to manage and maintain data storage space.

[0057] like Figure 5As shown, the startup command module 151 stores a large number of operation commands to better offload the load of the control chip 110. Each operation command also contains a lot of command information. For example, a cmd (cmd0, cmd1, cmd2, ..., cmdN as shown in the figure) contains command information such as cmd_enable, cmd_ctrl, lba_blocks_sts, map_info, etc. The startup bit flag (i.e., cmd_enable) corresponding to each operation command indicates whether the current cmd is valid. When the control chip 110 configures the cmd, it sets cmd_enable to 1. After the hardware accelerator 150 finishes executing the cmd, it sets cmd_enable to 0, indicating that the execution of the cmd is complete. For N cmds, each cmd contains M bits of command information, and the required equivalent register is M*N bits. For the storage of this part of command information, there are two existing schemes:

[0058] Option 1: Use a flip-flop memory (DFF) to store M*N bit information, requiring an M*N bit DFF;

[0059] Option 2: Use static random access memory (SRAM) to store M*N bit information, which requires an SRAM with a depth of N and a width of M.

[0060] like Figure 6 As shown, a common approach to executing stored operation commands is to execute them sequentially. After the current cmd_m command (i.e., the cmd_m process shown in the diagram) completes, the next valid cmd command (i.e., the cmd_n process shown in the diagram) is searched by incrementing by 1. Considering that there may be invalid commands (ENTRY) between two valid cmd commands, a certain search time (i.e., long latency) is required before finding the next valid cmd command (i.e., the srch nxt cmd command shown in the diagram). Based on this, the above-mentioned command information storage scheme has the following disadvantages:

[0061] Regarding the first option mentioned above: using DFFs to store M*N bits of information requires M*N bits of DFFs. When the values ​​of M and N are large, the number of DFFs used is also large. Considering the area and power consumption of the DFFs, this may lead to a large area overhead for the entire main control chip, and also introduces the problem of high power consumption. In addition, during back-end layout and routing, this part of the DFFs may experience routing congestion, thereby introducing the risk of increased latency. This poses a significant challenge to the timing convergence and PPA performance of the entire main control chip.

[0062] Regarding the second option mentioned above: using SRAM to store M*N bit information requires an SRAM of depth N and width M. The advantage of using SRAM compared to DFF is the relatively smaller area overhead. However, SRAM operations have a higher latency than DFF operations, especially when reading data from SRAM. Furthermore, storing command-type data in SRAM may require frequent SRAM accesses, leading to increased power consumption.

[0063] The above-mentioned scheme of executing stored command information sequentially has the following drawbacks: multiple operation commands are not necessarily consecutive in the storage space, and the next operation command is usually processed sequentially. However, after executing one operation command, searching for the next valid operation command and executing it, in extreme cases such as from valid cmd0 to valid cmdN, with an interval of N-1 invalid cmds, would take at least N-1 clock cycles to search sequentially. This results in significant latency and has a noticeable impact on the overall system performance.

[0064] Based on this, this application provides an operation command processing method. This application provides a method to locate the next operation command to be executed by finding the bit field corresponding to the start bit identifier whose least significant bit is 1 from the register of the SSD controller 100. This achieves fast location of operation commands and reduces power consumption.

[0065] Please see Figure 7 The method will now be explained in detail.

[0066] S10, activate the hardware accelerator 150 of the SSD controller 100 to obtain the boot bit identifier of all operation commands.

[0067] S20: When it is determined that the boot bit flag is not zero, the bit field corresponding to the boot bit flag with the least significant bit set to 1 is retrieved from the register of the SSD controller 100.

[0068] S30 reads the configuration information corresponding to the target operation command through the bit field.

[0069] S40 executes the target operation command according to the configuration information, and changes the start bit flag to zero when the execution is completed, until the start bit flag of all operation commands is zero.

[0070] In this embodiment, the hardware accelerator 150 is pre-enabled via the control chip 110 of the SSD controller 100. When the hardware accelerator 150 is started, the hardware of the hardware accelerator 150 obtains the start bit identifier (i.e., cmd_enable bit) of all operation commands (i.e., cmd). This start bit identifier is used to indicate the current status of the corresponding operation command, and the start bit identifier is only one bit. If the start bit identifier is 0, it means that the operation command has been executed or is invalid; if the start bit identifier is 1, it means that the operation command is pending execution.

[0071] Furthermore, if it is determined that the boot bit flag corresponding to an operation command is not zero, the least significant bit of the boot bit flag is found to be 1 in the registers within the SSD controller 100. The operation command corresponding to this boot bit flag is then identified as the next target operation command to be executed. The bit field corresponding to this boot bit flag is determined, where the bit field indicates the storage location of the target operation command to be executed. Further, if the boot bit flag of the operation command is zero, the operation command processing flow ends.

[0072] The configuration information corresponding to the target operation command is read through this bit field, and the target operation command is then executed. Upon completion of the target operation command, its activation bit is changed to zero. Similarly, the above steps are repeated until the activation bit of all operation commands is zero, indicating that there are currently no operation commands to be executed.

[0073] It's understandable that the hardware accelerator 150 determines whether there is a valid operation command to be executed based on whether all the cmd_enable bits are 0. If all the cmd_enable bits are 0, it is considered that no operation command needs to be executed, and the operation command processing flow is directly terminated. If not all the cmd_enable bits are 0, it is considered that there is a valid operation command to be executed. At this time, the position of the first operation command to be executed is determined by searching the bit field where the least significant bit is 1. Then, the configuration information related to the operation command is read through the position information, and the operation command is executed according to the read configuration information. When the current operation command is completed, the cmd_enable bit is written back, and the bit field corresponding to the current operation command is written to 0, indicating that the current operation command has been executed.

[0074] As an optional implementation method, such as Figure 8 As shown, prior to S10 above, the embodiments of this application further include the following steps:

[0075] S51, invert the initial start bit flags of all operation commands bit by bit to obtain the start bit flag inverse code.

[0076] S52 performs carry processing on the inverse code of the start bit identifier to obtain the complement code of the start bit identifier.

[0077] S53 performs a bitwise AND operation on the initial start bit flag and the start bit flag complement to obtain the start bit flag, and then combines all the start bit flags into a register.

[0078] It's understandable that data in computer programs is stored in two's complement form. Negative numbers need to be converted from their original code to two's complement for storage. For example, the two's complement of a positive number is its original code. Let's say we have a number to be stored in a computer program, denoted as 'a', and its negative form as 'b'. We know that a + b = 0. The solution is to first invert all the bits that are 0 in the binary number, then add 1, causing a carry-over, resulting in an overflow of 0. For example, 6 = 0000 0110, -6 = 1111 1001 + 1 = 11111010. It's clear that the least significant bit is 1, and after inverting the value 0, all bits become 1. Adding 1 and carrying over, all the 1s obtained from the inversion are carried over, and the least significant bit remains unchanged.

[0079] Then, through the above logic, the initial start bit identifier of all operation commands is inverted bit by bit, and then carry is performed (i.e., 1 is added) to obtain the start bit identifier complement. The start bit identifier complement is ANDed with the initial start bit identifier to obtain the start bit identifier corresponding to the operation command, which is the start bit identifier corresponding to the operation command that is stored by the computer.

[0080] The cmd_enable bits of N cmd are set into an N-bit wide register according to the predetermined execution order of cmd. Therefore, the position of the bit with the least significant bit being 1 can be found through the above logic.

[0081] As an optional implementation method, such as Figure 9 As shown, prior to S10 above, the embodiments of this application further include the following steps:

[0082] S61 divides the command information corresponding to all operation commands according to their functional attributes, resulting in static information and dynamic information.

[0083] S62, store static information in static random access memory and dynamic information in trigger memory.

[0084] In this embodiment, since each operation command contains multiple bits of command information, the command information corresponding to all operation commands can be divided according to functional attributes and stored separately. Static information is stored in Static Random Access Memory (SRAM), and dynamic information is stored in Trigger Memory (DFF). When subsequently reading the configuration information corresponding to the target operation command, the static information corresponding to the target operation command is read from the SRAM, and the dynamic information corresponding to the target operation command is read from the DFF. Furthermore, the static information read from the SRAM can be stored in a preset common DFF for convenient subsequent processing of this static information.

[0085] Specifically, the M bits of cmd are divided into static and dynamic configurations based on their functional attributes. Static configuration refers to configuration content that does not change during the execution of the operation command, such as the operation command type, LBA information, and mapping information. Dynamic configuration refers to configuration content that changes during the execution of the operation command, such as operation command enable, execution status, presence of errors, and execution completion flags. Using DFF to store dynamic information facilitates timely processing by the hardware accelerator 150 / control chip 110. Given the small number of bits in this part, compared to storing all configuration information entirely in SRAM, it reduces the latency and power consumption overhead caused by frequent SRAM accesses, thus effectively achieving a balance between performance and power consumption.

[0086] Furthermore, dynamic information is stored using DFF (Dynamic File Frame) and static information is stored using SRAM. A common DFF is used to store the static information of the currently executing command. The static information of each command only needs to be read from SRAM when that command is executed; otherwise, SRAM access is not required. Since the static information configuration is usually extensive, using SRAM for storage helps save area overhead and reduces the frequency of SRAM access from a functional perspective, further reducing power consumption. Subsequently, the control chip 110 writes the startup command module 151 through the configuration register. The hardware accelerator 150 internally distinguishes between dynamic and static information and stores them in DFF and SRAM respectively.

[0087] As an optional implementation method, such as Figure 10 As shown, if the target operation command is used to instruct the reading of target data from flash memory 300, then this embodiment further includes the following steps after S40:

[0088] S71 reads target data from the flash memory 300 of the SSD controller 100 via target operation commands.

[0089] S72 stores the target data in the corresponding cache and sends a data read completion message to the control chip 110 of the SSD controller 100.

[0090] S73 reads the target data from the cache and transmits the target data to the peripheral controller 200.

[0091] In this embodiment, if target data is read from flash memory 300 through target operation instructions and sent to peripheral controller 200, the operation of reading data from SSD main controller 100 is realized. Subsequently, the corresponding target data is read through the target operation instructions and stored in the cache so that the target data can be transmitted to peripheral controller 200 through the cache.

[0092] Similarly, if the target data is written to the SSD controller 100 through the target operation command, the process is the reverse of the process of reading data from the SSD controller 100, so it will not be described in detail here.

[0093] This embodiment locates the next operation command to be executed by finding the bit field corresponding to the start bit identifier with the least significant bit set to 1 in the register of the SSD main controller 100. This achieves rapid location of operation commands, reduces power consumption, and reduces the execution delay between operation commands. Furthermore, since this embodiment does not sequentially traverse to find the next operation command to be executed according to the configuration order, it does not require that the effective operation commands be filled in tightly when configuring operation commands, so as to ensure the flexibility of the configuration of the control chip 110.

[0094] Please see Figure 11 This application provides an operation command processing device, the device comprising:

[0095] The module 510 is used to start the hardware accelerator 150 of the SSD controller 100 to obtain the start bit identifier of all operation commands.

[0096] The lookup module 520 is used to find the bit field corresponding to the boot bit identifier whose least significant bit is 1 from the register of the SSD main controller 100 when it is determined that the boot bit identifier is not zero; wherein, the bit field is used to indicate the storage location of the target operation command to be executed;

[0097] The reading module 530 is used to read the configuration information corresponding to the target operation command through the bit field;

[0098] The processing module 540 is used to execute the target operation command according to the configuration information, and change the start bit identifier to zero when the execution is completed, until the start bit identifier of all the operation commands is zero.

[0099] It is understood that the above-described operation command processing device corresponds to the operation command processing method of the above embodiment; any option in the above embodiment is also applicable to this embodiment, and will not be described in detail here.

[0100] This application also provides a computer device, which includes a solid-state drive and at least one processor. The solid-state drive stores a computer program, and the processor is used to execute the computer program to implement the operation command processing method of the above embodiments.

[0101] Solid-state drives (SSDs) may include a program storage area and a data storage area. The program storage area may store the operating system and at least one application required for a function; the data storage area may store data created based on the use of the computer device (such as configuration information). Furthermore, the memory may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device, flash memory, or other volatile solid-state storage devices.

[0102] This application also provides a computer storage medium storing computer-executable instructions. When the computer-executable instructions are invoked and executed by a processor, the computer-executable instructions cause the processor to perform the steps of the operation command processing method described in the above embodiments.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable operational commands for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer operational commands.

[0104] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0105] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several operation commands to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for processing operation commands, characterized in that, include: Start the hardware accelerator of the SSD controller to obtain the boot bit identifier of all operation commands; When it is determined that the boot bit identifier is not zero, the bit field corresponding to the boot bit identifier with the least significant bit set to 1 is retrieved from the register of the SSD controller; wherein, the bit field is used to indicate the storage location of the target operation command to be executed; The configuration information corresponding to the target operation command is read through the bit field; According to the configuration information, the target operation command is executed, and upon completion of execution, the start bit identifier is changed to zero until the start bit identifier of all the operation commands is zero; Before the hardware accelerator of the SSD controller is started to obtain the boot bit identifier of all operation commands, the following is also included: Invert the initial start bit flags of all the operation commands bit by bit to obtain the start bit flag inverse code; Perform carry processing on the inverse code of the start bit identifier to obtain the complement code of the start bit identifier; After performing a bitwise AND operation on the initial start bit identifier and the two's complement of the start bit identifier, the start bit identifier is obtained, and all the start bit identifiers are combined into a register.

2. The operation command processing method according to claim 1, characterized in that, Before the hardware accelerator of the SSD controller is started to obtain the boot bit identifier of all operation commands, the following is also included: The command information corresponding to all the operation commands is divided according to functional attributes to obtain static information and dynamic information; wherein, each operation command contains multiple bits of command information; The static information is stored in a static random access memory, and the dynamic information is stored in a trigger memory.

3. The operation command processing method according to claim 1 or 2, characterized in that, The step of reading the configuration information corresponding to the target operation command includes: The static information corresponding to the target operation command is read from the static random access memory, and the dynamic information corresponding to the target operation command is read from the trigger memory.

4. The operation command processing method according to claim 1 or 2, characterized in that, The method further includes: if the start bit flag of the operation command is zero, then the operation command processing flow is terminated.

5. The operation command processing method according to claim 1 or 2, characterized in that, If the target operation command is used to instruct the reading of target data from flash memory, after executing the target operation command according to the configuration information, the method further includes: The target data is read from the flash memory of the SSD controller using the target operation command. The target data is stored in the corresponding cache, and a data read completion message is sent to the control chip of the SSD controller.

6. The operation command processing method according to claim 5, characterized in that, After storing the target data in the corresponding cache and sending data read completion information to the control chip of the SSD controller, the process further includes: The target data is read from the cache and transmitted to the peripheral controller.

7. An operation command processing device, characterized in that, include: The acquisition module is used to start the hardware accelerator of the SSD controller to obtain the start bit identifier of all operation commands; The lookup module is used to find the bit field corresponding to the boot bit identifier whose least significant bit is 1 from the register of the SSD controller when it is determined that the boot bit identifier is not zero; wherein, the bit field is used to indicate the storage location of the target operation command to be executed; The reading module is used to read the configuration information corresponding to the target operation command through the bit field; The processing module is configured to execute the target operation command according to the configuration information, and change the start bit identifier to zero when the execution is completed, until the start bit identifier of all the operation commands is zero; Before the hardware accelerator of the SSD controller is started to obtain the boot bit identifier of all operation commands, the following is also included: Invert the initial start bit flags of all the operation commands bit by bit to obtain the start bit flag inverse code; Perform carry processing on the inverse code of the start bit identifier to obtain the complement code of the start bit identifier; After performing a bitwise AND operation on the initial start bit identifier and the two's complement of the start bit identifier, the start bit identifier is obtained, and all the start bit identifiers are combined into a register.

8. A computer device, characterized in that, The computer device includes a solid-state drive and at least one processor, the solid-state drive storing a computer program, and the processor executing the computer program to implement the operation command processing method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed, implements the operation command processing method according to any one of claims 1-6.

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