Instruction generation method and device, equipment and storage medium

Abstract

The invention provides an instruction generation method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a first instruction format, the first instruction format comprises a coding position of a fixed bit field, and the coding position is provided with corresponding preset coding information; according to a coding length corresponding to the coding position, randomly generating a plurality of preset splicing instructions; the coding length of the preset splicing instruction is consistent with the coding length; selecting the preset instruction of which the instruction format is not consistent with the second instruction format from a plurality of preset instructions as a generated target instruction; the preset instruction is an instruction after the preset splicing instruction is coded and filled, and the second instruction format is any one of a plurality of instruction formats included in the current instruction set architecture except the first instruction format. The instruction generation efficiency can be improved, and the verification accuracy can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction generation method, device, electronic device and computer-readable storage medium. Background Art

[0002] The CPU core (Central Processing Unit Core) is the core part of the central processing unit, responsible for executing various instructions and processing data. During the CPU design and development process, an instruction generator is needed to perform in-core verification. When verifying the CPU core, it is necessary to perform large-scale testing on illegal instructions, or to interleave testing on legal instructions and illegal instructions. Therefore, when the instruction generator generates an instruction stream, it is necessary to be able to generate illegal instructions in batches on a large scale.

[0003] In the related art, when generating illegal instructions, it is usually necessary to first generate legal instructions, and then manually modify the fixed bit segment encoding of the legal instructions to make them illegal instructions. However, using this method, it is necessary to analyze the encoding format of the legal instructions one by one, and manually modify the specific bit segments, which cannot achieve batch generation, resulting in low instruction generation efficiency. In addition, since manual modification of the bit segments may accidentally generate legal instructions, it is impossible to trigger the target verification scenario, which will result in some functional points not being actually tested, and there may be hidden functional defects that are not discovered, thereby causing security vulnerabilities. Summary of the invention

[0004] The embodiments of the present application provide an instruction generation method, device, electronic device and computer-readable storage medium to solve the problems in the related art.

[0005] In a first aspect, an embodiment of the present application provides a method for generating an instruction, the method comprising: Acquire a first instruction format, wherein the first instruction format includes an encoding position of a fixed bit segment, and corresponding preset encoding information is set at the encoding position; According to the code length corresponding to the code position, a plurality of preset splicing instructions are randomly generated; the code length of the preset splicing instructions is consistent with the code length; From multiple preset instructions, select the preset instruction whose instruction format does not conform to the second instruction format as the generated target instruction; the preset instruction is the instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format of the multiple instruction formats included in the current instruction set architecture except the first instruction format.

[0006] In a second aspect, an embodiment of the present application provides an instruction generation device, the device comprising: An acquisition module, used for acquiring a first instruction format, wherein the first instruction format includes an encoding position of a fixed bit segment, and corresponding preset encoding information is set at the encoding position; A generating module, used for randomly generating a plurality of preset splicing instructions according to the code length corresponding to the code position; the code length of the preset splicing instructions is consistent with the code length; A determination module is used to select, from multiple preset instructions, a preset instruction whose instruction format does not conform to a second instruction format as a generated target instruction; the preset instruction is an instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format other than the first instruction format among the multiple instruction formats included in the current instruction set architecture.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0009] In the embodiment of the present application, by obtaining a first instruction format, the first instruction format includes a coding position of a fixed bit segment, and the coding position is provided with corresponding preset coding information; according to the coding length corresponding to the coding position, a plurality of preset splicing instructions are randomly generated; the coding length of the preset splicing instruction is consistent with the coding length; from a plurality of preset instructions, the preset instruction whose instruction format does not conform to the second instruction format is selected as the generated target instruction; the preset instruction is the instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format other than the first instruction format among the plurality of instruction formats included in the current instruction set architecture. In this way, a large number of illegal instructions can be automatically generated at the same time through the preset first instruction format and the randomized generation mechanism, so that batch generation of instructions can be realized, and the efficiency of instruction generation can be improved; and by selecting the instruction format that does not conform to the second instruction format from a plurality of preset instructions (the instruction after encoding and filling the preset splicing instruction), as the target instruction, through this screening mechanism, the generation of legal instructions can be effectively avoided, and the generated instructions can be ensured to be illegal instructions, thereby improving the effectiveness of the instructions, so that the illegal instructions can more reliably trigger the target verification scenario, and improve the accuracy of verification.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a flow chart of an instruction generation method provided in an embodiment of the present application; Figure 2 is a flow chart of another instruction generation method provided in an embodiment of the present application; Figure 3 is a schematic diagram of an instruction format provided in an embodiment of the present application; Figure 4 is a schematic diagram of another instruction format provided in an embodiment of the present application; Figure 5 is a block diagram of an instruction generation device provided in an embodiment of the present application; Figure 6 is a block diagram of an electronic device provided by an embodiment of the present invention; Figure 7 is a block diagram of another electronic device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0015] Before introducing the instruction generation method, device, electronic device and storage medium provided by the present disclosure, the application scenarios involved in each embodiment of the present disclosure are first introduced. The present disclosure can be applied to the CPU core verification scenario, where the CPU is the core part of the central processing unit, responsible for executing various instructions and processing data.

[0016] The in-core verification of the CPU is an important process to ensure the correct implementation of the CPU core functions. It requires comprehensive testing of various situations, including the handling of illegal instructions and the handling of situations where legal instructions and illegal instructions are mixed. Among them, the instruction generator is a commonly used tool in in-core verification. Its function is to generate instruction streams to test the CPU core. Since in-core verification requires large-scale testing and interleaving testing of illegal instructions, the instruction generator must have the ability to generate illegal instructions in large batches.

[0017] An illegal instruction is an instruction whose binary code is different from the fixed-bit segment code of any instruction in any format in the instruction set architecture. In other words, if the binary code of the instruction does not match the fixed-bit segment code of all known legal instructions in the fixed-bit segment, it can be determined to be an illegal instruction. When the CPU encounters an illegal instruction during execution, a corresponding mechanism is set up to handle it, such as generating an abnormal interrupt, and the purpose of in-core verification is to test whether the CPU handles the illegal instruction correctly.

[0018] Among them, the instructions in the instruction set architecture contain some bit encodings, which represent information such as logical register numbers (for example, registers specified to participate in operations), immediate values ​​(constants directly included in instructions), etc. Because this information can change in different instruction usage scenarios, the corresponding bit segments are called variable bit segments. For example, in an addition instruction, the operands can be different registers or immediate values, which are represented by variable bit segments. There are also some bits whose encodings are fixed, which play a key role in identifying instruction formats, types, etc. in instructions. These are fixed bit segments. Instructions of different formats have different numbers of fixed bit segments. The position of fixed bit segments in instructions will also vary depending on the instruction format. For different instructions of the same format, although the format is the same, the encoding of the fixed bit segment is different, so as to distinguish the specific instruction functions. For example, in the same arithmetic operation instruction format, the fixed bit segment encodings of addition instructions and subtraction instructions will be different, so that the CPU can recognize different operation operations.

[0019] In the related art, when generating illegal instructions, it is usually necessary to first generate legal instructions, and then manually modify the fixed bit segment encoding of the legal instructions to make them illegal instructions. However, using this method, it is necessary to analyze the encoding format of the legal instructions one by one, and manually modify the specific bit segments, which cannot achieve batch generation, resulting in low instruction generation efficiency. In addition, since manual modification of the bit segments may accidentally generate legal instructions, it is impossible to trigger the target verification scenario, which will result in some functional points not being actually tested, and there may be hidden functional defects that are not discovered, thereby causing security vulnerabilities.

[0020] In order to solve the above problems, the present disclosure provides an instruction generation method, device, electronic device and computer-readable storage medium, which can automatically and simultaneously generate a large number of illegal instructions through a preset first instruction format and a randomized generation mechanism, and can realize batch generation of instructions to improve instruction generation efficiency, and by selecting from multiple preset instructions (instructions after encoding and filling preset splicing instructions), the instruction format that does not conform to the second instruction format is selected as the target instruction. Through this screening mechanism, it is possible to effectively avoid the generation of legal instructions and ensure that the generated instructions are illegal instructions, thereby improving the effectiveness of illegal instructions, enabling illegal instructions to more reliably trigger target verification scenarios, and improving the accuracy of verification.

[0021] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0022] Figure 1 is a flow chart of a method for generating instructions provided in an embodiment of the present application, such as Figure 1 As shown, the method is applied in a CPU, which is the core part of a central processing unit and is responsible for executing various instructions and processing data.

[0023] The method may include the following steps.

[0024] In step 101, a first instruction format is obtained.

[0025] The first instruction format includes a coding position of a fixed bit segment, and corresponding preset coding information is set at the coding position.

[0026] In this embodiment, the instruction format is a regulation of the binary encoding structure of the instruction, which clarifies how the instruction is represented and organized in the computer. Different instruction set architectures have different instruction formats, which determine the position and length of each part of the instruction (such as opcode, operand, etc.) in the binary encoding. The first instruction format is any instruction format among the many instruction formats contained in the instruction set architecture corresponding to the current instruction generation scenario.

[0027] For example, in the first instruction format, fixed bit segments and variable bit segments may be included, wherein the fixed bit segment is used to refer to a binary bit combination with a fixed meaning and function in a specific instruction type or operation. The positions and encodings of these bit segments are usually predefined and will not be changed at will. For example, in some instructions, the opcode part is a fixed bit segment, which is used to indicate the specific operation to be performed by the CPU (such as addition, subtraction, data transfer, etc.).

[0028] The encoding position refers to the specific position of the fixed bit segment in the entire instruction binary encoding. It is usually expressed as a bit number or range. For example, in a 32-bit instruction, the opcode may be located at bits 0-7, then this "bits 0-7" is the encoding position of the fixed bit segment of the opcode. Clarifying the encoding position helps to accurately extract and process the information of these fixed bit segments later.

[0029] Preset coding information refers to the pre-set binary coding values ​​at the coding positions of the fixed bit segment. These values ​​represent specific meanings or operations. For example, if the opcode fixed bit segment is encoded as "00000010", it may mean that the instruction is an addition operation. Different preset coding information corresponds to different instruction functions or attributes.

[0030] For example, in a 16-bit instruction format, the first 4 bits are the opcode, the next 6 bits are the source register number, and the last 6 bits are the target register number. The encoding position of the opcode is bits 0-3, the encoding position of the source register number is bits 4-9, and the encoding position of the target register number is bits 10-15. If the opcode "0001" represents an addition operation and "0010" represents a subtraction operation, then "0001" and "0010" are the preset encoding information of the fixed bit segment of the opcode at the corresponding encoding position.

[0031] In step 102, a plurality of preset splicing instructions are randomly generated according to the code length corresponding to the code position.

[0032] The encoding length of the preset splicing instruction is consistent with the encoding length.

[0033] In this step, the first instruction format obtained in the above step 101 includes the encoding position of the fixed bit segment, and each fixed bit segment has its corresponding encoding length. Therefore, the encoding length corresponding to the encoding position is used to refer to the number of bits occupied by the fixed bit segment in the binary code. For example, if the encoding position of the opcode fixed bit segment is the 0th to 3rd bit, then its encoding length is 4 bits; if the encoding position of the source register number fixed bit segment is the 4th to 9th bit, then its encoding length is 6 bits.

[0034] When randomly generating a preset splicing instruction, the encoding value of each encoding bit of the preset splicing instruction is determined in a random manner, and for each fixed bit segment, a binary code of the corresponding number of bits is generated according to its encoding length. For example, for an opcode fixed bit segment with an encoding length of 4 bits, the randomly generated codes are "0110", "1001", etc.; for a source register number fixed bit segment with an encoding length of 6 bits, the randomly generated codes are "001101", "110010", etc.

[0035] The encoding length of the generated preset splicing instruction must be the same as the encoding length of the corresponding fixed bit segment. This is to ensure that the preset splicing instruction matches the fixed bit segment in the first instruction format in structure, so that the subsequent encoding filling and instruction generation operations can be performed correctly. If the encoding lengths are inconsistent, the preset splicing instruction cannot be accurately applied to the first instruction format, which may cause instruction generation errors.

[0036] For example, the first instruction format may include two fixed bit segments: an opcode fixed bit segment, the encoding position is bits 0-3, and the encoding length is 4 bits; a source register number fixed bit segment, the encoding position is bits 4-9, and the encoding length is 6 bits. The encoding length of the fixed bit segment of the first instruction format is 10 bits. Therefore, when randomly generating multiple preset splicing instructions, the following preset splicing instructions "0000000000", "000000001", ..., "1111111111" and other preset splicing instructions can be randomly generated according to the encoding bits of the 10-bit encoding. Multiple preset splicing instructions can constitute a preset splicing instruction set CAT_SET={0000000000, ..., 1111111111}.

[0037] In step 103, a preset instruction whose instruction format does not conform to the second instruction format is selected from a plurality of preset instructions as a generated target instruction.

[0038] The preset instruction is an instruction obtained by encoding and filling the preset splicing instruction, and the second instruction format is any instruction format other than the first instruction format among the plurality of instruction formats included in the instruction set architecture corresponding to the current instruction generation scenario.

[0039] In this step, each preset splicing instruction determined in step 102 can first be encoded and filled to obtain the corresponding preset instruction, and then from multiple preset instructions, the preset instruction whose instruction format does not conform to any instruction format other than the first instruction format among the many instruction formats contained in the instruction set architecture corresponding to the current instruction generation scenario can be selected as the generated target instruction.

[0040] Optionally, the preset instruction is obtained by encoding and filling the preset splicing instruction. Since in step 102, the preset splicing instruction randomly generated according to the encoding length of the fixed bit segment in the first instruction format only corresponds to the encoding of the fixed bit segment in the first instruction format. The encoding filling process can supplement other necessary encoding information for the preset splicing instruction based on the complete structure of the first instruction format, such as the encoding of the variable bit segment, so that the preset splicing instruction becomes a complete preset instruction that complies with the instruction format specification.

[0041] Then, you can check whether the preset instructions are consistent with any instruction format in the instruction set architecture except the first instruction format. The basis for judgment is usually to compare the encoding information of the preset instruction and the fixed bit segment in each instruction format, including the encoding position and the encoding value. If there is a preset instruction whose encoding is inconsistent with the encoding of the corresponding instruction format in the key fixed bit segment of all these instruction formats, then it is considered that the preset instruction does not conform to these instruction formats and can be selected as the generated target instruction.

[0042] By adopting the above technical solution, a large number of illegal instructions can be automatically generated at the same time through the preset first instruction format and the randomization generation mechanism, which can realize batch generation of instructions and improve the efficiency of instruction generation. In addition, by selecting the instruction format that does not conform to the second instruction format from multiple preset instructions (instructions after encoding and filling the preset splicing instructions), as the target instruction, through this screening mechanism, it is possible to effectively avoid the generation of legal instructions and ensure that the generated instructions are illegal instructions, thereby improving the effectiveness of illegal instructions, enabling illegal instructions to more reliably trigger the target verification scenario and improve the accuracy of verification.

[0043] Figure 2 is a flowchart of another instruction generation method provided in an embodiment of the present application. Figure 2As shown, the method is applied in a CPU, which is the core part of a central processing unit and is responsible for executing various instructions and processing data.

[0044] The method may include the following steps.

[0045] In step 201, a first instruction format is obtained.

[0046] The first instruction format includes a coding position of a fixed bit segment, and corresponding preset coding information is set at the coding position.

[0047] In this embodiment, the execution steps are consistent with step 101, and the specific steps are not repeated here.

[0048] In step 202, the first instruction format is split according to the encoding position of the fixed bit segment to obtain at least one fixed bit segment of the first instruction format.

[0049] In this step, when the encoding position of the fixed bit segment of the first instruction format (i.e., the specific position range of the fixed bit segment in the binary encoding of the entire instruction) is obtained by the above steps, the first instruction format can be split. Specifically, the entire binary encoding corresponding to the first instruction format can be split according to the position boundary of the fixed bit segment based on the encoding position of the fixed bit segment to obtain at least one fixed bit segment of the first instruction format.

[0050] For example, taking the instruction length of a certain instruction set architecture as 12 bits, Figure 3 As shown, instruction format 1 has two fixed bit segments and two variable bit segments. Among them, fixed bit segment 1 is located from bit 8 to bit 6, which is binary 101, fixed bit segment 2 is located from bit 3 to bit 0, which is binary 0000, variable bit segment 1 is located from bit 11 to bit 9, and variable bit segment 2 is located from bit 5 to bit 4.

[0051] First, the first instruction format can be split according to the encoding positions of fixed bit segment 1 and fixed bit segment 2, so that the entire binary code corresponding to the first instruction format is divided according to the position boundary of fixed bit segment 1 and fixed bit segment 2 to obtain the corresponding fixed bit segment "1010000" of the first instruction format.

[0052] In step 203, the number of coded bits of the at least one fixed bit segment is used as a first coding length.

[0053] The number of coded bits refers to the number of binary bits contained in each fixed bit segment.

[0054] In this step, each fixed bit segment is a code consisting of a certain number of binary digits (bits).

[0055] For example, from the above examples, it can be seen that the fixed bit segment "010" has 3 coded bits, and the fixed bit segment "1010" has 4 coded bits.

[0056] If there are multiple fixed bit segments in the first instruction format, the sum of the number of coding bits in the multiple fixed bit segments can be used as the first coding length. For example, in the fixed bit segment "010", the number of coding bits is 3; in the fixed bit segment "1010", the number of coding bits is 4, the number of coding bits is 7, then the first coding length is 7.

[0057] In step 204, a plurality of preset splicing instructions having a code length equal to the first code length are randomly generated.

[0058] Random generation means that the generated code has no fixed pattern and is unpredictable. In a possible implementation, it can usually be achieved through a random number generator, which can generate a series of seemingly random numbers based on a certain algorithm (such as a pseudo-random number algorithm). These numbers can be converted into binary form to obtain a random binary code.

[0059] In this step, when the fixed bit segment 1 is "010" (the number of coding bits is 3) and the fixed bit segment 2 is "1010" (the number of coding bits is 4) determined in the above step 203, the first code length is 3+4=7, and then a plurality of binary codes with a length of 7 can be randomly generated as preset splicing instructions. For example, the following preset splicing instructions can be randomly generated: "1100101", "0011100", "1010011", and so on.

[0060] In step 205, a plurality of first splicing instructions in a first splicing instruction set are obtained.

[0061] The first splicing instruction is an instruction obtained by splicing the preset coding information at the coding position of the fixed bit segment, and the first splicing instruction set includes the first splicing instruction corresponding to the first instruction format.

[0062] In this step, the preset coding information at the coding position of the fixed bit segment of the first instruction format can be obtained first, and then the preset coding information at the coding position of each fixed bit segment can be connected in sequence according to the order of the fixed bit segments in the instruction format to form a new binary code. This new binary code is the first splicing instruction, and then a first splicing instruction set can be established based on multiple first splicing instructions corresponding to the first instruction format.

[0063] Then, multiple first splicing instructions in the first splicing instruction set may be obtained.

[0064] For example, an instruction set architecture has an instruction length of 12 bits and includes two instruction formats, such as Figure 3 As shown, instruction format 1 has two fixed bit segments and two variable bit segments. Fixed bit segment 1 is located from bit 8 to bit 6, fixed bit segment 2 is located from bit 3 to bit 0, variable bit segment 1 is located from bit 11 to bit 9, and variable bit segment 2 is located from bit 5 to bit 4.

[0065] Among them, instruction format 1 includes two instructions A and B; the fixed bit segment 1 of instruction A is encoded as binary 101, and the fixed bit segment 2 is encoded as binary 0000; the fixed bit segment 1 of instruction B is encoded as binary 010, and the fixed bit segment 2 is encoded as 1010.

[0066] According to instruction A, the corresponding first splicing instruction can be determined to be "1010000", and according to instruction B, the corresponding first splicing instruction can be determined to be "0101010", so the first splicing instruction set STI_INSTRS1={1010000,1010010} can be established.

[0067] In step 206, for each of the first splicing instructions, the coding information at each coding position in the preset splicing instruction is compared with the coding information at the corresponding coding position in the first splicing instruction to obtain a comparison result at each coding position.

[0068] In this embodiment, the preset splicing instructions with a plurality of code lengths of the first code length generated in the above steps are the objects to be judged as target instructions in the subsequent step. Since the lengths of the preset splicing instructions and the first splicing instructions are the same (both are the first code lengths), each position has corresponding code information (0 or 1). Therefore, the code information of the preset splicing instructions and the first splicing instructions at the same position can be compared. For example, if the preset splicing instruction is "1010011" and the first splicing instruction is "1100101", the first bit (the first bit of the preset splicing instruction is 1, and the first bit of the first splicing instruction is also 1) and the second bit (the second bit of the preset splicing instruction is 0, and the second bit of the first splicing instruction is 1) can be compared first, and so on, until all positions are compared.

[0069] By comparing each encoding position, a comparison result will be obtained. The comparison result is usually a Boolean value. If the encoding information at the same position is the same, the comparison result is true (True), and if it is different, it is false (False). For example, in the above example, the comparison result of the first position is True, and the comparison result of the second position is False. In the end, a comparison result sequence with the same length as the instruction will be obtained, which is used to subsequently determine whether the preset splicing instruction matches the first splicing instruction.

[0070] In this way, by comparing the preset splicing instruction with each first splicing instruction in the first splicing instruction set, it can be determined whether the preset splicing instruction matches any of the first splicing instructions that match. If the comparison results of the preset splicing instruction and a first splicing instruction at all coding positions are true, then it means that the preset splicing instruction is a legal instruction; if the comparison results with all the first splicing instructions do not completely match, then this preset splicing instruction is an illegal instruction. By comparing bit by bit, the difference between the preset splicing instruction and the first splicing instruction at each coding position can be accurately checked. Even if the coding information of only one position is different, it can be accurately detected, thereby improving the accuracy of judging the legality of the instruction.

[0071] In step 207, when the comparison result at at least one encoding position of each first splicing instruction is inconsistent, it is determined that the preset splicing instruction does not belong to the first splicing instruction set, and the preset splicing instruction that does not belong to the first splicing instruction set is used as a candidate splicing instruction.

[0072] In this step, first, for each first splicing instruction, the preset splicing instruction can be compared with it bit by bit and the comparison result at each coding position can be obtained. For example, if there are two first splicing instructions in the first splicing instruction set: "1010000" and "0101010", the preset splicing instruction is "1100110". When the preset splicing instruction is compared with "1010000", it may be found that the position coding information of the second and third bits is different; when compared with "0101010", the position coding information of the first and fourth bits may be different. That is, for these two first splicing instructions, the preset splicing instruction has at least one position that is inconsistent with them.

[0073] If there is a difference between the preset splicing instruction and each first splicing instruction in the first splicing instruction set, it can be determined that the preset splicing instruction is not in the first splicing instruction set. Because the elements in the first splicing instruction set are legal instructions spliced ​​from the preset encoding information of the fixed bit segment under the first instruction format, the preset splicing instruction is different from all legal instructions, so it does not belong to this set.

[0074] If it is determined that the preset splicing instruction does not belong to the first splicing instruction set, it can be marked as a candidate splicing instruction. A candidate splicing instruction means that it may become an illegal instruction to be generated eventually, but further judgment is required (such as comparison with splicing instruction sets of other instruction formats).

[0075] For example, taking an instruction set architecture whose instruction length is 12 bits, including instruction format 1 as an example, Figure 3As shown, instruction format 1 has two fixed bit segments and two variable bit segments. Fixed bit segment 1 is located from bit 8 to bit 6, fixed bit segment 2 is located from bit 3 to bit 0, variable bit segment 1 is located from bit 11 to bit 9, and variable bit segment 2 is located from bit 5 to bit 4.

[0076] For instruction format 1, two instructions A and B may be included, wherein the fixed bit segment 1 of instruction A is encoded as binary 101, and the fixed bit segment 2 is encoded as binary 0000; the fixed bit segment 1 of instruction B is encoded as binary 010, and the fixed bit segment 2 is encoded as 1010. It can be obtained that the first splicing instruction set STI_INSTRS1 = {1010000, 1010010}.

[0077] When the preset splicing instruction is "0001010", it does not belong to the set STI_INSTRS1, that is, the preset splicing instruction belongs to the first splicing instruction set and can be used as a candidate splicing instruction.

[0078] By adopting the above technical scheme, since the first splicing instruction set represents the legal instruction set under the first instruction format, by comparing the preset splicing instructions with the elements in the set, the preset splicing instructions that are different from all legal instructions are screened out as candidate splicing instructions. This can preliminarily exclude those legal instructions that conform to the first instruction format, making the candidate splicing instructions more likely to be illegal instructions, laying the foundation for further judgment on whether they are truly illegal instructions.

[0079] In step 208 , when the comparison results at each encoding position of any of the first splicing instructions are consistent, it is determined that the preset splicing instruction belongs to the first splicing instruction set.

[0080] In this step, if the preset splicing instruction and a first splicing instruction in the first splicing instruction set are the same in all coding positions, then it can be determined that the preset splicing instruction is an element in the first splicing instruction set, that is, it belongs to the first splicing instruction set. Because the elements in the first splicing instruction set are legal instructions spliced ​​from preset coding information of fixed bit segments under the first instruction format, by judging whether the preset splicing instruction is completely consistent with an element in the set, it can be clear whether the preset splicing instruction is a legal instruction, and the correctness and effectiveness of subsequent operations can be guaranteed. For example, if a legal instruction is mistakenly treated as a candidate illegal instruction and continued to be processed, the final generated instruction will not meet the requirements of the illegal instruction, affecting the result of the entire process.

[0081] In step 209, the candidate splicing instruction is encoded and filled according to the first instruction format to obtain a corresponding preset instruction.

[0082] In this step, the candidate splicing instruction can first be split according to the encoding position of the fixed bit segment of the first instruction format to obtain multiple candidate bit segments; then the multiple candidate bit segments are filled into the fixed bit segment of the first instruction format, and the encoding information at other encoding positions in the preset instruction except the fixed bit segment is randomly generated to obtain the corresponding preset instruction.

[0083] In step 210, the preset instruction is split according to the encoding position of the fixed bit segment corresponding to the second instruction format to obtain a second candidate splicing instruction.

[0084] Among them, in addition to the first instruction format, there may be other instruction formats in the current instruction set architecture, such as the second instruction format; the second spliced ​​instruction set is a set of all legal instructions spliced ​​by the preset encoding information of the fixed bit segment under the second instruction format. It is similar to the first spliced ​​instruction set and represents the legal instruction range under the second instruction format.

[0085] In this step, the preset instruction is a complete instruction obtained after encoding and filling according to the first instruction format in step 209. Here, according to the encoding position of the fixed bit segment of the second instruction format, the encoding information of the corresponding position is extracted from the preset instruction. And the encoding information extracted from the preset instruction according to the encoding position of the fixed bit segment of the second instruction format is spliced ​​to obtain the second candidate splicing instruction. This splicing instruction only contains the encoding information of the fixed bit segment under the second instruction format, which will be used for subsequent comparison with the second splicing instruction set corresponding to the second instruction format to determine whether the preset instruction is legal for the second instruction format.

[0086] For example, taking the instruction length of a certain instruction set architecture as 12 bits, it also includes instruction format 2, such as Figure 4 As shown, instruction format 2 has three fixed bit ends and two variable bit segments. Fixed bit segment 1 is located at bit 11 to bit 10, fixed bit segment 2 is located at bit 7 to bit 5, fixed bit segment 3 is located at bit 2 to bit 0, variable bit segment 1 is located at bit 9 to bit 8, and variable bit segment 2 is located at bit 4 to bit 3.

[0087] In this step, the candidate splicing instruction can be first checked to see whether it is a legal instruction in the second instruction format. By comparing the candidate splicing instruction with each element in the second splicing instruction set, if the same instruction is not found in the set, it means that the candidate splicing instruction does not meet the legal rules of the second instruction format, that is, it is also illegal for the second instruction format.

[0088] For example, and for instruction format 2, three instructions C, D, and E may be included: instruction C has fixed bit segment 1 encoded as 00, fixed bit segment 2 encoded as 101, and fixed bit segment 3 encoded as 100; instruction D has fixed bit segment 1 encoded as 11, fixed bit segment 2 encoded as 001, and fixed bit segment 3 encoded as 010; instruction E has fixed bit segment 1 encoded as 10, fixed bit segment 2 encoded as 000, and fixed bit segment 3 encoded as 111. It can be obtained that the second splicing instruction set STI_INSTRS2 = {00101100, 11001010, 10000111}.

[0089] When the preset splicing instruction is "0001010", it is concluded through comparison that it does not belong to the set STI_INSTRS1, so it can be encoded and filled according to the first instruction format to obtain the corresponding preset instruction "1100001001010", and then the preset instruction can be split according to the encoding position of the fixed bit segment corresponding to the second instruction format to obtain the second candidate splicing instruction "11001010".

[0090] When the preset splicing instruction is "1010101", it is concluded through comparison that it does not belong to the set STI_INSTRS1, so it can be encoded and filled according to the first instruction format to obtain the corresponding preset instruction "1001010010101", and then the preset instruction can be split according to the encoding position of the fixed bit segment corresponding to the second instruction format to obtain the second candidate splicing instruction "10010101".

[0091] In some embodiments, the preset encoding information at the encoding position of the fixed bit segment of the second instruction format can be spliced ​​to obtain a second splicing instruction; the second splicing instruction includes multiple instructions; and then an instruction set composed of multiple second splicing instructions is used as the second splicing instruction set.

[0092] In step 211, when the second candidate splicing instruction is not found in the second splicing instruction set corresponding to the second instruction format, the preset instruction corresponding to the second candidate splicing instruction is used as the generated target instruction.

[0093] In this step, the second candidate splicing instruction obtained in step 210 can be compared with each instruction in the second splicing instruction set. If it is found through comparison that the second candidate splicing instruction is different from any instruction in the set, this means that the second candidate splicing instruction does not meet the rules of legal instructions in the second instruction format.

[0094] Since the second candidate splicing instruction is obtained by splitting the preset instruction according to the encoding position of the fixed bit segment of the second instruction format, when the second candidate splicing instruction is not found in the second splicing instruction set, it means that the preset instruction is an illegal instruction for the second instruction format. And because it has been determined in the previous step that the preset instruction is also an illegal instruction for the first instruction format (derived by the relevant operations on the candidate splicing instruction), it can be determined at this time that the preset instruction is a real illegal instruction, that is, the preset instruction is used as the generated target instruction.

[0095] Therefore, from the example in step 210, it can be known that when the second candidate splicing instruction is "11001010", it can be determined that it belongs to STI_INSTRS2, so the preset instruction "1100001001010" cannot be used as the target instruction. In the case of the second candidate splicing instruction "10010101", it can be determined that it also does not belong to STI_INSTRS2, so the preset instruction "1100001001010" can be used as the target instruction.

[0096] By adopting the above technical solution, a large number of illegal instructions can be automatically generated at the same time through the preset first instruction format and the randomization generation mechanism, which can realize batch generation of instructions and improve the efficiency of instruction generation. In addition, by selecting the instruction format that does not conform to the second instruction format from multiple preset instructions (instructions after encoding and filling the preset splicing instructions), as the target instruction, through this screening mechanism, it is possible to effectively avoid the generation of legal instructions and ensure that the generated instructions are illegal instructions, thereby improving the effectiveness of illegal instructions, enabling illegal instructions to more reliably trigger the target verification scenario and improve the accuracy of verification.

[0097] Figure 5 is a block diagram of an instruction generation device provided in an embodiment of the present application, the device 300 includes: An acquisition module 301 is used to acquire a first instruction format, where the first instruction format includes an encoding position of a fixed bit segment, where corresponding preset encoding information is set; A generating module 302, for randomly generating a plurality of preset splicing instructions according to the code length corresponding to the code position; the code length of the preset splicing instructions is consistent with the code length; The determination module 303 is used to select a preset instruction whose instruction format does not conform to the second instruction format from multiple preset instructions as a generated target instruction; the preset instruction is an instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format of the multiple instruction formats included in the current instruction set architecture except the first instruction format.

[0098] Optionally, the determination module 303 is used to use the preset splicing instruction that does not belong to the first splicing instruction set as a candidate splicing instruction among the multiple preset splicing instructions; the first splicing instruction set includes a first splicing instruction corresponding to the first instruction format, and the first splicing instruction is an instruction obtained by splicing the preset coding information at the coding position of the fixed bit segment; encode and fill the candidate splicing instruction according to the first instruction format to obtain the corresponding preset instruction; split the preset instruction according to the coding position of the fixed bit segment corresponding to the second instruction format to obtain a second candidate splicing instruction; when the second candidate splicing instruction is not found in the second splicing instruction set corresponding to the second instruction format, the preset instruction corresponding to the second candidate splicing instruction is used as the generated target instruction.

[0099] Optionally, the determination module 303 is used to split the candidate splicing instruction according to the encoding position of the fixed bit segment of the first instruction format to obtain multiple candidate bit segments; fill the multiple candidate bit segments into the fixed bit segment of the first instruction format, and randomly generate encoding information at other encoding positions in the preset instruction except the fixed bit segment to obtain the corresponding preset instruction.

[0100] Optionally, the determination module 303 is used to splice the preset coding information at the coding position of the fixed bit segment of the second instruction format to obtain a second splicing instruction; the second splicing instruction includes multiple instructions; and an instruction set composed of multiple second splicing instructions is used as the second splicing instruction set.

[0101] Optionally, the determination module 303 is used to obtain multiple first splicing instructions in the first splicing instruction set; for each of the first splicing instructions, compare the coding information at each coding position in the preset splicing instruction with the coding information at the corresponding coding position in the first splicing instruction to obtain the comparison result at each coding position; when there is an inconsistent comparison result at at least one coding position in each of the first splicing instructions, determine that the preset splicing instruction does not belong to the first splicing instruction set, and use the preset splicing instruction that does not belong to the first splicing instruction set as a candidate splicing instruction.

[0102] Optionally, the determination module 303 is configured to determine that the preset splicing instruction belongs to the first splicing instruction set when the comparison results at each encoding position of any first splicing instruction are consistent.

[0103] Optionally, the generation module 302 is used to split the first instruction format according to the encoding position of the fixed bit segment to obtain at least one fixed bit segment of the first instruction format; use the number of encoding bits of the at least one fixed bit segment as the first encoding length; and randomly generate multiple preset splicing instructions with the encoding length of the first encoding length.

[0104] In summary, in the embodiments of the present application, a large number of illegal instructions can be automatically generated at the same time through the preset first instruction format and the randomization generation mechanism, which can realize batch generation of instructions and improve the efficiency of instruction generation, and by selecting from multiple preset instructions (instructions after encoding and filling the preset splicing instructions), the instruction format that does not conform to the second instruction format is selected as the target instruction. Through this screening mechanism, it is possible to effectively avoid the generation of legal instructions and ensure that the generated instructions are illegal instructions, thereby improving the effectiveness of illegal instructions, enabling illegal instructions to more reliably trigger target verification scenarios, and improving the accuracy of verification.

[0105] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0108] An embodiment of the present application provides an instruction generation device, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the methods described in one or more of the above embodiments.

[0109] Figure 6 4 is a block diagram of an electronic device 400 according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0110] Reference Figure 6 , the electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output interface 412 , a sensor component 414 , and a communication component 416 .

[0111] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0112] The memory 404 is used to store various types of data to support the operation of the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, multimedia, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0113] The power supply component 404 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400.

[0114] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0115] The audio component 410 is used to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0116] The input / output interface 412 provides an interface between the processing component 402 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0117] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of the components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of contact between the user and the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0118] The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0119] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0120] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the instructions can be executed by a processor 420 of an electronic device 400 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0121] Figure 7 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be provided as a server. Figure 7 , the electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions that can be executed by the processing component 522, such as an application. The application stored in the memory 532 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0122] The electronic device 500 may also include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server 2003. TM , MacOSX TM , Unix TM , Linux TM , FreeBSD TM or similar.

[0123] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0124] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0125] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for generating an instruction, characterized in that: The method comprises: Acquire a first instruction format, wherein the first instruction format includes an encoding position of a fixed bit segment, and corresponding preset encoding information is set at the encoding position; According to the code length corresponding to the code position, a plurality of preset splicing instructions are randomly generated; the code length of the preset splicing instructions is consistent with the code length; From multiple preset instructions, select the preset instruction whose instruction format does not conform to the second instruction format as the generated target instruction; the preset instruction is the instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format of the multiple instruction formats included in the current instruction set architecture except the first instruction format.

2. The method according to claim 1, characterized in that The step of selecting, from a plurality of preset instructions, the preset instruction whose instruction format does not conform to the second instruction format as the generated target instruction comprises: Among the plurality of preset splicing instructions, the preset splicing instructions that do not belong to the first splicing instruction set are used as candidate splicing instructions; the first splicing instruction set includes a first splicing instruction corresponding to the first instruction format, and the first splicing instruction is an instruction obtained by splicing preset coding information at the coding position of the fixed bit segment; Encode and fill the candidate splicing instructions according to the first instruction format to obtain corresponding preset instructions; Splitting the preset instruction according to the encoding position of the fixed bit segment corresponding to the second instruction format to obtain a second candidate splicing instruction; When the second candidate splicing instruction is not found in the second splicing instruction set corresponding to the second instruction format, the preset instruction corresponding to the second candidate splicing instruction is used as the generated target instruction.

3. The method according to claim 2, characterized in that The encoding and filling of the candidate splicing instructions according to the first instruction format to obtain the corresponding preset instructions includes: Splitting the candidate splicing instruction according to the encoding position of the fixed bit segment of the first instruction format to obtain a plurality of candidate bit segments; The fixed bit segment of the first instruction format is filled with the multiple candidate bit segments, and encoding information at other encoding positions in the preset instruction except the fixed bit segment is randomly generated to obtain the corresponding preset instruction.

4. The method according to claim 2, characterized in that: The method further comprises: splicing the preset coding information at the coding position of the fixed bit segment of the second instruction format to obtain a second splicing instruction; the second splicing instruction includes multiple instructions; An instruction set consisting of a plurality of the second splicing instructions is used as the second splicing instruction set.

5. The method according to claim 2, characterized in that: The taking the preset splicing instruction that does not belong to the first splicing instruction set as a candidate splicing instruction comprises: Obtaining a plurality of the first splicing instructions in the first splicing instruction set; For each of the first splicing instructions, comparing the coding information at each coding position in the preset splicing instruction with the coding information at the corresponding coding position in the first splicing instruction to obtain a comparison result at each coding position; When the comparison result at at least one encoding position of each of the first splicing instructions is inconsistent, it is determined that the preset splicing instruction does not belong to the first splicing instruction set, and the preset splicing instruction that does not belong to the first splicing instruction set is used as a candidate splicing instruction.

6. The method according to claim 5, characterized in that The method further comprises: When the comparison results at each encoding position of any of the first splicing instructions are consistent, it is determined that the preset splicing instruction belongs to the first splicing instruction set.

7. The method according to claim 1, characterized in that The randomly generating a plurality of preset splicing instructions according to the code length corresponding to the code position comprises: Splitting the first instruction format according to the encoding positions of the fixed bit segments to obtain at least one fixed bit segment of the first instruction format; Using the number of coded bits of the at least one fixed bit segment as a first coding length; A plurality of preset splicing instructions with a code length equal to the first code length are randomly generated.

8. An instruction generating device, characterized in that: The device comprises: An acquisition module, used for acquiring a first instruction format, wherein the first instruction format includes an encoding position of a fixed bit segment, and corresponding preset encoding information is set at the encoding position; A generating module, used for randomly generating a plurality of preset splicing instructions according to the code length corresponding to the code position; the code length of the preset splicing instructions is consistent with the code length; A determination module is used to select, from multiple preset instructions, a preset instruction whose instruction format does not conform to a second instruction format as a generated target instruction; the preset instruction is an instruction after encoding and filling the preset splicing instruction, and the second instruction format is any instruction format other than the first instruction format among the multiple instruction formats included in the current instruction set architecture.

9. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 7.

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