FPGA-based reconfigurable brain-like computing system on chip

Abstract

The application relates to the technical field of brain-like computing, in particular to a reconfigurable brain-like computing system on chip based on FPGA, which comprises five subsystems of neuron processing, synapse connection, multi-chip communication, simulation scheduling and microprocessor, the core function of brain-like computing is completed through the use of the neuron processing subsystem, the synapse connection subsystem and the multi-chip communication subsystem, and the reconfiguration of neuron models, synapse models and neural network connection models at the model level is completed; the operation flow of the three subsystems is uniformly scheduled through the simulation scheduling subsystem; the storage in the computing system is uniformly addressed through the microprocessor subsystem, and external communication of the system is realized through UART. The system can meet the diversified needs of brain science researchers and brain-like intelligent application developers for brain-like computing hardware, and can provide strong support for the research of brain science and brain-like intelligent models.

Description

Technical Field

[0001] The present invention relates to the field of brain-inspired computing technology, and in particular to a reconfigurable brain-inspired computing system-on-chip based on FPGA. Background Art

[0002] Brain-inspired computing, also known as neuromorphic computing, is a general term for computing theories, architectures, chip designs, and application models and algorithms that draw on the information processing patterns and structures of biological neural systems. As a new computing paradigm, it aims to achieve higher-level intelligent computing tasks with greater energy efficiency by mimicking the brain's structure and information processing mechanisms.

[0003] Currently, brain-inspired computing, as a new computing paradigm, aims to achieve higher-level intelligent computing tasks with higher energy efficiency by mimicking the brain's structure and information processing mechanisms. Researching and designing specialized hardware for brain-inspired computing is key to promoting its development. However, existing dedicated hardware for brain-inspired computing is limited in the types of neurons, synapses, and network connectivity models it can simulate, and its computational accuracy, performance metrics, and system scalability are relatively fixed. Therefore, it cannot meet the diverse needs of brain science researchers and developers of brain-inspired intelligent applications for brain-inspired computing hardware, and thus cannot provide strong support for research in brain science and brain-inspired intelligent models.

[0004] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the Invention

[0005] The purpose of the present invention is to overcome the problems of the above-mentioned prior art and provide a reconfigurable brain-like computing system-on-chip based on FPGA to solve the problem that the prior art cannot meet the diverse needs of brain science researchers and brain-like intelligent application developers for brain-like computing hardware, and cannot provide strong technical support for the research of brain science and brain-like intelligent models.

[0006] The above objectives are achieved through the following technical solutions:

[0007] A reconfigurable brain-inspired computing system-on-chip based on FPGA, including a neuron processing subsystem, a multi-chip communication subsystem, a synaptic connection subsystem, a simulation scheduling subsystem, and a microprocessor subsystem;

[0008] The simulation scheduling subsystem receives a simulation start signal sent by the microprocessor subsystem, controls and schedules the neuron processing subsystem, the synaptic connection subsystem, and the multi-chip communication subsystem through corresponding control signals to complete a simulation of one time step; after the simulation is completed, an interrupt signal is sent to the microprocessor subsystem to wait for the start of the next time step simulation;

[0009] The neuron processing subsystem receives the synaptic connection sent by the synaptic connection subsystem, and indexes the corresponding neuron state parameter through the destination neuron ID in the connection, and accumulates the synaptic weight on the connection with it; after receiving all synaptic connections in the current time step, it sequentially extracts the neuron state information to update the membrane potential. If the membrane potential exceeds the threshold, a pulse is issued, and the pulse data packet is the neuron's own ID;

[0010] The multi-chip communication subsystem receives pulse data packets sent by other chips and the local neuron processing subsystem, uses the neuron ID to index its routing entry in the routing table, and determines the direction of the pulse according to the routing entry information. The pulse sent to the local area will be sent to the local synaptic connection subsystem;

[0011] After receiving the pulse, the synaptic connection subsystem indexes a synaptic index entry according to the pulse ID, indexes several synaptic connections in the subsystem according to the synaptic connection storage first address and quantity in the synaptic index entry, and sends the destination neuron ID in the synaptic connection to the corresponding neuron processing unit in the neuron processing subsystem;

[0012] The microprocessor subsystem uniformly addresses the storage in the computing system and communicates with the outside of the system through the UART.

[0013] Furthermore, the microprocessor subsystem is connected to the simulation scheduling subsystem via a signal line, and the simulation scheduling subsystem is connected to the neuron processing subsystem, the multi-chip communication subsystem and the synaptic connection subsystem via signal lines respectively to realize the transmission of control data.

[0014] Furthermore, the pulse and weight data between the neuron processing subsystem, the multi-chip communication subsystem, the synaptic connection subsystem and the microprocessor subsystem are transmitted via the AXI4 stream bus protocol.

[0015] Furthermore, the simulation scheduling subsystem is controlled by a state machine, which includes 6 states: initial state, clear state, memory read state, weight accumulation state, membrane potential update state and memory write state; and controls state jumps through the Sim_startpluse signal from the microprocessor subsystem, the rwdone signal from the neuron processing subsystem, a built-in Timer counter and three built-in time window registers.

[0016] Furthermore, the neuron processing subsystem includes reconfigurable control logic, configurable model parameter generation logic, a reconfigurable parallel computing unit, a reconfigurable neuron address generation module, a pulse time update module, a pulse transceiver, a DMA supporting floating point error optimization, and a random number generator module.

[0017] Furthermore, the multi-chip communication subsystem includes four groups of SerDes transceiver modules and one multicast router responsible for communicating with four directional chips;

[0018] The SerDes transceiver module uses Xilinx's Aurora8B / 10B IP to achieve conversion between high-speed serial differential signals and AXI4-Stream bus;

[0019] The multicast router is responsible for receiving pulse data packets transmitted by the four directional chips and the local neuron processing subsystem and the microprocessor subsystem. After the three steps of unpacking, table lookup and routing, the pulse data packets are routed to the four adjacent chips and the local synaptic connection subsystem.

[0020] Furthermore, the content of the pulse data packet is a neuron ID.

[0021] Furthermore, the synaptic connection subsystem includes a pulse address decoding module, a synaptic index DMA module, a synaptic connection distribution module and a DDR storage. The DDR storage stores synaptic connection information. The working process is as follows:

[0022] (a) the synaptic connection subsystem receives the pulse ID i sent from the multi-chip communication subsystem and sends it to the pulse address decoding module;

[0023] (b) the pulse address decoding module converts the pulse ID into the address and length information of the synapse index and sends it to the synapse index DMA module;

[0024] (c) The synapse index DMA module retrieves the synapse index Indexi,c corresponding to the pulse i in the current chip from the DDR storage via the microprocessor subsystem and sends it to the pulse address decoding module;

[0025] (d) the pulse address decoding module parses the synaptic connection storage first address staddri,c and the synaptic connection number fanouti,c in the synaptic index Indexi,c, and sends the index address and length information of the synaptic connection to the synaptic index DMA module;

[0026] (e) The synaptic index DMA module takes out fanouti,c synaptic connections si,j from the DDR storage according to the new index address and length information and sends them to the synaptic connection distribution module;

[0027] (f) the synaptic connection distribution module sends the synaptic connection weight to the corresponding neuron processing unit in the neuron processing subsystem by decoding the destination neuron j information in si,j.

[0028] Further, the synaptic index DMA module needs to pass through the microprocessor subsystem to read data from the DDR memory.

[0029] Further, the microprocessor subsystem includes 1 MicroBlaze soft core, 1 MIG module, 1 BRAM memory controller module, 1 interrupt controller module, 1 UART communication module, 1 MemBridge module, 1 AXI4 Intc1 module, 1 AXI4 Intc2 module and multiple GPIO modules.

[0030] The MicroBlaze soft core connects the AXI4 Intc2 module and the MIG module in sequence through the AXI4 Intc1 module to access the DDR, connects the BRAM memory controller module to access the on-chip BRAM and register resources through the Mem Bridge module, connects the GPIO module to issue control signals or detect state information, and connects the interrupt controller to detect the interrupt signal issued by the simulation scheduling subsystem.

[0031] The GPIO module controls the simulation scheduling subsystem and detects the configuration UART communication module.

[0032] Advantages

[0033] The FPGA-based reconfigurable brain-like computing system on chip provided by the application completes the core functions of brain-like computing by using the neuron processing subsystem, the synaptic connection subsystem and the multi-chip communication subsystem, and completes the reconfiguration of the neuron model, the synaptic model and the neural network connection model at the model level. The simulation scheduling subsystem is used to uniformly schedule the running processes of the three subsystems. The microprocessor subsystem uniformly addresses the storage in the computing system, and communicates with the outside of the system through UART, so that more flexible interaction with the outside of the system is achieved, and more efficient storage management is realized. The system can meet the diversified needs of brain science researchers and brain-like intelligent application developers for brain-like computing hardware, and can provide strong support for the research of brain science and brain-like intelligent models. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The figure is the architecture diagram of the FPGA-based reconfigurable brain-like computing system on chip.

[0035] Figure 2This is a table of functions of each subsystem in the FPGA-based reconfigurable brain-inspired computing system-on-chip described in the present invention;

[0036] Figure 3 This is an architecture diagram of the neuron processing subsystem in the FPGA-based reconfigurable brain-inspired computing system-on-chip described in the present invention;

[0037] Figure 4 This is a diagram of the architecture of the multi-chip communication subsystem in the FPGA-based reconfigurable brain-inspired computing system-on-chip described in the present invention;

[0038] Figure 5 This is an architecture diagram of the synaptic connection subsystem in the FPGA-based reconfigurable brain-inspired computing system-on-chip described in the present invention;

[0039] Figure 6 This is an architecture diagram of the microprocessor subsystem in the FPGA-based reconfigurable brain-inspired computing system-on-chip described in the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and examples. The described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

[0041] Example 1

[0042] This solution provides a reconfigurable brain-like computing system-on-chip based on FPGA, including a neuron processing subsystem, a multi-chip communication subsystem, a synaptic connection subsystem, a simulation scheduling subsystem, and a microprocessor subsystem;

[0043] The simulation scheduling subsystem receives a simulation start signal sent by the microprocessor subsystem, controls and schedules the neuron processing subsystem, the synaptic connection subsystem, and the multi-chip communication subsystem through corresponding control signals to complete a simulation of one time step; after the simulation is completed, an interrupt signal is sent to the microprocessor subsystem to wait for the start of the next time step simulation;

[0044] The neuron processing subsystem receives the synaptic connection sent by the synaptic connection subsystem, and indexes the corresponding neuron state parameter through the destination neuron ID in the connection, and accumulates the synaptic weight on the connection with it; after receiving all synaptic connections in the current time step, it sequentially extracts the neuron state information to update the membrane potential. If the membrane potential exceeds the threshold, a pulse is issued, and the pulse data packet is the neuron's own ID;

[0045] The multi-chip communication subsystem receives pulse data packets sent by other chips and the local neuron processing subsystem, uses the neuron ID to index its routing entry in the routing table, and determines the direction of the pulse according to the routing entry information. The pulse sent to the local area will be sent to the local synaptic connection subsystem;

[0046] After receiving the pulse, the synaptic connection subsystem indexes a synaptic index entry according to the pulse ID, indexes several synaptic connections in the subsystem according to the synaptic connection storage first address and quantity in the synaptic index entry, and sends the destination neuron ID in the synaptic connection to the corresponding neuron processing unit in the neuron processing subsystem;

[0047] The microprocessor subsystem uniformly addresses the storage in the computing system and communicates with the outside of the system through UART.

[0048] The microprocessor subsystem is connected to the simulation scheduling subsystem via a signal line, and the simulation scheduling subsystem is connected to the neuron processing subsystem, the multi-chip communication subsystem and the synaptic connection subsystem via signal lines respectively to realize the transmission of control data.

[0049] The pulse and weight data between the neuron processing subsystem, the multi-chip communication subsystem, the synaptic connection subsystem and the microprocessor subsystem are transmitted via the AXI4 stream bus protocol.

[0050] This solution meets the diverse needs of brain science researchers and brain-inspired intelligence application developers for brain-inspired computing hardware, providing strong support for the research of brain science and brain-inspired intelligence models.

[0051] like Figure 1 As shown, this solution first uses the neuron processing subsystem, synaptic connection subsystem and multi-chip communication subsystem to complete the core functions of brain-like computing, and completes the reconfiguration of the neuron model, neural synapse model and neural network connection model at the model level.

[0052] Then, the simulation scheduling subsystem is used to uniformly schedule the operation processes of the three subsystems.

[0053] Finally, in order to interact more flexibly with the outside of the system and achieve more efficient storage management, the microprocessor subsystem uniformly addresses the storage in the computing system and communicates with the outside of the system through UART.

[0054] like Figure 2 As shown, this system realizes the reconfiguration of simulation time through the simulation scheduling subsystem;

[0055] The neuron processing subsystem achieves reconfigurable neuron models and computational accuracy through reconfigurable control logic, configurable model parameter generation logic, and reconfigurable parallel computing units. The expansion of the neuron processing units improves the system's parallel processing capabilities while increasing the number of neurons that can be simulated on a single chip. Furthermore, a floating-point combination error processing mechanism is designed to reduce the floating-point combination error inherent in the brain-inspired computing model, which uses a floating-point number system.

[0056] The synaptic connection subsystem realizes a synaptic connection mechanism with unlimited neuron connection range and number of connections and limited total number of network connections through the source index mechanism, and realizes the reconfiguration of neuron model through the synaptic connection information storage design;

[0057] The multi-chip communication subsystem realizes the reconfiguration of routing paths and communication loads through source routing mechanism and group routing mechanism, and can form a chip array with a 2D-Mesh (two-dimensional mesh) structure through chip networking expansion;

[0058] The integrated microprocessor subsystem enables unified storage management of the entire on-chip computing system and communication interaction with external systems.

[0059] Example 2

[0060] The optimization of the simulation scheduling subsystem in this FPGA-based reconfigurable brain-inspired computing system-on-chip is described as follows:

[0061] The simulation scheduling subsystem described in this embodiment is responsible for the control scheduling of each subsystem within a time step (scheduling the operation process of each subsystem in the system within each time step to complete the calculation update of neurons and synapses and the information transmission of pulses and weights).

[0062] The system achieves simulation time reconfiguration through counters and time window registers.

[0063] The operation process of the simulation scheduling subsystem is as follows:

[0064] (1) Assign values ​​to the time window register of the simulation scheduling subsystem during the initialization phase;

[0065] (2) Receive the simulation start signal sent by the microprocessor subsystem, control and schedule the neuron processing subsystem, synaptic connection subsystem and multi-chip communication subsystem through corresponding control signals, and complete the simulation of one time step;

[0066] (3) After the simulation is completed, an interrupt signal is sent to the microprocessor subsystem, and then waits for the start of the next time step simulation.

[0067] The simulation scheduling subsystem described in this embodiment is responsible for interacting with the microprocessor subsystem throughout the entire time step, as well as controlling the neuron processing, synaptic connection, and multi-chip communication subsystems.

[0068] Specifically, the simulation scheduling subsystem is controlled by a state machine, which includes 6 states: initial state (IDLE), clear state (CLEAR), memory read state (MEM_R), weight accumulation state (WACC), membrane potential update state (VCALCU) and memory write state (MEM_W); and the state jump is controlled by the Sim_startpluse signal from the microprocessor subsystem, the rwdone signal from the neuron processing subsystem, a built-in Timer counter and three built-in time window registers.

[0069] It should be noted that the built-in timer counter and three time window registers realize precise control of the running time of the three states CLEAR, WACC and VCALCU.

[0070] Example 3

[0071] The optimization of the neuron processing subsystem in this FPGA-based reconfigurable brain-inspired computing system-on-chip is described as follows:

[0072] The neuron processing subsystem described in this embodiment is responsible for the calculation of neuron and synaptic dynamics models, and is used to complete the two calculation processes of synaptic connection weight accumulation and neuron state update in brain-like computing.

[0073] Among them, the accumulation of synaptic connection weights is performed through discrete accumulation calculation operations through event triggering, and the neuron state update continuously updates the neuron state value in the memory through time division multiplexing. The number of neurons that the system can simulate changes with the size of the memory in the subsystem.

[0074] As a carrier for realizing reconfigurable neurons, the neuron processing subsystem not only needs to complete basic functions such as the accumulation calculation of synaptic connection weights, the update calculation of neuron states, and pulse emission, but also needs to consider how to realize the reconfiguration of neuron models, neural synapse models and calculation accuracy.

[0075] To this end, this embodiment designs a neuron processing architecture, which implements the computational process control of synaptic connection weight accumulation and neuron state update through a reconfigurable control logic composed of a weight accumulation state machine and a sequence mapping table;

[0076] Build the data path between memory and computing unit by generating logic through configurable model parameters.

[0077] Reconfigurable neuron and synapse models are achieved through parameter assignment via data remapping;

[0078] Reconfigurable computing accuracy is achieved by selecting reconfigurable parallel computing units and combining data flow splitting and computing process optimization.

[0079] The operation process of the neuron processing subsystem in this embodiment is as follows:

[0080] (1) The neuron processing subsystem receives the synaptic connection sent by the synaptic connection subsystem, and indexes the corresponding neuron state parameter through the destination neuron ID in the connection, and accumulates the synaptic weight on the connection with it;

[0081] (2) After receiving all synaptic connections in the current time step, the neuron state information is taken out in turn to update the membrane potential. If the membrane potential exceeds the threshold, a pulse is issued, and the pulse data packet is the neuron's own ID.

[0082] like Figure 3 As shown, as a further optimization of the neuron processing subsystem, the neuron processing subsystem includes reconfigurable control logic, configurable model parameter generation logic, a reconfigurable parallel computing unit, a reconfigurable neuron address generation module, a pulse time update module, a pulse transceiver, a DMA supporting floating-point error optimization, and a random number generator module.

[0083] Specifically, the functions of each functional module are as follows:

[0084] The reconfigurable control logic controls the operation of the neuron processing subsystem by generating a set of control instruction words (OP, A1, A2, M1, M2, S and P) and some configuration registers (cfg).

[0085] In the weight accumulation state (WACC) of the simulation scheduling subsystem, the instruction word of the control logic is generated by the weight accumulation state machine, while in the membrane potential update state (VCALCU), the instruction word of the control logic is generated by the sequence mapping table.

[0086] In addition, when the reconfigurable parallel computing unit is INT32, INT16 and INT8, the truncation interval of the multiplication unit product can be selected by configuring the register cfg.

[0087] The configurable model parameter generation logic selects operands required for calculation for the calculation unit under the control of the control instruction word, and stores the result of the calculation unit in the corresponding destination register.

[0088] Model parameters consist of three parts: shared constant registers, shared variable registers, and exclusive constant / exclusive variable registers.

[0089] Among them, the value of the shared constant register is written uniformly by the microprocessor subsystem;

[0090] The value of the shared variable register is generated by the random number generator module or other function modules;

[0091] The value of the exclusive constant / exclusive variable register is partly derived from the data indexed by the destination neuron ID in the synaptic connection in the BRAM cache, and partly derived from the weight value in the synaptic connection;

[0092] The reconfigurable parallel computing unit is composed of a 32-bit multi-way parallel multiplication unit and a 32-bit multi-way parallel addition unit.

[0093] The two computing units can be configured into computing modes of five data types: FP32, INT32, FP16, INT16, and INT8 through FPGA hardware reconfiguration. When configured in 16-bit computing mode, two 16-bit operations can be executed in parallel at the same time. When configured in 8-bit computing mode, four 8-bit operations can be executed in parallel at the same time.

[0094] Among them, the three fixed-point types INT32, INT16 and INT8 of the 32-bit multi-mode multiplication unit also require truncation interval selection for their products.

[0095] The reconfigurable neuron address generation module: indexes neuron state information and needs to use a special address generation mechanism to generate corresponding BRAM cache addresses at different stages according to the control signal of the simulation scheduling state machine.

[0096] This scheme changes the address of the BRAM cache by assigning a value to the address register. In the weight accumulation stage, whenever a synaptic connection comes, the address register is triggered to intercept the destination neuron ID in the synaptic connection and use it as the address register value; in the membrane potential update stage, the address register is initialized to 0, and the address register is incremented by one only when the OP field in the control instruction is End. In other cases, the address register remains unchanged.

[0097] The pulse timing update module is used to implement the neuron refractory period mechanism.

[0098] The pulse transceiver is used for neuron pulse transmission, reception and storage.

[0099] The DMA supporting floating point error optimization: BRAM cache is initialized and supports floating point error optimization.

[0100] The random number generator module generates random numbers.

[0101] Example 4

[0102] The optimization of the multi-chip communication subsystem in this FPGA-based reconfigurable brain-inspired computing system-on-chip is described as follows:

[0103] The multi-chip communication subsystem described in this embodiment is mainly responsible for receiving and forwarding pulse data packets sent by local and adjacent chips. Therefore, it needs to establish a reliable communication link with the surrounding chips and needs to route the data packets; it completes the transmission, reception and transfer of pulse data packets in the chip array on a chip basis, realizing the network expansion of the chip.

[0104] In addition, the multi-chip communication subsystem implements a multicast routing mechanism through a multicast router based on the above functions, realizes reconfigurable routing paths through the configuration of routing tables, and realizes reconfigurable maximum communication load by changing entries in routing tables through fine-grained hardware reconfiguration.

[0105] The multi-chip communication subsystem is responsible for receiving and forwarding pulse data packets (source neuron ID). The system can achieve reconfigurable routing paths through the routing table, thereby achieving reconfigurable network connections.

[0106] The operation process of the multi-chip communication subsystem is as follows:

[0107] (1) The multi-chip communication subsystem receives pulse data packets sent by other chips and the local neuron processing subsystem;

[0108] (2) Use the neuron ID to index its routing entry in the routing table;

[0109] (3) The direction to which the pulse will be sent is determined based on the routing entry information, where the pulse sent to the local area will be sent to the local synaptic connection subsystem.

[0110] like Figure 4 As shown, the multi-chip communication subsystem includes four groups of SerDes transceiver modules responsible for communicating with four direction chips and one multicast router;

[0111] Among them, the SerDes transceiver module uses Xilinx's Aurora8B / 10B IP to realize the conversion between high-speed serial differential signals and AXI4-Stream bus.

[0112] The SerDes transceiver module uses Xilinx's Aurora8B / 10B IP to achieve conversion between high-speed serial differential signals and AXI4-Stream bus;

[0113] The multicast router is responsible for receiving pulse data packets transmitted by the four directional chips and the local neuron processing subsystem and the microprocessor subsystem. After the three steps of unpacking, table lookup and routing, the pulse data packets are routed to the four adjacent chips and the local synaptic connection subsystem.

[0114] In this embodiment, the content of the pulse data packet is the neuron ID.

[0115] Example 5

[0116] The optimization of the synaptic connection subsystem in this FPGA-based reconfigurable brain-inspired computing system-on-chip is described as follows:

[0117] The synaptic connection subsystem described in this embodiment is responsible for the indexing and distribution of synaptic connections, defining the neuron corresponding to the pulse ID as the source neuron and the local neuron connected to it as the destination neuron. The connection relationship and connection weight between the source neuron and the destination neuron are stored in the synaptic connection subsystem.

[0118] The operation process of the synaptic connection subsystem is as follows:

[0119] (1) After receiving the pulse, the chip's synaptic connection subsystem indexes the synaptic index entry based on the pulse ID;

[0120] (2) Indexing several synaptic connections in the subsystem based on the synaptic connection storage first address and number in the synaptic index entry (the synaptic connection stores the target neuron ID and synaptic connection weight);

[0121] (3) According to the target neuron ID in the synaptic connection, it is sent to the corresponding neuron processing unit in the neuron processing subsystem.

[0122] In addition to realizing the two basic functions of indexing pulses to synaptic connections and distributing synaptic connections, the design of the synaptic connection subsystem described in this embodiment also needs to consider how to achieve the reconfiguration of neural synaptic models and the reconfiguration of network connections with unlimited neuron connection range and number of connections.

[0123] Specifically, the synaptic connection subsystem includes a pulse address decoding module, a synaptic index DMA module, a synaptic connection distribution module and a DDR storage, and the DDR storage stores synaptic connection information.

[0124] Among them, the synaptic DMA module needs to go through the microprocessor subsystem to read data from the DDR.

[0125] like Figure 5 As shown in the figure, in order to support high-performance, large-volume data access, the synaptic index DMA module uses the AXI4 protocol to implement address data decoupling and burst data transmission.

[0126] The synaptic connection subsystem works in a source indexing manner, and its workflow is as follows:

[0127] (a) the synaptic connection subsystem receives the pulse ID i sent from the multi-chip communication subsystem and sends it to the pulse address decoding module;

[0128] (b) the pulse address decoding module converts the pulse ID into the address and length information of the synapse index and sends it to the synapse index DMA module;

[0129] (c) The synapse index DMA module retrieves the synapse index Indexi,c corresponding to the pulse i in the current chip from the DDR storage via the microprocessor subsystem and sends it to the pulse address decoding module;

[0130] (d) the pulse address decoding module parses the synaptic connection storage first address staddri,c and the synaptic connection number fanouti,c in the synaptic index Indexi,c, and sends the index address and length information of the synaptic connection to the synaptic index DMA module;

[0131] (e) The synaptic index DMA module takes out fanouti,c synaptic connections si,j from the DDR storage according to the new index address and length information and sends them to the synaptic connection distribution module;

[0132] (f) The synaptic connection distribution module sends the synaptic connection weight to the corresponding neuron processing unit in the neuron processing subsystem by decoding the destination neuron j information in si,j.

[0133] Example 6

[0134] The optimization of the microprocessor subsystem in this FPGA-based reconfigurable brain-inspired computing system-on-chip is described as follows:

[0135] The microprocessor subsystem in this embodiment is responsible for controlling the start of simulation and monitoring the end of simulation (by controlling the simulation scheduling subsystem), as well as uniformly managing storage resources in itself and other subsystems and being responsible for data interaction with the outside of the chip.

[0136] like Figure 6As shown, the microprocessor subsystem includes 1 MicroBlaze soft core, 1 MIG module (Memory Interface Generator, MIG), 1 BRAM storage controller module (Bram Controller), a plurality of GPIO modules, 1 interrupt controller module, 1 UART communication module, 1 Mem Bridge module, 1 AXI4 Intc1 module, 1 AXI4 Intc2 module and a plurality of GPIO modules.

[0137] The MicroBlaze soft core accesses the DDR through the AXI4 Intc1 module and the MIG module in turn, connects the BRAM storage controller module to access the on-chip BRAM and register resources through the Mem Bridge module, connects the GPIO module to send control signals or detect state information, and connects the interrupt controller to detect the interrupt signal sent by the simulation scheduling subsystem.

[0138] The MicroBlaze soft core directly transmits data to the multi-chip communication subsystem through the AXI4 Stream bus protocol.

[0139] The GPIO module controls the simulation scheduling subsystem and detects the configuration of the UART communication module.

[0140] The UART communication module converts the data on the AXI4 Stream bus of the MicroBlaze module into the UART protocol and sends it out, and converts the data received from the UART protocol into the AXI4 Stream bus protocol and sends it to the MicroBlaze soft core.

[0141] The neuron processing subsystem uses the AXI4 full protocol to perform DDR read and write through the AXI4 intc2 module.

[0142] The synapse connection subsystem only uses the read address and read data channels in the AXI4 protocol to read DDR data through the AXI4 intc2 module.

[0143] The above only describes the embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A reconfigurable brain-inspired computing system-on-chip based on FPGA, characterized in that: include: Neuron processing subsystem, multi-chip communication subsystem, synaptic connection subsystem, simulation scheduling subsystem and microprocessor subsystem; The simulation scheduling subsystem receives a simulation start signal sent by the microprocessor subsystem, controls and schedules the neuron processing subsystem, the synaptic connection subsystem, and the multi-chip communication subsystem through corresponding control signals to complete a simulation of one time step; after the simulation is completed, an interrupt signal is sent to the microprocessor subsystem to wait for the start of the next time step simulation; The neuron processing subsystem receives the synaptic connection sent by the synaptic connection subsystem, and indexes the corresponding neuron state parameter through the target neuron ID in the connection, and accumulates the synaptic weight on the connection with it; after receiving all synaptic connections in the current time step, the neuron state information is sequentially retrieved to update the membrane potential. If the membrane potential exceeds a threshold, a pulse data packet is issued, and the content of the pulse data packet is the neuron ID; The multi-chip communication subsystem receives pulse data packets sent by other chips and the local neuron processing subsystem, uses the neuron ID to index its routing entry in the routing table, and determines the direction of the pulse according to the routing entry information. The pulse sent to the local area will be sent to the local synaptic connection subsystem; After receiving the pulse, the synaptic connection subsystem indexes a synaptic index entry according to the pulse ID, indexes several synaptic connections in the subsystem according to the synaptic connection storage first address and quantity in the synaptic index entry, and sends the destination neuron ID in the synaptic connection to the corresponding neuron processing unit in the neuron processing subsystem; The microprocessor subsystem uniformly addresses the storage in the computing system and communicates with the outside of the system through the UART.

2. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The microprocessor subsystem is connected to the simulation scheduling subsystem via a signal line, and the simulation scheduling subsystem is connected to the neuron processing subsystem, the multi-chip communication subsystem and the synaptic connection subsystem via signal lines respectively to realize the transmission of control data.

3. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 2, characterized in that: The pulse and weight data between the neuron processing subsystem, the multi-chip communication subsystem, the synaptic connection subsystem and the microprocessor subsystem are transmitted via the AXI4 stream bus protocol.

4. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The simulation scheduling subsystem is controlled by a state machine, which includes 6 states: initial state, clear state, memory read state, weight accumulation state, membrane potential update state and memory write state; and the state jump is controlled by the Sim_startpluse signal from the microprocessor subsystem, the rwdone signal from the neuron processing subsystem, a built-in Timer counter and three built-in time window registers.

5. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The neuron processing subsystem includes reconfigurable control logic, configurable model parameter generation logic, reconfigurable parallel computing unit, reconfigurable neuron address generation module, pulse time update module, pulse transceiver, DMA supporting floating point error optimization, and random number generator module.

6. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The multi-chip communication subsystem includes four groups of SerDes transceiver modules responsible for communicating with four directional chips and one multicast router; The SerDes transceiver module uses Xilinx's Aurora8B / 10B IP to achieve conversion between high-speed serial differential signals and AXI4-Stream bus; The multicast router is responsible for receiving pulse data packets transmitted by the four directional chips and the local neuron processing subsystem and the microprocessor subsystem. After the three steps of unpacking, table lookup and routing, the pulse data packets are routed to the four adjacent chips and the local synaptic connection subsystem.

7. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The synaptic connection subsystem includes a pulse address decoding module, a synaptic index DMA module, a synaptic connection distribution module and a DDR storage. The DDR storage stores synaptic connection information. The working process is as follows: (a) the synaptic connection subsystem receives the pulse ID i sent from the multi-chip communication subsystem and sends it to the pulse address decoding module; (b) the pulse address decoding module converts the pulse ID i into the address and length information of the synapse index and sends it to the synapse index DMA module; (c) The synapse index DMA module retrieves the synapse index Indexi,c corresponding to the pulse ID i in the current chip from the DDR storage via the microprocessor subsystem and sends it to the pulse address decoding module; (d) the pulse address decoding module parses the synaptic connection storage first address staddri,c and the synaptic connection number fanouti,c in the synaptic index Indexi,c, and sends the index address and length information of the synaptic connection to the synaptic index DMA module; (e) The synaptic index DMA module fetches fanouti,c synaptic connections s from the DDR storage according to the new index address and length information ij Sending to the synaptic connection distribution module; (f) The synaptic connection distribution module decodes s ij The destination neuron j information in sends the synaptic connection weight to the corresponding neuron processing unit in the neuron processing subsystem.

8. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 7, characterized in that: The synaptic DMA module needs to go through the microprocessor subsystem to read data from the DDR storage.

9. The FPGA-based reconfigurable brain-inspired computing system-on-chip according to claim 1, characterized in that: The microprocessor subsystem includes a MicroBlaze soft core, a MIG module, a BRAM storage controller module, an interrupt controller module, a UART communication module, a Mem Bridge module, an AXI4 Intc1 module, an AXI4Intc2 module and multiple GPIO modules; The MicroBlaze soft core is connected to the AXI4 Intc2 module and the MIG module in sequence through the AXI4 Intc1 module to access the DDR, connected to the BRAM storage controller module to access the on-chip BRAM and register resources through the Mem Bridge module, connected to the GPIO module to send control signals or detect status information, and connected to the interrupt controller to detect interrupt signals sent by the simulation scheduling subsystem; The GPIO module controls the simulation scheduling subsystem and detects and configures the UART communication module.

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