Automatic boundary selection and segmentation iterative processing method, system, device and medium

Abstract

The present application provides an automatic boundary selection segmentation iterative processing method, system, device and medium, which are applied to the field of electronic design automation technology. According to the user design, a target syntax tree is first constructed according to a preset syntax tree file structure, and then the target syntax tree is initially segmented at any segmentation boundary to obtain a number of aggregated node clusters. Then, after reselecting the origin node from these nodes, the position of the non-origin node to be adjusted is adjusted to realize the segmentation process of automatic boundary selection segmentation iterative processing. At the same time, in the segmentation result formed, the relationship between the non-origin node and the origin node is closer, avoiding falling into a local optimal solution and failing to obtain a global optimal solution, and the final segmentation result is more reasonable.

Description

Technical Field

[0001] The present application relates to the technical field of electronic design automation (EDA), and in particular to an automatic boundary selection and segmentation iterative processing method, system, device and medium. Background Art

[0002] Currently, the scale of chip design is getting larger and larger, and prototype design verification needs to be carried out based on a prototype verification system composed of multiple verification chips. For example, the verification chip uses FPGA (Field Programmable Gate Array) to form a multi-FPGA verification system. This requires dividing the entire user design into a specified number of different parts, and then allocating each part to the corresponding FPGA, so that the functions and performance of the entire user design can be verified through the collaborative work of multiple FPGAs.

[0003] In the current segmentation process, due to various reasons, such as the segmentation boundary is fixed, and the global optimal solution cannot be obtained through clustering during segmentation, etc., the segmentation scheme has many shortcomings, such as unreasonable segmentation results.

[0004] Based on this, a new segmentation technology solution is needed. Summary of the Invention

[0005] In view of this, the embodiments of this specification provide an automatic boundary selection segmentation iterative processing method, system, device and medium, which first identifies and aggregates node clusters of dense nodes through preliminary segmentation, and performs hypergraph node adjustment after the preliminary segmentation, thereby realizing automatic boundary selection segmentation iterative processing and improving segmentation quality.

[0006] The embodiments of this specification provide the following technical solutions:

[0007] The embodiment of this specification provides an automatic boundary selection and segmentation iterative processing method, including:

[0008] Obtain the leaf nodes and the level information of the leaf nodes recorded in the syntax tree file structure, and create each level node in the syntax tree layer by layer according to the level information of the leaf nodes to build the target syntax tree in memory;

[0009] Performing an initial segmentation of the target syntax tree at an arbitrary segmentation boundary to obtain a first hypergraph including a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship;

[0010] Selecting a number of nodes from the number of node clusters in the first hypergraph as origin nodes, where the number of origin nodes corresponds to the number of verification chips in the verification system;

[0011] Traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

[0012] Preferably, selecting several origin nodes from the several node clusters includes:

[0013] Performing edge splitting processing on the first hypergraph, wherein the hyperedges in the first hypergraph are split into a plurality of common graphs connecting the driver nodes and the load nodes according to the number of load nodes, and the weights of the edges remain unchanged;

[0014] Add several virtual nodes to the edge according to the edge weight, and connect the virtual nodes to the two endpoints of the original edge in sequence to form a new graph, where the number of virtual nodes is the edge weight and the following relationship is satisfied: N = W-1, where N is the number of virtual nodes and W is the edge weight.

[0015] Marking corresponding distance values ​​for all nodes in the new graph;

[0016] Several nodes are selected as origin nodes according to the distance value.

[0017] Preferably, marking corresponding distance values ​​for all nodes in the new graph includes:

[0018] Traversing the new graph to select a target node with the largest degree value, wherein the degree value is used to represent the number of edges owned by the node;

[0019] After establishing the first queue and the second queue, the target node is added to the first queue, and all neighboring nodes of the target node are traversed to add all neighboring nodes of the target node to the second queue, and a first distance value is marked for all nodes in the first queue, and a second distance value is marked for all nodes in the second queue;

[0020] After marking, delete all nodes in the first queue, add all nodes in the neighboring nodes of each node in the second queue that have not been marked with distance values ​​to the first queue, mark all nodes in the first queue with a third distance value, and delete all nodes in the second queue, and add all nodes in the neighboring nodes of each node in the first queue that have not been marked with distance values ​​to the second queue, and repeat the above operations until all nodes are marked with corresponding distance values.

[0021] Preferably, after the several origin nodes are selected, all the virtual nodes are deleted.

[0022] Preferably, before adjusting each non-origin node to be adjusted to the verification chip where the corresponding target origin node is located, the automatic boundary selection and segmentation iterative processing method further includes:

[0023] Determine an adjustment benefit corresponding to each non-origin node, where the adjustment benefit is used to represent the cost of excess resource increase or decrease of the first verification chip and the second verification chip when the non-origin node is adjusted from the first verification chip to the second verification chip, where the first verification chip is the verification chip of the node cluster to which the non-origin node belongs, and the second verification chip is the verification chip of the target origin node to which the non-origin node is to be adjusted;

[0024] The non-origin node to be adjusted is determined according to the adjustment benefit.

[0025] Preferably, the adjustment benefit corresponding to the non-origin node to be adjusted is: De_Cut + K1×ΣDei–K2×ΣExj;

[0026] Among them, De_Cut is the decrease in the split size of the second verification chip caused by the non-origin node adjusting from the first verification chip to the second verification chip, Dei is the percentage corresponding to the i-th over-limit resource reduced by the first verification chip, Exj is the percentage corresponding to the j-th over-limit resource added to the second verification chip, K1 and K2 are configurable parameters, and i and j are positive integers.

[0027] Preferably, determining the non-origin node to be adjusted according to the adjustment benefit includes:

[0028] Calculate the follow probability of all neighbor nodes of the non-origin node, where the follow probability of each neighbor node is the total number of endpoints of the hyperedges connected to the non-origin node divided by the total number of neighbor nodes;

[0029] Determine a set of nodes to be adjusted according to the following probability, wherein the set of nodes to be adjusted is a set consisting of the non-origin node to be adjusted and other non-origin nodes that follow the non-origin node to be adjusted to the verification chip where the target origin node is located;

[0030] Calculating the movement probability of the node set to be adjusted to each verification chip according to the adjustment benefits corresponding to the movement of the node set to be adjusted to each verification chip;

[0031] The non-origin node to be adjusted is determined according to the magnitude of the movement probability.

[0032] Preferably, when the current number of iterations does not exceed the preset optimal convergence iteration limit number, the movement probability is:

[0033]

[0034] Where Pi→j is the movement probability of the node set to be adjusted from the i-th verification chip to the j-th verification chip, Cut_Cost_i_j is the cutting cost of the node set to be adjusted from the i-th verification chip to the j-th verification chip, The adjustment gain corresponding to the movement of the node set to be adjusted from the i-th verification chip to the x-th verification chip is GAIN, which is the adjustment gain set, that is, GAIN = {Cut_Gain_i_1, Cut_Gain_i_2, Cut_Gain_i_3, ..., Cut_Gain_i_n}, where Cut_Gain_i_i is preset to zero to indicate the adjustment gain when no movement occurs; n is the total number of verification chips;

[0035] When the current number of iterations exceeds the preset optimal convergence iteration limit, the movement probability is assigned a preset value to indicate that the node set to be adjusted can be adjusted to the verification chip corresponding to the maximum adjustment gain in the adjustment gain set.

[0036] Preferably, the input user design is initially segmented according to a preset segmentation strategy to obtain a first hypergraph containing a plurality of node clusters, including:

[0037] First, a corresponding edge complement graph is constructed for the second hypergraph corresponding to the user design. Then, the target node in the edge complement graph is traversed and the corresponding overdegree of the target node is marked. All nodes are sorted in ascending order of overdegree value and stored in a cache queue. The cache queue is used as the residual graph of the edge complement graph. The following traversal operation is performed on the first node in the residual graph: the first node in the cache queue is added to the cache set from the cache queue, and the neighbor nodes with hyperedge connection relationships with the first node and the hyperedges connected to all the neighbor nodes are deleted from the cache queue to obtain a new residual graph. The above traversal operation is continued for the first node in the new residual graph until the residual graph is empty.

[0038] And, find all corresponding nodes in the cache set in the second hypergraph and cluster them into node clusters to obtain the first hypergraph, wherein the node clusters in the first hypergraph no longer expose internal details during the segmentation process, the weight of the node cluster is the sum of the weights of all internal nodes, and the connection relationship of the node cluster inherits the connection relationship of all internal nodes.

[0039] Preferably, creating each level node in the syntax tree layer by layer according to the level information of the leaf node includes:

[0040] For each leaf node, the following hierarchical processing is performed in memory according to the hierarchical information of the leaf node to obtain the hierarchical nodes that constitute the target syntax tree: determine whether the first-level node has been created. If not, create the first-level node and assign a unique node name to the first-level node. If it has been created, obtain the first-level node and then delete the first-level information, and perform next-level node processing until the last level node.

[0041] Preferably, the preliminary segmentation process includes:

[0042] Select n seed segmentation boundaries in the target syntax tree. The n segmentation boundaries are evenly distributed at more than 1 / 2 of the syntax tree layer height. Perform a segmentation on each segmentation boundary to obtain the segmentation particle size corresponding to each segmentation boundary. By traversing each segmentation boundary and its corresponding segmentation particle size, determine the starting segmentation boundary, where the starting segmentation boundary is the segmentation boundary with the smallest product of the corresponding segmentation particle size and the layer height among the n seed segmentation boundaries.

[0043] The optimal boundary search is performed downward from the initial segmentation boundary. As the segmentation boundary continues to descend, it stops when the segmentation particles cannot be made smaller. The segmentation boundary at this time is taken as the optimal segmentation boundary.

[0044] The preliminary segmentation process is completed according to the optimal segmentation boundary.

[0045] Preferably, before performing the initial segmentation, the automatic boundary selection segmentation iterative processing method further includes:

[0046] Perform timing analysis on the third hypergraph corresponding to the input user design, mark the timing attributes of the nodes in the hypergraph, and obtain the setup time redundancy and hold time redundancy corresponding to each timing path;

[0047] The weight values ​​of the edges in the hypergraph are updated according to the setup time margin and the hold time margin, where the weight values ​​of the edges are updated according to the following relationship: , where Worg is the original weight of the edge, Wnew is the new weight of the edge, C1 and C2 are configurable parameters, and s and h are the setup time margin and hold time margin of the timing path, respectively.

[0048] Preferably, during the initial segmentation, the automatic boundary selection segmentation iterative processing method further comprises: calculating the resource variance corresponding to all node clusters currently being aggregated, and suspending the current aggregation of the target node cluster when the resource variance caused by the aggregation of the target node cluster exceeds a preset threshold;

[0049] And / or, when adjusting each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, the automatic boundary selection segmentation iterative processing method also includes: calculating the resources occupied by the target segmentation result after adjusting the non-origin node to the corresponding target origin node to form the target segmentation result, and when the resources occupied by the target segmentation result exceed the resources of the verification chip, suspending the adjustment of the non-origin node to the corresponding target origin node.

[0050] The embodiment of this specification also provides an automatic boundary selection and segmentation iterative processing system, including:

[0051] The acquisition module is used to obtain the leaf nodes and the hierarchical information of the leaf nodes recorded in the syntax tree file structure, and create the hierarchical nodes of each level in the syntax tree layer by layer according to the hierarchical information of the leaf nodes to construct the target syntax tree in the memory;

[0052] A preliminary segmentation module, configured to perform an initial segmentation of the target syntax tree at any segmentation boundary to obtain a first hypergraph comprising a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship;

[0053] a selection module, configured to select a number of nodes from the number of node clusters in the first hypergraph as origin nodes, wherein the number of origin nodes corresponds to the number of verification chips in the verification system;

[0054] An adjustment module is used to traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

[0055] An embodiment of this specification further provides an electronic device, including:

[0056] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the automatic boundary selection and segmentation iterative processing method described in any one of the present specifications.

[0057] An embodiment of the present specification further provides a computer storage medium storing computer executable instructions. When the computer executable instructions are executed by a processor, the automatic boundary selection and segmentation iterative processing method described in any one of the present specification is executed.

[0058] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0059] By constructing a syntax tree directly in memory and performing preliminary segmentation of arbitrary segmentation boundaries based on the syntax tree, a hypergraph containing several clustered nodes is generated. This allows the identification of closely connected clusters and their repositioning. While this adds processing steps and may consume some computing resources, it significantly impacts the final segmentation results. For example, identifying closely connected clusters of nodes can reduce the occurrence of direct connections and loops, significantly improving timing performance. Furthermore, by repositioning some hypergraph nodes, a pre-defined segmentation convergence strategy can be implemented, helping to escape from local optimal solutions and ultimately achieve a globally optimal final segmentation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] Figure 1 It is a schematic diagram of forming straight-through and loop paths in the existing segmentation scheme;

[0062] Figure 2 This is a schematic diagram of the structure of the automatic boundary selection and segmentation iterative processing implemented in this application;

[0063] Figure 3 It is a flowchart of the automatic boundary selection and segmentation iterative processing method in this application;

[0064] Figure 4 This is a schematic diagram of the process of determining the origin node in this application;

[0065] Figure 5 This is a schematic diagram of forming a normal graph from a hypergraph by removing edges in this application;

[0066] Figure 6 It is a schematic diagram of inserting a virtual node in this application;

[0067] Figure 7 It is a schematic diagram of the leaf nodes and their hierarchical information in this application;

[0068] Figure 8 It is a syntax tree diagram constructed based on the syntax tree structure file in this application;

[0069] Figure 9 It is a syntax tree diagram constructed based on the syntax tree structure file in this application;

[0070] Figure 10 This is a schematic diagram of segmentation based on the constructed syntax tree in this application;

[0071] Figure 11 This is a schematic diagram of segmenting the segmentation boundary based on the syntax tree in this application;

[0072] Figure 12 It is a schematic diagram of how node disassembly affects the cutting process in the segmentation process in this application;

[0073] Figure 13 It is a schematic diagram of the structure of the automatic boundary selection and segmentation iterative processing system in this application;

[0074] Figure 14 It is a structural diagram of the electronic device in this application. DETAILED DESCRIPTION

[0075] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0076] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0077] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0078] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0079] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0080] The key steps in the current segmentation process are divided into three parts: coarsening, segmentation, and refinement, which are executed sequentially. The coarsening stage clusters smaller circuit modules into larger modules of a certain granularity according to a specific strategy based on the user design's hierarchy or resource distribution, and then segments them as a whole. The segmentation stage segments the user design, expressed as a hypergraph, according to a specified number of segments. Classic algorithms aim to minimize the cost of the segments. The refinement and improvement stage, after segmentation, further adjusts and improves the segmentation results with the goal of minimizing the cost of the segments. The final segmentation result is then distributed and compiled onto the corresponding verification chip (such as an FPGA) for prototype verification.

[0081] Furthermore, the split boundary refers to the granularity at which the user design is segmented. Because user designs are composed of many modules, each with a parallel or nested relationship, the modules and their interrelationships form a syntax tree. Therefore, the split boundary is a curve on the syntax tree that divides the tree into two parts. The modules below the curve are treated as a whole, without exposing any details. Therefore, the nodes on the split boundary form a hypergraph representing the user design, and the segmentation algorithm is the process of segmenting on this hypergraph.

[0082] In existing solutions, segmentation boundaries are usually selected by a certain strategy or method and remain fixed after selection. Therefore, segmentation is performed after forming a hypergraph with fixed boundaries, which easily leads to poor segmentation results.

[0083] In addition, in fast-iteration scenarios, the segmentation scheme with fixed boundaries is obviously not flexible, convenient, or fast enough, and the segmentation results obtained are generally poor, often with many feedthrough signals, loops, etc.

[0084] like Figure 1 In order to connect the starting node, a direct line spans multiple FPGAs (such as Figure 1 Therefore, a straight-through line will result in excessive line delay costs;

[0085] like Figure 1 As shown in the figure, some signal lines pass through many FPGAs to transmit signals to corresponding modules and then return to the origin, forming a ring connection. Therefore, the ring line will seriously affect the overall performance of the system.

[0086] Furthermore, interconnect resources between verification chips (such as FPGAs) are relatively limited due to the limited number of pins. However, with existing technologies, the cost of segmenting between FPGAs is still significant, leading to tight interconnect utilization and congestion in inter-FPGA communication, which in turn affects the operating frequency of the verification system. Furthermore, FPGAs contain multiple types of resources, and the resource consumption of the portion of a user design assigned to an FPGA cannot exceed the total resource consumption of an FPGA. Existing segmentation tools often result in excessively large cut sizes when moving nodes to meet resource constraints, thereby increasing the cost of interconnect consumption.

[0087] In view of this, the inventors conducted in-depth analysis and explored improvements on the segmentation scheme and found that:

[0088] On the one hand, the existing syntax tree contains a lot of information that is not required for segmentation, which affects the segmentation effect of the segmentation algorithm;

[0089] Secondly, the segmentation algorithm cannot effectively identify closely connected node clusters during the coarsening clustering stage, making it difficult for the segmentation algorithm to obtain reasonable segmentation results. For example, it may fall into the local optimal solution and miss the global optimal solution, or the cut size may increase excessively when moving nodes in the later stage.

[0090] Specifically, node aggregation is a prerequisite for segmentation, and its effectiveness directly impacts the final segmentation quality. Existing node aggregation schemes typically rely primarily on the weights of hyperedges between nodes, resulting in suboptimal aggregation. The size of aggregated node resources varies, the cut size (segmentation granularity) cannot be reduced, and the timing performance of the segmentation results is generally poor.

[0091] Therefore, given that the identification of syntax trees and clusters are both prerequisite steps in segmentation, it is necessary to first identify node clusters that are particularly closely connected, so as to ensure that nodes with closely connected relationships can be segmented into the same verification chip for prototype verification during segmentation.

[0092] Based on this, this application proposes a segmentation iterative processing solution with automatic boundary selection: Figure 2Schematic diagram, designed for user input, using the information recorded in the preset syntax tree file structure, quickly constructing the nodes of each level of the syntax tree after reading it into the memory, making the syntax tree very simple and very suitable for subsequent segmentation; then performing preliminary segmentation of any segmentation boundary for the syntax tree, so that based on the connection relationship between the leaf nodes, the connection relationship between the nodes on any segmentation boundary in the syntax tree can be recursively inferred, so that effective node aggregation is performed in the early stage of the segmentation stage, and a set of closely connected nodes is preliminarily identified through aggregation, that is, node clusters are obtained, so that the nodes in the node clusters are no longer exposed, so that the identified set of closely connected nodes can be treated as a whole for subsequent processing through the node clusters, and then the positions of some hypergraph nodes in the hypergraph of the preliminary obtained node clusters are adjusted to obtain the final globally optimal segmentation result, thereby realizing the segmentation iterative processing of automatic boundary selection, which can avoid the segmentation problem of falling into local optimality and failing to obtain the global optimal solution.

[0093] By quickly building a syntax tree in memory and performing arbitrary boundary segmentation attempts, it is possible to effectively identify tightly connected node clusters, reduce the occurrence of through-links and loops, and greatly improve timing performance. By adjusting the positions of some hypergraph nodes in the hypergraph containing aggregated node clusters, it is possible to implement a preset segmentation convergence strategy and help escape from the local optimal solution, thereby obtaining a globally optimal solution and a relatively reasonable final segmentation result.

[0094] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0095] like Figure 3 As shown, the embodiment of this specification provides an automatic boundary selection and segmentation iterative processing method, which may include:

[0096] Step S202: Obtain the leaf nodes and the hierarchical information of the leaf nodes recorded in the syntax tree file structure, and create the hierarchical nodes of each level in the syntax tree layer by layer according to the hierarchical information of the leaf nodes to construct the target syntax tree in the memory.

[0097] Given that obtaining existing segmentation boundaries requires parsing the user design in the form of RTL or netlist through a parser to form a syntax tree, the parsing process requires analyzing the syntax structure, processing syntax rules, etc. All syntax features are retained, which consumes a lot of time. In addition, when the syntax tree is retained in memory and referenced in the form of a linked list, the data storage space is huge and difficult to save and exchange. Therefore, in the scenario of rapid iteration, the above method is not flexible, convenient, and fast enough. Therefore, this description provides a preferred solution for quickly building a syntax tree in memory based on a new syntax tree file structure, which is convenient for quickly building a syntax tree based on the information required for the segmentation process.

[0098] During implementation, a new syntax tree is created based on the newly defined syntax tree file structure. This syntax tree can serve as a hypergraph for segmentation. The syntax tree file structure defines information related to leaf nodes. For example, the syntax tree file structure includes the name and hierarchical structure of the leaf nodes, and may also include one or more information such as resource size, node connectivity, and inclusion relationships.

[0099] Step S204: Perform an initial segmentation on the target syntax tree at any segmentation boundary to obtain a first hypergraph including a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship.

[0100] In the early stage of the segmentation phase, cluster identification can first identify node clusters with particularly close connections (i.e., aggregation), ensuring that the set of nodes with close connections is first aggregated to form node clusters, and the node clusters can be subsequently processed as a whole, avoiding falling into local optimality too early.

[0101] It should be noted that the initial segmentation can be understood as a preliminary clustering process, and the new nodes obtained by clustering are densely connected node clusters.

[0102] In the hypergraph obtained after clustering, node clusters serve as hypergraph nodes, so the points in the hypergraph can represent the modules in the circuit, and the edges in the hypergraph represent the connections between modules. The weight of a hypergraph node depends on which other modules are nested inside it and the number of resources used by these modules. The weight of an edge in the hypergraph depends on the signal bit width of the transmitted signal.

[0103] Step S206: Select several nodes from the several node clusters in the first hypergraph as origin nodes again, where the number of origin nodes corresponds to the number of verification chips in the verification system.

[0104] After initially obtaining a hypergraph containing node clusters, the positions of some nodes in the hypergraph can be further adjusted to refine the initial segmentation. Therefore, the deployment plan for the segmentation results to the verification chip can be redefined based on the verification chip status in the verification system. Therefore, the origin node can be determined first, and then non-origin nodes with close connections to the origin node can be adjusted together, so that multiple closely connected nodes can be deployed on the same verification chip.

[0105] In implementation, assuming that there are P verification chips (such as FPGAs) in the verification system's network, it is necessary to find P origin nodes in the hypergraph (denoted as Map). Each origin node will be placed in an FPGA, and other nodes in the Map will continuously select FPGAs and join them based on the connection relationship and weight with each origin node to complete the segmentation.

[0106] Step S208: traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

[0107] By traversing the hypergraph, that is, traversing each node in the Map, calculating the shortest distance from each node to P origin nodes, selecting the origin node with the shortest distance, and counting it into the verification chip (such as FPGA) corresponding to the origin node, the final segmentation result is formed. At this time, the segmentation result can be deployed to the verification chip Sang for prototype verification.

[0108] In summary, through preliminary segmentation, closely connected nodes can be aggregated into node clusters, effectively reducing the presence of unreasonable signal paths (such as direct and loop paths) in the segmentation results, which is beneficial for improving the timing performance of the segmentation results. Furthermore, by reselecting the origin node and adjusting the position of non-origin nodes, the positions of each hypergraph node are made more reasonable, avoiding falling into local optimal solutions during segmentation. Therefore, through the effective identification of node clusters and the adjustment of the positions of some hypergraph nodes, the preset segmentation convergence strategy can be implemented, and it can also help to escape the local optimal solution, thereby obtaining the final segmentation result of the global optimal solution.

[0109] It should be noted that the origin node can be selected according to a preset screening strategy, such as selecting according to the size of the resources occupied by the node, or selecting according to the timing performance requirements of the node, etc.

[0110] In some embodiments, the present specification may provide a new approach to selecting origin nodes, such as Figure 4 For example, the selection of origin nodes may include:

[0111] Step S2042: perform edge splitting processing on the first hypergraph obtained above, wherein the hyperedges in the first hypergraph are split into multiple ordinary graphs connecting driving nodes and load nodes according to the number of load nodes, and the edge weights remain unchanged.

[0112] In the implementation, the identified node cluster will be regarded as a node in the hypergraph. The updated hypergraph is assumed to be Map(V, E). When the Map is split, the hyperedge will be split into multiple common graphs connecting the driver nodes and the load nodes according to the number of load nodes, and the edge weights remain unchanged. Figure 5 For example, node D has two load nodes L, so the relationship between nodes and hyperedges before edge removal is shown on the left side of the figure, and the relationship between nodes and hyperedges after edge removal is shown on the right side of the figure.

[0113] Step S2044: Add several virtual nodes to the edge according to the weight of the edge, and connect the several virtual nodes to the two endpoints of the original edge in sequence to form a new graph, where the number of virtual nodes and the weight of the edge satisfy the following relationship: N=W-1, N is the number of virtual nodes, and W is the weight value of the edge.

[0114] Before selecting the origin node, the hypergraph Map can be preprocessed by traversing each edge in the Map. If the weight of the edge is greater than 1, the edge is processed as follows: Figure 6 Assume the weight of the edge is W (W is an integer greater than 0). Then, add W-1 fake nodes to the edge, set the resource value of each fake node to 0, and connect the two endpoints of the original edge in sequence. It should be noted that after all nodes have found their own FPGAs, all fake nodes are deleted.

[0115] Step S2046: Mark all nodes in the new graph with corresponding distance values.

[0116] During implementation, a reference node for distance calculation may be selected according to a predetermined selection strategy, for example, any node may be selected as a reference, and then the distance values ​​between all other nodes and the reference node may be calibrated.

[0117] In some embodiments, the present description provides a solution for determining a reference node (i.e., an origin node) by the degree value of the node and marking the distance, so that the distance values ​​between all other nodes and the reference node better reflect the closeness of the connection relationship.

[0118] First, the new graph is traversed to select the target node (i.e., the reference node) with the largest degree value, where the degree value is used to represent the number of edges owned by the node;

[0119] Then, after establishing the first queue and the second queue, the target node is added to the first queue, and all neighboring nodes of the target node are traversed to add all neighboring nodes of the target node to the second queue, and the first distance value is marked for all nodes in the first queue, and the second distance value is marked for all nodes in the second queue;

[0120] Finally, after marking, all nodes in the first queue are deleted, and the nodes in all neighboring nodes of each node in the second queue that have not been marked with distance values ​​are added to the first queue, and the third distance value is marked for all nodes in the first queue, and all nodes in the second queue are deleted, and the nodes in all neighboring nodes of each node in the first queue that have not been marked with distance values ​​are added to the second queue, and the above operations are repeated until all nodes are marked with corresponding distance values.

[0121] The schematic process is as follows: traverse the Map to find the node node1 with the largest degree value, that is, the node with the most edges; establish two queues q1 and q2, and initialize them to empty; add node1 to q1, traverse all neighbor nodes of node1, and add all neighbor nodes to q2, mark the distance value of all nodes in q1 as 0, and the distance value of all nodes in q2 as 1; delete all nodes in q1, add all neighbor nodes of each node in q2 (excluding nodes that have been marked with distance) to q1, mark the distance value of all nodes in q1 as 2, delete all nodes in q2, and let the neighbor nodes of each node in q1 be added to q2, and repeat the above operations until all nodes are marked with distance values.

[0122] Step S2048: Select several nodes as origin nodes according to the distance values.

[0123] After marking the distance values, we can determine the origin nodes based on the distance values. Assuming that P origin nodes are selected and the maximum distance value in the map is d_max, we can first select the node with a distance value of 0 as the first origin node; then select the node with the largest degree among all nodes with a distance value of [d_max / (P-1)] as the second origin node, where P>1 and [] is the rounding function; then select the node with the largest degree among all nodes with a distance value of [2 * d_max / (P-1)] as the third origin node, and so on until a total of P origin nodes are obtained.

[0124] In some implementations, that is, when adjusting the positions of hypergraph nodes after the initial segmentation of the hypergraph, the definition of the benefit of node movement can be updated in this step: the original benefit refers to the reduction in the overall cut-size (cutting particles) generated after a node is moved from one verification chip (such as FPGA) to another verification chip (such as FPGA); the current benefit value can be linked to the resources of the node and the FPGA resources. The advantage of this is that while making the segmentation result meet the resource constraints, the cost of increasing the cut size is minimized, which is actually a balancing method.

[0125] Specifically, before adjusting each non-origin node to be adjusted to the verification chip where the corresponding target origin node is located, the adjustment benefit corresponding to each non-origin node is first determined, wherein the adjustment benefit is used to characterize the cost of excessive resource increase or decrease of the first verification chip and the second verification chip when the non-origin node is adjusted from the first verification chip to the second verification chip. The first verification chip is the verification chip where the node cluster to which the non-origin node belongs is located, and the second verification chip is the verification chip where the target origin node to which the non-origin node will be adjusted is located; then, the non-origin nodes to be adjusted are determined based on the adjustment benefit, so that after the non-origin nodes to be adjusted are determined, the positions of these non-origin nodes to be adjusted can be adjusted in a targeted manner.

[0126] It should be noted that the cost of the excess resources brought to the two verification chips by the position adjustment can be determined based on the type and size of the resources.

[0127] In one example, the cost can be quantitatively calculated based on the excess percentage of the excess resource, so that the cost result can be better determined based on the quantitative result. Therefore, the adjustment benefit corresponding to the non-origin node to be adjusted can be defined as follows, that is, the adjustment benefit is defined as: De_Cut + K1×ΣDei–K2×ΣExj;

[0128] Among them, De_Cut is the decrease in the split size of the second verification chip caused by the non-origin node adjusting from the first verification chip to the second verification chip, Dei is the percentage corresponding to the i-th over-limit resource reduced by the first verification chip, Exj is the percentage corresponding to the j-th over-limit resource added to the second verification chip, K1 and K2 are configurable parameters, and i and j are positive integers.

[0129] The quantitative calculation process is as follows: If node A moves from FPGA1 to FPGA2, FPGA2 will add k2 types of over-limit resources, with corresponding over-limit percentages of Ex1, Ex2, ..., Exk2. Furthermore, FPGA1 will reduce its over-limit resources to k1 types, with corresponding percentages of De1, De2, ..., Dek1. Furthermore, moving node A from FPGA1 to FPGA2 will reduce the cut size of FPGA2 by De_Cut (which can be negative). Therefore, the adjustment benefit can be quantified as De_Cut + K1*(de1+de2+…dek1) – K2*(ex1+ex2+…exk2), where K1 and K2 are configurable parameters.

[0130] Therefore, after obtaining the quantitative adjustment benefits, we can determine which nodes can actually be repositioned based on the benefits. For example, only when the benefits meet a preset threshold, such as a positive number, can we consider the actual position movement.

[0131] In some embodiments, when determining the non-origin nodes to be adjusted based on the adjustment benefits, that is, when determining which nodes can actually move their positions, the following probability can be used, that is, the size of the following probability can be used to qualitatively and roughly quantitatively determine the non-origin nodes that need to be adjusted.

[0132] In one example, the following probabilities of all neighbor nodes of a non-origin node are first calculated, where the following probability of each neighbor node is the total number of endpoints of the hyperedges connecting it to the non-origin node divided by the total number of neighbor nodes; then, a set of nodes to be adjusted is determined based on the following probability, where the set of nodes to be adjusted is a set consisting of the non-origin node to be adjusted and other non-origin nodes that follow the non-origin node to be adjusted to the verification chip where the target origin node is located; then, based on the adjustment benefits corresponding to the movement of the set of nodes to be adjusted to each verification chip, the moving probability corresponding to the movement of the set of nodes to be adjusted to each verification chip is calculated; finally, the non-origin node to be adjusted is determined based on the size of the moving probability.

[0133] It should be noted that the movement probability can be a parameter that is continuously adjusted during iteration, which is more conducive to the iterative process of automatic boundary selection.

[0134] Specifically, when the current number of iterations does not exceed the preset optimal convergence iteration threshold number, the relationship between the movement probability and the adjustment gain is as follows:

[0135]

[0136] Where Pi→j is the movement probability of the node set to be adjusted from the i-th verification chip to the j-th verification chip, Cut_Cost_i_j is the cutting cost of the node set to be adjusted from the i-th verification chip to the j-th verification chip, is the adjustment gain corresponding to the movement of the node set to be adjusted from the i-th verification chip to the x-th verification chip, GAIN is the adjustment gain set, that is, GAIN={Cut_Gain_i_1, Cut_Gain_i_2, Cut_Gain_i_3, ..., Cut_Gain_i_n}, where Cut_Gain_i_i is preset to zero to indicate the adjustment gain when no movement is performed;

[0137] When the current number of iterations exceeds the preset optimal convergence iteration limit, the movement probability is assigned a preset value to indicate that the node set to be adjusted can be adjusted to the verification chip corresponding to the maximum adjustment gain in the adjustment gain set.

[0138] Furthermore, the schematic illustration of the position adjustment can be as follows:

[0139] (1) Call the segmentation engine to perform the initial segmentation of the hypergraph G. If there are N FPGAs in the network, G will be segmented into N parts, and the N parts will be distributed to the corresponding FPGAs. Each FPGA is assigned a number of hypergraph nodes, and the sum of the weights of the connections between the hypergraph nodes of different FPGAs is the cut cost (Cut_Cost);

[0140] (2) Traverse each FPGA, such as FPGAi. First, initialize the position adjustment node set S_move to be empty, traverse the nodes of FPGAi, such as node Vi, then add node Vi to S_move and calculate the follow probability of all neighbor nodes of Vi. Neighbor nodes are nodes with direct hyperedge connections. Assume that the set of neighbor nodes of Vi is composed of neighbors, and the number is L. The follow probability of each neighbor node is the total number of endpoints of the hyperedge connecting it to node Vi divided by the total number of neighbor nodes. The neighbor node chooses whether to join S_move according to the probability, that is, whether to follow Vi to adjust the position. The probability selection method can be simulated by relying on the pseudo-random process of calculation, and each node is determined to follow according to the pseudo-random number.

[0141] (3) Try to move S_move in FPGAi to each other FPGA in the network and record the corresponding benefit of Cut_Cost reduction. This is to obtain the amount of Cut_Cost reduction that can be achieved by moving S_move to each other FPGA. If S_move does not move, that is, the benefit of remaining in FPGAi is counted as 0. Statistically assume that the benefit value of S_move moving to each target FPGA is GAIN = {Cut_Gain_i_1, Cut_Gain_i_2, Cut_Gain_i_3…Cut_Gain_i_n}.

[0142] Assuming the expected number of iterations is N, the current number of iterations is k, and the preset optimal convergence iteration cutoff number is B, then when k <= B, calculate the probability of S_move moving to each target FPGA. For example, the probability of moving to target FPGAj is as follows:

[0143]

[0144] When K>B, directly move S_move to the target FPGA corresponding to the maximum Cut_Gain in GAIN.

[0145] (4) Repeat steps (2) and (3) until the number of iterations reaches the preset N, and then the iterative segmentation process can be ended.

[0146] In some implementation examples, the selection of the moving position utilizes a computer pseudo-random process based on probability. The computer pseudo-random method can be to call a pseudo-random function based on the computer's system time and hash function to obtain a random number, pre-map a numerical range to a set event, and determine which event occurs by determining the range within which the random number falls. It should be noted that those skilled in the art can use the corresponding pseudo-random process to determine the probability based on the position adjustment diagrams in this description, and thus the computer pseudo-random process is not further described.

[0147] In some embodiments, during the initial segmentation (i.e., aggregating node clusters), a graph computation method may be used to determine which nodes are closely connected by graph complementation, and then these nodes may be segmented (also referred to as aggregation, clustering, etc.) into clusters, thereby treating the cluster as a whole in subsequent processing, and the internal nodes within the cluster are no longer exposed.

[0148] In practice, the initial segmentation may include the following processes:

[0149] First, a corresponding edge complement graph is constructed for the second hypergraph corresponding to the user design. Then, the target node in the edge complement graph is traversed and the corresponding overdegree of the target node is marked. All nodes are sorted in ascending order of overdegree value and stored in a cache queue. The cache queue is used as the residual graph of the edge complement graph. The following traversal operation is performed on the first node in the residual graph: the first node in the cache queue is added to the cache set from the cache queue, and the neighbor nodes with hyperedge connection relationships with the first node and the hyperedges connected to all the neighbor nodes are deleted from the cache queue to obtain a new residual graph. The above traversal operation is continued for the first node in the new residual graph until the residual graph is empty.

[0150] Then, all corresponding nodes in the cache set are found in the second hypergraph and clustered into node clusters to obtain the first hypergraph, wherein the node clusters in the first hypergraph no longer expose internal details during the segmentation process, the weight of the node cluster is the sum of the weights of all internal nodes, and the connection relationship of the node cluster inherits the connection relationship of all internal nodes.

[0151] The preliminary segmentation is performed by patching the image, and the schematic process can be as follows:

[0152] (1) Input the user design expressed in the form of a hypergraph G(V, E). The nodes in the hypergraph represent the modules in the circuit, and the edges in the hypergraph represent the connections between modules. The weight of the hypergraph node depends on which other modules are nested inside it and the number of resources used by these modules. The weight of the edge in the hypergraph depends on the signal bit width of the transmission signal.

[0153] (2) Construct an edge complement graph G* of G. The nodes of the edge complement graph G* are the same as those of G, and the edges in G* are the complement edges of G. That is, if there is a connection between two nodes in G, then there is no edge between the corresponding node pairs in G*; if there is no connection between two nodes in G, then there is an edge connection between the corresponding two nodes in G*.

[0154] (3) In G*, traverse all nodes V* except the new nodes clustered and marked in step (4) and record the excess degree of each node, that is, the total number of other nodes directly connected to the node through hyperedges E*. Arrange all nodes in ascending order of excess degree and store them in a queue q. Pop the first node K in the current queue and add the node to the set S. At the same time, delete the neighbor nodes with hyperedge connections to the node K and the hyperedges connected to all the above neighbor nodes in the queue to obtain the residual graph G*_left of G*. Repeat step (3) until G*_left is empty;

[0155] (4) Find all corresponding nodes in set S in G and cluster them into a new node N of G and mark them. The new node no longer exposes internal details during the segmentation process. The weight of the new node is the sum of the weights of all internal nodes, and the connection relationship of the new node inherits the connection relationship of all internal nodes. Therefore, the clustered new node is a tightly connected node cluster;

[0156] (5) Clear the S set and repeat step (2) using the updated G graph until all nodes in G are cluster nodes.

[0157] The iterative aggregation process is implemented by graph complementation, which can quickly and accurately aggregate nodes with dense connections into node clusters, and can also effectively avoid falling into the segmentation of local optimal solutions.

[0158] In some implementations, the construction of nodes at each level in the syntax tree may be started from the level of leaf nodes, or may be started from the first level in the leaf level information.

[0159] The following is an illustrative process of creating a node from the first level of information:

[0160] First, read the syntax tree file structure that records the leaf nodes. Figure 7 All leaf nodes shown in the figure each contain level information. For example, the level information of the node g0 includes the first level a1, the second level b1 and the third level c1.

[0161] Then, for each leaf node, the following hierarchical processing is performed in memory according to the hierarchical information of the leaf node to obtain the hierarchical nodes that constitute the target syntax tree: determine whether the first-level node has been created. If not, create the first-level node and assign a unique node name to the first-level node. If it has been created, obtain the first-level node and delete the first-level information, and perform next-level node processing until the last level node.

[0162] For example, for each leaf node, first read in the information of the leaf node, then read in the hierarchical information of each node in turn, and execute according to the hierarchical information: determine whether the first-level node of the leaf node has been created, if not, create the first-level node, and create a unique node number that is different from all existing nodes for the first-level node; if it has been created, obtain the first-level node and delete the first-level information; then check the second-level information, repeat the above judgment steps and numbering operations until the last hierarchical information, and construct the target syntax tree corresponding to the user design so that the syntax tree can be used for splitting iteration.

[0163] The schematic process of quickly building a syntax tree based on the above information is as follows:

[0164] (1) Read in leaf node information;

[0165] (2) Read the hierarchical information of each node in turn and build a special syntax tree for segmentation in memory, such as Figure 7 In the syntax tree, first determine whether the first-level node a1 has been created. If not, create the a1 node and assign it a unique node number that is different from all existing nodes. If it has been created, get the node and delete the first-level information. Then check the second-level information and repeat the above steps until the last level, such as c1 in the example. Create a new node and retain the node name for the last level without assigning a new name.

[0166] (3) Repeat step (2) for each leaf node until each leaf node is constructed in the syntax tree.

[0167] For example, reference Figure 8As shown in the figure, for the leaf node g0, its first-level information is a1. Since it has just been read into the memory, its corresponding level node (i.e., the first-level node, referred to as the first-level node) has not been established, so the first-level node can be established and named with a unique number g4; then it is determined whether the second-level node has been established. At the same time, it is found that the second-level node has not been established, so it is established as the second-level node g5, and finally to the leaf node g0 level, it is also established, so it is established as the last-level node (i.e., the leaf level node g0); and for the leaf node read into the memory Node g1, based on its hierarchical information, finds that the first-level node (i.e., the first-level node g4 corresponding to the hierarchical information a1) has been established, so there is no need to establish this hierarchical node. The node corresponding to the second-level information b2 has not been established, so the second-level node g6 is established until the leaf node g1 is established. Similarly, for leaf node g2, since the first-level node g4 and the second-level node g6 have been established, only the last leaf node g2 needs to be established. Similarly, for leaf node gp0, nodes g7 and gp0 can be established in memory in sequence.

[0168] The syntax tree constructed according to the above process can be seen in the following example: Figure 8 、 Figure 9 .For example Figure 8 In the diagram, nodes g0, g1, g2, g3, and gp0 in the syntax tree form the leaf node boundary, while nodes g4, g5, g6, and g7 are newly named nodes in the syntax tree according to the hierarchical information. Figure 9 In the diagram, nodes g5, g6, and g7 form a new node gp10, which is called a hyperedge and its name to be updated. This hyperedge can be used as an arbitrary segmentation boundary for segmentation attempts.

[0169] Therefore, after the above-mentioned hierarchical processing, a hierarchical relationship between each node is established, so the syntax tree can be expressed by these hierarchical nodes and their hierarchical relationships.

[0170] By constructing a syntax tree specifically for iterative segmentation, it helps to speed up the segmentation process; at the same time, the syntax tree based on the new syntax tree file structure is very convenient for transmitting and copying the syntax tree.

[0171] In one example, a segmentation engine can be used to attempt segmentation on any segmentation boundary in the syntax tree based on the syntax tree created above, and a balance can be made between the quality of the segmentation result and the time consumed to obtain the most optimized segmentation result. The usual order of attempts is to start from the top layer and attempt the segmentation boundary toward the bottom of the syntax tree. The connection relationship of the parent node is inherited from all its child nodes. For example, the parent node a has two child nodes x and y. Then, in the external connection relationship of the a node, the connection relationship between xy is called a self-loop and will be hidden; the connection relationship and weight of x or y to other child nodes of a, such as xz, z is an external node and will be inherited by a; if x, y are both connected to z, then the connection weight of a and z is the sum of xz and yz. According to the above rules, the connection relationship between the nodes on any segmentation boundary in the syntax tree can be recursively inferred based on the connection relationship between the leaf nodes.

[0172] The split boundary involves finding a boundary of nodes within the syntax tree representing the user's design. This boundary divides the syntax tree into two parts: the upper part contains information about the connections between the boundary nodes, while the lower part hides the details of the splitting process. The number of nodes on the split boundary increases as the boundary moves downward, and the time required by the splitting algorithm increases accordingly. In theory, an ideal splitting algorithm will produce better segmentation results.

[0173] The usual "try order" is to start from the top part and try the split boundary towards the bottom of the syntax tree. The specific method can be: Figure 10 Assume that the syntax tree has N layers, meaning there are at most N layers of instantiation relationships from vertex to leaf node. Then, select n seed split boundaries in the syntax tree, evenly distributed over 1 / 2 of the syntax tree layer height, that is, evenly distributed in the upper half of the tree. Perform a quick and rough split on each split boundary to obtain the corresponding cut size for each split boundary. For example, if the layer height of a split boundary edge_i is i, the corresponding cut_size_i is traversed, and cut_size_i * i is calculated. The split boundary with the smallest product is taken as the starting split boundary. Starting from the starting split boundary, the optimal boundary search is performed downward. As the split boundaries continue to decrease, the search stops when the cut size cannot be reduced any further. The split boundary at this time is taken as the optimal split boundary. Finally, the initial segmentation process is completed according to the optimal split boundary.

[0174] In some examples, the above example selects n seed segmentation boundaries in the syntax tree, and the n segmentation boundaries are evenly distributed according to more than 1 / 2 of the syntax tree layer height, and then performs a quick and rough segmentation on each segmentation boundary to obtain the cut size corresponding to each segmentation boundary.

[0175] Specifically, to achieve rapid processing speed while meeting loose requirements that only require rough resolution, the solution can start with the topmost boundary of n boundaries, perform a complete segmentation on the first boundary, and obtain its cut size. Nodes on the first boundary are then decomposed in a specific order, and the child nodes of the nodes on the first boundary are assigned to the FPGAs in the network according to a specific strategy. The decomposition of the child nodes continues until the second boundary is reached. At this point, the assignment positions of each node on the second boundary, i.e., the segmentation result, and its corresponding cut size, are directly obtained. Similarly, the segmentation result and cut size of the third boundary are obtained, and this continues until the bottommost boundary of the n boundaries, finally obtaining the corresponding segmentation result and cut size for each of the n boundaries. This process does not perform a complete segmentation on all boundaries, but only on the first boundary. Subsequent node decomposition and incremental processing are used to obtain the segmentation results for all boundaries, achieving rapid processing.

[0176] The following is an example to illustrate:

[0177] like Figure 11 The example is a part of the syntax tree between two adjacent boundaries among n boundaries. In fact, there may be many layers of nodes between the i-th boundary and the i+1-th boundary. For the sake of illustration, only the (5th, 6th, 7th, 8th, 9th, 10th) layer exists in the example. However, the principle is explained by using the example without losing generality.

[0178] As mentioned above, a complete segmentation was performed on the first boundary, i=1. Therefore, we can determine the segmentation result and corresponding cut size for i=1. The segmentation result refers to the FPGA location assigned to each node on the boundary, and the cut size is the sum of the weights of the signal lines crossing the FPGA between nodes. Therefore, if we can prove that, given the segmentation result of the i-th boundary (i>1), a certain method can be used to obtain the segmentation result of the i+1th boundary, then we can also obtain the segmentation result for any value i. This illustrates the generality of the method.

[0179] like Figure 12 As shown in the figure, after knowing the allocation position of each node on the i-th boundary, for example, assuming there are 3 FPGAs, node 1 is allocated to FPGA1, nodes 2 and 3 are allocated to FPGA2, and node 4 is allocated to FPGA3, the resulting cut size is C1.

[0180] Continue with the following processing:

[0181] Step (1) Sort nodes 1, 2, 3, and 4 to determine which node to disassemble first. The sorting method is to first compare the resource sizes of the above nodes. The node with larger resources is ranked first. If the node resource sizes are equal, the node with more child nodes is ranked first. The nodes ranked first are disassembled first. The reason for this is that if the node with larger resources is disassembled, it will help expand the FPGA location selection range of other nodes, so that they do not sacrifice cut size due to resource limitations. Disassembling nodes with more child nodes will help disperse their resources, which is also beneficial to node allocation.

[0182] After the sorting is completed in step (2), the nodes in the front row are split. If node 2 is in the front row, then node 2 is removed from FPGA2 and all child nodes of node 2 are exposed. That is, nodes 6, 7, and 8 are the nodes to be allocated. At this time, the allocation positions of nodes 1, 3, and 4 remain unchanged. Note that nodes 6, 7, and 8 may have signal connections with each other and with external nodes 1, 3, and 4, so their position changes will directly cause changes in the cut size. For nodes 6, 7, and 8, each of them has three position options, namely FPGA1, 2, and 3. For example, if node 6 chooses FPGA1, the cut size caused by the signal line between nodes 1-6 will be eliminated. However, if node 7 chooses FPGA3, the cut size between nodes 6 and 7 will be increased. At the same time, during the allocation process, it is also necessary to consider whether the FPGA resources are exceeded. In other words, the resource capacity of an FPGA node is limited, and resource legitimacy checks must be performed before adding nodes.

[0183] Alternatively, a new array of length 3 can be created, with each element representing nodes 6, 7, and 8. The element size can be any integer in [1, 3], representing the selected FPGA location. A recursive backtracking method is used to find the optimal allocation solution for the above nodes. The array is initialized with values, each element is set to 0 (i.e., no location is selected), and location selection begins with the first element. Entering the backtracking function, if all elements in a have been selected and meet resource constraints, the allocation results in the array are calculated against the existing nodes in the network and the signal lines between the nodes in the array to obtain the cut size of the current result. If it is smaller than the recorded cut size, a and the corresponding cut size are recorded. Otherwise, a is discarded and the next round of attempts is performed. At this point, the element being selected is p. After having element p select all possible locations, the recursion is entered, and element p+1 is allowed to make another selection attempt until the recursion is complete. The following is an example of the recursive code (Hard Code) execution strategy:

[0184] Trace(int a[], int p) {

[0185] If every member in a>0{

[0186] Test resource constraint and evaluate a cut size, if smaller than minvalue in record, thensave a and update min value;

[0187] Return;

[0188] }

[0189] For(int i=1;i<=Num;i++) / / Num is the number of FPGAs

[0190] {

[0191] a[p]=i / / make choice

[0192] Trace(a, p+1)

[0193] a[p] = 0; / / undo choice

[0194] }

[0195] }.

[0196] After splitting node 2 and optimally allocating its child nodes in step (3), the other nodes are split and allocated in the same order as in step (1), and so on. Thus, the allocation result of the nodes at the layer (5, 6, 7, 8, 9, 10) can be obtained. Similarly, the splitting of the nodes at the layer (5, 6, 7, 8, 9, 10) can be continued downwards, and finally the segmentation result of the i+1 layer can be obtained.

[0197] Therefore, the reason why the above method is fast is that each step of the operation is to find the local optimal solution in a limited number of nodes. Compared with finding the global optimal segmentation in a large range of nodes, the difficulty is greatly reduced and the time is shorter.

[0198] In some implementations, the aggregation (ie, preliminary segmentation) process may be driven based on temporal analysis, thereby aggregating nodes with close temporal relationships into corresponding node clusters.

[0199] Perform timing analysis on the third hypergraph corresponding to the input user design. First, mark the timing properties of the nodes in the hypergraph and distinguish them into sequential elements and combinational elements. Elements that need to be driven by clock signals are called sequential elements, and elements that do not need to be driven by clock signals are combinational elements. The module type represented by the hypergraph node is compared with the standard device library to obtain the delay time of each node in the hypergraph, and an initial delay time is assigned to each hyperedge.

[0200] The path between adjacent sequential elements is called a timing path. Several combinational devices may exist on a timing path. Since each combinational device generates a certain amount of delay, it is desirable to evenly distribute the delay caused by these combinational devices between the aggregated nodes to ensure that the time delay required for each node to connect externally is as equal as possible. This inevitably results in excessive outbound connection times for both communicating aggregated nodes, and they are assigned to different verification chips (such as FPGAs). This leads to even worse delays due to crossing the interconnect lines between the FPGAs, thus affecting timing performance. Therefore, during aggregation, the summed delay of the combinational elements between two sequential elements is calculated. The combinational logic is then assigned to the sequential elements on either side for aggregation, with the summed delay being approximately 1 / 2 of the total delay.

[0201] In addition, after performing static timing analysis (STA) on the hypergraph, the setup slack and hold slack of each timing path will be obtained.

[0202] Setup time refers to the time margin between two adjacent sequential elements for a new data signal to travel from the driver element to the load element within a cycle. A negative time margin indicates that the new data is not yet ready when the sampling clock edge reaches the driver element, potentially causing data sampling errors and, consequently, logic design failure. A margin greater than or equal to 0 ensures correct sampling, and the larger the margin, the better. The greater the delay between two sequential elements, the smaller the setup time margin.

[0203] Hold time is the amount of time, within a clock cycle, that a signal being sampled remains constant while being sampled. A negative hold time margin indicates that the signal currently being sampled may be replaced by the signal prepared by a subsequent element for the next clock cycle, causing signal acquisition errors and, consequently, logic operation errors. A positive hold time margin ensures correct acquisition. The greater the delay between two sequential elements, the greater the hold time margin.

[0204] Therefore, for timing paths with smaller setup slack, the delay between the components at both ends should be as small as possible during segmentation. That is, the distance between the components should be as close as possible, so that they are clustered together and allocated to the same FPGA in the future. For timing paths with smaller hold slack, the delay between the components at both ends should be as large as possible during segmentation. That is, the distance between the components should be as far as possible, so that they are not clustered together and are preferably allocated to different FPGAs.

[0205] By modifying the weights of the edges in the hypergraph based on the setup time slack and the hold time slack, timing information is incorporated into the considerations of the original aggregation technology. Assuming that the original weight of the net on a timing path is Worg, and the setup slack and hold slack of this timing path are s and h respectively, its new weight can be defined as:

[0206]

[0207] C1 and C2 are configurable parameters used to balance the influence of setup time margin and hold time margin on the weight.

[0208] Through existing aggregation technology, the hypergraph can be further aggregated according to the weights based on the new weights, and the node clusters obtained by aggregation are more conducive to obtaining the global optimal solution.

[0209] In some implementations, the resource differences between aggregated nodes may also affect the segmentation process. If some of the resources of the aggregated nodes are too large, the mobility of the large-resource nodes will be limited because the resource capacity of a single verification chip (such as an FPGA) is limited. For example, when a node already placed in an FPGA has occupied a portion of the resources, the large-resource node will not be able to be relocated due to its large size. However, if the large-resource node is split into two relatively smaller nodes, the benefits of the relocation can be attempted and checked.

[0210] Therefore, in order to split the process and improve the flexibility of the process, during the aggregation process, the resource variance of all current aggregation nodes can be calculated in real time. When the resource variance caused by the aggregation of certain nodes exceeds a certain threshold, the aggregation will be suspended to avoid the situation where the aggregation node size is too large.

[0211] In the specific implementation, during the initial segmentation, the resource variance corresponding to all node clusters that are currently being aggregated is calculated, and when the resource variance caused by the aggregation of the target node cluster exceeds the preset threshold, the current aggregation of the target node cluster is suspended. Although this may increase the number of iterations, it will allow the aggregated nodes to merge at a slower speed, thereby avoiding the generation of aggregated nodes with too large resources that cannot be turned back, thereby improving the efficiency of the overall segmentation process.

[0212] Similarly, when adjusting each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, the resources occupied by the segmentation result can be calculated in real time, that is, the resources occupied by the target segmentation result formed by adjusting the non-origin node to the corresponding target origin node. When the resources occupied by the target segmentation result exceed the resources of the verification chip, the adjustment of the non-origin node to the corresponding target origin node is suspended to avoid the segmentation result being unable to be deployed on the verification chip.

[0213] Based on the same inventive concept, this specification also provides an automatic boundary selection and segmentation iterative processing system, an electronic device, and a computer storage medium corresponding to the aforementioned method embodiments.

[0214] like Figure 13 As shown, an automatic boundary selection and segmentation iterative processing system includes:

[0215] An acquisition module 1100 is configured to acquire leaf nodes and their hierarchical information recorded in a syntax tree file structure, and to create nodes at each level of the syntax tree layer by layer based on the hierarchical information of the leaf nodes, so as to construct a target syntax tree in memory.

[0216] A preliminary segmentation module 1101 is configured to perform an initial segmentation of the target syntax tree at any segmentation boundary to obtain a first hypergraph comprising a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship;

[0217] A selection module 1103 is configured to select a number of nodes from the number of node clusters in the first hypergraph as origin nodes, where the number of origin nodes corresponds to the number of verification chips in the verification system;

[0218] The adjustment module 1105 is used to traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

[0219] Optionally, selecting several origin nodes from the several node clusters includes:

[0220] Performing edge splitting processing on the first hypergraph, wherein the hyperedges in the first hypergraph are split into a plurality of common graphs connecting the driver nodes and the load nodes according to the number of load nodes, and the weights of the edges remain unchanged;

[0221] Add several virtual nodes to the edge according to the edge weight, and connect the virtual nodes to the two endpoints of the original edge in sequence to form a new graph, where the number of virtual nodes is the edge weight and the following relationship is satisfied: N = W-1, where N is the number of virtual nodes and W is the edge weight.

[0222] Marking corresponding distance values ​​for all nodes in the new graph;

[0223] Several nodes are selected as origin nodes according to the distance value.

[0224] Optionally, marking corresponding distance values ​​for all nodes in the new graph includes:

[0225] Traversing the new graph to select a target node with the largest degree value, wherein the degree value is used to represent the number of edges owned by the node;

[0226] After establishing the first queue and the second queue, the target node is added to the first queue, and all neighboring nodes of the target node are traversed to add all neighboring nodes of the target node to the second queue, and a first distance value is marked for all nodes in the first queue, and a second distance value is marked for all nodes in the second queue;

[0227] After marking, delete all nodes in the first queue, add all nodes in the neighboring nodes of each node in the second queue that have not been marked with distance values ​​to the first queue, mark all nodes in the first queue with a third distance value, and delete all nodes in the second queue, and add all nodes in the neighboring nodes of each node in the first queue that have not been marked with distance values ​​to the second queue, and repeat the above operations until all nodes are marked with corresponding distance values.

[0228] Optionally, the automatic boundary selection and segmentation iterative processing system also includes: a benefit module, which is used to determine the adjustment benefit corresponding to each non-origin node before adjusting each non-origin node to be adjusted to the verification chip where the corresponding target origin node is located, wherein the adjustment benefit is used to characterize the cost of excessive resource increase or decrease of the first verification chip and the second verification chip when the non-origin node is adjusted from the first verification chip to the second verification chip, the first verification chip is the verification chip where the node cluster to which the non-origin node belongs is located, and the second verification chip is the verification chip where the target origin node to which the non-origin node will be adjusted is located; then, the non-origin node to be adjusted is determined based on the adjustment benefit.

[0229] Optionally, the adjustment benefit corresponding to the non-origin node to be adjusted is: De_Cut + K1×ΣDei–K2×ΣExj;

[0230] Among them, De_Cut is the decrease in the split size of the second verification chip caused by the non-origin node adjusting from the first verification chip to the second verification chip, Dei is the percentage corresponding to the i-th over-limit resource reduced by the first verification chip, Exj is the percentage corresponding to the j-th over-limit resource added to the second verification chip, K1 and K2 are configurable parameters, and i and j are positive integers.

[0231] Optionally, determining the non-origin node to be adjusted according to the adjustment benefit includes:

[0232] Calculate the follow probability of all neighbor nodes of the non-origin node, where the follow probability of each neighbor node is the total number of endpoints of the hyperedges connected to the non-origin node divided by the total number of neighbor nodes;

[0233] Determine a set of nodes to be adjusted according to the following probability, wherein the set of nodes to be adjusted is a set consisting of the non-origin node to be adjusted and other non-origin nodes that follow the non-origin node to be adjusted to the verification chip where the target origin node is located;

[0234] Calculating the movement probability of the node set to be adjusted to each verification chip according to the adjustment benefits corresponding to the movement of the node set to be adjusted to each verification chip;

[0235] The non-origin node to be adjusted is determined according to the magnitude of the movement probability.

[0236] Optionally, when the current number of iterations does not exceed a preset optimal convergence iteration threshold number, the movement probability is:

[0237]

[0238] Where Pi→j is the movement probability of the node set to be adjusted from the i-th verification chip to the j-th verification chip, Cut_Cost_i_j is the cutting cost of the node set to be adjusted from the i-th verification chip to the j-th verification chip, is the adjustment gain corresponding to the node set to be adjusted moving from the i-th verification chip to the j-th verification chip, GAIN is the adjustment gain set, that is, GAIN={Cut_Gain_i_1, Cut_Gain_i_2, Cut_Gain_i_3, ..., Cut_Gain_i_n}, where Cut_Gain_i_i is preset to zero to indicate the adjustment gain when not moving;

[0239] When the current number of iterations exceeds the preset optimal convergence iteration limit, the movement probability is assigned a preset value to indicate that the node set to be adjusted can be adjusted to the verification chip corresponding to the maximum adjustment gain in the adjustment gain set.

[0240] Optionally, the initial segmentation includes:

[0241] First, a corresponding edge complement graph is constructed for the second hypergraph corresponding to the user design. Then, the target node in the edge complement graph is traversed and the corresponding overdegree of the target node is marked. All nodes are sorted in ascending order of overdegree value and stored in a cache queue. The cache queue is used as the residual graph of the edge complement graph. The following traversal operation is performed on the first node in the residual graph: the first node in the cache queue is added to the cache set from the cache queue, and the neighbor nodes with hyperedge connection relationships with the first node and the hyperedges connected to all the neighbor nodes are deleted from the cache queue to obtain a new residual graph. The above traversal operation is continued for the first node in the new residual graph until the residual graph is empty.

[0242] And, find all corresponding nodes in the cache set in the second hypergraph and cluster them into node clusters to obtain the first hypergraph, wherein the node clusters in the first hypergraph no longer expose internal details during the segmentation process, the weight of the node cluster is the sum of the weights of all internal nodes, and the connection relationship of the node cluster inherits the connection relationship of all internal nodes.

[0243] Optionally, creating each level node in the syntax tree layer by layer according to the level information of the leaf node includes:

[0244] For each leaf node, the following hierarchical processing is performed in memory according to the hierarchical information of the leaf node to obtain the hierarchical nodes that constitute the target syntax tree: determine whether the first-level node has been created. If not, create the first-level node and assign a unique node name to the first-level node. If it has been created, obtain the first-level node and then delete the first-level information, and perform next-level node processing until the last level node.

[0245] Optionally, the preliminary segmentation process includes:

[0246] Select n seed segmentation boundaries in the target syntax tree. The n segmentation boundaries are evenly distributed at more than 1 / 2 of the syntax tree layer height. Perform a segmentation on each segmentation boundary to obtain the segmentation particle size corresponding to each segmentation boundary. By traversing each segmentation boundary and its corresponding segmentation particle size, determine the starting segmentation boundary, where the starting segmentation boundary is the segmentation boundary with the smallest product of the corresponding segmentation particle size and the layer height among the n seed segmentation boundaries.

[0247] The optimal boundary search is performed downward from the initial segmentation boundary. As the segmentation boundary continues to descend, it stops when the segmentation particles cannot be made smaller. The segmentation boundary at this time is taken as the optimal segmentation boundary.

[0248] The preliminary segmentation process is completed according to the optimal segmentation boundary.

[0249] Optionally, the automatic boundary selection and segmentation iterative processing system further includes: a timing analysis module (not shown in the figure), which is used to perform timing analysis on the third hypergraph corresponding to the input user design before performing the initial segmentation, mark the timing attributes of the nodes in the hypergraph, and obtain the setup time margin and hold time margin corresponding to each timing path; then, update the weight values ​​of the edges in the hypergraph based on the setup time margin and the hold time margin, wherein the edge weight values ​​are updated according to the following relationship: , where Worg is the original weight of the edge, Wnew is the new weight of the edge, C1 and C2 are configurable parameters, and s and h are the setup time margin and hold time margin of the timing path, respectively.

[0250] Optionally, the automatic boundary selection and segmentation iterative processing system further includes: a first resource determination module (not shown in the figure), configured to calculate the resource variance corresponding to each of all node clusters currently being aggregated during the initial segmentation, and suspend the current aggregation of the target node cluster when the resource variance caused by the aggregation of the target node cluster exceeds a preset threshold;

[0251] And / or, the automatic boundary selection segmentation iterative processing system also includes: a second resource determination module (shown in the figure), which is used to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, calculate the resources occupied by the target segmentation result after adjusting the non-origin node to the corresponding target origin node to form the target segmentation result, and when the resources occupied by the target segmentation result exceed the resources of the verification chip, suspend the adjustment of the non-origin node to the corresponding target origin node.

[0252] like Figure 14 As shown, the present invention also provides an electronic device for automatic boundary selection, segmentation and iterative processing. The figure shows the structure of the electronic device 500 for implementing the aforementioned automatic boundary selection, segmentation and iterative processing scheme. The electronic device 500 here is only an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0253] like Figure 14 As shown, the electronic device 500 may include: at least one processor 510; and

[0254] A memory 520 communicatively connected to the at least one processor; wherein the memory storage 520 has instructions executable by the at least one processor 510, and the instructions are executed by the at least one processor 510 to enable the at least one processor 510 to execute: the automatic boundary selection and segmentation iterative processing method described in any embodiment of this specification.

[0255] It should be noted that the electronic device 500 may be in the form of a general-purpose computing device, for example, it may be a server device.

[0256] In implementation, the components of the electronic device 500 may include but are not limited to: the above-mentioned at least one processor 510, the above-mentioned at least one memory 520, and a bus 530 connecting different system components (including the memory 520 and the processor 510), wherein the bus 530 may include a data bus, an address bus, and a control bus.

[0257] In implementation, the memory 520 may include a volatile memory, such as a random access memory (RAM) 5201 and / or a cache memory 5202 , and may further include a read-only memory (ROM) 5203 .

[0258] The memory 520 may also include a program tool 5205 having a set (at least one) of program modules 5204, such program modules 5204 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0259] The processor 510 executes various functional applications and data processing by running computer programs stored in the memory 520 .

[0260] The electronic device 500 can also communicate with one or more external devices 540 (e.g., a keyboard, pointing device, etc.). This communication can be performed via an input / output (I / O) interface 550. Furthermore, the electronic device 500 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 560. The network adapter 560 communicates with other modules in the electronic device 500 via a bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device 500, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID (RAID) systems, tape drives, and data backup storage systems.

[0261] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0262] This specification provides a computer storage medium storing computer-executable instructions. When the computer-executable instructions are executed by a processor, the automatic boundary selection and segmentation iterative processing method described in any embodiment of this specification is performed.

[0263] It should be noted that computer storage media may include, but are not limited to, portable disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0264] In a possible implementation, the present invention may also provide a method for implementing data processing in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute several steps of the method described in any one of the aforementioned embodiments.

[0265] The program code for executing the present invention may be written in any combination of one or more programming languages, and the program code may be executed entirely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or entirely on the remote device.

[0266] In this specification, references to the same or similar parts between the various embodiments can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0267] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An automatic boundary selection segmentation iterative processing method, characterized in that: include: Obtain the leaf nodes and the level information of the leaf nodes recorded in the syntax tree file structure, and create each level node in the syntax tree layer by layer according to the level information of the leaf nodes to build the target syntax tree in memory; Performing an initial segmentation of the target syntax tree at an arbitrary segmentation boundary to obtain a first hypergraph including a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship; Selecting a number of nodes from the number of node clusters in the first hypergraph as origin nodes, where the number of origin nodes corresponds to the number of verification chips in the verification system; Traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

2. The automatic boundary selection and segmentation iterative processing method according to claim 1, characterized in that: Selecting a number of origin nodes from the plurality of node clusters includes: Performing edge splitting processing on the first hypergraph, wherein the hyperedges in the first hypergraph are split into a plurality of common graphs connecting the driver nodes and the load nodes according to the number of load nodes, and the weights of the edges remain unchanged; Add several virtual nodes to the edge according to the edge weight, and connect the virtual nodes to the two endpoints of the original edge in sequence to form a new graph, where the number of virtual nodes is the edge weight and the following relationship is satisfied: N = W-1, where N is the number of virtual nodes and W is the edge weight. Marking corresponding distance values ​​for all nodes in the new graph, including: selecting reference nodes for distance calculation according to a predetermined selection strategy; Several nodes are selected as origin nodes according to the distance value.

3. The automatic boundary selection and segmentation iterative processing method according to claim 2, characterized in that: The distance values ​​corresponding to all node labels in the new graph include: Traversing the new graph to select a target node with the largest degree value, wherein the degree value is used to represent the number of edges owned by the node; After establishing the first queue and the second queue, the target node is added to the first queue, and all neighboring nodes of the target node are traversed to add all neighboring nodes of the target node to the second queue, and a first distance value is marked for all nodes in the first queue, and a second distance value is marked for all nodes in the second queue; After marking, delete all nodes in the first queue, add all nodes in the neighboring nodes of each node in the second queue that have not been marked with distance values ​​to the first queue, mark all nodes in the first queue with a third distance value, and delete all nodes in the second queue, and add all nodes in the neighboring nodes of each node in the first queue that have not been marked with distance values ​​to the second queue, and repeat the above operations until all nodes are marked with corresponding distance values.

4. The automatic boundary selection and segmentation iterative processing method according to claim 1, characterized in that: Before adjusting each non-origin node to be adjusted to the verification chip where the corresponding target origin node is located, the automatic boundary selection and segmentation iterative processing method further includes: Determine an adjustment benefit corresponding to each non-origin node, where the adjustment benefit is used to represent the cost of excess resource increase or decrease of the first verification chip and the second verification chip when the non-origin node is adjusted from the first verification chip to the second verification chip, where the first verification chip is the verification chip of the node cluster to which the non-origin node belongs, and the second verification chip is the verification chip of the target origin node to which the non-origin node is to be adjusted; The non-origin node to be adjusted is determined according to the adjustment benefit.

5. The automatic boundary selection and segmentation iterative processing method according to claim 4, characterized in that: The adjustment benefit corresponding to the non-origin node to be adjusted is: De_Cut + K1×ΣDei–K2×ΣExj; Among them, De_Cut is the decrease in the split size of the second verification chip caused by the non-origin node adjusting from the first verification chip to the second verification chip, Dei is the percentage corresponding to the i-th over-limit resource reduced by the first verification chip, Exj is the percentage corresponding to the j-th over-limit resource added to the second verification chip, K1 and K2 are configurable parameters, and i and j are positive integers.

6. The automatic boundary selection and segmentation iterative processing method according to claim 4, characterized in that: The non-origin nodes to be adjusted according to the adjustment benefit include: Calculate the follow probability of all neighbor nodes of the non-origin node, where the follow probability of each neighbor node is the total number of endpoints of the hyperedges connected to the non-origin node divided by the total number of neighbor nodes; Determine a set of nodes to be adjusted according to the following probability, wherein the set of nodes to be adjusted is a set consisting of the non-origin node to be adjusted and other non-origin nodes that follow the non-origin node to be adjusted to the verification chip where the target origin node is located; Calculating the movement probability of the node set to be adjusted to each verification chip according to the adjustment benefits corresponding to the movement of the node set to be adjusted to each verification chip; The non-origin node to be adjusted is determined according to the magnitude of the movement probability.

7. The automatic boundary selection and segmentation iterative processing method according to claim 6, characterized in that: When the current number of iterations does not exceed the preset optimal convergence iteration limit, the movement probability is: Where Pi→j is the movement probability of the node set to be adjusted from the i-th verification chip to the j-th verification chip, Cut_Cost_i_j is the cutting cost of the node set to be adjusted from the i-th verification chip to the j-th verification chip, The adjustment gain corresponding to the movement of the node set to be adjusted from the i-th verification chip to the x-th verification chip is GAIN, which is the adjustment gain set, that is, GAIN = {Cut_Gain_i_1, Cut_Gain_i_2, Cut_Gain_i_3, ..., Cut_Gain_i_n}, where Cut_Gain_i_i is preset to zero to indicate the adjustment gain when no movement occurs; n is the total number of verification chips; When the current number of iterations exceeds the preset optimal convergence iteration limit, the movement probability is assigned a preset value to indicate that the node set to be adjusted can be adjusted to the verification chip corresponding to the maximum adjustment gain in the adjustment gain set.

8. The automatic boundary selection and segmentation iterative processing method according to claim 1, characterized in that: The initial segmentation includes: First, a corresponding edge complement graph is constructed for the second hypergraph corresponding to the user design, wherein the edge complement graph and the second hypergraph have the same node set, and the edges in the edge complement graph are the complement edges of the edges in the second hypergraph; then, the target node in the edge complement graph is traversed and the corresponding excess degree of the target node is marked, and all nodes are arranged in ascending order of excess value and stored in a cache queue, and the cache queue is used as the residual graph of the edge complement graph. The following traversal operation is performed on the first node in the residual graph: the first node in the cache queue is added from the cache queue to the cache set, and the neighbor nodes with hyperedge connection relationship with the first node and the hyperedges connected to all the neighbor nodes are deleted from the cache queue to obtain a new residual graph, and the above traversal operation is continued for the first node in the new residual graph until the residual graph is empty; And, find all corresponding nodes in the cache set in the second hypergraph and cluster them into node clusters to obtain the first hypergraph, wherein the node clusters in the first hypergraph no longer expose internal details during the segmentation process, the weight of the node cluster is the sum of the weights of all internal nodes, and the connection relationship of the node cluster inherits the connection relationship of all internal nodes.

9. The automatic boundary selection and segmentation iterative processing method according to claim 1, characterized in that: The various level nodes in the syntax tree are created layer by layer according to the level information of the leaf nodes, including: For each leaf node, the following hierarchical processing is performed in memory according to the hierarchical information of the leaf node to obtain the hierarchical nodes that constitute the target syntax tree: determine whether the first-level node has been created. If not, create the first-level node and assign a unique node name to the first-level node. If it has been created, obtain the first-level node and then delete the first-level information, and perform next-level node processing until the last level node.

10. The automatic boundary selection segmentation iterative processing method according to claim 1, characterized in that: The initial segmentation process includes: Select n seed segmentation boundaries in the target syntax tree. The n segmentation boundaries are evenly distributed at more than 1 / 2 of the syntax tree layer height. Perform a segmentation on each segmentation boundary to obtain the segmentation particle size corresponding to each segmentation boundary. By traversing each segmentation boundary and its corresponding segmentation particle size, determine the starting segmentation boundary, where the starting segmentation boundary is the segmentation boundary with the smallest product of the corresponding segmentation particle size and the layer height among the n seed segmentation boundaries. The optimal boundary search is performed downward from the initial segmentation boundary. As the segmentation boundary continues to descend, it stops when the segmentation particles cannot be made smaller. The segmentation boundary at this time is taken as the optimal segmentation boundary. The preliminary segmentation process is completed according to the optimal segmentation boundary.

11. The automatic boundary selection segmentation iterative processing method according to claim 1, characterized in that: Before performing the initial segmentation, the automatic boundary selection segmentation iterative processing method further includes: Perform timing analysis on the third hypergraph corresponding to the input user design, mark the timing attributes of the nodes in the hypergraph, and obtain the setup time redundancy and hold time redundancy corresponding to each timing path; The weight values ​​of the edges in the hypergraph are updated according to the setup time margin and the hold time margin, where the weight values ​​of the edges are updated according to the following relationship: , where Worg is the original weight of the edge, Wnew is the new weight of the edge, C1 and C2 are configurable parameters, and s and h are the setup time margin and hold time margin of the timing path, respectively.

12. The automatic boundary selection segmentation iterative processing method according to claim 1, characterized in that: During the initial segmentation, the automatic boundary selection segmentation iterative processing method further includes: calculating the resource variance corresponding to each of all node clusters currently being aggregated, and suspending the current aggregation of the target node cluster when the resource variance caused by the aggregation of the target node cluster exceeds a preset threshold; And / or, when adjusting each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, the automatic boundary selection segmentation iterative processing method also includes: calculating the resources occupied by the target segmentation result after adjusting the non-origin node to the corresponding target origin node to form the target segmentation result, and when the resources occupied by the target segmentation result exceed the resources of the verification chip, suspending the adjustment of the non-origin node to the corresponding target origin node.

13. An automatic boundary selection and segmentation iterative processing system, characterized in that: include: The acquisition module is used to obtain the leaf nodes and the hierarchical information of the leaf nodes recorded in the syntax tree file structure, and create the hierarchical nodes of each level in the syntax tree layer by layer according to the hierarchical information of the leaf nodes to construct the target syntax tree in the memory; A preliminary segmentation module, configured to perform an initial segmentation of the target syntax tree at any segmentation boundary to obtain a first hypergraph comprising a plurality of node clusters, wherein a node cluster is a cluster consisting of a plurality of nodes having a connection relationship; a selection module, configured to select a number of nodes from the number of node clusters in the first hypergraph as origin nodes, wherein the number of origin nodes corresponds to the number of verification chips in the verification system; An adjustment module is used to traverse each non-origin node in the first hypergraph to adjust each non-origin node to be adjusted to the corresponding target origin node to form a target segmentation result, wherein the target origin node is the origin node with the shortest distance to the non-origin node, and the target segmentation result is a segmentation result for deployment on a verification chip of a verification system for prototype verification.

14. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the automatic boundary selection and segmentation iterative processing method described in any one of claims 1-12.

15. A computer storage medium, characterized in that The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the automatic boundary selection and segmentation iterative processing method according to any one of claims 1 to 12 is executed.

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