Light emitting drive circuit

Abstract

A light emission driving circuit is used to provide a plurality of light emission driving signals to a pixel array. The light emission driving circuit includes a plurality of first shift circuits and a plurality of second shift circuits. The first shift circuits receive a first clock signal, and the first shift circuits provide a plurality of first light emission timing signals sequentially enabled according to the received first clock signal. The second shift circuits receive one of the first light emission timing signals, and receive a second clock signal and a third clock signal, wherein each second shift circuit provides one of the light emission driving signals according to the received first light emission timing signal, the second clock signal and the third clock signal.

Description

Technical Field

[0001] This invention relates to a driving circuit, and more particularly to a light-emitting driving circuit. Background Technology

[0002] In recent years, self-emissive display technology has become the mainstream display device due to its advantages such as low power consumption, thinner display panels, vibrant colors, and better contrast. Furthermore, it overcomes the problem of motion blur. Self-emissive display panels need to receive both the gate signals required for writing data and the light-emitting signals needed to illuminate pixels. In traditional gate-on-array (GOA) circuits, each stage of the gate driving circuit and the light-emitting driving circuit provides a single output signal. That is, the output gate signal and light-emitting signal are used to drive both the display panel and the next stage of circuitry. Therefore, the pulse widths of the gate signal and light-emitting signal are usually fixed and cannot be adjusted, thus limiting the control capability of the driving circuit. Summary of the Invention

[0003] The present invention provides a light-emitting driving circuit having a light-emitting driving signal with adjustable pulse width, thereby improving the control capability of the light-emitting driving circuit.

[0004] The light-emitting driving circuit of the present invention provides a plurality of light-emitting driving signals to a pixel array, and includes a plurality of first displacement circuits and a plurality of second displacement circuits. The first displacement circuits receive a first clock signal and provide a plurality of first light-emitting timing signals sequentially enabled according to the received first clock signal. The second displacement circuits receive one of the first light-emitting timing signals, and receive a second clock signal and a third clock signal, wherein each second displacement circuit provides one of the light-emitting driving signals according to the received first light-emitting timing signal, second clock signal, and third clock signal.

[0005] Based on the above, in the light-emitting driving circuit of this embodiment, since the operation timing of the light-emitting driving circuit is controlled by the timing shift circuit, and the driving shift circuit can only be used to provide the light-emitting driving signal for driving the pixel, the phases of the second clock signal and the third clock signal can be varied to adjust the output characteristics (e.g., pulse width) of the light-emitting driving signal, without affecting the operation of the light-emitting driving circuit. Therefore, the control capability of the light-emitting driving circuit over pixel light emission can be improved.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention.

[0008] Figure 2 This is a circuit diagram of a first displacement circuit and a second displacement circuit according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to another embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to another embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures: 100: Display device 110: Pixel Array 120: Gate drive circuit 130: Light-emitting driving circuit C1: First capacitor C2: Second capacitor C3: Third capacitor C4: Fourth capacitor C5: Fifth capacitor CK1: First clock signal CK2: Second clock signal CK3: Third clock signal CK4: Fourth clock signal CK5: Fifth clock signal CK6: Sixth clock signal EM_STV: Start signal EMDR, EMDR_1~EMDR_n: Light emission driving signals EMTI, EMTI_1~EMTI_n: Emission timing signals EMTIpre: Preamplifier timing signal Gate_1~Gate_n: Gate signals PWA, PWB, PWC: Pulse Width PX: Self-illuminating pixel SHA, SHA_1~SHA_n: Timing shift circuits SHB, SHB_1~SHB_n: Drive displacement circuit T1: First transistor T10: Tenth Transistor T11: Eleventh transistor T12: Twelfth Transistor T13: Thirteenth Transistor T14: Fourteenth Transistor T2: Second transistor T3: Third transistor T4: Fourth transistor T5: Fifth transistor T6: Sixth transistor T7: Seventh Transistor T8: Eighth transistor T9: Ninth Transistor VGH: Gate High Voltage VGL: Gate Low Voltage Detailed Implementation

[0013] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0014] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0015] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0016] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the display device 100 includes at least a pixel array 110, a gate driving circuit 120, and a light-emitting driving circuit 130. The pixel array 110 has a plurality of self-emissive pixels PX (i.e., pixels with light-emitting elements) arranged in an array. The gate driving circuit 120 is coupled to the pixel array 110 to provide a plurality of sequentially enabled gate signals Gate_1 to Gate_n, and the light-emitting driving circuit 130 is coupled to the pixel array 110 to provide a plurality of sequentially enabled light-emitting driving signals EMDR_1 to EMDR_n, where n is a positive integer. The pixel array 110, the gate driving circuit 120, and the light-emitting driving circuit 130 can be disposed on the same substrate to form a display panel, but this embodiment of the invention is not limited thereto.

[0017] In this embodiment, the light-emitting driving circuit 130 includes multiple timing shift circuits SHA_1~SHA_n and multiple driving shift circuits SHB_1~SHB_n, wherein the timing shift circuits SHA_1~SHA_n and the driving shift circuits SHB_1~SHB_n jointly receive a gate high voltage VGH (corresponding to a first gate level voltage) and a gate low voltage VGL (corresponding to a second gate level voltage). Odd-numbered timing shift circuits (such as SHA_1, SHA_3) (corresponding to the first shift circuit) jointly receive a first clock signal CK1, and even-numbered timing shift circuits (such as SHA_2, SHA_n) (corresponding to the third shift circuit) jointly receive a fourth clock signal CK4. Furthermore, odd-numbered driving shift circuits (such as SHB_1, SHB_3) (corresponding to the second shift circuit) jointly receive a second clock signal CK2 and a third clock signal CK3, and even-numbered driving shift circuits (such as SHB_2, SHB_n) (corresponding to the fourth shift circuit) jointly receive a fifth clock signal CK5 and a sixth clock signal CK6.

[0018] Odd-numbered timing shift circuits (such as SHA_1, SHA_3) provide light-emitting timing signals (such as EMTI_1, EMTI_3) (corresponding to the first light-emitting timing signal) based on the received first clock signal CK1, and even-numbered timing shift circuits (such as SHA_2, SHA_n) provide light-emitting timing signals (such as EMTI_2a, EMTI_na) (corresponding to the second light-emitting timing signal) based on the received fourth clock signal CK4. Furthermore, odd-numbered drive shift circuits (such as SHB_1, SHB_3) provide light-emitting drive signals (such as EMDR_1, EMDR_3) based on the received second clock signal CK2 and third clock signal CK3, and even-numbered drive shift circuits (such as SHB_2, SHB_n) provide light-emitting drive signals (such as EMDR_2, EMDR_n) based on the received fifth clock signal CK5 and sixth clock signal CK6.

[0019] In this embodiment, the emission timing signals EMTI_1 to EMTI_n are individually provided to the next-level timing shift circuit (such as SHA_2 to SHA_n) to drive the next-level timing shift circuit (such as SHA_2 to SHA_n). For example, emission timing signal EMTI_1 is provided to timing shift circuit SHA_2 to drive (or trigger) timing shift circuit SHA_2; emission timing signal EMTI_2 is provided to timing shift circuit SHA_3 to drive (or trigger) timing shift circuit SHA_3, and so on, which will not be elaborated here. Furthermore, the first timing shift circuit (such as SHA_1) can receive the start signal EM_STV.

[0020] Based on the above, since the operating timing of the light-emitting driving circuit 130 is controlled by the timing shift circuits SHA_1 to SHA_n, and the driving shift circuits SHB_1 to SHB_n can be used only to provide the light-emitting driving signals EMDR_1 to EMDR_n for driving the pixel PX, the phases of the second clock signal CK2, the third clock signal CK3, the fifth clock signal CK5, and the sixth clock signal CK6 can be varied to adjust the output characteristics (e.g., pulse width) of the light-emitting driving signals EMDR_1 to EMDR_n, without affecting the operation of the light-emitting driving circuit 130. Therefore, the control capability of the light-emitting driving circuit 130 over the light emission of the pixel PX can be improved.

[0021] Figure 2 This is a circuit diagram of a first displacement circuit and a second displacement circuit according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In this embodiment, the timing displacement circuits SHA_1 to SHA_n are illustrated by example using the timing displacement circuit SHA, and the driving displacement circuits SHB_1 to SHB_n are illustrated by example using the driving displacement circuit SHB. However, this embodiment of the invention is not limited thereto.

[0022] In this embodiment, the timing shift circuit SHA includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and a third capacitor C3, wherein the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0023] The first transistor T1 has a first terminal for receiving a start signal EM_STV or a pre-amplifier timing signal EMTIpre, a control terminal for receiving a first clock signal CK1 (or a fourth clock signal CK4), and a second terminal. The second transistor T2 has a first terminal, a control terminal for receiving the start signal EM_STV or the pre-amplifier timing signal EMTIpre, and a second terminal for receiving a gate high voltage VGH. A first capacitor C1 is coupled between the first clock signal CK1 (or the fourth clock signal CK4) and the first terminal of the second transistor T2. The third transistor T3 has a first terminal for receiving a gate low voltage VGL, a control terminal coupled to the first terminal of the second transistor T2, and a second terminal.

[0024] The fourth transistor T4 has a first terminal coupled to the second terminal of the third transistor T3, a control terminal coupled to the second terminal of the first transistor T1, and a second terminal receiving a high gate voltage VGH. The fifth transistor T5 has a first terminal coupled to the second terminal of the first transistor T1, a control terminal coupled to the second terminal of the third transistor T3, and a second terminal receiving a first gate level voltage VGH.

[0025] The sixth transistor T6 has a first terminal receiving a low gate voltage VGL, a control terminal coupled to the second terminal of the first transistor T1, and a second terminal providing the corresponding light emission timing signal EMTI. A second capacitor C2 is coupled between the control terminal and the second terminal of the sixth transistor T6. The seventh transistor T7 has a first terminal coupled to the second terminal of the sixth transistor T6, a control terminal coupled to the second terminal of the third transistor T3, and a second terminal receiving a high gate voltage VGH. A third capacitor C3 is coupled between the second terminal of the sixth transistor T6 and the high gate voltage VGH.

[0026] In this embodiment, the drive displacement circuit SHB includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fourth capacitor C4, and a fifth capacitor C5. The eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0027] The eighth transistor T8 has a first terminal for receiving the corresponding light emission timing signal EMTI, a control terminal for receiving the second clock signal CK2 (or the fifth clock signal CK5), and a second terminal. The ninth transistor T9 has a first terminal, a control terminal for receiving the corresponding light emission timing signal EMTI, and a second terminal for receiving the gate high voltage VGH. The fourth capacitor C4 is coupled between the third clock signal CK3 (or the sixth clock signal CK6) and the first terminal of the ninth transistor T9.

[0028] The tenth transistor T10 has a first terminal that receives a low gate voltage VGL, a control terminal coupled to the first terminal of the ninth transistor T9, and a second terminal. The eleventh transistor T11 has a first terminal coupled to the second terminal of the tenth transistor T10, a control terminal coupled to the second terminal of the eighth transistor T8, and a second terminal that receives a first gate level voltage VGH. The twelfth transistor T12 has a first terminal coupled to the second terminal of the eighth transistor T8, a control terminal coupled to the second terminal of the tenth transistor T10, and a second terminal that receives a high gate voltage VGH.

[0029] The thirteenth transistor T13 has a first terminal that receives a low gate voltage VGL, a control terminal coupled to the second terminal of the eighth transistor T8, and a second terminal that provides the corresponding light-emitting drive signal EMDR. The fifth capacitor C5 is coupled between the control terminal and the second terminal of the thirteenth transistor T13. The fourteenth transistor T14 has a first terminal coupled to the second terminal of the thirteenth transistor T13, a control terminal coupled to the second terminal of the tenth transistor T10, and a second terminal that receives a high gate voltage VGH.

[0030] Figure 3 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to an embodiment of the present invention. Please refer to... Figures 1 to 3 In this embodiment, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are used as examples for illustration. The first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are enabled in sequence (e.g., switching from a high voltage level to a low voltage level) and can have the same pulse width.

[0031] When the start signal EM_STV is enabled (e.g., switching from a high voltage level to a low voltage level), the second transistor T2 is turned on, causing the third transistor T3 to be turned off due to the influence (or control) of the high gate voltage VGH. Then, when the first clock signal CK1 switches from a high voltage level to a low voltage level, the first transistor T1 is turned on, and the fourth transistor T4 and the sixth transistor T6 are turned on due to the influence (or control) of the low voltage level of the start signal EM_STV. At this time, the fifth transistor T5 and the seventh transistor T7 are turned off due to the influence (or control) of the high gate voltage VGH, and the light emission timing signal EMTI switches from the high gate voltage VGH to the low gate voltage VGL (i.e., the timing shift circuit SHA provides the corresponding light emission timing signal EMTI).

[0032] Next, when the first clock signal CK1 switches from a low voltage level to a high voltage level, the first transistor T1 switches to the off state, but the fourth transistor T4 and the sixth transistor T6 remain on. The second transistor T2 is turned on by the enable start signal EM_STV, and the third transistor T3, the fifth transistor T5, and the seventh transistor T7 remain in the off state.

[0033] Next, when the start signal EM_STV is disabled (e.g., switched from a low voltage level to a high voltage level), the second transistor T2 is turned off, but the first transistor T1, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 remain off, while the fourth transistor T4 and the sixth transistor T6 remain on.

[0034] Next, when the first clock signal CK1 switches from a high voltage level to a low voltage level again, the first transistor T1 and the third transistor T3 are turned on, while the fourth transistor T4 and the sixth transistor T6 are turned off due to the high voltage level of the start signal EM_STV. At this time, the fifth transistor T5 and the seventh transistor T7 are turned on due to the low gate voltage VGL, and the light emission timing signal EMTI switches from the low gate voltage VGL to the high gate voltage VGH (that is, the timing shift circuit SHA stops providing the corresponding light emission timing signal EMTI). Therefore, the pulse width PWA (i.e., the length of the enable time) of the light emission timing signal EMTI is determined based on the period of the first clock signal CK1 (i.e., the time length between two adjacent falling edges).

[0035] When the light-emitting timing signal EMTI is enabled (e.g., switching from a high voltage level to a low voltage level), the ninth transistor T9 is turned on, causing the tenth transistor T10 to be turned off due to the influence (or control) of the gate high voltage VGH. Then, when the second clock signal CK2 switches from a high voltage level to a low voltage level, the eighth transistor T8 is turned on, and the eleventh transistor T11 and the thirteenth transistor T13 are turned on due to the influence (or control) of the low voltage level of the light-emitting timing signal EMTI. At this time, the twelfth transistor T12 and the fourteenth transistor T14 are turned off due to the influence (or control) of the gate high voltage VGH, and the light-emitting drive signal EMDR switches from the gate high voltage VGH to the gate low voltage VGL (i.e., the drive displacement circuit SHB provides the corresponding light-emitting drive signal EMDR).

[0036] Next, when the second clock signal CK2 switches from a low voltage level to a high voltage level, the eighth transistor T8 switches to the off state, but the eleventh transistor T11 and the thirteenth transistor T13 remain on. The ninth transistor T9 is turned on by the enable light emission timing signal EMTI, and the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 remain in the off state.

[0037] Next, when the light emission timing signal EMTI is disabled (e.g., switched from a low voltage level to a high voltage level), the ninth transistor T9 is turned off, but the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 remain off, while the eleventh transistor T11 and the thirteenth transistor T13 remain on.

[0038] Next, when the third clock signal CK3 switches from a high voltage level to a low voltage level, the tenth transistor T10 is turned on, causing the twelfth transistor T12 and the fourteenth transistor T14 to be turned on under the influence (or control) of the low gate voltage VGL, and the eleventh transistor T11 and the thirteenth transistor T13 to be turned off under the influence (or control) of the high gate voltage VGH, while the ninth transistor T9 remains off. Therefore, the light-emitting drive signal EMDR switches from the low gate voltage VGL to the high gate voltage VGH (i.e., the drive displacement circuit SHB stops providing the corresponding light-emitting timing signal EMTI). In this embodiment, the pulse width PWB (i.e., the length of the enable time) of the light-emitting drive signal EMDR is determined based on the time length between the falling edge of the second clock signal CK2 and the falling edge of the adjacent third clock signal CK3 (also determined based on the phase difference between the second clock signal CK2 and the third clock signal CK3).

[0039] Figure 4 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to another embodiment of the present invention. Please refer to... Figures 1 to 4 , Figure 4 and Figure 3 The difference lies in the position of the second clock signal CK2 and the third clock signal CK3 relative to the first clock signal CK1. For example... Figure 3 As described in the embodiment, when the second clock signal CK2 switches from a high voltage level to a low voltage level, the light emission driving signal EMDR switches from a gate high voltage VGH to a gate low voltage VGL.

[0040] However, when the adjacent third clock signal CK3 switches from a high voltage level to a low voltage level, the ninth transistor T9 is turned on by the enabled light-emitting timing signal EMTI, causing the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 to remain in the off state. Then, when the next third clock signal CK3 switches from a high voltage level to a low voltage level, the ninth transistor T9 is in the off state, so the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 are turned on to switch the light-emitting drive signal EMDR from a low gate voltage VGL to a high gate voltage VGH. In this embodiment, the pulse width PWC (i.e., the length of the enable time) of the light-emitting drive signal EMDR is determined based on the time length between the falling edge of the second clock signal CK2 and the falling edge of the next adjacent third clock signal CK3 (also determined based on the phase difference between the second clock signal CK2 and the third clock signal CK3 and the period of the third clock signal CK3).

[0041] Figure 5 This is a schematic diagram of the driving waveform of a light-emitting driving circuit according to another embodiment of the present invention. Please refer to... Figure 1 and Figure 5 In this embodiment, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are enabled sequentially, as are the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6, and the fourth clock signal CK4 is the inverse of the first clock signal CK1. However, the enabling of the second clock signal CK2 and the third clock signal CK3 is independent of the fourth clock signal CK4, and the enabling of the fifth clock signal CK5 and the sixth clock signal CK6 is independent of the first clock signal CK1.

[0042] In this embodiment, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6 may have the same pulse width.

[0043] In this embodiment, since the fourth clock signal CK4 and the first clock signal CK1 are inverses of each other, that is, the fourth clock signal CK4 and the first clock signal CK1 are related in timing, the light emission timing signals EMTI_1~EMTI_3 are still enabled in sequence. The pulse width (i.e., the length of the enabling time) of the odd-numbered light emission timing signals (such as EMTI_1, EMTI_3) is determined based on the period of the first clock signal CK1, and the pulse width (i.e., the length of the enabling time) of the even-numbered light emission timing signals (such as EMTI_2, EMTI_n) is determined based on the period of the fourth clock signal CK4.

[0044] The pulse width (i.e., the enable time) of odd-numbered LED driving signals (such as EMDR_1, EMDR_3) is determined based on the time length between the falling edge of the second clock signal CK2 and the falling edge of the adjacent (or next adjacent) third clock signal CK3 (also determined based on the phase difference between the second clock signal CK2 and the third clock signal CK3). The pulse width (i.e., the enable time) of even-numbered LED driving signals (such as EMDR_2, EMDR_n) is determined based on the time length between the falling edge of the fifth clock signal CK5 and the falling edge of the adjacent (or next adjacent) sixth clock signal CK6 (also determined based on the phase difference between the fifth clock signal CK5 and the sixth clock signal CK6).

[0045] In summary, the light-emitting driving circuit of this embodiment of the invention, since the operation timing of the light-emitting driving circuit is controlled by a timing shift circuit, and the driving shift circuit can be used only to provide the light-emitting driving signal for driving the pixel, the phases of the second clock signal and the third clock signal can be varied to adjust the output characteristics (e.g., pulse width) of the light-emitting driving signal, without affecting the operation of the light-emitting driving circuit. Therefore, the control capability of the light-emitting driving circuit over pixel light emission can be improved.

[0046] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A light-emitting driving circuit for providing a plurality of light-emitting driving signals to a pixel array, comprising: Multiple first displacement circuits receive a first clock signal, and the first displacement circuits provide multiple first light emission timing signals that are sequentially enabled according to the received first clock signal; as well as Multiple second displacement circuits receive one of the first light-emitting timing signals, and receive a second clock signal and a third clock signal, wherein each of the second displacement circuits provides one of the light-emitting drive signals according to the received first light-emitting timing signal, the second clock signal, and the third clock signal. The pulse width of each of the light-emitting driving signals is determined based on the phase difference between the second clock signal and the third clock signal.

2. The light-emitting driving circuit as claimed in claim 1, wherein the first clock signal, the second clock signal, and the third clock signal are enabled sequentially.

3. The light-emitting driving circuit as claimed in claim 1, wherein the first light-emitting timing signals are individually provided to the next-stage third displacement circuit to drive the next-stage third displacement circuit.

4. The light-emitting driving circuit as claimed in claim 1, wherein each of the first displacement circuits comprises: A first transistor has a first terminal for receiving a start signal or a first emission timing signal from a preceding stage, a control terminal for receiving the first clock signal, and a second terminal. A second transistor has a first terminal, a control terminal that receives the start signal or the first light emission timing signal of the preceding stage, and a second terminal that receives a first gate level voltage; A first capacitor is coupled between the first clock signal and the first terminal of the second transistor; A third transistor has a first terminal that receives a second gate level voltage, a control terminal coupled to the first terminal of the second transistor, and a second terminal; A fourth transistor has a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the second terminal of the first transistor, and a second terminal receiving the first gate level voltage; A fifth transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal coupled to the second terminal of the third transistor, and a second terminal receiving the first gate level voltage; A sixth transistor has a first terminal for receiving the second gate level voltage, a control terminal coupled to the second terminal of the first transistor, and a second terminal for providing a corresponding first light emission timing signal; A second capacitor is coupled between the control terminal of the sixth transistor and the second terminal of the sixth transistor; A seventh transistor has a first terminal coupled to the second terminal of the sixth transistor, a control terminal coupled to the second terminal of the third transistor, and a second terminal receiving the first gate level voltage; and A third capacitor is coupled between the second terminal of the sixth transistor and the first gate voltage level.

5. The light-emitting driving circuit as claimed in claim 1, wherein each of the second displacement circuits comprises: An eighth transistor has a first terminal for receiving a corresponding first light emission timing signal, a control terminal for receiving the second clock signal, and a second terminal; A ninth transistor has a first terminal, a control terminal that receives the corresponding first light emission timing signal, and a second terminal that receives a first gate level voltage; A fourth capacitor is coupled between the third clock signal and the first terminal of the ninth transistor; A tenth transistor has a first terminal that receives a second gate level voltage, a control terminal coupled to the first terminal of the ninth transistor, and a second terminal; An eleventh transistor has a first terminal coupled to the second terminal of the tenth transistor, a control terminal coupled to the second terminal of the eighth transistor, and a second terminal receiving the first gate level voltage. A twelfth transistor has a first terminal coupled to the second terminal of the eighth transistor, a control terminal coupled to the second terminal of the tenth transistor, and a second terminal receiving the first gate level voltage; A thirteenth transistor has a first terminal for receiving the second gate level voltage, a control terminal coupled to the second terminal of the eighth transistor, and a second terminal for providing a corresponding light-emitting drive signal; A fifth capacitor is coupled between the control terminal of the thirteenth transistor and the second terminal of the thirteenth transistor; and A fourteenth transistor has a first terminal coupled to the second terminal of the thirteenth transistor, a control terminal coupled to the second terminal of the tenth transistor, and a second terminal receiving the first gate level voltage.

6. The light-emitting driving circuit as described in claim 1, further comprising: Multiple third displacement circuits receive a fourth clock signal, and these third displacement circuits provide multiple second light emission timing signals that are sequentially enabled according to the received fourth clock signal; as well as Multiple fourth displacement circuits receive one of the second light emission timing signals, and receive a fifth clock signal and a sixth clock signal, wherein each of the fourth displacement circuits provides one of the light emission driving signals according to the received second light emission timing signal, the fifth clock signal and the sixth clock signal.

7. The light-emitting driving circuit of claim 6, wherein the pulse width of the light-emitting driving signal provided by each of the fourth displacement circuits is determined based on the phase difference between the fifth clock signal and the sixth clock signal.

8. The light-emitting driving circuit as claimed in claim 6, wherein the fourth clock signal is inverse of the first clock signal, and the fourth clock signal, the fifth clock signal, and the sixth clock signal are enabled sequentially.

Images