Packaging structures and their fabrication methods, semiconductor devices

Abstract

This disclosure provides a packaging structure and its fabrication method, as well as a semiconductor device. The packaging structure includes: an isolation layer with multiple vias, the vias exposing a portion of an interconnect layer, the interconnect layer being disposed on the surface of a semiconductor functional structure; N first pads; each first pad being composed of an interconnect layer exposed by a via; N being a positive integer greater than 1; N redistribution layers, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; a first insulating layer covering and exposing a portion of each redistribution layer; at least some of the exposed portions of the redistribution layers include second pads and third pads; the center point of each second pad has the same offset direction and offset distance relative to the center point of the corresponding first pad; the first pads and second pads are used for testing the semiconductor functional structure at different operating speeds, respectively, and the third pad is used to perform functional interactions corresponding to the content tested by the second pads.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a packaging structure and its manufacturing method, and semiconductor devices. Background Technology

[0002] With the rapid increase in the penetration rate of electronic devices and the booming development of the electronic device market, there is an increasing demand for electronic products to evolve towards miniaturization and thinning while possessing high performance, multifunctionality, high reliability, and convenience. This demand places higher requirements on semiconductor device packaging, demanding better, lighter, thinner packaging, higher packaging density, better electrical and thermal performance, higher reliability, and higher cost-effectiveness.

[0003] To ensure that the performance of semiconductor devices meets the corresponding requirements, ports for testing and performing functional interactions need to be fabricated on the package structure. Summary of the Invention

[0004] Based on this, in order to solve one or more of the related technical problems, this disclosure provides a packaging structure and its manufacturing method, as well as a semiconductor device.

[0005] According to one aspect of the embodiments of this disclosure, a packaging structure is provided, including:

[0006] An isolation layer having multiple vias covers the surface of an interconnect layer, the vias exposing portions of the interconnect layer, the interconnect layer being disposed on the surface of a semiconductor functional structure;

[0007] N first pads; each first pad is formed by an interconnect layer exposed by one of the vias; N is a positive integer greater than 1;

[0008] N rewiring layers, each rewiring layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads;

[0009] A first insulating layer covers and exposes a portion of each of the redistribution layers;

[0010] At least a portion of the redistribution layer is exposed, including a second pad and a third pad; wherein the center point of each second pad is offset from the center point of the corresponding first pad in both direction and distance; the first pad and the second pad are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad.

[0011] In the above scheme, N first pads are arranged side by side along the first direction at a position close to the first edge of the semiconductor functional structure;

[0012] At least a portion of the second pad and the corresponding third pad are arranged side by side along a second direction, which is perpendicular to the first direction.

[0013] In the above scheme, the orthographic projection of the center point of each second pad on the plane where the interconnect layer is located is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

[0014] In the above scheme, the shape of the redistribution layer in the orthographic projection of the plane where the interconnect layer is located includes a strip shape.

[0015] In the above scheme, a portion of the first pads are arranged side by side along the first direction at a position close to the first edge of the semiconductor functional structure; a portion of the second pads and the corresponding third pads are arranged side by side along the second direction, the second direction being perpendicular to the first direction;

[0016] The remaining portion of the first pad is arranged side by side along the second direction at a position close to the second edge of the semiconductor functional structure, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure; the remaining second pad and the third pad corresponding to the first pad are arranged side by side along the first direction.

[0017] In the above scheme, the orthographic projection of the center point of the second pad onto the plane where the interconnect layer is located is offset by a second distance in a third direction relative to the center point of the corresponding first pad, and the angle between the third direction and the first direction is 45° or 135°.

[0018] In the above scheme, the shape of each of the first pads includes an elongated strip, the shape of the orthographic projection of a portion of the redistribution layers onto the plane where the interconnect layer is located includes an L-shape, and the shape of the orthographic projection of another portion of the redistribution layers onto the plane where the interconnect layer is located includes a Z-shape.

[0019] In the above scheme, the second pad is located at one end of the redistribution layer closer to the first pad, and the third pad is located at one end of the redistribution layer farther from the first pad.

[0020] In the above scheme, the redistribution layer is in direct contact with the corresponding first pad;

[0021] Alternatively, the packaging structure may further include: a conductive pillar located between the redistribution layer and the corresponding first pad, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillar.

[0022] In the above scheme, the packaging structure includes the conductive pillar, the orthographic projection of the conductive pillar on the plane of the interconnect layer overlaps with the first pad, and the orthographic projection of the conductive pillar on the plane of the interconnect layer does not overlap with the orthographic projections of the second pad and the third pad on the plane of the interconnect layer.

[0023] In the above scheme, the redistribution layer is in direct contact with the corresponding first pad, and the packaging structure further includes:

[0024] A second insulating layer is located within the groove formed by each of the redistribution layers; the hardness of the material of the second insulating layer is less than the hardness of the material of the redistribution layer.

[0025] According to another aspect of the present disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in any one of the above embodiments of the present disclosure.

[0026] In the above scheme, the semiconductor device further includes:

[0027] substrate;

[0028] Multiple stacked dies; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure;

[0029] Each die is electrically connected to the substrate via a lead on the third pad in the package structure.

[0030] According to another aspect of the present disclosure, a method for manufacturing an encapsulation structure is provided, comprising:

[0031] A semiconductor functional structure is provided, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure;

[0032] An isolation layer with multiple vias is formed, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1;

[0033] After completing the first type of test, N rewiring layers are formed on the N first pads and the isolation layer, each rewiring layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads.

[0034] A first insulating layer is formed to cover and expose a portion of the redistribution layer, the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad is offset in both direction and distance relative to the center point of the corresponding first pad; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

[0035] In various embodiments of this disclosure, N first pads are provided in the top metal layer for testing the semiconductor functional structure at a first operating speed. After the test at the first operating speed is completed, second pads corresponding one-to-one with the first pads are provided in the redistribution layer on the first pads for testing the semiconductor functional structure at a second operating speed. The center point of each second pad is set to be offset by the same direction and distance relative to the center point of the corresponding first pad, ensuring that the N first pads and N second pads maintain identical relative positions. Thus, the two different operating speed tests can be achieved using the same set of probe cards, saving testing costs and time compared to using two separate sets of probe cards, thereby reducing production cycle and manufacturing costs. Attached Figure Description

[0036] Figure 1 This is a cross-sectional schematic diagram of a packaging structure provided in an embodiment of this disclosure;

[0037] Figure 2a This is a cross-sectional schematic diagram of another packaging structure provided in an embodiment of this disclosure;

[0038] Figure 2b This is a cross-sectional schematic diagram of a packaging structure with conductive pillars provided in an embodiment of this disclosure;

[0039] Figure 3a This is a schematic diagram showing the relative positions of a single row of first pads and a single row of second pads provided in an embodiment of this disclosure;

[0040] Figure 3b for Figure 3a Enlarged view of the central area;

[0041] Figures 4a-4c This is a schematic diagram showing the relative positions of the first T-shaped pad and the second T-shaped pad provided in the embodiments of this disclosure;

[0042] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a packaging structure according to an embodiment of this disclosure;

[0043] Figures 6a-6d This is a schematic diagram illustrating the manufacturing process of a packaging structure provided in an embodiment of this disclosure.

[0044] Explanation of reference numerals in the attached figures

[0045] 101-Top metal layer; 102-First type pad; 103-Redistribution layer; 104-Second type pad; 105-Third type pad; 200-Semiconductor functional structure; 201-Semiconductor functional layer; 202-Interconnect layer; 203-Isolation layer; 204-Via; 205-First pad; 206-Redistribution layer; 207-Conductive pillar; 208-First insulating layer; 209-Groove; 210-Second insulating layer; 211-Second pad; 212-Third pad; 600-Semiconductor functional structure; 601-Semiconductor functional layer; 602-Interconnect layer; 603-Isolation layer; 604-Via; 605-First pad; 606-Redistribution layer; 608-First insulating layer; 609-Groove; 610-Second insulating layer; 611-Second pad; 612-Third pad.

[0046] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0047] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0048] The embodiments of this disclosure are described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of this disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this disclosure.

[0049] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0050] In this embodiment of the disclosure, the term "A and B connected" includes the case where A and B are in direct contact, or the case where A and B are in indirect contact through an intermediate conductive structure.

[0051] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] In the embodiments of this disclosure, the term "layer" refers to a portion of material including a region of thickness. A layer may extend onto the lower or upper surface of a structure, and its area may be less than or equal to the area of ​​the extending surface. It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0053] The semiconductor functional structure disclosed herein is a part of the process that will be used in subsequent manufacturing processes to form the final semiconductor device, and is a core component for realizing the main functions of the semiconductor device. Here, the final semiconductor device may include, but is not limited to, memory.

[0054] In the design of packaging structures for semiconductor devices such as Dynamic Random Access Memory (DRAM), pads (also known as solder pads) can be set in two ways: one is by opening windows in the top metal layer; the other is by opening windows in the redistribution layer (RDL).

[0055] The aforementioned top-layer metal windowing refers to forming a passivation layer or insulating layer on the top-layer metal layer of the semiconductor functional structure to protect it from damage. Then, a window area is formed on the passivation layer or insulating layer to expose a portion of the top-layer metal layer, forming a pad. Probe pin piercing tests can be performed on this pad to test the electrical performance of the semiconductor functional structure; bonding wires can also be led out on this pad to electrically expose the semiconductor functional structure.

[0056] The redistribution layer windowing refers to forming a redistribution layer on the top metal layer of the semiconductor functional structure, forming a passivation layer or insulating layer on the redistribution layer, and then forming a window area on the passivation layer or insulating layer to expose part of the redistribution layer, forming two pads arranged side by side. One of these pads is used for probe pin insertion testing, and the other is used for the lead-out of bonding wires on the pad. Here, the redistribution layer in the semiconductor device can adjust the position of the pads and also enhance the power supply network.

[0057] Understandably, the top metal layer is relatively thin and has a pad structure underneath, allowing for probe jacking testing on the same windowed metal area before wire bonding encapsulation at the packaging plant, without affecting the yield of wire bonding. The redistribution layer is generally also made of metal, but it is thicker than the top metal layer. Probe jacking leaves deeper and rougher pin marks, which affect the yield of wire bonding. Therefore, the pads used for testing and those used for wire bonding in the redistribution layer need to be separate. Regardless of the windowing method used in the packaging structure, it does not significantly affect the function of the semiconductor device. Windowing in the redistribution layer improves performance but increases production cycle time and cost.

[0058] In related technologies, one of the two windowing methods mentioned above is generally chosen to design the packaging structure based on the actual needs of the semiconductor device. However, in practical applications, the needs in the semiconductor device manufacturing process are not singular; multiple needs often exist. Several examples of multiple needs are given below:

[0059] For example, before the mass production of semiconductor devices (or "products"), there is a lengthy functional debugging process. During this debugging process, testing is conducted at a low operating speed of the semiconductor functional structure. At this time, only the top-layer metal windowing method is needed to complete the packaging and testing of the semiconductor functional structure. However, after the product's manufacturing process matures, when it is necessary to test the state of the semiconductor functional structure under high-speed operation, a redistribution layer windowing method is required for packaging and testing.

[0060] For example, when semiconductor functional structures have different functional requirements, the same semiconductor functional structure can be divided into standard-level testing and high-level testing according to different requirements. Different testing levels have different requirements for the windowing method of the semiconductor functional structure. When performing standard-level testing on semiconductor functional structures, the top metal windowing method can be used for packaging and testing, and the effect of the redistribution layer is not obvious. When performing high-level testing on semiconductor functional structures, the redistribution layer windowing method needs to be used for packaging and testing to improve product performance.

[0061] Based on this, the present disclosure provides a packaging structure, referencing Figure 1The packaging structure includes a top-layer metal windowing method and a redistribution layer windowing method. In the top-layer metal windowing method, a first type of pad 102 is provided in the top-layer metal layer 101. This first type of pad 102 can be used for low-speed testing and for bonding wire routing. In the redistribution layer windowing method, two types of pads (a second type of pad 104 and a third type of pad 105) are provided in the redistribution layer 103. The second type of pad 104 is used for high-speed testing, and the third type of pad 105 is used for bonding wire routing. Thus, in this embodiment of the present disclosure, a packaging structure compatible with two types of testing (low-speed testing and high-speed testing) meets the needs of different types of testing of semiconductor functional structures at different process stages, improving testing flexibility and reducing production cycle and manufacturing costs.

[0062] Here, when performing low-speed testing using the first type of pad 102, the test probe card needs to simultaneously hit the center point of all the first type of pads 102; when performing high-speed testing using the second type of pad 104, the test probe card needs to simultaneously hit the center point of all the second type of pads 104. However, from Figure 1 It can be seen that the first type of pad 102 and the second type of pad 104 are located in different layers of the packaging structure, and the relative positions of each first type of pad 102 and each second type of pad 104 in different layers are different. Thus, in order to meet the requirements of low-speed testing and high-speed testing, it is necessary to manufacture two sets of test probe cards, which will greatly increase the testing cost and testing time.

[0063] Based on this, this disclosure provides a packaging structure, a method for fabricating the same, and a semiconductor device. The packaging structure includes: an isolation layer with multiple vias covering the surface of an interconnect layer, the vias exposing portions of the interconnect layer, and the interconnect layer disposed on the surface of a semiconductor functional structure; N first pads; each first pad consisting of an interconnect layer exposed by one of the vias; N being a positive integer greater than 1; N redistribution layers, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; a first insulating layer covering and exposing a portion of each redistribution layer; at least a portion of the redistribution layers being exposed includes second and third pads; wherein the center point of each second pad has the same offset direction and offset distance relative to the center point of the corresponding first pad; the first and second pads are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad.

[0064] Here, for reference Figure 2a The packaging structure includes:

[0065] substrate ( Figure 2a(Not shown in the image), the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI).

[0066] A semiconductor functional structure 200 is located on a substrate. Specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnect layer 202 located on the surface of the semiconductor functional layer 201. Various functional structures can be disposed in the semiconductor functional layer 201 according to actual needs. Correspondingly, the interconnect layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to operate the functional structures. In some embodiments, the interconnect layer 202 includes a top metal layer, which not only extracts the electrical signals from the functional structures but also supports the semiconductor functional structure 200.

[0067] It should be noted that any signals connected by the redistribution layer formed in subsequent processes are connected to the interconnect layer 202, which ensures that the function of the semiconductor functional structure 20 is complete even without the redistribution layer. Figure 2a The image shown is a cross-sectional view of a section of interconnect layer 202 after a portion has been removed. In practical applications, the parts of the interconnect layer are not cut off, but interconnected. That is, the parts of the interconnect layer may be continuous on other sections.

[0068] An isolation layer 203 covers the surface of the interconnect layer 202 and is used to isolate the interconnect layer 202 and the subsequently formed redistribution layer 205 in a partial area. A via 204 is provided in the isolation layer 203, exposing a portion of the interconnect layer 202. The via 204 can be cylindrical, inverted trapezoidal, or any suitable shape. The constituent materials of the isolation layer 203 include, but are not limited to, tetraethyl orthosilicate (TEOS).

[0069] A first pad 205 is formed by an interconnect layer 202 exposed by a via 204; an isolation layer 203 may contain multiple vias 204, thereby forming multiple first pads 205 exposed by the vias 204. Here, the first pads 205 can be used for performing a first type of test; on the other hand, they can also be used to perform functional interactions corresponding to the content of the first type of test. For example, the first type of test can be understood as performing some tests on the semiconductor functional structure at a low operating speed. It should be noted that in memory, the operating speed refers to the read and write speed of the memory. The performance of functional interactions corresponding to the content of the first type of test can be understood as leading bonding wires on the first pads. That is, when performing the first type of test, the first pads 205 can be used to contact a probe card, and multiple probes in the probe card correspond one-to-one with N first pads to realize the electrical connection between the interconnect layer and other test systems.

[0070] refer to Figure 2a A redistribution layer 206 is located on the surface of the isolation layer 203 and within the via 204. Here, the redistribution layer 206 covers the isolation layer 203; and the redistribution layer 206 is in direct contact with the corresponding first pad 205. In other words, each first pad 205 can serve as a region where a corresponding redistribution layer 206 is electrically connected to the interconnect layer 202.

[0071] The redistribution layer 206 is composed of materials including but not limited to metals; preferably, the material of the redistribution layer 206 is aluminum (Al).

[0072] The redistribution layer 206 and the first pad 205 can be in direct contact (see reference). Figure 2a Indirect contact is also possible, i.e., a conductive material layer is disposed between the redistribution layer 206 and the first pad 205 (see reference). Figure 2b ).

[0073] In some embodiments, the redistribution layer is in direct contact with the corresponding first pad; or, the encapsulation structure further includes a conductive post 207 located between the redistribution layer 206 and the corresponding first pad 205, wherein the redistribution layer 206 is electrically connected to the interconnect layer 202 through the conductive post 207.

[0074] The conductive pillar 207 may be made of the same material as or different from the redistribution layer 206. For example, the conductive pillar 207 may be made of aluminum (Al), copper (Cu), etc. It should be noted that the height of the conductive pillar 207 may be less than or equal to the depth of the via 204. Figure 2b The diagram shows the case where the height of the conductive post 207 is equal to the depth of the via 204.

[0075] It should be noted that, Figure 2b The image shown is a cross-sectional view of the conductive post 207 after filling the via 204. In practical applications, the conductive post 207 can also be set in other shapes or in other positions. In other words, the shape of the conductive post 207 and the shape of the via 204 are complementary, that is, the conductive post 207 completely fills the via 204.

[0076] Here, the orthographic projection of the conductive post 207 onto the plane of the interconnect layer 202 overlaps with the first pad 205.

[0077] In other words, the conductive pillar 207 is located directly above the first pad 205, which facilitates the transmission of electrical signals between the semiconductor functional structure 200 and the redistribution layer 206.

[0078] In the above embodiments, the number of conductive posts 207 in the same via 204 may include one or more, and adjacent conductive posts 207 are isolated by insulating material; correspondingly, each conductive post 207 corresponds to a first pad 205, that is, when the number of conductive posts 207 is multiple, the bottom of the same via 204 has multiple first pads 205.

[0079] It is understood that when there are multiple conductive posts 207, all of them are connected to the redistribution layer 206 and the interconnect layer 202, thereby increasing the reliability of the electrical connection between the redistribution layer 206 and the interconnect layer 202. In other words, in a package structure with multiple conductive posts 207, if one conductive post fails to electrically connect the redistribution layer 206 and the interconnect layer 202, the remaining conductive posts can still connect the redistribution layer and the interconnect layer, thus improving the reliability of the electrical connection between the redistribution layer, the conductive posts, and the interconnect layer.

[0080] It is understandable that by setting multiple first pads 205 while keeping the bottom area of ​​the via constant, it is beneficial to reduce the total area of ​​all first pads 205 at the bottom of the same via 204, thereby reducing the parasitic capacitance between the first pads 205 and the surrounding conductive material, which is beneficial to further optimize signal transmission performance.

[0081] It is understandable that directly setting the redistribution layer 206 in the via 204, that is, the redistribution layer 206 directly contacts the first pad 205, or forming only one conductive pillar 207 in the via 204, can reduce the process flow of forming the conductive pillar 207, thereby improving process efficiency.

[0082] refer to Figure 2a The first insulating layer 208 is located on the redistribution layer 206.

[0083] The first insulating layer 208 covers the surface of the redistribution layer 206, serving two purposes: firstly, to isolate the redistribution layer 206 from electrical connections with other conductive materials, and secondly, to protect the redistribution layer 206 from damage. The material of the first insulating layer 208 includes, but is not limited to, polyimide (PI).

[0084] It should be noted that the thickness of the redistribution layer 206 on the exposed portion of the interconnect layer 202 can be the same as the thickness of the redistribution layer 206 on the surface of the isolation layer 203. In some embodiments, when the diameter of the via 204 is greater than twice the thickness of the redistribution layer 206, the redistribution layer 206 covers the sidewalls and bottom of the via 204, and the redistribution layer 206 forms a groove 209.

[0085] In some embodiments, reference Figure 2a The redistribution layer is in direct contact with the corresponding first pad. The encapsulation structure further includes a second insulating layer 210 located within the groove 209 formed by each redistribution layer. The hardness of the material of the second insulating layer 210 is less than that of the material of the redistribution layer 206. In this way, on the one hand, the stress of the encapsulation structure can be reduced and the reliability of the encapsulation structure can be increased; on the other hand, compared with using the redistribution layer 206 to fill the groove 208, using the material of the second insulating layer 210 to fill the groove 208 can avoid generating more parasitic capacitance.

[0086] In some embodiments, the second insulating layer 210 may be made of the same material as the first insulating layer 208, or the hardness of the material of the second insulating layer 210 may be less than that of the material of the first insulating layer 208, thereby further reducing structural stress. For example, the constituent materials of the second insulating layer 210 include, but are not limited to, polyimide (PI). In some embodiments, the second insulating layer 210 and the first insulating layer 208 may also be an integral structure.

[0087] refer to Figure 2a A portion of the first insulating layer 208 is removed, such that at least a portion of the redistribution layers 206 of the N redistribution layers 206 are exposed, including the second pad 211 and the third pad 212.

[0088] Here, each of the N redistribution layers 206 has a second pad 211 and a third pad 212; in other words, the N second pads 211 and N third pads 212 correspond one-to-one. The second pad 211 is used for performing a second type of test, and the third pad 212 is used to perform functional interactions corresponding to the content of the second type of test. The second type of test can be understood as some tests performed on the semiconductor functional structure at high operating speeds. The performance of functional interactions corresponding to the content of the second type of test can be understood as leading out bonding wires on the third pad.

[0089] In other words, the redistribution layer 206 is used to redistribute the wire paths laid out based on the first pad 205; here, the redistributed wire paths are more conducive to the electrical testing and functional interaction of semiconductor devices.

[0090] It should be noted that the second pad 211 and the third pad 212 can be continuously arranged, that is, there is no partition between the second pad 211 and the third pad 212; or they can be spaced apart, that is, there is a partition between the second pad 211 and the third pad 212.

[0091] Here, when the second pad 211 and the third pad 212 are continuously arranged, damage to the probe card caused by the partition wall can be avoided during the test process if the probe is misaligned, thereby extending the service life of the probe card; at the same time, the generation of impurities is reduced, thereby improving the test efficiency; in addition, the damage to the partition wall caused by the probe card is reduced, thus improving the overall reliability of the packaging structure.

[0092] When a partition wall is provided between the second pad 211 and the third pad 212, the machine's recognition accuracy for each pad can be improved during the test.

[0093] In the following embodiments, the example of a partition wall being provided between the second pad 211 and the third pad 212 is used for illustration. However, it should be understood that the following description of the partition wall is only for illustrating the present invention and is not intended to limit the scope of the present invention.

[0094] In some embodiments, the packaging structure further includes a conductive pillar, wherein the orthographic projection of the conductive pillar onto the plane of the interconnect layer does not overlap with the orthographic projections of the second and third pads onto the plane of the interconnect layer. This increases the distance between the conductive pillar and the second or third pad, thereby reducing stress damage to the second or third pad caused by the conductive pillar.

[0095] In some embodiments, the second pad 211 is located at one end of the redistribution layer 206 near the first pad 205, and the third pad 212 is located at one end of the redistribution layer 206 away from the first pad 205.

[0096] Here, when performing the first and second type tests using the same set of probes, setting the position of the second pad relatively close to the corresponding first pad can reduce the movement distance of the same set of probe cards, thereby improving testing efficiency and reducing the probability of errors.

[0097] To ensure that each probe in the probe card corresponds to a second pad during the second type of test, in this embodiment, the center point of each second pad 211 is offset by the same direction and equal distance relative to the center point of the corresponding first pad 205. This ensures that the N first pads and N second pads maintain identical relative positions. Consequently, after performing the first type of test, the same probe card can be moved a certain distance in a certain direction from the center point of the first pad 205 to align with the center points of all the second pads 211. In other words, the probe card can directly perform the second type of test on all the second pads requiring testing without needing to replace it with a new probe card. The following two examples illustrate the specific arrangement of the first and second pad positions.

[0098] In some embodiments, N first pads 205 are arranged side by side along a first direction at a position close to the first edge of the semiconductor functional structure; at least some of the second pads and the corresponding third pads are arranged side by side along a second direction, the second direction being perpendicular to the first direction.

[0099] It should be noted that in this application example, when there are not many points to be tested, the number of corresponding first pads is not too many. In this case, all the first pads can be arranged side by side near the edge of the semiconductor, that is, all the first pads are arranged in a single row. Correspondingly, the redistribution layer is also arranged near the edge of the semiconductor, which can reduce the length of subsequent bonding wires.

[0100] Herein and below, the first direction is parallel to the surface of the semiconductor functional structure, and the second direction is parallel to the semiconductor functional structure and perpendicular to the first direction. In some embodiments, the first direction may be parallel to the X-axis direction, and the second direction may be parallel to the Y-axis direction. In other embodiments, the first direction may also be parallel to the Y-axis direction, and the second direction may be parallel to the X-axis direction. The following and accompanying drawings will only illustrate the case where the first direction is parallel to the X-axis direction and the second direction is parallel to the Y-axis direction.

[0101] Here, the first edge can refer to any edge of a semiconductor functional structure.

[0102] For example, refer to Figure 3a , Figure 3a To the left of the middle arrow, three first pads 205 are arranged side by side along the X-axis near the first edge of the semiconductor functional structure; Figure 3a The right side of the middle arrow shows three redistribution layers arranged side by side along the X-axis near the first edge of the semiconductor functional structure. Meanwhile, the second pad and the corresponding third pad in the redistribution layer are arranged side by side along the Y-axis. Figure 3aThe dashed line in the diagram shows the straight line where the center points of the three first pads 205 are located.

[0103] In some embodiments, the first pad 205, the second pad 211, and the third pad 212 are all elongated strips. The width of each first pad 205 along the first direction is the same as the width of each second pad 211 and the third pad 212 along the first direction, and the length of each first pad 205 along the second direction is different from the length of each second pad 211 and the third pad 212 along the second direction. In some specific examples, the dimensions of the first pad 205 are 45μm × 60μm, and the dimensions of the second pad 211 and the third pad 212 are both 45μm × 55μm.

[0104] In some embodiments, the orthographic projection of the center point of each of the second pads onto the plane of the interconnect layer is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

[0105] Here, the first distance is the distance the probe card moves from the center point of the first pad to the center point of the second pad after completing the first type of test.

[0106] For example, refer to Figure 3a The center point O2 of each second pad is offset by a first distance H1 relative to the center point O1 of the corresponding first pad along the Y-axis.

[0107] In some embodiments, the shape of the orthographic projection of each redistribution layer 206 onto the plane where the interconnect layer is located includes a strip shape.

[0108] For example, refer to Figure 3b The shape of each redistribution layer 206, as projected onto the plane containing the interconnect layer, includes a strip shape. Additionally, from... Figure 3b It can be seen that when the packaging structure includes the conductive pillar, the orthographic projection of the conductive pillar on the plane where the interconnect layer is located overlaps with the first pad, and the orthographic projection of the conductive pillar on the plane where the interconnect layer is located does not overlap with the orthographic projections of the second pad and the third pad on the plane where the interconnect layer is located.

[0109] In other embodiments, a portion of the first pad is disposed side-by-side along a first direction near a first edge of the semiconductor functional structure; a portion of the second pad and the corresponding third pad are disposed side-by-side along a second direction, the second direction being perpendicular to the first direction.

[0110] The remaining portion of the first pad is arranged side by side along the second direction at a position close to the second edge of the semiconductor functional structure, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure; the remaining second pad and the third pad corresponding to the first pad are arranged side by side along the first direction.

[0111] It should be noted that in this application example, when there are many points to be tested, the number of first pads is relatively large. In this case, a single row arrangement may not be able to arrange all the first pads properly. The first pads can be arranged in a similar T-shape.

[0112] Here, the first edge 20a and the second edge 20b are two opposite edges of the semiconductor functional structure.

[0113] Here, the N first pads are divided into two parts, namely a first part and a second part; wherein, the first part includes M1 first pads; the M1 first pads in the first part are arranged side by side along a first direction near the first edge 20a of the semiconductor functional structure; the second part includes M2 first pads; the M2 first pads in the second part are arranged side by side along a second direction near the second edge of the semiconductor functional structure. Here, M1 + M2 = N.

[0114] Accordingly, the N second pads are divided into two parts, namely a third part and a fourth part; wherein the third part includes M1 second pads; the fourth part includes M2 second pads; the M1 second pads in the third part are arranged side by side along a first direction near the first edge of the semiconductor functional structure; the M2 second pads in the fourth part are arranged side by side along a second direction near the second edge of the semiconductor functional structure. Similarly, the N third pads are divided into two parts, namely a fifth part and a sixth part; wherein the fifth part includes M1 third pads; the sixth part includes M2 third pads; the M1 third pads and M1 second pads in the fifth part are arranged side by side along a first direction near the first edge of the semiconductor functional structure; the M2 third pads and M2 second pads in the sixth part are arranged side by side along a first direction near the second edge of the semiconductor functional structure.

[0115] For example, refer to Figure 4a , Figure 4a The left side of the middle arrow shows three first pads 205 arranged side by side along the X-axis near the first edge of the semiconductor functional structure, while two first pads 205 are arranged side by side along the Y-axis near the second edge of the semiconductor functional structure. Figure 4aThe right side of the arrow shows three redistribution layers arranged side by side along the X-axis near the first edge of the semiconductor functional structure. The second pad and the corresponding third pad in these three redistribution layers are arranged side by side along the Y-axis. At the same time, two redistribution layers are arranged side by side along the Y-axis near the second edge of the semiconductor functional structure. The second pad and the corresponding third pad in these two redistribution layers are arranged side by side along the X-axis. Figure 3a The dashed line in the diagram shows the straight line where the center points of the three first pads 205 are located.

[0116] It is understood that the second pad and the corresponding third pad, which are located near the second edge of the semiconductor functional structure, are arranged side by side along the X-axis to reduce the risk of the redistribution layer extending beyond the second edge.

[0117] It should be noted that the first pads arranged side-by-side along the Y-axis near the second edge of the semiconductor functional structure can have the same shape as the first pads arranged side-by-side along the X-axis near the first edge of the semiconductor functional structure (e.g., Figure 4b As shown in Figure 4a), it can also be rotated 90° relative to the center point of the first pad arranged side by side along the X-axis near the first edge of the semiconductor functional structure (as shown in Figure 4a).

[0118] In some embodiments, the orthographic projection of the center point of the second pad onto the plane of the interconnect layer is offset by a second distance in a third direction relative to the center point of the corresponding first pad, wherein the angle between the third direction and the first direction is 45° or 135°. In other embodiments, the angle between the third direction and the first direction is 0 to 45° or 135° to 180°, for example, 15°, 30°, 150°, and 165°.

[0119] Here, the second distance is the distance the probe card moves from the center point of the first pad to the center point of the second pad after completing the first type of test.

[0120] For example, refer to Figure 4a Or 4b, the center point O2 of each second pad is offset by a second distance H2 in three directions relative to the center point O1 of the corresponding first pad, wherein the third direction is parallel to the surface of the semiconductor functional structure and the angle α between it and the first direction is 45° or 135°.

[0121] It is understood that when the angle α between the third direction and the first direction is 45° or 135°, in other embodiments, the angle between the third direction and the first direction is 0 to 45° or 135° to 180°, such as 15°, 30°, 150° and 165°, which can simultaneously accommodate changes in two mutually perpendicular directions, thereby ensuring that the offset direction and offset distance of the center point of the T-shaped arrangement of the second pad relative to the center point of the corresponding first pad are equal.

[0122] In some embodiments, each of the first pads has a strip shape, some of the redistribution layers have an L-shaped orthographic projection onto the plane where the interconnect layer is located, and other parts of the redistribution layers have a Z-shaped orthographic projection onto the plane where the interconnect layer is located.

[0123] For example, refer to Figure 4c A portion of the N rerouting layers have an L-shaped orthographic projection onto the plane containing the interconnect layer.

[0124] For example, refer to Figure 4a Or 4b, multiple redistribution layers located near the second edge 20b of the semiconductor functional structure, all have a Z-shaped orthographic projection onto the plane of the interconnect layer.

[0125] In various embodiments of this disclosure, N first pads are provided in the top metal layer for testing the semiconductor functional structure at a first operating speed. After the test at the first operating speed is completed, second pads corresponding one-to-one with the first pads are provided in the redistribution layer on the first pads for testing the semiconductor functional structure at a second operating speed. The center point of each second pad is set to be offset by the same direction and distance relative to the center point of the corresponding first pad, ensuring that the N first pads and N second pads maintain identical relative positions. Thus, the two different operating speed tests can be achieved using the same set of probe cards, saving testing costs and time compared to using two separate sets of probe cards, thereby reducing production cycle and manufacturing costs.

[0126] According to another aspect of the present disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the present disclosure.

[0127] In some embodiments, the semiconductor device further includes: a substrate; a plurality of stacked dies; each die including a semiconductor functional structure and a package structure located on the semiconductor functional structure; each die being electrically connected to the substrate via a lead on a third pad in the package structure.

[0128] According to another aspect of the embodiments of this disclosure, a method for manufacturing an encapsulation structure is provided, such as... Figure 5 As shown, the manufacturing method of the packaging structure provided in this embodiment includes the following steps:

[0129] Step S501: Provide a semiconductor functional structure, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure;

[0130] Step S502: Form an isolation layer with multiple vias, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1;

[0131] Step S503: After completing the first type of test, N redistribution layers are formed on the N first pads and the isolation layer, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads;

[0132] Step S504: A first insulating layer is formed that covers and exposes a portion of the redistribution layer, the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad has the same offset direction and offset distance relative to the center point of the corresponding first pad; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

[0133] It should be understood that Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be adjusted in order according to actual needs. Figures 6a to 6d This is a cross-sectional schematic diagram illustrating the fabrication process of a packaging structure provided in an embodiment of this disclosure. The following is in conjunction with... Figure 5 , Figures 6a to 6d The method for manufacturing the packaging structure provided in the embodiments of this disclosure will be described in detail.

[0134] In step S501, refer to Figure 6a A semiconductor functional structure 600 is provided, the semiconductor functional structure 600 including a semiconductor functional layer 601 and an interconnect layer 602. Providing the semiconductor functional structure 600 includes: providing a substrate (…). Figure 6a (Not shown in the image), a semiconductor functional layer 601 is formed on the substrate, and an interconnect layer 602 is formed on the semiconductor functional layer.

[0135] Specifically, the semiconductor functional layer 601 comprises a single or multiple thin films, and has a conductive layer and / or a dielectric layer. Depending on actual needs, various functional structures can be disposed in the semiconductor functional layer 601. Correspondingly, the interconnect layer 602 is used to extract the electrical signals of the functional structures in the semiconductor functional layer 601 to operate the functional structures. In some embodiments, the interconnect layer 602 includes a top metal layer, which not only extracts the electrical signals of the functional structures but also supports the semiconductor functional structure 600.

[0136] Here, the interconnect layer can be formed on the semiconductor functional layer by means of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0137] In some embodiments, the method further includes: removing a portion of the interconnect layer 602 to reduce the area of ​​the interconnect layer, thereby reducing the parasitic capacitance generated by the interconnect layer. Figure 6a The image shown is a cross-sectional view of a section of interconnect layer 602 after a portion has been removed. In practical applications, the parts of the interconnect layer are not cut off but interconnected. That is, the parts of the interconnect layer may be continuous on other sections.

[0138] In step S502, refer to Figure 6b An isolation layer 603 is formed on the interconnect layer 602. The compositional materials of the isolation layer include, but are not limited to, tetraethyl orthosilicate. The methods for forming the isolation layer include, but are not limited to, PVD, CVD, ALD, and other processes.

[0139] Next, a portion of the isolation layer is removed to form a plurality of vias 604. Each via exposes a portion of the interconnect layer, and each exposed portion of the interconnect layer serves as a first pad 605, forming N first pads 605. The via 604 can be cylindrical, inverted trapezoidal, or any suitable shape. The cross-sectional area of ​​the via includes the area of ​​its orthographic projection onto the plane of the interconnect layer. For example, if the via is an inverted trapezoid, then the cross-sectional area of ​​the first pad is the minimum cross-sectional area of ​​the via.

[0140] The first pad 605 can be used to perform a first type of test; it can also be used to perform functional interactions corresponding to the content of the first type of test, such as leading out bonding wires. The first type of test can be understood as performing some tests on the semiconductor functional structure at a lower operating speed. It should be noted that, in memory, the operating speed refers to the read and write speed of the memory.

[0141] In step S503, refer to Figure 6c A redistribution layer 606 is formed in the isolation layer 603 and the via 604.

[0142] The specific method for forming the redistribution layer 606 on the isolation layer 603 includes: forming a new conductor pattern on the isolation layer by exposure and development; and then forming the redistribution layer according to the new conductor pattern using electroplating technology. The redistribution layer includes new conductor paths that are conductively connected to the interconnect layer. In other embodiments, the redistribution layer 606 can also be formed on the first pad 605 and the isolation layer 603 using a maskless deposition process. The maskless deposition process can be understood as forming the redistribution layer directly on the first pad and the isolation layer without forming a mask.

[0143] In step S504, refer to Figure 6d A first insulating layer 608 is formed on the redistribution layer 606.

[0144] Here, the methods for forming the first insulating layer 608 include, but are not limited to, PVD, CVD, ALD and other processes; the removal process includes, but is not limited to, etching process.

[0145] Next, a portion of the first insulating layer 608 is removed, exposing a portion of the redistribution layer 606. Here, the exposed portion of the redistribution layer includes a second pad 611 and a third pad 612. The second pad 612 is used for performing a second type of test, and the third pad is used to perform a functional interaction corresponding to the content of the second type of test. The second type of test can be understood as some tests performed on the semiconductor functional structure at a high operating speed. The functional interaction corresponding to the content of the second type of test can be understood as leading out bonding wires on the third pad. Here, the positions of the second pad 611 and the third pad 612 can be selected and set according to actual needs.

[0146] It should be noted that, in this embodiment, reference is used. Figure 6dIn addition to exposing a portion of the redistribution layer to form the second and third pads, the first insulating layer also exposes the redistribution layer above the first pad to fill the subsequent second insulating layer 610 within the groove 609 formed by the redistribution layer. In this case, the density of the second insulating layer may be less than or equal to that of the first insulating layer. In other embodiments, the first insulating layer also covers the bottom surface and sidewalls of the groove 609 formed by the redistribution layer, and the subsequent second insulating layer 610 is formed within the groove 609 formed by the first insulating layer.

[0147] It should be noted that the second insulating layer can be made of the same material as the first insulating layer. Correspondingly, the second insulating layer can be formed in the same process step as the first insulating layer, and the second insulating layer and the first insulating layer are an integral structure.

[0148] In other embodiments, the packaging structure further includes conductive pillars, and correspondingly, the method further includes: forming conductive pillars on the first pad after completing the first type of test; the step of forming a redistribution layer on the first pad and the isolation layer includes: forming a redistribution layer on the conductive pillars and the isolation layer, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillars, and the method for forming the conductive pillars includes, but is not limited to, PVD, CVD, ALD and other processes.

[0149] It should be noted that the offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal. In this way, after performing the first type of test, the same set of probe cards can be aligned with the center points of all the second pads after moving a certain distance in a certain direction from the center point of the first pad. That is, the probe card can directly perform the second type of test on all the second pads without replacing the probe card.

[0150] Additionally, it should be noted that in the above embodiments of this disclosure, a packaging structure compatible with two types of testing is adopted to meet the requirement that the semiconductor functional structure can be tested in different types of processes at different stages. However, it should be noted that when designing the layout of the packaging structure, via positions for the redistribution layer need to be reserved on the top metal layer to ensure that when a redistribution layer needs to be added, the top metal layer or any other photomask and process should not be modified.

[0151] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0152] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0153] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0154] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A package structure, characterized by, include: An isolation layer having multiple vias covers the surface of an interconnect layer, the vias exposing portions of the interconnect layer, the interconnect layer being disposed on the surface of a semiconductor functional structure; N first pads; each first pad is formed by an interconnect layer exposed by one of the vias; N is a positive integer greater than 1; N rewiring layers, each rewiring layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; A first insulating layer covers and exposes a portion of each of the redistribution layers; At least a portion of the redistribution layer is exposed, including a second pad and a third pad; wherein the center point of each second pad is offset from the center point of the corresponding first pad in both direction and distance; the first pad and the second pad are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad; wherein the redistribution layer and the second pad are formed after the first operating speed test is performed using the first pad.

2. The packaging structure according to claim 1, characterized in that, N first pads are arranged side by side along a first direction at a position close to the first edge of the semiconductor functional structure; At least a portion of the second pad and the corresponding third pad are arranged side by side along a second direction, which is perpendicular to the first direction.

3. The package structure of claim 2, wherein, The orthographic projection of the center point of each of the second pads onto the plane of the interconnect layer is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

4. The package structure of claim 3, wherein, The shape of the rewiring layer in the orthographic projection of the plane containing the interconnect layer includes a strip shape.

5. The packaging structure according to claim 1, characterized in that, A portion of the first pad is arranged side-by-side along a first direction at a position close to the first edge of the semiconductor functional structure; a portion of the second pad and the corresponding third pad are arranged side-by-side along a second direction, the second direction being perpendicular to the first direction. The remaining portion of the first pad is arranged side by side along the second direction at a position close to the second edge of the semiconductor functional structure, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure; the remaining second pad and the third pad corresponding to the first pad are arranged side by side along the first direction.

6. The package structure of claim 5, wherein, The center point of the second pad is projected onto the plane of the interconnect layer by a second distance in a third direction relative to the center point of the corresponding first pad, and the angle between the third direction and the first direction is 45° or 135°.

7. The package structure of claim 6, wherein, Each of the first pads has a strip-shaped shape, and the shape of the orthographic projection of a portion of the redistribution layers onto the plane where the interconnect layer is located is L-shaped, while the shape of the orthographic projection of another portion of the redistribution layers onto the plane where the interconnect layer is located is Z-shaped.

8. The packaging structure according to claim 1, characterized in that, The second pad is located at one end of the redistribution layer near the first pad, and the third pad is located at one end of the redistribution layer away from the first pad.

9. The packaging structure according to claim 1, characterized in that, The redistribution layer is in direct contact with the corresponding first pad; Alternatively, the packaging structure may further include: a conductive pillar located between the redistribution layer and the corresponding first pad, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillar.

10. The package structure of claim 9, wherein, The encapsulation structure includes the conductive pillar, the orthographic projection of the conductive pillar onto the plane of the interconnect layer overlaps with the first pad, and the orthographic projection of the conductive pillar onto the plane of the interconnect layer does not overlap with the orthographic projections of the second pad and the third pad onto the plane of the interconnect layer.

11. The package structure of claim 9, wherein, The redistribution layer is in direct contact with the corresponding first pad, and the packaging structure further includes: A second insulating layer is located within the groove formed by each of the redistribution layers; the hardness of the material of the second insulating layer is less than the hardness of the material of the redistribution layer.

12. A semiconductor device, characterized by comprising: include: Semiconductor functional structure and packaging structure as described in any one of claims 1 to 11.

13. The semiconductor device of claim 12, wherein, The semiconductor device further includes: substrate; Multiple stacked dies; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure; Each die is electrically connected to the substrate via a lead on the third pad in the package structure.

14. A method for manufacturing an encapsulation structure, characterized in that, include: A semiconductor functional structure is provided, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure; An isolation layer with multiple vias is formed, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1; After completing the first type of test, N rewiring layers are formed on the N first pads and the isolation layer, each rewiring layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads. A first insulating layer is formed to cover and expose a portion of the redistribution layer, the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad is offset in both direction and distance relative to the center point of the corresponding first pad; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

Images