LED epitaxial wafers and their fabrication methods, LEDs
By introducing a stress-relieving layer structure, including a Si-doped GaN layer, a porous GaN layer, and a GaN leveling layer, into GaN-based LED devices, the problems of dislocation defects and compressive stress caused by lattice mismatch are solved, thereby improving the luminous efficiency of the light-emitting diode.
CN117199203BActive Publication Date: 2026-06-30JIANGXI ZHAO CHI SEMICON CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2023-10-25
- Publication Date
- 2026-06-30
Smart Images
Figure CN117199203B_ABST
Abstract
This invention discloses a light-emitting diode (LED) epitaxial wafer and its fabrication method. The LED epitaxial wafer includes a substrate and a buffer layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate. The stress relief layer includes a Si-doped GaN layer, a Si-doped porous GaN layer, a GaN leveling layer, and an InGaN / GaN superlattice layer sequentially stacked on the N-type GaN layer. The LED fabricated by this invention can reduce the stress and defect density of the epitaxial layer material, improve the quality of the multiple quantum well layer, and enhance the radiative recombination efficiency in the multiple quantum well layer, thereby improving the luminous efficiency of the LED.
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