A SAR ADC circuit based on capacitor decomposition and its quantization method
By using a capacitor-based SAR ADC circuit, which utilizes the comparison and logic control of the upper plates of the capacitor array, the power consumption waste and quantization accuracy problems of traditional SAR ADCs are solved, achieving more efficient signal conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2023-08-18
- Publication Date
- 2026-06-30
AI Technical Summary
Traditional SAR ADCs suffer from unnecessary conversion cycles, leading to wasted power consumption. Bypass window structures increase power consumption and reduce quantization accuracy. Existing structures are sensitive to process and temperature, resulting in poor accuracy.
A SAR ADC circuit based on capacitor decomposition is adopted. By comparing differential signals on the plates of the capacitor array and using logic control, the voltage switching of the capacitor array is realized, thereby reducing power consumption and improving quantization accuracy.
It reduces power consumption and improves quantization accuracy, achieving more efficient signal conversion.
Smart Images
Figure CN117200794B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a SAR ADC circuit based on capacitor decomposition and its quantization method. Background Technology
[0002] Successive approximation register (SAR) analog-to-digital converters primarily convert continuous analog signals from nature into digital signals that can be processed by circuit systems. Due to the unique quantization method and circuit structure of SAR ADCs, they have consistently demonstrated significant advantages and potential in energy efficiency, and their internal digital structure continues to benefit from the miniaturization of CMOS technology. However, traditional successive binary approximation quantization methods require switching the capacitor array voltage according to a fixed program. For certain ranges of input signals, this results in unnecessary conversion cycles, leading to substantial power consumption waste. This constitutes a design bottleneck for reducing the energy efficiency of SAR ADCs.
[0003] The power consumption of SAR ADCs is mainly concentrated in three modules: the DAC, the comparator, and the digital logic circuit. For medium-resolution SAR ADCs, capacitor switching, which increases exponentially with quantization accuracy, accounts for the majority of the power consumption. Using appropriate capacitor arrays and switching strategies can significantly reduce ADC power consumption. Therefore, to further reduce power consumption and avoid unnecessary conversion cycles, the concept of a bypass window switch has been proposed. However, existing bypass window switch structures require two additional comparators and a dedicated external reference voltage for bypass detection, which leads to problems such as window size affecting quantization accuracy, complex bypass window detection logic circuitry, and additional power consumption. In contrast, an existing structure that adds a dynamically trackable bypass window based on physiological signal characteristics can dynamically adjust the window function range according to different changes in human physiological signals. When the signal exceeds the predefined bypass window range, the ADC switches back to full-range mode to reacquire the signal. The window adjustment process wastes energy. Furthermore, for existing bypass window SAR ADC structures, adding the bypass window requires a coarse window detection circuit and a precise window judgment circuit. These two circuit modules are extremely sensitive to semiconductor manufacturing processes and temperature, leading to issues with the accuracy of bypass window addition during operation. This not only increases the ADC's power consumption but also reduces the ADC's quantization accuracy. Summary of the Invention
[0004] To address the aforementioned technical problems, the present invention aims to provide a SAR ADC circuit and its quantization method based on capacitor decomposition. When the quantized voltage falls within the bypass window formed by the decomposition capacitor, the voltage switching of the subsequent capacitors can be skipped, and the voltage transformation of the lower-weighted capacitors can be performed directly, thereby reducing power consumption and improving quantization accuracy.
[0005] The first technical solution adopted in this invention is: a SAR ADC circuit based on capacitor decomposition, comprising a sampling switch circuit module, a DAC decomposition capacitor array module, a comparator module, and a logic control circuit module. The output terminal of the sampling switch circuit module is connected to the first input terminal of the DAC decomposition capacitor array module, the output terminal of the DAC decomposition capacitor array module is connected to the first input terminal of the comparator module, the output terminal of the comparator module is connected to the input terminal of the logic control circuit module, and the output terminal of the logic control circuit module is fed back to the second input terminal of the DAC decomposition capacitor array module and the second input terminal of the comparator module, respectively.
[0006] The sampling switch circuit module is used to acquire differential analog signals;
[0007] The DAC split capacitor array module is used to sample the differential analog signal onto the upper plate of the capacitor in the DAC split capacitor array module according to the sampling clock signal, and output the positive terminal voltage value and the negative terminal voltage value.
[0008] The comparator module is used to acquire the control clock signal, compare the positive terminal voltage value with the negative terminal voltage value, and output the voltage switching control result.
[0009] The logic control circuit module is used to control the operation of the comparator module and the voltage switching of the DAC split capacitor array module according to the voltage switching control result.
[0010] Furthermore, the DAC split capacitor array module includes a first sub-capacitor array module, a second sub-capacitor array module, a third sub-capacitor array module, and a fourth sub-capacitor array module. The input terminal of the first sub-capacitor array module is connected to the first output terminal of the sampling switch circuit module. The output terminal of the first sub-capacitor array module is connected to the input terminal of the second sub-capacitor array module. The output terminal of the second sub-capacitor array module is connected to the positive terminal of the comparator module. The input terminal of the third sub-capacitor array module is connected to the second output terminal of the sampling switch circuit module. The output terminal of the third sub-capacitor array module is connected to the input terminal of the fourth sub-capacitor array module. The output terminal of the fourth sub-capacitor array module is connected to the negative terminal of the comparator module, wherein:
[0011] The first sub-capacitor array module, the second sub-capacitor array module, the third sub-capacitor array module, and the fourth sub-capacitor array module are used to acquire the sampling clock signal, and to sample the differential analog signal according to the sampling clock signal, and output the positive terminal voltage value and the negative terminal voltage value.
[0012] Furthermore, the first sub-capacitor array module includes a first capacitor group and a first switch group, the second sub-capacitor array module includes a second capacitor group and a second switch group, the third sub-capacitor array module includes a third capacitor group and a third switch group, and the fourth sub-capacitor array module includes a fourth capacitor group and a fourth switch group, wherein:
[0013] The first capacitor bank includes multiple first capacitors C a1 ~C aj The first switch group includes a plurality of first switches, and the first terminal of each of the first capacitors is used to receive a first differential analog signal V. in+ The second terminals of the first capacitors are all electrically connected to the first terminal of the first switch, and the second terminal of the first switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0014] The second capacitor bank includes a plurality of second capacitors C b1 ~C bj The second switch group includes a plurality of second switches, and the first terminal of each second capacitor is used to receive a first differential analog signal V. in+ The second terminals of the second capacitors are all electrically connected to the first terminal of the second switch, and the second terminal of the second switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0015] The third capacitor bank includes multiple third capacitors C. d1 ~C dj The third switch group includes multiple third switches, and the first terminal of each third capacitor is used to receive the second differential analog signal V. in- The second terminals of the third capacitors are all electrically connected to the first terminal of the third switch, and the second terminal of the third switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0016] The fourth capacitor bank includes multiple fourth capacitors C. e1 ~C ej The fourth switch group includes multiple fourth switches, and the first terminal of each of the fourth capacitors is used to receive the second differential analog signal V. in- The second terminals of the fourth capacitor are all electrically connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level VGND .
[0017] The second technical solution adopted in this invention is: a quantization method for a SAR ADC circuit based on capacitor decomposition, comprising the following steps:
[0018] Differential analog signals are obtained based on the sampling switch circuit module;
[0019] Based on the sampling clock signal, the differential analog signal is sampled and processed by the DAC split capacitor array module, and the positive terminal voltage value and the negative terminal voltage value are output.
[0020] The control clock signal is acquired, and the positive terminal voltage value and the negative terminal voltage value are compared and processed based on the comparator module to output the voltage switching control result.
[0021] The operation of the comparator module and the voltage switching of the DAC split capacitor array module are controlled according to the voltage switching control result.
[0022] Furthermore, the step of sampling and processing the differential analog signal according to the sampling clock signal through the DAC split capacitor array module and outputting the positive and negative terminal voltage values specifically includes:
[0023] Acquire the sampling clock signal;
[0024] When the sampling clock signal is in the high-level band, the DAC split capacitor array module is triggered to enter the sampling stage, and the differential analog signal is sampled to obtain the positive terminal voltage value and the negative terminal voltage value.
[0025] The step of sampling and processing the differential analog signal to obtain the positive and negative terminal voltage values includes:
[0026] The first capacitor C in the first capacitor group of the DAC split capacitor array module aj C aj-1 C aj-2 The lower electrode plate and the fourth capacitor C in the fourth capacitor group of the DAC split capacitor array module ej C ej-1 C ej-2 The lower electrode is connected to the reference voltage V. REF The second capacitor C in the second capacitor group of the DAC split capacitor array module. bj C bj-1 C bj-2 The lower electrode plate and the third capacitor C in the third capacitor group of the DAC split capacitor array module dj C dj-1 C dj-2 The grounding level of the lower electrode plate VGND ;
[0027] The first capacitor C in the first capacitor group of the DAC split capacitor array module aj-3 To C a1 The lower electrode plate, the second capacitor C in the second capacitor group of the DAC split capacitor array module bj-3 To C b1 The lower electrode plate, the third capacitor C in the third capacitor group of the DAC split capacitor array module dj-3 To C d1 The lower electrode plate and the fourth capacitor C in the fourth capacitor group of the DAC split capacitor array module ej-3 To C e1 The lower electrode is connected to the reference voltage V. CM ;
[0028] The first differential analog signal V in+ The input is fed to the upper plates of the first capacitor bank and the second capacitor bank in the DAC split capacitor array module and sampled as the positive terminal voltage value V. p The second differential analog signal V in- The input is fed to the upper plates of the third capacitor group and the fourth capacitor group in the DAC split capacitor array module and sampled as the negative terminal voltage value V. n .
[0029] Furthermore, the step of acquiring the control clock signal, comparing the positive terminal voltage value with the negative terminal voltage value based on the comparator module, and outputting the voltage switching control result specifically includes:
[0030] Acquire a control clock signal, wherein the control clock signal includes a first control clock signal and a second control clock signal;
[0031] When the first control clock signal is high, the comparator module receives the positive terminal voltage value V. p With the negative terminal voltage value V n And perform the first comparison process;
[0032] If the positive terminal voltage value V p Greater than the negative terminal voltage value V n Then the output quantization value D[9] = 1;
[0033] If the positive terminal voltage value V p Less than the negative terminal voltage value V n If so, the output quantization value D[9] = 0;
[0034] When the second control clock signal is high, the comparator module receives the positive terminal voltage value V. pWith the negative terminal voltage value V n A second comparison is performed, and the quantized value D[8] is output. 1st , where the quantization value D[8] includes the quantization value D[8]. 1st And the quantization value D[8] 2nd If the quantization value D[9] and the quantization value D[8] are... 1st Alternatively, if the result is 1, output the value of D[8]; otherwise, perform requantization to obtain the quantized value D[8]. 2nd Then output the quantized value D[8];
[0035] Integrate the quantized value D[9] and the quantized value D[8]. 1st The voltage switching control results are obtained.
[0036] Furthermore, the step of controlling the operation of the comparator module and the voltage switching of the DAC split capacitor array module based on the voltage switching control result specifically includes:
[0037] The quantization value D[9] is judged;
[0038] If the quantization value D[9] = 1, then control the first capacitor C in the first capacitor group of the DAC split capacitor array module. aj The lower electrode plate is switched to ground level V. GND And control the third capacitor C in the third capacitor group of the DAC split capacitor array module. dj The lower plate is switched to the reference voltage V. REF ;
[0039] If the quantization value D[9] = 0, then control the second capacitor C in the second capacitor group of the DAC split capacitor array module. bj The lower plate is switched to the reference voltage V. REF And control the fourth capacitor C in the fourth capacitor group of the DAC split capacitor array module. ej The lower electrode plate is switched to ground level V. GND ;
[0040] A bypass window function is introduced for the quantized value D[9] and the quantized value D[8]. 1st Perform XOR logic judgment and switch the voltage of the DAC split capacitor array module.
[0041] Furthermore, the introduction of a bypass window function applies to the quantized value D[9] and the quantized value D[8]. 1st The step of performing an XOR logic judgment and switching the voltage of the DAC split capacitor array module specifically includes:
[0042] A bypass window function is introduced for the quantized value D[9] and the quantized value D[8]. 1st Perform an XOR logic check;
[0043] If the quantization value D[9] and the quantization value D[8] 1st If they are not equal, the XOR logic result is 1, and the first capacitor C in the first capacitor group is... aj-3 The lower electrode plate, the second capacitor C in the second capacitor group bj-3 The lower electrode plate, the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate performs voltage switching;
[0044] If the quantization value D[9] and the quantization value D[8] 1st If they are equal, the XOR logic result is 0, and the first capacitor C in the first capacitor group is... aj-1 The lower electrode plate, the second capacitor C in the second capacitor group bj-1 The lower electrode plate, the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower electrode plate performs voltage switching.
[0045] Furthermore, the quantization value D[9] and the quantization value D[8] are further... 1st If they are not equal, the XOR logic result is 1, and the first capacitor C in the first capacitor group is... aj-3 The lower electrode plate, the second capacitor C in the second capacitor group bj-3 The lower electrode plate, the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The step of switching the voltage on the lower electrode plate specifically includes:
[0046] If the quantization value D[9] = 1 and the quantization value D[8] 1st =0, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate is switched to ground level V. GND ;
[0047] If the quantization value D[9] = 0 and the quantization value D[8] 1st=1, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower plate is switched to the reference voltage V. REF .
[0048] Furthermore, the quantization value D[9] and the quantization value D[8] are further... 1st If they are equal, the XOR logic result is 0, and the first capacitor C in the first capacitor group is... aj-1 The lower electrode plate, the second capacitor C in the second capacitor group bj-1 The lower electrode plate, the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group rj-1 The step of switching the voltage on the lower electrode plate specifically includes:
[0049] If the quantization value D[9] and the quantization value D[8] 1st If both are 1, then for the first capacitor C in the first capacitor group aj-1 The lower electrode and the second capacitor C in the second capacitor group bj-1 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower plate is switched to the reference voltage V. REF ;
[0050] The quantization value D[8] is introduced. 2nd If the quantization value D[8] 2nd =0, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate is switched to ground level V. GND If the quantization value D[8] 2nd =1, then for the first capacitor C in the first capacitor group aj-2 The lower electrode and the second capacitor C in the second capacitor group bj-2 The lower electrode plate is switched to ground level V. GNDFor the third capacitor C in the third capacitor group dj-2 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-2 The lower plate is switched to the reference voltage V. REF ;
[0051] If the quantization value D[9] and the quantization value D[8] 1st If both are 0, then for the first capacitor C in the first capacitor group aj-1 The lower electrode and the second capacitor C in the second capacitor group bj-1 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower electrode plate is switched to ground level V. GND ;
[0052] The quantization value D[8] is introduced. 2nd If the quantization value D[8] 2nd =1, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower plate is switched to the reference voltage V. REF If the quantization value D[8] 2nd If the voltage is 0, then no switching is performed on the first capacitor C in the first capacitor group. aj-2 The lower electrode and the second capacitor C in the second capacitor group bj-2 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-2 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-2 The lower electrode plate is switched to ground level V. GND .
[0053] The beneficial effects of the circuit and quantization method of this invention are as follows: By closing the sampling switch circuit, the differential signal is sampled onto the upper plate of the capacitor by the DAC split capacitor array through the sampling switch circuit and held. The dummy capacitor with the lowest weight is used as the quantization capacitor. The comparator connected to the upper plate of the capacitor array directly compares the sampled signal, reducing the total capacitance value of the capacitor array to half of its original value, thereby reducing the quantization power consumption by half and improving the matching degree of the capacitor array. Based on the comparison result of the comparator, the operation of the comparator and the voltage switching of the capacitor array are further controlled by the logic control circuit, thereby achieving the purpose of reducing power consumption and improving the quantization accuracy, and finally realizing the quantization of the differential signal. Attached Figure Description
[0054] Figure 1 This is a schematic diagram of a SAR ADC circuit based on capacitor decomposition according to an embodiment of the present invention;
[0055] Figure 2 This is a schematic flowchart of a quantization method for a SAR ADC circuit based on capacitor decomposition according to an embodiment of the present invention.
[0056] Figure 3 This is a schematic diagram of the circuit principle of a traditional 10-bit SAR ADC structure;
[0057] Figure 4 This is a schematic diagram of the circuit principle of the existing SAR ADC structure based on the concept of bypass window;
[0058] Figure 5 This is a schematic diagram of the circuit principle of an existing dynamic trackable bypass window SAR ADC structure based on physiological signal characteristics;
[0059] Figure 6 This is a schematic diagram of the circuit principle of an existing coarse and fine correction bypass window SAR ADC structure;
[0060] Figure 7 This is a schematic diagram of the principle framework of a SAR ADC circuit based on capacitor decomposition according to a specific embodiment of the present invention;
[0061] Figure 8 This is a schematic diagram of the SAR ADC quantization timing in a specific embodiment of the present invention;
[0062] Figure 9 This is a schematic diagram of the circuit principle of the capacitor array sampling module in a specific embodiment of the present invention;
[0063] Figure 10 This is a schematic diagram of the FFT spectrum when the sampling frequency Fin = 20.84 kHz in a specific embodiment of the present invention;
[0064] Figure 11 This is a schematic diagram of the circuit principle of the 11-bit SAR ADC structure in a specific embodiment of the present invention;
[0065] Figure 12 This is a schematic diagram of the circuit principle of a 9-bit SAR ADC structure according to a specific embodiment of the present invention.
[0066] Reference numerals: 1. Sampling switch circuit module; 2. DAC split capacitor array module; 3. Comparator module; 4. Logic control circuit module; 211. First sub-capacitor array module; 212. Second sub-capacitor array module; 213. Third sub-capacitor array module; 214. Fourth sub-capacitor array module. Detailed Implementation
[0067] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
[0068] like Figure 3 The traditional successive binary search approximation quantization method shown requires switching the capacitor array voltage according to a fixed procedure. For input signals within a certain range, there will be unnecessary switching cycles, resulting in a large amount of power consumption waste.
[0069] like Figure 4 As shown, in order to further reduce power consumption and avoid unnecessary switching cycles, the concept of a bypass window switch was proposed. However, this structure requires two additional comparators and a dedicated external reference voltage to implement bypass detection, which has problems such as the window size affecting quantization accuracy, complex circuitry for bypass window detection logic, and additional power consumption.
[0070] like Figure 5 The paper proposes a structure that adds a dynamically trackable bypass window based on physiological signal characteristics. This allows for dynamic adjustment of the window function's range according to different changes in human physiological signals. However, when the signal exceeds the predefined bypass window range, the ADC switches back to full-range mode to reacquire the signal, resulting in energy waste during the window adjustment process.
[0071] like Figure 6 The diagram shows a bypass window SAR ADC structure. Adding a bypass window to this structure requires a coarse window detection circuit and a precise window determination circuit. These two circuit modules are extremely sensitive to semiconductor manufacturing processes and temperature, leading to issues with the accuracy of bypass window addition during operation. This not only increases the ADC's power consumption but also reduces its quantization accuracy.
[0072] Based on this, the present invention reduces the quantization power consumption of the ADC and improves the quantization accuracy by employing a split capacitor array and a bypass window quantization timing.
[0073] Reference Figure 1 and Figure 7 This invention provides a SAR ADC circuit based on capacitor decomposition, including a sampling switch circuit module 1, a DAC decomposition capacitor array module 2, a comparator module 3, and a logic control circuit module 4. The output terminal of the sampling switch circuit module 1 is connected to the first input terminal of the DAC decomposition capacitor array module 2, the output terminal of the DAC decomposition capacitor array module 2 is connected to the first input terminal of the comparator module 3, the output terminal of the comparator module 3 is connected to the input terminal of the logic control circuit module 4, and the output terminal of the logic control circuit module 4 is fed back to the second input terminals of the DAC decomposition capacitor array module 2 and the second input terminal of the comparator module 3, respectively.
[0074] Sampling switch circuit module 1 is used to acquire differential analog signals;
[0075] Specifically, the sampling switch circuit mainly consists of a bootstrap circuit;
[0076] The DAC split capacitor array module 2 is used to sample the differential analog signal onto the upper plate of the capacitor in the DAC split capacitor array module 2 according to the sampling clock signal, and output the positive terminal voltage value and the negative terminal voltage value.
[0077] Specifically, such as Figure 9 As shown, the DAC split capacitor array module 2 includes a first sub-capacitor array module 211, a second sub-capacitor array module 212, a third sub-capacitor array module 213, and a fourth sub-capacitor array module 214. The input terminal of the first sub-capacitor array module 211 is connected to the first output terminal of the sampling switch circuit module 1, the output terminal of the first sub-capacitor array module 211 is connected to the input terminal of the second sub-capacitor array module 212, the output terminal of the second sub-capacitor array module 212 is connected to the positive terminal of the comparator module 3, the input terminal of the third sub-capacitor array module 213 is connected to the second output terminal of the sampling switch circuit module 1, the output terminal of the third sub-capacitor array module 213 is connected to the input terminal of the fourth sub-capacitor array module 214, and the output terminal of the fourth sub-capacitor array module 214 is connected to the negative terminal of the comparator module 3. The first, second, third, and fourth sub-capacitor array modules are used to acquire the sampling clock signal and perform sampling processing on the differential analog signal according to the sampling clock signal, outputting the positive and negative terminal voltage values.
[0078] Furthermore, the first capacitor bank includes multiple first capacitors C a1 ~C ajThe first switch group includes multiple first switches, and the first terminal of each first capacitor is used to receive a first differential analog signal V. in+ The second terminals of the first capacitors are all electrically connected to the first terminal of the first switch, and the second terminal of the first switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0079] The second capacitor bank includes multiple second capacitors C. b1 ~C bj The second switch group includes multiple second switches, and the first terminal of each second capacitor is connected to the first differential analog signal V. in+ The second terminals of the second capacitors are all electrically connected to the first terminal of the second switch, and the second terminal of the second switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0080] The third capacitor bank includes multiple third capacitors C. d1 ~C dj The third switch group includes multiple third switches, and the first terminal of each third capacitor is connected to the second differential analog signal V. in- The second terminals of the third capacitors are all electrically connected to the first terminal of the third switch, and the second terminal of the third switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0081] The fourth capacitor bank includes multiple fourth capacitors C. e1 ~C ej The fourth switch group includes multiple fourth switches, and the first terminal of each fourth capacitor is connected to the second differential analog signal V. in- The second terminals of the fourth capacitor are all electrically connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is selectively connected to the reference voltage V. CM Reference voltage V REF or ground level V GND ;
[0082] Furthermore, the capacitor array after decomposition is composed of unit capacitors. In this invention, a 4μm×5μm MIM capacitor with a capacitance value of 19.38fF is used based on the SMIC 0.18μm CMOS process. The capacitor array connected to the positive terminal of the comparator is: 32C, 32C, 32C, 16C, 8C, 4C, 2C, C, C, 32C, 32C, 32C, 16C, 8C, 4C, 2C, C, C; the capacitor array connected to the negative terminal of the comparator is the same as that of the positive terminal.
[0083] Comparator module 3 is used to acquire the control clock signal, compare the positive terminal voltage value with the negative terminal voltage value, and output the voltage switching control result.
[0084] Specifically, the comparator uses a traditional strong ARM Latch comparator.
[0085] The logic control circuit module 4 is used to control the operation of the comparator module 3 and the voltage switching of the DAC split capacitor array module 2 according to the voltage switching control result.
[0086] Specifically, the entire operation of the ADC is mainly controlled by two clocks, CLK and Sample. CLK is the control clock of the comparator, and Sample is the sampling clock of the ADC. The frequency of Sample is also equal to the sampling frequency and data output frequency of the entire ADC.
[0087] Reference Figure 2 A quantization method for a SAR ADC circuit based on capacitor decomposition includes the following steps:
[0088] S1. Obtain differential analog signals based on sampling switch circuit module 1;
[0089] S2. Based on the sampling clock signal, the differential analog signal is sampled and processed by the DAC split capacitor array module 2, and the positive terminal voltage value and the negative terminal voltage value are output.
[0090] Specifically, the sampling clock signal is acquired. When the sampling clock signal is in the high-level band, the DAC split capacitor array module 2 is triggered to enter the sampling stage, and the differential analog signal is sampled and processed, and the first capacitor C in the first capacitor group is... aj C aj-1 C aj-2 The lower electrode and the fourth capacitor C in the fourth capacitor group ej C ej-1 C ej-2 The lower electrode is connected to the reference voltage V. REF The second capacitor C in the second capacitor group bj C bj-1 C bj-2 The lower electrode and the third capacitor C in the third capacitor group dj C dj-1 C dj-2 The grounding level of the lower electrode plate V GND The first capacitor C in the first capacitor group aj-3 To C a1 The lower electrode plate, the second capacitor C in the second capacitor group bj-3 To C b1The lower electrode plate, the third capacitor C in the third capacitor group dj-3 To C d1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 To C e1 The lower electrode is connected to the reference voltage V. CM The first differential analog signal V in+ The sampled value is the positive terminal voltage V. p The second differential analog signal V in- The sampled voltage value V is the negative terminal voltage value. n ;
[0091] In this embodiment, when Sample is high, the ADC is in the sampling phase, such as... Figure 8 As shown, when the switching circuit is closed, the upper plates of all capacitors sample the differential input signal, i.e.: V n =V in- V p =V in+ Simultaneously, the highest and second-highest capacitors (Ca) of the a-CDAC (first sub-capacitor array module 211) and the e-CDAC (fourth sub-capacitor array module array 214) are... a9 C a8 C a7 C e9 C e8 C e7 The lower electrode plate is connected to V. REF b-CDAC refers to the highest and second-highest level capacitors of the second sub-capacitor array module 212 and d-CDAC refers to the highest and second-highest level capacitors of the third sub-capacitor array module array 213 (C b9 C b8 C b7 C d9 C d8 C d7 The lower electrode plate is connected to V. GND The remaining capacitors are connected to the reference voltage V. CM Sampling ends when Sample is low. The sampled signal V is obtained using the upper plate. n and V p Perform a direct comparison;
[0092] When CLK1 is high, the comparator performs its first comparison: if V p Greater than V n Then D[9] = 1, and the lower plate of Ca9 is connected to V. GND Meanwhile, C d9 The lower electrode plate was modified to connect to V. REF Conversely, D[9] = 0, C b9 The lower electrode plate was modified to connect to V. REF Meanwhile, C e9The lower electrode plate was modified to connect to V. GND Then, when CLK2 is high, the comparator performs a second voltage comparison. Since the value of D[8] is obtained by quantizing the voltage after the flip of 64C, i.e., "32C+32C", the value obtained at this time is not completely equal to D[8]. The value quantized by the first group of 32C is defined as D[8]. 1st The value of the second group of 32C quantized values is defined as D[8]. 2nd , D[8] 1st With D[8] 2nd Together they form D[8].
[0093] S3. Obtain the control clock signal, compare the positive terminal voltage value with the negative terminal voltage value based on comparator module 3, and output the voltage switching control result.
[0094] Specifically, the control clock signal is acquired, which includes a first control clock signal and a second control clock signal. When the first control clock signal indicates a high level, the comparator module 3 receives the positive terminal voltage value V. p With negative terminal voltage value V n And perform the first comparison process. If the positive terminal voltage value V p Greater than the negative terminal voltage value V n Then the output quantization value D[9] = 1, if the positive terminal voltage value V p Less than the negative terminal voltage value V n Then the output quantization value D[9] = 0. When the second control clock signal indicates a high level, the comparator module 3 receives the positive terminal voltage value V. p With negative terminal voltage value V n A second comparison is performed, and the quantized value D[8] is output. 1st The quantization value D[8] includes the quantization value D[8]. 1st And the quantization value D[8] 2nd If the quantization value D[9] and the quantization value D[8] 1st Alternatively, if the result is 1, the value of D[8] can be deduced; otherwise, the quantized value D[8] needs to be quantized in the next step. 2nd Only then can the quantized value D[8] be obtained, and the quantized value D[9] and the quantized value D[8] be integrated. 1st The results of the next voltage switching control are obtained.
[0095] S4. Control the operation of comparator module 3 and the voltage switching of DAC split capacitor array module 2 according to the voltage switching control result.
[0096] Specifically, the quantization value D[9] is judged. If the quantization value D[9] = 1, then the first capacitor C in the first capacitor group... aj The lower electrode plate is switched to ground level V.GND The third capacitor C in the third capacitor group dj The lower plate is switched to the reference voltage V. REF If the quantization value D[9] = 0, then the second capacitor C in the second capacitor group bj The lower plate is switched to the reference voltage V. REF The fourth capacitor C in the fourth capacitor group ej The lower electrode plate is switched to ground level V. GND A bypass window function is introduced to apply the quantization values D[9] and D[8]. 1st Perform XOR logic judgment and switch the voltage of DAC split capacitor array module 2;
[0097] If the quantization value D[9] and the quantization value D[8] 1st If they are not equal, the XOR logic result is 1, and the first capacitor C in the first capacitor group is also set to 1. aj-3 The lower electrode plate, the second capacitor C in the second capacitor group bj-3 The lower electrode plate, the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate performs voltage switching, wherein if the quantization value D[9] = 1, the quantization value D[8] 1st =0, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate is switched to ground level V. GND If the quantization value D[9] = 0, the quantization value D[8] 1st =1, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower plate is switched to the reference voltage V. REF ;
[0098] If the quantization value D[9] and the quantization value D[8] 1st If they are equal, the XOR logic result is 0, and the first capacitor C in the first capacitor group is also equal. aj-1 The lower electrode plate, the second capacitor C in the second capacitor group bj-1 The lower electrode plate, the third capacitor C in the third capacitor groupdj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower electrode plate performs voltage switching, wherein the quantization value D[9] and the quantization value D[8] are... 1st If both are 1, then for the first capacitor C in the first capacitor group aj-1 The lower electrode and the second capacitor C in the second capacitor group bj-1 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower plate is switched to the reference voltage V. REF , and introduce a quantization value D[8] 2nd If the quantization value D[8] 2nd =0, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower electrode plate is switched to ground level V. GND If the quantization value D[8] 2nd =1, then for the first capacitor C in the first capacitor group aj-2 The lower electrode and the second capacitor C in the second capacitor group bj-2 The lower electrode plate is switched to ground level V. GND For the third capacitor C in the third capacitor group dj-2 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-2 The lower plate is switched to the reference voltage V. REF If the quantization value D[9] and the quantization value D[8] 1st If both are 0, then for the first capacitor C in the first capacitor group aj-1 The lower electrode and the second capacitor C in the second capacitor group bj-1 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-1 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-1 The lower electrode plate is switched to ground level V. GND , and introduce a quantization value D[8] 2nd If the quantization value D[8] 2nd =1, then for the first capacitor C in the first capacitor group aj-3 The lower electrode and the second capacitor C in the second capacitor group bj-3 The lower electrode plate is switched to ground level V. GNDFor the third capacitor C in the third capacitor group dj-3 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-3 The lower plate is switched to connect to the ground reference voltage V. REF If the quantization value D[8] 2nd =0, then for the first capacitor C in the first capacitor group aj-2 The lower electrode and the second capacitor C in the second capacitor group bj-2 The lower plate is switched to the reference voltage V. REF For the third capacitor C in the third capacitor group dj-2 The lower electrode and the fourth capacitor C in the fourth capacitor group ej-2 The lower electrode plate is switched to ground level V. GND ;
[0099] In this embodiment, the following judgment environment exists, specifically:
[0100] (1) When CLK1 is high, the comparator performs its first comparison: if V p Greater than V n Then D[9]=1, C a9 The lower electrode plate was modified to connect to V. GND Meanwhile, C d9 The lower electrode plate was modified to connect to V. REF Conversely, D[9] = 0, C b9 The lower electrode plate was modified to connect to V. REF Meanwhile, C e9 The lower electrode plate was modified to connect to V. GND Then, when CLK2 is high, the comparator performs a second voltage comparison. Since the value of D[8] is obtained by quantizing the voltage after the flip of 64C, i.e., "32C+32C", the value obtained at this time is not completely equal to D[8]. The value quantized by the first group of 32C is defined as D[8]. 1st The value of the second group of 32C quantized values is defined as D[8]. 2nd , D[8] 1st With D[8] 2nd Together they form D[8];
[0101] (2) If D[9] = 1 and D[8] 1st =0, the XOR logic result of the two is 1, which means that after the voltage switching of the first group of 32C, V p and V n The polarity of V has changed, which can determine V. p The range is [V CM 5V REF / 8]. Therefore, C can be skipped directly. a8 C a7 Cb8 C b7 C d8 C d7 C e8 and C e7 For voltage switching, set D[8] and D[7] to 0. Then directly perform 16C voltage conversion, i.e., C a6 and C b6 Connect to V REF C d6 and C e6 Connect to V GND Then, quantization is performed according to normal SAR logic, such as... Figure 8 The timing diagram (a) is shown; if D[9] = 0 and D[8] = 0, then... 1st =1, the XOR logic result of the two is 1, which also means that after the voltage switching of the first group of 32C, V p and V n The polarity of V has changed, which can determine V. p The range is [3V] REF / 8,V CM You can skip C directly. a8 C a7 C b8 C b7 C d8 C d7 C e8 and C e7 The voltage is switched by setting D[8] and D[7] to 1. Then the voltage of 16C is directly transformed, that is, C a6 and C b6 Connect to V GND C d6 and C e6 Connect to V REF Then, quantization is performed according to normal SAR logic, as shown in the timing diagram (b);
[0102] (3) If D[9] = 1 and D[8] 1st =1, the XOR logic result of the two is 0, which means that after the voltage switching of the first group of 32C, V p and V n If the polarity does not change, then according to normal SAR logic, the voltage of the second group of 32Cs in the array is transformed, i.e., C a8 Connect V GND C d8 Connect V REF Then, when CLK3 is high, a voltage comparison is performed to obtain the third comparison value D[8]. 2nd If D[8] 2nd =0 indicates that V pIt just so happens to fall into [5V] REF / 8.6V REF Within [ / 8], the third group 32C can be skipped, and the voltage switching of 16C in the array can be performed directly, i.e., C a6 and C b6 Connect to V REF C d6 and C e6 Connect to V GND At this point, D[8] = 0, D[7] = 1. Then, quantize according to the SAR logic order, such as... Figure 8 As shown in (c). If D[8] 2nd =1, then quantization is performed according to the traditional SAR logical order, where D[8]=1, such as timing Figure 8 As shown in (d);
[0103] (4) If D[9] = 0 and D[8] 1st =0, the XOR logic result of the two is 0, which means that after the voltage switching of the first group of 32C, V p and V n If the polarity does not change, then according to traditional SAR logic, the second group of 32C capacitors in the array, i.e., C... a8 and C b8 Connect V REF C d8 and C d8 Connect V GND Then, when CLK3 is high, a voltage comparison is performed to obtain the third quantized value D[8]. 2nd If D[8] 2nd =1, then skip the third group of 32C capacitors in the array and directly perform voltage transformation on the 16C capacitor, that is: C a6 and C b6 Connect V GND C d6 and C e6 Connect V REF , where D[8] = 1, D[7] = 0, as shown in timing diagram (e). If D[8] 2nd =0, then quantization is performed according to the traditional SAR logic sequence, where D[8]=0, as shown in the timing diagram (f);
[0104] (5) For the comparison result of the second lowest bit: if V p Greater than V n Then D[1] = 1, C b1 Lower electrode plate reconnected to V GND Conversely, if D[1] = 0, C b1 Lower electrode plate reconnected to V REF Then, compare V. p and V nThe size of D[0] is then determined. This completes one quantization operation of the entire capacitance-fractionated window function SAR ADC.
[0105] Additionally, it should be noted that the SAR ADC structure of this invention is designed based on SMIC 0.18μm CMOS technology. Its supply voltage is 0.6V, and its sampling frequency is 20.84kHz. Therefore, when the input signal is 10.23kHz, Figure 10 The 1024-point Fast Fourier Transform (FFT) curves of the transient ADC output from transistor-level simulation are shown. The SAR ADC has an effective bit width (ENOB) of 9.72 bits, a spurious-free dynamic range (SFDR) of 71.2 dB, and a power consumption of approximately 44.3 nW. (Based on Power / (2)) ENOB The FoM calculation formula defined by *fs) gives FoM approximately 2.56 (fJ / Conv.-step);
[0106] In addition to the methods mentioned in this embodiment, the following transformations can also be made: For an 11-bit SAR ADC, the entire fragmented capacitor array is as follows: Figure 11 As shown, one side should be: 64C, 64C, 64C, 32C, 16C, 8C, 4C, 2C, C, C, 64C, 64C, 64C, 32C, 16C, 8C, 4C, 2C, C, C. The other side of the array is the same. For a 9-bit SAR ADC, the entire fragmented capacitor array is as follows. Figure 12 As shown, one side should be: 16C, 16C, 16C, 8C, 4C, 2C, C, C, 16C, 16C, 16C, 8C, 4C, 2C, C, C. The other side of the array is the same. Furthermore, for other precision ADCs, such as higher precision 12-bit, 13-bit, and 14-bit SAR ADCs, and lower precision 8-bit and 7-bit SAR ADCs, this capacitor-split bypass window timing is applicable to SAR ADCs with any precision of 5 bits and above.
[0107] In summary, the SAR ADC circuit structure proposed in this invention is as follows: Figure 7 As shown, it mainly includes: a sample-and-hold circuit module, a capacitor array module, a comparator, and a SAR logic module. During the sampling phase, the switching circuit is closed, and the analog signal V... in+ and V in- Through a switching circuit and the upper plate of the capacitor array being sampled. Where V in+ The sampled capacitor is placed on the upper plate of the capacitor array, which is connected to the positive terminal of the comparator; V in- The signal is sampled onto the upper plate of the capacitor array, which is connected to the negative terminal of the comparator. At this point, the capacitor array has completed the sampling of the analog signal V. in+and V in- Sampling.
[0108] After sampling, the comparator directly compares the voltages at the positive and negative terminals. The comparison result is input to the logic circuit, where logic control, DAC control, and DAC control are used to switch the voltage of the lower plate of the capacitor array, thereby changing the voltage of the upper plate of the capacitor array. Then, the comparator continues to compare and quantize the voltage of the upper plate of the capacitor array. This process is repeated until the input analog signal is finally quantized into a 10-bit digital signal D[9:0].
[0109] During the quantization process, the logic control also adds a bypass window function judgment module based on the quantization result of the comparator. This module primarily uses the result of an XOR operation on the quantization results before and after the capacitor array voltage switching as the judgment criterion. If the XOR result is 1, bypass window quantization is selected; otherwise, traditional quantization timing is used.
[0110] The content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.
[0111] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. A quantization method for a capacitively-fractured SAR ADC circuit, characterized by, Includes the following steps: Differential analog signals are obtained based on the sampling switch circuit module; Based on the sampling clock signal, the differential analog signal is sampled and processed by the DAC split capacitor array module, and the positive terminal voltage value and the negative terminal voltage value are output. The control clock signal is acquired, and the positive terminal voltage value and the negative terminal voltage value are compared and processed based on the comparator module to output the voltage switching control result. The operation of the comparator module and the voltage switching of the DAC split capacitor array module are controlled according to the voltage switching control result. The step of sampling and processing the differential analog signal according to the sampling clock signal through the DAC split capacitor array module and outputting the positive and negative terminal voltage values specifically includes: Acquire the sampling clock signal; When the sampling clock signal is in the high-level band, the DAC split capacitor array module is triggered to enter the sampling stage, and the differential analog signal is sampled to obtain the positive terminal voltage value and the negative terminal voltage value. The step of sampling and processing the differential analog signal to obtain the positive and negative terminal voltage values includes: The first capacitor in the first capacitor group of the DAC split capacitor array module , , The lower electrode plate and the fourth capacitor in the fourth capacitor group of the DAC split capacitor array module , , The lower electrode is connected to the reference voltage. The second capacitor in the second capacitor group of the DAC split capacitor array module , , The lower electrode plate and the third capacitor in the third capacitor group of the DAC split capacitor array module , , The grounding level of the lower electrode plate ; The first capacitor in the first capacitor group of the DAC split capacitor array module to The lower electrode plate, the second capacitor in the second capacitor group of the DAC split capacitor array module to The lower electrode plate, the third capacitor in the third capacitor group of the DAC split capacitor array module to The lower electrode plate and the fourth capacitor in the fourth capacitor group of the DAC split capacitor array module to The lower electrode is connected to the reference voltage. ; The first differential analog signal The input is fed to the upper plates of the first capacitor bank and the second capacitor bank in the DAC split capacitor array module and sampled as the positive terminal voltage value. The second differential analog signal The input is fed to the upper plates of the third capacitor group and the fourth capacitor group in the DAC split capacitor array module and sampled as the negative terminal voltage value. ; The step of acquiring the control clock signal, comparing the positive terminal voltage value with the negative terminal voltage value based on the comparator module, and outputting the voltage switching control result specifically includes: Acquire a control clock signal, wherein the control clock signal includes a first control clock signal and a second control clock signal; When the first control clock signal is high, the comparator module receives the positive terminal voltage value. With the negative terminal voltage value And perform the first comparison process; If the positive terminal voltage value Greater than the negative terminal voltage value Then output the quantized value. ; If the positive terminal voltage value Less than the negative terminal voltage value Then output the quantized value. ; When the second control clock signal is high, the comparator module receives the positive terminal voltage value. With the negative terminal voltage value A second comparison is then performed to output the quantized value. Among them, quantized value Including quantified values and quantization value If the quantization value and quantization value Alternatively, if the result is 1, output... If the value is positive, then requantize to obtain the quantized value. Then output the quantized value ; Integrate the quantized values and quantization value The voltage switching control results are obtained. The step of controlling the operation of the comparator module and the voltage switching of the DAC split capacitor array module based on the voltage switching control result specifically includes: For the quantized value Make a judgment; If the quantization value Then control the first capacitor in the first capacitor group of the DAC split capacitor array module. The lower electrode plate is switched to ground level. And control the third capacitor in the third capacitor group of the DAC split capacitor array module. The lower plate is switched to the reference voltage. ; If the quantization value Then control the second capacitor in the second capacitor group of the DAC split capacitor array module. The lower plate is switched to the reference voltage. And control the fourth capacitor in the fourth capacitor group of the DAC split capacitor array module. The lower electrode plate is switched to ground level. ; Introducing a bypass window function for the quantized value and the quantized value Perform an XOR logic check and switch the voltage of the DAC split capacitor array module.
2. The quantization method for a SAR ADC circuit based on capacitor decomposition according to claim 1, characterized in that, The introduction of a bypass window function applies to the quantized value. and the quantized value The step of performing an XOR logic judgment and switching the voltage of the DAC split capacitor array module specifically includes: Introducing a bypass window function for the quantized value and the quantized value Perform an XOR logic check; If the quantization value and the quantized value If they are not equal, the XOR logic result is 1, and the first capacitor in the first capacitor group is... The lower electrode plate, the second capacitor in the second capacitor group The lower electrode plate, the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate performs voltage switching; If the quantization value and the quantized value If they are equal, the XOR logic result is 0, and the first capacitor in the first capacitor group is... The lower electrode plate, the second capacitor in the second capacitor group The lower electrode plate, the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate performs voltage switching.
3. The quantization method for a SAR ADC circuit based on capacitor decomposition according to claim 2, characterized in that, If the quantization value and the quantized value If they are not equal, the XOR logic result is 1, and the first capacitor in the first capacitor group is... The lower electrode plate, the second capacitor in the second capacitor group The lower electrode plate, the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The step of switching the voltage on the lower electrode plate specifically includes: If the quantization value And the quantization value Then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower plate is switched to the reference voltage. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate is switched to ground level. ; If the quantization value And the quantization value Then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower electrode plate is switched to ground level. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower plate is switched to the reference voltage. .
4. The quantization method for a SAR ADC circuit based on capacitor decomposition according to claim 3, characterized in that, If the quantization value and the quantized value If they are equal, the XOR logic result is 0, and the first capacitor in the first capacitor group is... The lower electrode plate, the second capacitor in the second capacitor group The lower electrode plate, the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The step of switching the voltage on the lower electrode plate specifically includes: If the quantization value and the quantized value If both are 1, then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower electrode plate is switched to ground level. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower plate is switched to the reference voltage. ; Introducing the quantization value If the quantization value Then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower plate is switched to the reference voltage. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate is switched to ground level. If the quantization value Then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower electrode plate is switched to ground level. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower plate is switched to the reference voltage. ; If the quantization value and the quantized value If all values are 0, then for the first capacitor in the first capacitor group... The lower electrode and the second capacitor in the second capacitor group The lower plate is switched to the reference voltage. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate is switched to ground level. ; Introducing the quantization value If the quantization value Then for the first capacitor in the first capacitor group The lower electrode and the second capacitor in the second capacitor group The lower electrode plate is switched to ground level. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower plate is switched to the reference voltage. If the quantization value If the voltage is not switched, then the first capacitor in the first capacitor group will be switched. The lower electrode and the second capacitor in the second capacitor group The lower plate is switched to the reference voltage. For the third capacitor in the third capacitor group The lower electrode and the fourth capacitor in the fourth capacitor group The lower electrode plate is switched to ground level. .
5. A SAR ADC circuit based on capacitance splitting for implementing the quantization method of the SAR ADC circuit based on capacitance splitting as described in any one of claims 1-4, characterized in that, The system includes a sampling switch circuit module, a DAC split capacitor array module, a comparator module, and a logic control circuit module. The output of the sampling switch circuit module is connected to the first input of the DAC split capacitor array module. The output of the DAC split capacitor array module is connected to the first input of the comparator module. The output of the comparator module is connected to the input of the logic control circuit module. The output of the logic control circuit module is fed back to the second input of both the DAC split capacitor array module and the comparator module. The sampling switch circuit module is used to acquire differential analog signals; The DAC split capacitor array module is used to sample the differential analog signal onto the upper plate of the capacitor in the DAC split capacitor array module according to the sampling clock signal, and output the positive terminal voltage value and the negative terminal voltage value. The comparator module is used to acquire the control clock signal, compare the positive terminal voltage value with the negative terminal voltage value, and output the voltage switching control result. The logic control circuit module is used to control the operation of the comparator module and the voltage switching of the DAC split capacitor array module according to the voltage switching control result; The DAC split capacitor array module includes a first sub-capacitor array module, a second sub-capacitor array module, a third sub-capacitor array module, and a fourth sub-capacitor array module. The input terminal of the first sub-capacitor array module is connected to the first output terminal of the sampling switch circuit module. The output terminal of the first sub-capacitor array module is connected to the input terminal of the second sub-capacitor array module. The output terminal of the second sub-capacitor array module is connected to the positive terminal of the comparator module. The input terminal of the third sub-capacitor array module is connected to the second output terminal of the sampling switch circuit module. The output terminal of the third sub-capacitor array module is connected to the input terminal of the fourth sub-capacitor array module. The output terminal of the fourth sub-capacitor array module is connected to the negative terminal of the comparator module. Wherein: The first sub-capacitor array module, the second sub-capacitor array module, the third sub-capacitor array module, and the fourth sub-capacitor array module are used to acquire the sampling clock signal, and to sample the differential analog signal according to the sampling clock signal, and output the positive terminal voltage value and the negative terminal voltage value.
6. The SAR ADC circuit based on capacitor decomposition according to claim 5, characterized in that, The first sub-capacitor array module includes a first capacitor group and a first switch group; the second sub-capacitor array module includes a second capacitor group and a second switch group; the third sub-capacitor array module includes a third capacitor group and a third switch group; and the fourth sub-capacitor array module includes a fourth capacitor group and a fourth switch group, wherein: The first capacitor bank includes multiple first capacitors. The first switch group includes a plurality of first switches, and the first terminal of each of the first capacitors is used to receive a first differential analog signal. The second terminals of the first capacitors are all electrically connected to the first terminal of the first switch, and the second terminal of the first switch is selectively connected to a reference voltage. Reference voltage or ground level ; The second capacitor bank includes multiple second capacitors. The second switch group includes a plurality of second switches, and the first terminal of each second capacitor is used to receive a first differential analog signal. The second terminals of the second capacitors are all electrically connected to the first terminal of the second switch, and the second terminal of the second switch is selectively connected to a reference voltage. Reference voltage or ground level ; The third capacitor bank includes multiple third capacitors. The third switch group includes multiple third switches, and the first terminal of each third capacitor is used to receive a second differential analog signal. The second terminals of the third capacitors are all electrically connected to the first terminal of the third switch, and the second terminal of the third switch is selectively connected to a reference voltage. Reference voltage or ground level ; The fourth capacitor bank includes multiple fourth capacitors. The fourth switch group includes multiple fourth switches, and the first terminal of each of the fourth capacitors is used to receive the second differential analog signal. The second terminals of the fourth capacitor are all electrically connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is selectively connected to a reference voltage. Reference voltage or ground level .