Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a plurality of sub-pixels disposed in a display area; at least one barrier dam disposed in a peripheral area; a first electrode layer disposed on a substrate; a pixel defining layer disposed on the side of the first electrode layer away from the substrate; a spacer layer disposed on the side of the pixel defining layer away from the substrate; and an encapsulation structure disposed on the side of the spacer layer away from the substrate, including a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The display panel includes a plurality of spacers located in the spacer layer, the plurality of spacers including a first spacer located in the peripheral area, and, among the plurality of spacers, the first spacer is located at a position furthest from the center of the display area; the second encapsulation layer includes a boundary located on the side of the second encapsulation layer away from the display area; and the orthographic projection of the boundary of the second encapsulation layer on the substrate is located on the side of the orthographic projection of at least one barrier dam on the substrate near the display area, and the orthographic projection of the first spacer on the substrate is located on the side of the orthographic projection of the boundary of the second encapsulation layer on the substrate near the display area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, Organic Light Emitting Diode (OLED) display panels are increasingly being used in various electronic devices due to their advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed. In the fabrication process of OLED display panels, light-emitting materials need to be deposited at each opening defined by the pixel delimiting layer to form the light-emitting layer. For example, protruding supports on the backplate can be used to separate the photomask from the backplate, avoiding large-area contact between the backplate and the photomask.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display panel is provided, comprising: a substrate, the substrate including a display area and a peripheral area; a plurality of sub-pixels disposed in the display area, each sub-pixel including a first electrode, a second electrode, and a functional layer located between the first electrode and the second electrode; at least one barrier dam disposed in the peripheral area; a first electrode layer disposed on the substrate, the first electrodes of the plurality of sub-pixels being located on the first electrode layer; a pixel defining layer disposed on a side of the first electrode layer away from the substrate; a spacer layer disposed on the pixel defining layer away from the substrate; and an encapsulation structure disposed on the side of the spacer layer away from the substrate, the encapsulation structure comprising: a first encapsulation layer disposed on the side of the spacer layer away from the substrate; a second encapsulation layer disposed on the side of the first encapsulation layer away from the substrate; and a second encapsulation layer disposed on the side of the second encapsulation layer away from the substrate. A third encapsulation layer on one side, wherein the first encapsulation layer and the third encapsulation layer are inorganic material encapsulation layers, and the second encapsulation layer is an organic material encapsulation layer; wherein the display panel includes a plurality of spacers located in the spacer layer, the plurality of spacers including a first spacer located in the peripheral region, and wherein, among the plurality of spacers, the first spacer is located at a position furthest from the center of the display region; the second encapsulation layer includes a boundary located on the side of the second encapsulation layer furthest from the display region, the boundary being the boundary of the portion of the second encapsulation layer extending from the display region; and the orthographic projection of the boundary of the second encapsulation layer on the substrate is located on the side of the orthographic projection of the at least one barrier dam on the substrate closer to the display region, and the orthographic projection of the first spacer on the substrate is located on the side of the orthographic projection of the boundary of the second encapsulation layer on the substrate closer to the display region.

[0005] According to some exemplary embodiments, the peripheral region includes a first side region and a second side region, the first side region and the second side region being located on opposite sides of the display region along a first direction; the display panel further includes at least one scan driving circuit disposed in at least one of the first side region and the second side region of the peripheral region, the scan driving circuit being used to provide scan driving signals to pixel driving circuits of at least a portion of sub-pixels; and the display panel includes a plurality of first spacers, a portion of the plurality of first spacers being located in at least one of the first side region and the second side region of the peripheral region, the orthographic projection of the portion of the first spacers located in at least one of the first side region and the second side region falling within the orthographic projection of the at least one scan driving circuit on the substrate.

[0006] According to some exemplary embodiments, the peripheral area further includes a third side area, a fourth side area, and a plurality of corner areas. The third side area and the fourth side area are located on opposite sides of the display area along a second direction. The plurality of corner areas are located between adjacent pairs of the first side area, the third side area, the second side area, and the fourth side area, respectively. A portion of the at least one scan driving circuit is also located in at least one corner area. A portion of the plurality of first spacers is located in the at least one corner area, and the orthographic projection of the portion of the first spacers located in the at least one corner area falls within the orthographic projection of the at least one scan driving circuit on the substrate.

[0007] According to some exemplary embodiments, the at least one scanning driving circuit includes a first scanning driving circuit and a second scanning driving circuit. The first scanning driving circuit is used to provide a light emission control signal to the pixel driving circuit of at least a portion of the sub-pixels, and the second scanning driving circuit is used to provide a gate scanning signal to the pixel driving circuit of at least a portion of the sub-pixels. The orthographic projection of the first scanning driving circuit on the substrate is located on the side of the orthographic projection of the second scanning driving circuit on the substrate that is away from the display area. A portion of the orthographic projection of the first spacer on the substrate falls within the orthographic projection of the first scanning driving circuit on the substrate.

[0008] According to some exemplary embodiments, a portion of the boundary of the second encapsulation layer is projected onto the substrate and falls within the projected image of the at least one scan driving circuit onto the substrate.

[0009] According to some exemplary embodiments, a portion of the boundary of the second encapsulation layer is projected onto the substrate and falls within the projection of the first scanning drive circuit onto the substrate.

[0010] According to some exemplary embodiments, the display panel further includes: a first voltage lead for transmitting a first voltage; the orthographic projection of the at least one blocking dam on the substrate at least partially overlaps with the orthographic projection of the first voltage lead on the substrate; and a portion of the orthographic projection of the first spacer on the substrate is spaced apart from the orthographic projection of the first voltage lead on the substrate, and the orthographic projection of the first spacer on the substrate is located on the side of the orthographic projection of the first voltage lead on the substrate closer to the display area.

[0011] According to some exemplary embodiments, at least a portion of the boundary of the second encapsulation layer is orthographically projected onto the substrate at a distance from the orthographic projection of the first voltage lead onto the substrate, and the orthographic projection of at least a portion of the boundary of the second encapsulation layer onto the substrate is located on the side of the orthographic projection of the first voltage lead onto the substrate closer to the display area.

[0012] According to some exemplary embodiments, the at least one barrier includes a first barrier located at the center closest to the center of the display area; and the orthographic projection of the first spacer on the substrate is spaced apart from the orthographic projection of the first barrier on the substrate by a first distance, the first distance being greater than 100 micrometers.

[0013] According to some exemplary embodiments, the orthographic projection of the boundary of the second encapsulation layer on the substrate is separated from the orthographic projection of the first barrier dam on the substrate by a second distance, the second distance being less than the first distance, and the second distance being greater than 100 micrometers.

[0014] According to some exemplary embodiments, at least one of the first distance and the second distance is between 100 and 300 micrometers.

[0015] According to some exemplary embodiments, the first voltage lead includes a first lead boundary near the display area, the first lead boundary being the boundary of the first voltage lead's orthographic projection on the substrate closest to the display area; the first barrier dam includes a first barrier dam boundary near the display area, the first barrier dam boundary being the boundary of the first barrier dam's orthographic projection on the substrate closest to the display area; the first lead boundary is closer to the display area than the first barrier dam boundary, and in the transition region between the first lead boundary and the first barrier dam boundary, the packaging structure includes only a first packaging layer and a third packaging layer, and the plurality of spacers are not disposed in the transition region.

[0016] According to some exemplary embodiments, a plurality of the first spacers are spaced apart along a first contour line, the first contour line being a contour line that surrounds the display area and has a generally similar orientation to the outer contour line of the display area, the first contour line being spaced apart from the outer contour line of the display area; and the plurality of spacers are arrayed in a first direction and a second direction, starting from the outermost first spacer and moving toward the center of the display area.

[0017] According to some exemplary embodiments, the plurality of spacers are arranged at a first interval in a first direction and at a second interval in a second direction, wherein the ratio of the first interval to the second interval is between 0.8 and 1.2.

[0018] According to some exemplary embodiments, for a first spacer, the distance between the first spacer and the spacer adjacent to it in a first direction is substantially equal to the first spacing distance; and / or, for a first spacer, the distance between the first spacer and the spacer adjacent to it in a second direction is substantially equal to the second spacing distance.

[0019] According to some exemplary embodiments, for two adjacent corner regions in a first direction, the distribution of spacers in the two corner regions is symmetrical with respect to a first axis of symmetry; and / or, for two adjacent corner regions in a second direction, the distribution of spacers in the two corner regions is symmetrical with respect to a second axis of symmetry.

[0020] According to some exemplary embodiments, the display panel further includes: a planarization layer located on the side of the first electrode layer near the substrate; an auxiliary conductive portion located in the peripheral region, the auxiliary conductive portion being located in the first electrode layer and electrically connected to the first voltage lead; a plurality of openings disposed in the auxiliary conductive portion, the plurality of openings respectively exposing a portion of the planarization layer; and a plurality of first covering portions located in the pixel defining layer, the plurality of first covering portions respectively covering the plurality of openings.

[0021] According to some exemplary embodiments, at least a portion of the orthographic projection of the first spacer on the substrate at least partially overlaps with at least a portion of the orthographic projection of the first cover on the substrate at least partially; and / or, at least a portion of the orthographic projection of the first spacer on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion on the substrate at least partially.

[0022] According to some exemplary embodiments, the plurality of spacers includes a second spacer located in the peripheral region, the orthographic projection of the second spacer on the substrate being located on the side of the orthographic projection of the first spacer on the substrate closer to the display area; and a portion of the orthographic projection of the second spacer on the substrate falling within the orthographic projection of the second scan driving circuit on the substrate.

[0023] According to some exemplary embodiments, at least a portion of the orthographic projection of the second spacer on the substrate at least partially overlaps with at least a portion of the orthographic projection of the first cover portion on the substrate at least partially; and / or, at least a portion of the orthographic projection of the second spacer on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion on the substrate at least partially.

[0024] In another aspect, a display device is provided, wherein the display panel described above is included. Attached Figure Description

[0025] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0026] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure.

[0027] Figure 2 This is a plan view of a display device according to some exemplary embodiments of the present disclosure, wherein the distribution of spacers in the display panel is schematically shown.

[0028] Figure 3A The display panel is based on some exemplary embodiments of this disclosure. Figure 2 A schematic diagram of the cross section intercepted by line AA' in the diagram.

[0029] Figure 3B yes Figure 3A A magnified view of part VII in the image.

[0030] Figure 4 This is a plan view of a display panel in the related art, which schematically illustrates the distribution of spacers in the display panel in the related art.

[0031] Figure 5 It is the display panel in the related technology. Figure 4 A schematic diagram of the cross section taken by line BB' in the diagram.

[0032] Figure 6 yes Figure 4 A magnified view of part I in the image.

[0033] Figure 7 The display panel is based on some exemplary embodiments of this disclosure. Figure 2 A schematic diagram of the cross section intercepted by line CC' in the diagram.

[0034] Figures 8 to 11 They are Figure 2The enlarged views of portions II, III, IV, and V schematically illustrate the distribution of spacers in various corner regions of a display panel according to some exemplary embodiments of the present disclosure.

[0035] Figure 12 yes Figure 7 A magnified view of part of VI in the image.

[0036] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0037] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0038] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0039] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0040] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0041] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0042] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0043] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0044] Embodiments of this disclosure provide a display panel and a display device. The display panel includes: a substrate, the substrate including a display area and a peripheral area; a plurality of sub-pixels disposed in the display area, each sub-pixel including a first electrode, a second electrode, and a functional layer located between the first electrode and the second electrode; at least one barrier dam disposed in the peripheral area; a first electrode layer disposed on the substrate, the first electrodes of the plurality of sub-pixels being located on the first electrode layer; a pixel defining layer disposed on the side of the first electrode layer away from the substrate; a spacer layer disposed on the side of the pixel defining layer away from the substrate; and an encapsulation structure disposed on the side of the spacer layer away from the substrate, the encapsulation structure including: a first encapsulation layer disposed on the side of the spacer layer away from the substrate; a second encapsulation layer disposed on the side of the first encapsulation layer away from the substrate; and a third encapsulation layer disposed on the side of the second encapsulation layer away from the substrate. The system comprises three encapsulation layers, wherein the first and third encapsulation layers are inorganic material encapsulation layers, and the second encapsulation layer is an organic material encapsulation layer. The display panel includes a plurality of spacers located within the spacer layer. The plurality of spacers includes a first spacer located in the peripheral region, and the first spacer is located at the position furthest from the center of the display region. The second encapsulation layer includes a boundary located on the side of the second encapsulation layer furthest from the display region, the boundary being the boundary of the portion of the second encapsulation layer extending from the display region. The orthographic projection of the boundary of the second encapsulation layer on the substrate is located on the side of the orthographic projection of the at least one barrier dam on the substrate closer to the display region. The orthographic projection of the first spacer on the substrate is located on the side of the orthographic projection of the boundary of the second encapsulation layer on the substrate closer to the display region. In embodiments of this disclosure, the outermost first spacer is located inside the boundary of the second encapsulation layer. Thus, a second encapsulation layer is provided at each location of the spacer, and this second encapsulation layer can act as a buffer, preventing the spacers from puncturing the first encapsulation layer. Therefore, this setup can effectively eliminate the risk of cracking in the first encapsulation layer, thereby improving the yield of the display panel.

[0045] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure. Figure 2 This is a plan view of a display device according to some exemplary embodiments of the present disclosure, wherein the distribution of spacers in the display panel is schematically shown. Figure 3A The display panel is based on some exemplary embodiments of this disclosure. Figure 2 A schematic diagram of the cross section intercepted by line AA' in the diagram.

[0046] Combined with reference Figure 1 and Figure 2 The display device 1000 may include a display panel. The display panel may include a substrate 10, and the substrate 10 may include a display area AA and a peripheral area NA located on at least one side of the display area. It should be noted that in... Figure 1 In the illustrated embodiment, the peripheral region NA surrounds the display region AA. However, the embodiments of this disclosure are not limited to this. In other embodiments, the peripheral region NA may be located on at least one side of the display region AA, but does not surround the display region AA.

[0047] The display panel may include multiple pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit used to display an image. For example, the pixel unit P may include a light-emitting device that emits white light and / or colored light.

[0048] Pixel units P can be configured in multiple ways, arranged in an array along rows extending in a first direction (e.g., row direction) X and columns extending in a second direction (e.g., column direction) Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units P, and pixel units P can be arranged in various forms. For example, pixel units P can be arranged such that the direction inclined relative to the first direction X and the second direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0049] A pixel unit P can include multiple sub-pixels. For example, a pixel unit P can include three sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. As another example, a pixel unit P can include four sub-pixels: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For instance, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, the third sub-pixel SP3 can be a blue sub-pixel, and the fourth sub-pixel can be a white sub-pixel.

[0050] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the first sub-pixel SP1 may include a first light-emitting element and a first pixel driving circuit for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element and a second pixel driving circuit for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element and a third pixel driving circuit for driving the third light-emitting element, and the third light-emitting element may emit blue light.

[0051] For example, in an OLED display panel, the light-emitting element of a subpixel may include an anode, a light-emitting material layer, and a cathode stacked together. For example, the light-emitting region of a subpixel may be the region corresponding to a portion of the light-emitting material layer sandwiched between and in contact with the anode and cathode. For example, a pixel-defining layer is formed on the anode, the pixel-defining layer has an opening exposing at least a portion of the anode, the light-emitting material layer is at least partially formed within the opening of the pixel-defining layer, and a cathode is formed on top of it; the light-emitting region of the subpixel may be the region defined by the opening of the pixel-defining layer. The light-emitting material layer may include one or more layers selected from hole injection layers, hole transport layers, light-emitting layers, hole blocking layers, electron transport layers, and electron injection layers, and may also include other functional film layers in addition to the above layers. These layers may include organic materials or inorganic materials such as quantum dots.

[0052] Reference Figure 1 The display panel may include components such as a load compensation unit 100, a test circuit 200, a scan drive circuit 300, and a multiplexer 400 located in the peripheral area NA.

[0053] The display area AA may include a first boundary AA1, a second boundary AA2, a third boundary AA3, and a fourth boundary AA4 (e.g., the top boundary, the bottom boundary, the left boundary, and the right boundary) connected in sequence.

[0054] In some embodiments of this disclosure, the orthographic projection of the display area AA onto the substrate 10 can be a rounded rectangle. For ease of description, the four rounded corners of the rounded rectangle can be referred to as the first rounded corner 10A, the second rounded corner 10B, the third rounded corner 10C, and the fourth rounded corner 10D, respectively. For example, the first rounded corner 10A can be located at... Figure 1 The second rounded corner 10B can be located at the upper left corner of the middle. Figure 1 The third rounded corner 10C can be located at the upper right corner of the middle. Figure 1 The fourth rounded corner 10D can be located at the bottom left corner of the image. Figure 1 It is located in the bottom right corner.

[0055] The test circuit 200 can be located on one side of the peripheral area NA adjacent to the first boundary AA1, and the test circuit 200 is arranged opposite to the first boundary AA1, the first rounded corner 10A and the second rounded corner 10B.

[0056] For example, the test circuit 200 may include a plurality of test pins, which may be used to provide test signals, such as data signals for a plurality of pixel units P in the display area AA.

[0057] The multiplexer 400 can be located on one side of the peripheral area NA adjacent to the second boundary AA2, and the multiplexer 400 is arranged opposite to the second boundary AA2, the third rounded corner 10C and the fourth rounded corner 10D.

[0058] For example, the multiplexer 400 can time-division multiplex signal lines in a wiring area. Figure 1 As shown, the display panel includes an integrated circuit (IC) disposed in the peripheral area NA and a wiring area 500 located between the IC and a multiplexer 400. Each signal output by the IC is transmitted to the multiplexer 400 via signal lines in the wiring area 500. Then, under the control of the signal control terminal of the multiplexer 400, each signal is output to each pixel unit P in the display area AA. By using the multiplexer 400, the number of signal lines arranged in the wiring area can be reduced, thereby reducing the wiring pressure in the wiring area.

[0059] The scan drive circuit 300 can be located on one side of the peripheral region NA adjacent to the third boundary AA3 and on one side of the peripheral region NA adjacent to the fourth boundary AA4. It should be noted that, although... Figure 1 The diagram shows the driving circuit located on the left and right sides of the display area AA; however, embodiments of this disclosure are not limited thereto, and the driving circuit may be located at any suitable location in the peripheral area NA.

[0060] For example, the scan driving circuit 300 may include at least one of a first scan driving circuit (e.g., a light emission control scan driving circuit) and a second scan driving circuit (a gate scan driving circuit). For instance, the gate scan driving circuit and the light emission control scan driving circuit may employ GOA technology, meaning the scan driving circuit 300 may include at least one of Gate GOA and EMGOA. In GOA technology, the gate driving circuit and the light emission control scan driving circuit are directly disposed on the array substrate, replacing an external driving chip. Each GOA unit serves as a first-level shift register, and each shift register is electrically connected to a gate line or a light emission control line. The successive output of turn-on voltages by each shift register sequentially achieves line-by-line scanning of pixels. In some embodiments, each shift register may also be connected to multiple gate lines or multiple light emission control lines. This adapts to the trend of high resolution and narrow bezels in display panels.

[0061] In embodiments of this disclosure, the scan driving circuit 300 may include a plurality of thin-film transistors and at least one capacitor. For example, each of Gate GOA and EM GOA may include a plurality of thin-film transistors and at least one capacitor. In this document, the expression "orthographic projection of the scan driving circuit onto the substrate" can refer to the orthographic projection of the region where the scan driving circuit is located onto the substrate. Specifically, the scan driving circuit may include multiple rows of shift registers, each shift register including a plurality of thin-film transistors and at least one capacitor. The region where the scan driving circuit is located can be defined by the boundaries of the thin-film transistors or capacitors constituting all rows of shift registers. For example, the at least one scan driving circuit 300 may include a first scan driving circuit 301 and a second scan driving circuit 302, wherein the first scan driving circuit 301 may include an EM GOA circuit, and the second scan driving circuit 302 may include a Gate GOA circuit. The first scan driving circuit 301 may include multiple rows of shift registers constituting the EM GOA. Each shift register may include multiple thin-film transistors and at least one capacitor. The region where the first scan driving circuit is located can be defined by the outer boundaries of the thin-film transistors or capacitors of all rows of shift registers constituting the EM GOA. Accordingly, the orthographic projection of the first scan driving circuit on the substrate can represent the orthographic projection of the region where the EM GOA circuit is located on the substrate. The second scan driving circuit 302 may include multiple rows of shift registers constituting the GATE GOA. Each shift register may include multiple thin-film transistors and at least one capacitor. The region where the second scan driving circuit is located can be defined by the outer boundaries of the thin-film transistors or capacitors of all rows of shift registers constituting the GATE GOA. Accordingly, the orthographic projection of the second scan driving circuit on the substrate can represent the orthographic projection of the region where the GATE GOA circuit is located on the substrate. "Within the orthographic projection of the at least one scan driving circuit on the substrate" means the orthographic projection of the region where at least one of the EM GOA circuit and the GATE GOA circuit is located on the substrate.

[0062] The display panel may include multiple load compensation units 100. For example... Figure 1 and Figure 2 As shown, some of the multiple load compensation units 100 are located in the peripheral area NA near the first rounded corner 10A, and others are located in the peripheral area NA near the second rounded corner 10B. All the multiple load compensation units 100 are located between the test circuit 200 and the display area AA.

[0063] In embodiments of this disclosure, each sub-pixel SP1, SP2, or SP3 may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the light-emitting device may include a first electrode, a second electrode, and a light-emitting material layer located between the first and second electrodes. The pixel driving circuit may include components such as transistors and capacitors. The pixel driving circuit receives signals from signal lines disposed on the display panel, generates a current to drive the light-emitting device, and achieves the purpose of driving the light-emitting device to emit light by connecting to one of the first or second electrodes. For example, the pixel driving circuit is disposed on a substrate, and the light-emitting device is located on the side of the pixel driving circuit away from the substrate. For example, the pixel driving circuit may include circuit structures commonly used in the art, such as 7T1C, 7T2C, 8T2C, or 4T1C. For example, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0064] Continue to refer to Figure 1 The display panel may further include at least one barrier dam 30 disposed on the substrate 10, the barrier dam 30 being located in the peripheral region NA. For example, each barrier dam 30 may be disposed circumferentially around the peripheral region NA, i.e., in a ring, to surround the display region AA. Figure 1 As shown, at least one barrier dam 30 is disposed on the side of the scan drive circuit 300 away from the center AAO of the display area AA. By providing at least one barrier dam 30, external moisture and oxygen can be prevented from entering the display panel, thereby avoiding display defects.

[0065] In embodiments of this disclosure, the display area AA has a center AAO and two axes of symmetry AX1 and AX2. In some examples, the first axis of symmetry AX1 is a straight line extending along the second direction Y through the center AAO, and the second axis of symmetry AX2 is a straight line extending along the first direction X through the center AAO. Embodiments of this disclosure are not limited to the above examples; for example, at least one of the first axis of symmetry AX1 and the second axis of symmetry AX2 may not pass through the center AAO. It should be noted that the center AAO and the two axes of symmetry AX1 and AX2 are imaginary centers and axes proposed for ease of description and do not imply that there are physical centers and axes in the display panel.

[0066] The embodiments of this disclosure will be further described in detail below, taking the top-gate TFT as an example of the thin-film transistor in the display panel.

[0067] Combined with reference Figure 2 and Figure 3AThe display panel includes: a substrate 10, a barrier layer or buffer layer BL disposed on the substrate 10, a semiconductor layer ACT disposed on the side of the barrier layer or buffer layer BL away from the substrate 10, a first insulating layer 111 disposed on the side of the semiconductor layer ACT away from the substrate 10, a first conductive layer 121 disposed on the side of the first insulating layer 111 away from the substrate 10, a second insulating layer 112 disposed on the side of the first conductive layer 121 away from the substrate 10, a second conductive layer 122 disposed on the side of the second insulating layer 112 away from the substrate 10, a third insulating layer 113 disposed on the side of the second conductive layer 122 away from the substrate 10, a first planarization layer PLN1 disposed on the side of the third insulating layer 113 away from the substrate 10, a third conductive layer 123 disposed on the side of the first planarization layer PLN1 away from the substrate 10, a second planarization layer PLN2 disposed on the side of the third conductive layer 123 away from the substrate 10, a first electrode layer 124 disposed on the side of the second planarization layer PLN2 away from the substrate 10, and a pixel delimiting layer PDL disposed on the side of the first electrode layer 124 away from the substrate 10.

[0068] The pixel defining layer (PLD) defines multiple openings (PLDOs), and the light-emitting element 52 can be located within these openings. The light-emitting element 52 may include an anode 521, a light-emitting layer 522, and a cathode 523, with the light-emitting layer 522 sandwiched between the anode 521 and the cathode 523. It should be noted that the term "light-emitting layer" here is an overview of the various functional layers of the OLED light-emitting element; for example, it may include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, and an organic light-emitting layer.

[0069] In embodiments of this disclosure, the pixel driving circuit for driving each sub-pixel may include a plurality of thin-film transistors 51. Each thin-film transistor 51 may include an active layer 511, a gate 513, a source 515, and a drain 516. The active layer 511 may be located in the semiconductor layer ACT, the gate 513 may be located in the first conductive layer 121, and the source 515 and drain 516 may be located in the second conductive layer 122. The source 515 and drain 516 of the thin-film transistor are electrically connected to the active layer 511 through their respective vias, grooves, or conductive plugs 517.

[0070] For example, the third conductive layer 123 can be made of the same conductive material as the second conductive layer 122. The third conductive layer 123 can be electrically connected to the source or drain of the thin-film transistor via conductive plugs formed in vias of the first planarization layer PLN1. The anode 521 or cathode 523 can be electrically connected to the third conductive layer 123 via conductive plugs formed in vias of the second planarization layer PLN2. For example, in the illustrated embodiment, the second conductive layer 122 is electrically connected to the drain 516, and the anode 521 is electrically connected to the third conductive layer 123. Thus, the anode 521 is electrically connected to the drain 516.

[0071] Reference Figure 2 and Figure 3A The display panel may further include a spacer layer PSL disposed on the side of the pixel defining layer PDL away from the substrate 10. The display panel includes a plurality of spacers PS located in the spacer layer PSL.

[0072] The display panel may further include an encapsulation structure 53 disposed on the side of the spacer layer PSL away from the substrate 10. The encapsulation structure 53 includes: a first encapsulation layer 531 disposed on the side of the spacer layer away from the substrate; a second encapsulation layer 532 disposed on the side of the first encapsulation layer away from the substrate; and a third encapsulation layer 533 disposed on the side of the second encapsulation layer away from the substrate. The first encapsulation layer 531 and the third encapsulation layer 533 are inorganic material encapsulation layers, and the second encapsulation layer 532 is an organic material encapsulation layer. For example, the first encapsulation layer 531 and the third encapsulation layer 533 can be formed by a deposition process such as chemical vapor deposition, and the second encapsulation layer 532 can be formed by an inkjet printing process.

[0073] Figure 4 This is a plan view of a display panel in the related art, which schematically illustrates the distribution of spacers in the display panel in the related art. Figure 5 It is the display panel in the related technology. Figure 4 A schematic diagram of the cross section taken by line BB' in the diagram. Figure 6 yes Figure 4 A magnified view of part I in the image.

[0074] In the manufacturing process of OLED display panels, light-emitting materials need to be deposited at each opening of the pixel defining layer (PDL). Specifically, a photomask, such as a fine metal mask (FMM), is used for the deposition process to form the light-emitting layer. In this deposition process, multiple spacers (PS) formed on the backplane can be used to separate the photomask from the backplane, avoiding large-area contact between the backplane and the photomask, thus facilitating the deposition of light-emitting materials at each opening. When the spacers (PS) come into contact with the photomask, equipment alignment can cause the photomask and the spacers (PS) to scrape against each other, resulting in PS foreign matter. During the formation of the encapsulation structure, the presence of PS foreign matter makes it difficult to form a complete film layer in the first encapsulation layer 531. Specifically, refer to... Figures 4 to 6 A spacer PS is formed at the boundary of the second encapsulation layer 532 away from the center of the display area. That is, the orthographic projection of the spacer PS onto the substrate 10 is at least partially located outside the boundary of the second encapsulation layer 532. Thus, during the formation of the encapsulation structure, due to the influence of shadows, the thickness of the first encapsulation layer 531 in the region where the boundary of the second encapsulation layer 532 is located cannot be guaranteed, potentially leading to insufficient thickness of the first encapsulation layer 531 at this location. Simultaneously, the inorganic material itself is relatively brittle, and the orthographic projection of the spacer PS onto the substrate 10 is small, meaning the spacer PS is sharp and columnar. Therefore, the spacer PS can easily puncture the first encapsulation layer 531. In other words, the first encapsulation layer 531 may break at the location of foreign matter accumulation or at the boundary of the second encapsulation layer 532, such as... Figure 5 As shown. Subsequent encapsulation processes can only encapsulate the surface and cannot improve the morphology of the fracture site. In reliability testing or high-temperature and high-humidity environments, moisture and oxygen can easily enter the display panel through the fracture site of the first encapsulation layer, causing device failure and defects.

[0075] Figure 7 The display panel is based on some exemplary embodiments of this disclosure. Figure 2 A schematic diagram of the cross section intercepted by line CC' in the diagram. Figures 8 to 11 They are Figure 2 The enlarged views of portions II, III, IV, and V schematically illustrate the distribution of spacers in various corner regions of a display panel according to some exemplary embodiments of the present disclosure. Figure 12 yes Figure 7 A magnified view of part of VI in the image.

[0076] Combined with reference Figure 2 , Figure 3A , Figures 7 to 12The display panel includes a plurality of spacers PS located in the spacer layer, the plurality of spacers including a first spacer PS1 located in the peripheral region, and the first spacer PS1 located at the center AAO furthest from the display region among the plurality of spacers PS.

[0077] For example, multiple first spacers PS1 are distributed at intervals along a first contour line LK1, where the first contour line LK1 is a contour line that surrounds the display area AA and has a roughly the same direction as the outer contour line LKA of the display area AA, and the first contour line LK1 is spaced apart from the outer contour line LKA of the display area.

[0078] The plurality of spacers PS are arranged in an array along the first direction X and the second direction Y, starting from the outermost first spacer PS1 and moving towards the center AAO of the display area. That is, the first spacer PS1 includes the outermost ring of spacers.

[0079] For example, the plurality of spacers PS are arranged with a first spacing distance PT1 in the first direction X and a second spacing distance PT2 in the second direction Y, wherein the ratio of the first spacing distance PT1 to the second spacing distance PT2 is between 0.8 and 1.2, including the two endpoints 0.8 and 1.2. For example, at least one of the first spacing distance PT1 and the second spacing distance PT2 is between 150 and 300 micrometers.

[0080] In embodiments of this disclosure, for the first spacer PS1, the distance between the first spacer PS1 and the spacer PS adjacent to it in the first direction X is substantially equal to the first gap distance PT1. For the first spacer PS1, the distance between the first spacer PS1 and the spacer PS adjacent to it in the second direction Y is substantially equal to the second gap distance PT2.

[0081] In embodiments of this disclosure, the peripheral area NA includes a first side area NA1, a second side area NA2, a third side area NA3, a fourth side area NA4, and multiple corner areas NA5, NA6, NA7, and NA8. For example, the first side area NA1 and the second side area NA2 are located on opposite sides of the display area AA along a first direction X. The third side area NA3 and the fourth side area NA4 are located on opposite sides of the display area AA along a second direction Y. The multiple corner areas NA5, NA6, NA7, and NA8 are respectively located between adjacent areas in the first side area, the third side area, the second side area, and the fourth side area. Figure 1 and Figure 2In the illustrated embodiment, the first side region NA1 and the second side region NA2 correspond to the third boundary AA3 and the fourth boundary AA4 of the display region AA, respectively. The third side region NA3 and the fourth side region NA4 correspond to the first boundary AA1 and the second boundary AA2 of the display region AA, respectively. The plurality of corner regions NA5, NA6, NA7, and NA8 correspond to the third rounded corner 10C, the first rounded corner 10A, the second rounded corner 10B, and the fourth rounded corner 10D, respectively.

[0082] In embodiments of this disclosure, for two adjacent corner regions in the first direction X, the distribution of spacers in the two corner regions is symmetrical with respect to the first axis of symmetry AX1. For example, the distribution of spacers in corner regions NA5 and NA8 is symmetrical with respect to the first axis of symmetry AX1. The distribution of spacers in corner regions NA6 and NA7 is symmetrical with respect to the first axis of symmetry AX1.

[0083] For two adjacent corner regions in the second direction Y, the distribution of spacers in the two corner regions is symmetrical with respect to the second axis of symmetry AX2. For example, the distribution of spacers in corner regions NA5 and NA6 is symmetrical with respect to the second axis of symmetry AX2. The distribution of spacers in corner regions NA7 and NA8 is symmetrical with respect to the second axis of symmetry AX2.

[0084] In embodiments of this disclosure, the second encapsulation layer 532 includes a boundary 5321 located on the side of the second encapsulation layer away from the display area AA. The orthographic projection of the boundary 5321 of the second encapsulation layer on the substrate 10 is located on the side of the orthographic projection of the at least one barrier dam on the substrate 10 closer to the display area, and the orthographic projection of the first spacer PS1 on the substrate 10 is located on the side of the orthographic projection of the boundary 5321 of the second encapsulation layer on the substrate 10 closer to the display area. In embodiments of this disclosure, the outermost first spacer is located inside the boundary of the second encapsulation layer. Thus, a second encapsulation layer is provided at each location of the spacer, and the second encapsulation layer here can act as a buffer to prevent the spacer from puncturing the first encapsulation layer. Therefore, this arrangement can effectively eliminate the risk of cracking of the first encapsulation layer, thereby improving the yield of the display panel.

[0085] Reference Figure 2 , Figure 3A , Figures 7 to 12A portion of the plurality of first spacers PS1 is located in at least one of the first side region NA1 and the second side region NA2 of the peripheral region, and the orthographic projection of the portion of the first spacers PS1 located in at least one of the first side region NA1 and the second side region NA2 on the substrate 10 falls within the orthographic projection of the at least one scan drive circuit 300 on the substrate 10.

[0086] In embodiments of this disclosure, a portion of the at least one scan driving circuit 300 is also located in at least one corner region NA5, NA6, NA7, NA8, and a portion of the plurality of first spacers PS1 is located in the at least one corner region NA5, NA6, NA7, NA8. The orthographic projection of a portion of the first spacers PS1 located in the at least one corner region NA5, NA6, NA7, NA8 onto the substrate 10 falls within the orthographic projection of the at least one scan driving circuit 300 onto the substrate 10. For example, in some exemplary embodiments, a portion of the at least one scan driving circuit 300 is also located in four corner regions NA5, NA6, NA7, NA8. A portion of the plurality of first spacers PS1 is located in the four corner regions NA5, NA6, NA7, NA8, and the orthographic projection of a portion of the first spacers PS1 located in the four corner regions NA5, NA6, NA7, NA8 onto the substrate 10 falls within the orthographic projection of the at least one scan driving circuit 300 onto the substrate 10.

[0087] For example, the at least one scan driving circuit 300 may include a first scan driving circuit 301 and a second scan driving circuit 302. The first scan driving circuit 301 is used to provide a light emission control signal to the pixel driving circuit of at least a portion of the sub-pixels; that is, the first scan driving circuit 301 may include an EM GOA circuit. The second scan driving circuit 302 is used to provide a gate scan signal to the pixel driving circuit of at least a portion of the sub-pixels; that is, the second scan driving circuit 302 may include a GATE GOA circuit. The orthographic projection of the first scan driving circuit 301 on the substrate 10 is located on the side of the orthographic projection of the second scan driving circuit 302 on the substrate 10 that is away from the display area; that is, the first scan driving circuit 301 is located on the outer side.

[0088] In embodiments of this disclosure, a portion of the orthographic projection of the first spacer PS1 onto the substrate 10 falls within the orthographic projection of the first scan driving circuit 301 onto the substrate 10. That is, in the display panel, the orthographic projection of a portion of the outermost first spacer PS1 onto the substrate 10 falls within the orthographic projection of the EM GOA circuit onto the substrate 10. In embodiments of this disclosure, all spacers are disposed in the display area and the area where the scan driving circuit is located. This arrangement effectively eliminates the risk of cracking in the first encapsulation layer, thereby improving the yield of the display panel.

[0089] In embodiments of this disclosure, a portion of the boundary 5321 of the second encapsulation layer is projected onto the substrate 10 in a way that falls within the projection of the at least one scan driving circuit 300 onto the substrate 10. For example, a portion of the boundary 5321 of the second encapsulation layer is projected onto the substrate 10 in a way that falls within the projection of the first scan driving circuit 301 onto the substrate 10. That is, the projection of the boundary 5321 of the second encapsulation layer onto the substrate 10 is a closed outline. In the first side region NA1, the second side region NA2, and at least one corner region NA5, NA6, NA7, NA8, a portion of this closed outline is projected onto the substrate 10 in a way that falls within the projection of the first scan driving circuit 301 onto the substrate 10. Compared to the boundary of the second encapsulation layer in related technologies, in embodiments of this disclosure, the second encapsulation layer adopts an inward-sloping design. This arrangement effectively eliminates the risk of cracking in the first encapsulation layer, thereby improving the yield of the display panel.

[0090] Reference Figure 7 The display panel further includes a first voltage lead 670 for transmitting a first voltage. The orthographic projection of the at least one blocking dam 30 on the substrate 10 at least partially overlaps with the orthographic projection of the first voltage lead 670 on the substrate 10. In some examples, the orthographic projection of the at least one blocking dam 30 on the substrate 10 falls within the orthographic projection of the first voltage lead 670 on the substrate 10.

[0091] For example, the first voltage can be the VSS voltage, which can be around -5V.

[0092] The orthographic projection of a portion of the first spacer PS1 on the substrate is spaced apart from the orthographic projection of the first voltage lead 670 on the substrate. Furthermore, the orthographic projection of a portion of the first spacer PS1 on the substrate is located on the side of the orthographic projection of the first voltage lead 670 on the substrate closer to the display area. That is, the orthographic projection of a portion of the first spacer PS1 on the substrate does not overlap with the orthographic projection of the first voltage lead 670 on the substrate, and the orthographic projection of a portion of the first spacer PS1 on the substrate is located inside the orthographic projection of the first voltage lead 670 on the substrate.

[0093] At least a portion of the boundary 5321 of the second encapsulation layer is positioned at an interval from the orthographic projection of the first voltage lead 670 on the substrate, and the orthographic projection of at least a portion of the boundary 5321 of the second encapsulation layer on the substrate is located on the side of the orthographic projection of the first voltage lead 670 on the substrate closer to the display area.

[0094] For example, in an embodiment of this disclosure, the at least one blocking dam 30 includes a first blocking dam 31, wherein the first blocking dam 31 is located at the position closest to the center AAO of the display area, that is, the first blocking dam 31 is the innermost blocking dam.

[0095] For example, the at least one barrier dam 30 further includes a second barrier dam 32, which is located on the side of the first barrier dam 31 away from the display area. By setting multiple barrier dams, the ability of the barrier dams to prevent water and oxygen intrusion can be improved. It should be noted that the embodiments of this disclosure are not limited thereto, and fewer barrier dams (e.g., one) or more barrier dams can be set according to actual needs.

[0096] In embodiments of this disclosure, a transition region 3011 exists between the first scan driving circuit 301 and the first blocking dam 31. Specifically, the first voltage lead 670 includes a first lead boundary 6701 near the display area, where the first lead boundary 6701 is the boundary of the first voltage lead 670's orthogonal projection on the substrate closest to the display area. The first blocking dam 31 includes a first blocking dam boundary 311 near the display area, where the first blocking dam boundary 311 is the boundary of the first blocking dam 31's orthogonal projection on the substrate closest to the display area. The first lead boundary 6701 is closer to the display area than the first blocking dam boundary 311. In the transition region 3011, the encapsulation structure 53 includes only a first encapsulation layer 531 and a third encapsulation layer 533, and the plurality of spacers PS are not provided in the transition region 3011. That is, neither the second encapsulation layer 532 nor the spacers PS are provided in the transition region 3011.

[0097] In embodiments of this disclosure, the boundaries 5321 of the first spacer PS1 and the second encapsulation layer are both spaced apart from the first barrier dam 31. Specifically, the orthographic projection of the first spacer PS1 on the substrate and the orthographic projection of the first barrier dam 31 on the substrate are separated by a first distance PT3, where the first distance PT3 is greater than 100 micrometers. The orthographic projection of the boundary 5321 of the second encapsulation layer on the substrate and the orthographic projection of the first barrier dam 31 on the substrate are separated by a second distance PT4, where the second distance PT4 is less than the first distance PT3, and the second distance PT4 is greater than 100 micrometers.

[0098] For example, at least one of the first distance PT3 and the second distance PT4 is between 100 and 300 micrometers.

[0099] Reference Figure 7 The display panel further includes an auxiliary conductive portion 251 located in the peripheral region NA, the auxiliary conductive portion 251 being situated within the first electrode layer 124, and electrically connected to the first voltage lead 670. In embodiments of this disclosure, the first voltage lead 670 located in the second conductive layer 122 and the auxiliary conductive portion 251 located in the first electrode layer 124 are connected in parallel, both used to transmit a first voltage (e.g., VSS). This reduces the resistance on the signal line transmitting the first voltage VSS.

[0100] Continue to refer to Figure 7The orthographic projection of the auxiliary conductive portion 251 on the substrate 10 at least partially overlaps with the orthographic projection of at least one scan driving circuit 300 on the substrate 10. For example, the orthographic projection of the auxiliary conductive portion 251 on the substrate 10 can substantially completely cover the orthographic projection of the first scan driving circuit 301 on the substrate 10, and the orthographic projection of the auxiliary conductive portion 251 on the substrate 10 can partially overlap with the orthographic projection of the second scan driving circuit 302 on the substrate 10. That is, the auxiliary conductive portion 251 is provided to be wider, which is beneficial to further reduce the resistance on the signal line transmitting the first voltage VSS.

[0101] Exemplarily, the display panel further includes a plurality of openings 252 disposed in the auxiliary conductive portion 251, each of the plurality of openings 252 exposing a portion of the planarization layer PLN2. The planarization layer PLN2 is typically formed using an organic resin material, and contains some organic substances that are easily volatile when heated, such as organic solvents or small molecule materials. These organic substances are easily volatile when heated during subsequent manufacturing processes of the display panel, leading to gas release in the planarization layer. By providing a plurality of openings 252 in the auxiliary conductive portion 251, it is beneficial for the organic substances in the planarization layer PLN2 to volatilize when heated during subsequent manufacturing processes of the display panel, thereby preventing the accumulation of bubbles on the surface of the auxiliary conductive portion 251 facing the planarization layer PLN2. This helps ensure the process yield of the display panel, and thus ensures a good display effect.

[0102] The display panel further includes a plurality of first covering portions PDL1, which are located in the pixel defining layer PDL and respectively cover the plurality of openings 252.

[0103] In embodiments of this disclosure, at least a portion of the orthographic projection of the first spacer PS1 on the substrate at least partially overlaps with at least a portion of the orthographic projection of the first cover PDL1 on the substrate. At least a portion of the orthographic projection of the first spacer PS1 on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion 251 on the substrate. For example, the orthographic projection of one first spacer PS1 on the substrate partially overlaps with the orthographic projection of the first cover PDL1 on the substrate, and the same first spacer PS1 on the substrate partially overlaps with the orthographic projection of the auxiliary conductive portion 251 on the substrate.

[0104] For example, the plurality of spacers PS includes a second spacer PS2 located in the peripheral region, the orthographic projection of the second spacer PS2 on the substrate being located on the side of the orthographic projection of the first spacer PS1 on the substrate closer to the display area. A portion of the orthographic projection of the second spacer PS2 on the substrate falls within the orthographic projection of the second scan driving circuit 302 on the substrate.

[0105] In embodiments of this disclosure, at least a portion of the orthographic projection of the second spacer PS2 on the substrate at least partially overlaps with at least a portion of the orthographic projection of the first cover PDL1 on the substrate. At least a portion of the orthographic projection of the second spacer PS2 on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion 251 on the substrate. For example, the orthographic projection of one second spacer PS2 on the substrate partially overlaps with the orthographic projection of the first cover PDL1 on the substrate, and the same second spacer PS2 on the substrate partially overlaps with the orthographic projection of the auxiliary conductive portion 251 on the substrate.

[0106] In other embodiments of this disclosure, a display device is also provided. The display device may include the display panel described above. For example, the display device may be a smartphone, mobile phone, video phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, or smartwatch), etc.

[0107] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, comprising: a substrate, comprising a display area and a peripheral area; a plurality of sub-pixels disposed in the display area, the sub-pixels comprising a first electrode, a second electrode, and a functional layer between the first electrode and the second electrode; at least one blocking dam disposed in the peripheral area; a first electrode layer disposed on the substrate, the first electrodes of the plurality of sub-pixels being located in the first electrode layer; a pixel definition layer disposed on a side of the first electrode layer distal to the substrate; a spacer layer disposed on a side of the pixel definition layer distal to the substrate; an encapsulation structure disposed on a side of the spacer layer distal to the substrate, the encapsulation structure comprising: a first encapsulation layer disposed on a side of the spacer layer distal to the substrate; a second encapsulation layer disposed on a side of the first encapsulation layer distal to the substrate; and a third encapsulation layer disposed on a side of the second encapsulation layer distal to the substrate, wherein the first encapsulation layer and the third encapsulation layer are inorganic material encapsulation layers, and the second encapsulation layer is an organic material encapsulation layer, wherein the display panel comprises a plurality of spacers located in the spacer layer, the plurality of spacers comprising a first spacer located in the peripheral area, and, among the plurality of spacers, the first spacer is located at a position farthest from a center of the display area; the second encapsulation layer comprises a boundary on a side of the second encapsulation layer distal to the display area, the boundary being a boundary of a portion of the second encapsulation layer extending from the display area; and a normal projection of the boundary of the second encapsulation layer on the substrate is located on a side of a normal projection of the at least one blocking dam on the substrate close to the display area, and a normal projection of the first spacer on the substrate is located on a side of a normal projection of the boundary of the second encapsulation layer on the substrate close to the display area; the display panel further comprises: a first voltage lead for transmitting a first voltage; a planarization layer on a side of the first electrode layer close to the substrate; an auxiliary conductive portion in the peripheral area, the auxiliary conductive portion being located in the first electrode layer, the auxiliary conductive portion being electrically connected to the first voltage lead; a plurality of openings in the auxiliary conductive portion, the plurality of openings respectively exposing a portion of the planarization layer; and a plurality of first covering portions in the pixel definition layer, the plurality of first covering portions respectively covering the plurality of openings.

2. The display panel of claim 1, wherein, the peripheral area comprises a first side area and a second side area, the first side area and the second side area being located on opposite sides of the display area along a first direction; the display panel further comprises at least one scan driving circuit disposed in at least one of the first side area and the second side area of the peripheral area, the scan driving circuit being configured to provide a scan driving signal to a pixel driving circuit of at least a portion of the sub-pixels; and the display panel further comprises a plurality of first auxiliary conductive portions in the first side area of the peripheral area, the plurality of first auxiliary conductive portions being electrically connected to the scan driving circuit. The display panel includes a plurality of the first spacers, a portion of the plurality of the first spacers is located in at least one of a first side region and a second side region of the peripheral region, and a projection of the portion of the first spacers on the substrate falls within a projection of the at least one scan driving circuit on the substrate.

3. The display panel of claim 2, wherein, The peripheral region further includes a third side region and a fourth side region located at opposite sides of the display region along a second direction, and a plurality of corner regions located between adjacent two of the first side region, the third side region, the second side region and the fourth side region, respectively; A portion of the at least one scan driving circuit is further located in at least one corner region; And A portion of the plurality of the first spacers is located in the at least one corner region, and a projection of the portion of the first spacers on the substrate falls within a projection of the at least one scan driving circuit on the substrate.

4. The display panel of claim 3, wherein, The at least one scan driving circuit includes a first scan driving circuit and a second scan driving circuit, the first scan driving circuit is configured to provide a light emitting control signal to a pixel driving circuit of at least a portion of the sub-pixels, and the second scan driving circuit is configured to provide a gate scanning signal to the pixel driving circuit of at least a portion of the sub-pixels, a projection of the first scan driving circuit on the substrate is located on a side of a projection of the second scan driving circuit on the substrate away from the display region; and And A projection of a portion of the first spacers on the substrate falls within a projection of the first scan driving circuit on the substrate.

5. The display panel of claim 4, wherein, A projection of a portion of the boundary of the second encapsulation layer on the substrate falls within a projection of the at least one scan driving circuit on the substrate.

6. The display panel of claim 4, wherein, A projection of a portion of the boundary of the second encapsulation layer on the substrate falls within a projection of the first scan driving circuit on the substrate.

7. The display panel of any one of claims 1-6, wherein, A projection of the at least one blocking dam on the substrate at least partially overlaps a projection of the first voltage lead on the substrate; And A projection of a portion of the first spacers on the substrate is arranged apart from a projection of the first voltage lead on the substrate, and a projection of the portion of the first spacers on the substrate is located on a side of the projection of the first voltage lead on the substrate close to the display region.

8. The display panel of claim 7, wherein, A projection of at least a portion of the boundary of the second encapsulation layer on the substrate is arranged apart from a projection of the first voltage lead on the substrate, and a projection of the at least a portion of the boundary of the second encapsulation layer on the substrate is located on a side of the projection of the first voltage lead on the substrate close to the display region.

9. The display panel of any of claims 1-6, 8, wherein, The at least one blocking dam includes a first blocking dam, and in the at least one blocking dam, the first blocking dam is located closest to a center of the display region; and And A projection of the first spacers on the substrate is spaced apart from a projection of the first barrier on the substrate by a first distance, the first distance being greater than 100 microns.

10. The display panel of claim 9, wherein, A projection of the boundary of the second encapsulation layer on the substrate is spaced apart from a projection of the first barrier on the substrate by a second distance, the second distance being less than the first distance, the second distance being greater than 100 microns.

11. The display panel of claim 10, wherein, At least one of the first distance and the second distance is between 100 microns and 300 microns.

12. The display panel of claim 9, wherein, The first voltage lead includes a first lead boundary close to the display area, the first lead boundary being a boundary of the first voltage lead on the substrate closest to the display area; the first barrier includes a first barrier boundary close to the display area, the first barrier boundary being a boundary of the first barrier on the substrate closest to the display area; The first lead boundary is closer to the display area than the first barrier boundary, in a transition area between the first lead boundary and the first barrier boundary, the encapsulation structure only includes the first encapsulation layer and the third encapsulation layer, and the transition area is not provided with the plurality of spacers.

13. The display panel of any of claims 1-6, 8, 10-12, wherein, The plurality of first spacers are distributed along a first contour line, the first contour line being a contour line surrounding the display area and having substantially the same orientation as an outer contour line of the display area, the first contour line being spaced apart from the outer contour line of the display area; and The plurality of spacers are arrayed in a first direction and a second direction from a first spacer of an outermost row towards a center of the display area.

14. The display panel of claim 13, wherein, The plurality of spacers are arranged at a first interval distance in the first direction and at a second interval distance in the second direction, a ratio of the first interval distance to the second interval distance being between 0.8 and 1.

2.

15. The display panel of claim 14, wherein, For a first spacer, a distance between the first spacer and a spacer adjacent to the first spacer in the first direction is substantially equal to the first interval distance; and / or, For a first spacer, a distance between the first spacer and a spacer adjacent to the first spacer in the second direction is substantially equal to the second interval distance.

16. The display panel of claim 3, wherein, For two corner areas adjacent in the first direction, a distribution of spacers in the two corner areas is symmetrical with respect to a first axis of symmetry; and / or, For two corner areas adjacent in the second direction, a distribution of spacers in the two corner areas is symmetrical with respect to a second axis of symmetry.

17. The display panel of claim 1, wherein, A projection of at least part of the first spacers on the substrate at least partially overlaps a projection of at least part of the first cover on the substrate; and / or, A projection of at least part of the first spacers on the substrate at least partially overlaps a projection of the auxiliary conductive portion on the substrate.

18. The display panel of claim 17, wherein, The plurality of spacers include a second spacer in the peripheral area, a projection of the second spacer on the substrate being located on a side of a projection of the first spacer on the substrate close to the display area; and and The display panel further includes at least one scan driving circuit disposed in at least one of a first side region and a second side region of the peripheral region, the at least one scan driving circuit including a second scan driving circuit configured to provide a gate scan signal to pixel driving circuits of at least a portion of the sub-pixels. A normal projection of at least part of the second spacers on the substrate falls within a normal projection of the second scan driving circuit on the substrate.

19. The display panel of claim 18, wherein, A normal projection of at least part of the second spacers on the substrate at least partially overlaps with a normal projection of at least part of the first cover portion on the substrate. And / or, A normal projection of at least part of the second spacers on the substrate at least partially overlaps with a normal projection of the auxiliary conductive portion on the substrate.

20. A display device comprising: A display panel, comprising any one of claims 1-19.

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