Method of manufacturing an air gap in an active region

Abstract

The application discloses a manufacturing method of active region air gap, comprising the following steps: step one, forming a plurality of word line structures on a semiconductor substrate by word line etching, each word line structure crossing each field oxide and each active region; step two, forming a protective side wall self-aligned to the side of the word line structure; step three, etching the field oxide by isotropic etching, so that the top surface of the field oxide in and out of the covering area of the word line structure is lowered, and an active region air gap is formed between the active regions, the word line structure crossing the active region air gap; and step four, removing the protective side wall. The application can well remove the field oxide under the covering area of the word line structure, form the active region air gap and not damage the word line structure, reduce the coupling capacitance between the active regions, improve the crosstalk, and is simple and easy to implement.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a method for manufacturing an air gap in the active area (AA). Background Technology

[0002] NAND flash memory, as a type of non-volatile memory, is suitable for data storage and widely used in consumer, automotive, and industrial electronics fields due to its advantages such as large capacity, fast write / erase speed, and low cost. With technological advancements, the size of active regions is continuously shrinking to meet the ever-increasing demand for storage capacity. However, as the distance between two adjacent active regions continues to decrease, crosstalk between them increases, affecting the memory's programming / erase window and consequently reducing reliability.

[0003] like FIG. 1A The image shown is a top view of the storage area of ​​an existing NAND flash memory; as shown... FIG. 1B As shown, it is along FIG. 1A The cross-sectional view at the dashed line AA in the figure shows that multiple word line structures are formed on a semiconductor substrate 101, and multiple field oxygen 102s are formed on the semiconductor substrate 101, with multiple active regions isolated by the field oxygen 102s. Each word line structure spans each field oxygen 102 and each active region.

[0004] FIG. 1A In this context, the semiconductor substrate 101 between each of the field oxygen 102 forms the active region. The cross-section at the dashed line AA is a cross-section along the word line structure.

[0005] The area covered by the word line structure on top of the active region constitutes the gate structure of the device unit; the gate structures of each device unit on the same word line structure are connected together to form a row structure.

[0006] The device units on the same active region form a column structure, and the row structure and the column structure form an array structure.

[0007] In the formation region of the array structure, the length directions of each active region are parallel to each other.

[0008] The length direction of each of the word line structures is perpendicular to the length direction of the active region.

[0009] In the storage area of ​​NAND flash memory, the device unit is a storage unit, and the array structure constitutes the storage array of the NAND flash memory.

[0010] like FIG. 1BAs shown, the gate structure of the memory cell includes a tunneling dielectric layer 105, a floating gate 103, an inter-gate dielectric layer 106, and a control gate 104 stacked sequentially. FIG. 1A In the above view, the top view structure of the word line structure is the same as that of the control gate 104.

[0011] like FIG. 1B As shown, the word line structure covering the top of the field oxygen 102 includes the inter-gate dielectric layer 106 and the control gate 104 stacked sequentially.

[0012] The tunneling medium layer 105 and the floating gate 103 are located in the overlapping area of ​​the control gate 104 and the active region. FIG. 1A In the diagram, the area where the floating gate 103 is formed is indicated by a dashed box.

[0013] Typically, both the floating gate 103 and the control gate 104 are formed using polysilicon, and the inter-gate dielectric layer 106 is also called an interpoly dielectric layer (IPD).

[0014] Depend on FIG. 1B As shown, the surface of the active region covered by the gate structure of the memory cell forms a channel region. As the device size shrinks, the spacing between two adjacent active regions continuously decreases, which increases the crosstalk between two adjacent memory cells on the same row. This affects the memory's programming / erasing window and reduces reliability.

[0015] One method to improve crosstalk between two adjacent memory cells is to provide an air gap between the active regions. Air has a lower dielectric constant than field oxygen, therefore, providing an air gap reduces the coupling capacitance between the active regions, thereby reducing crosstalk between memory cells in the active regions. However, due to… FIG. 1A As shown, with the miniaturization of device size, the device density is very high, making it very difficult to form air gaps between active regions. Summary of the Invention

[0016] The technical problem to be solved by the present invention is to provide a method for manufacturing an active region air gap, which can effectively remove field oxygen under the word line structure coverage area and thus form an active region air gap without damaging the word line structure, thereby effectively reducing the coupling capacitance between active regions and improving crosstalk.

[0017] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an active region air gap, comprising the following steps:

[0018] Step one, etching word lines on a semiconductor substrate to form a plurality of word line structures, a plurality of field oxides are formed on the semiconductor substrate and a plurality of active regions are isolated by the field oxides, each of the word line structures crosses each of the field oxides and each of the active regions.

[0019] Step two, forming a protective side wall self-aligned to the side of the word line structure, the material of the protective side wall and the field oxide have different etching rates.

[0020] Step three, isotropic etching the field oxide to lower the top surface of the field oxide in the area covered by the word line structure and the area not covered by the word line structure and thereby forming active region air gaps between the active regions, the word line structure crosses the active region air gaps; in the isotropic etching, the etching rate of the protective side wall is lower than the etching rate of the field oxide; after the isotropic etching, the protective side wall remains on the side of the word line structure and thereby protects the word line structure.

[0021] Step four, removing the protective side wall.

[0022] Further improvement is, before forming the protective side wall in step two, further comprising first etching the field oxide in the area not covered by the word line structure, the first etching is anisotropic etching, the first etching lowers the top surface of the field oxide in the area not covered by the word line structure to be lower than the top surface of the active region, the top surface of the field oxide in the area covered by the word line structure is higher than the top surface of the field oxide in the area not covered by the word line structure and thereby forming a side of the field oxide at the bottom of the word line structure.

[0023] In step two, in the area of the field oxide, the protective side wall further extends to the side of the field oxide at the bottom of the word line structure.

[0024] Further improvement is, the first etching is directly implemented by the word line etching.

[0025] Further improvement is, the area of the word line structure covering the top of the active region constitutes a gate structure of a device unit; the gate structures of each of the device units on the same word line structure are connected together and constitute a row structure.

[0026] Further improvement is, each of the device units on the same active region constitutes a column structure, the row structure and the column structure constitute an array structure.

[0027] Further improvement is, in the formation area of the array structure, the length direction of each of the active regions is parallel to each other.

[0028] Further improvement is, the length direction of each of the word line structures is perpendicular to the length direction of the active regions.

[0029] Further improvement is that the device unit comprises a memory cell of a NAND flash memory, and the array structure constitutes a memory array of the NAND flash memory.

[0030] Further improvement is that the gate structure of the memory cell comprises, in sequence, a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate.

[0031] Further improvement is that the structure covering on top of the field oxide comprises, in sequence, the inter-gate dielectric layer and the control gate.

[0032] The tunneling dielectric layer and the floating gate are located in the overlapping area of the control gate and the active region.

[0033] Further improvement is that the etching amount of the field oxide by the first etching is

[0034] Further improvement is that the material of the protection side wall is a polymer.

[0035] Further improvement is that the polymer is deposited in the etching machine table of the gate etching directly after the completion of the gate etching.

[0036] The self-aligned etching of the protection side wall is performed in the etching machine table of the gate etching directly after the completion of the polymer deposition.

[0037] Further improvement is that the deposition thickness of the polymer is

[0038] Further improvement is that the etching amount of the field oxide by the isotropic etching in step three is 1 / 2 of the width of the word line structure.

[0039] Further improvement is that the protection side wall is removed by wet etching in step four.

[0040] The present application adds the steps of self-aligned formation of the protection side wall on the side of the word line structure and isotropic etching of the field oxide after the etching of the word line, which not only removes the field oxide outside the covering area of the word line structure, but also removes the field oxide under the covering area of the word line structure well and forms the air gap of the active region, thereby effectively reducing the coupling capacitance between the active regions and improving the crosstalk. When the present application is applied to the NAND flash memory, the programming and erasing windows and the reliability can be improved.

[0041] The etching area of the field oxide in the embodiment of the present application is the protection side wall formed by self-alignment, and therefore the present application has the characteristics of simple process and easy implementation.

[0042] The protective side wall of the application can also protect the word line structure in isotropic etching of oxygen field, so that the component structure of the word line structure is not damaged. BRIEF DESCRIPTION OF DRAWINGS

[0043] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0044] FIG. 1A is a top view of a storage area of a prior art NAND flash memory;

[0045] FIG. 1B is a sectional view along the dotted line AA in FIG. 1A ;

[0046] FIG. 2 is a flow chart of the manufacturing method of the air gap of the active area of the embodiment of the application;

[0047] FIG. 3 is a top view of the storage area of the NAND flash memory formed by the manufacturing method of the air gap of the active area of the embodiment of the application;

[0048] FIG. 4A - FIG. 8A is a sectional view along the dotted line BB in FIG. 3 at each step of the manufacturing method of the air gap of the active area of the embodiment of the application;

[0049] FIG. 4B - FIG. 8B is a sectional view along the dotted line CC in FIG. 3 at each step of the manufacturing method of the air gap of the active area of the embodiment of the application;

[0050] FIG. 9 is a sectional view along the dotted line AA in FIG. 3 after the manufacturing method of the air gap of the active area of the embodiment of the application is completed. DETAILED DESCRIPTION

[0051] As shown in FIG. 2 , it is a flow chart of the manufacturing method of the air gap 208 of the active area of the embodiment of the application; as shown in FIG. 3 , it is a top view of the storage area of the NAND flash memory formed by the manufacturing method of the air gap 208 of the active area of the embodiment of the application; as shown in FIG. 4A to FIG. 8A , it is a sectional view along the dotted line BB in FIG. 3 at each step of the manufacturing method of the air gap 208 of the active area of the embodiment of the application; as shown in FIG. 4B to FIG. 8B , it is a sectional view along the dotted line CC in FIG. 3 at each step of the manufacturing method of the air gap 208 of the active area of the embodiment of the application; as shown in FIG. 9 , it is a sectional view along the dotted line AA in FIG. 3A cross-sectional view at the dashed line AA in the figure; the manufacturing method of the active region air gap 208 in this embodiment of the invention includes the following steps:

[0052] Step 1: Perform word line etching to form multiple word line structures on the semiconductor substrate 201. Multiple field oxygen 202s are formed on the semiconductor substrate 201, and multiple active regions are isolated by the field oxygen 202s. Each word line structure spans each field oxygen 202 and each active region.

[0053] FIG. 3 In this diagram, the semiconductor substrate 201 between each of the field oxides 202 forms the active region. The cross-section at dashed line BB is a cross-section along the active region, and the cross-section at dashed line CC is a cross-section along the field oxides 202. The cross-section at dashed line AA is a cross-section along the word line structure.

[0054] In some embodiments, the semiconductor substrate 201 is a silicon substrate, and the field oxide 202 is shallow trench isolation (STI).

[0055] In some embodiments, the area covered by the word line structure on top of the active region constitutes the gate structure of the device cell; the gate structures of each device cell on the same word line structure are connected together to form a row structure.

[0056] The device units on the same active region form a column structure, and the row structure and the column structure form an array structure.

[0057] In the formation region of the array structure, the length directions of each active region are parallel to each other.

[0058] The length direction of each of the word line structures is perpendicular to the length direction of the active region.

[0059] In some preferred embodiments, the device unit includes a NAND flash memory storage unit, and the array structure constitutes a storage array of the NAND flash memory.

[0060] like FIG. 4A As shown, the gate structure of the memory cell includes a tunneling dielectric layer 205, a floating gate 203, an inter-gate dielectric layer 206, and a control gate 204 stacked sequentially. FIG. 3 In the above view, the top view structure of the word line structure is the same as that of the control gate 204.

[0061] The word line structure covering the top of the field oxygen 202 includes the inter-gate dielectric layer 206 and the control gate 204 stacked in sequence.

[0062] The tunneling medium layer 205 and the floating gate 203 are located in the overlapping area of ​​the control gate 204 and the active region.FIG. 3 In the diagram, the area where the floating gate 203 is formed is indicated by a dashed box.

[0063] Both the floating gate 203 and the control gate 204 are formed of polysilicon, and the inter-gate dielectric layer 206 is also called the interpoly dielectric layer (IPD).

[0064] The material of the tunneling medium layer 205 is an oxide layer.

[0065] The gate inter-dielectric layer 206 is composed of an oxide layer or an ONO layer consisting of an oxide layer, a nitride layer, and an oxide layer.

[0066] In some embodiments, before the subsequent formation of the protective sidewall 207, a first etching is performed on the field oxide 202 outside the word line structure coverage area. This first etching is anisotropic, and the first etching causes the top surface of the field oxide 202 outside the word line structure coverage area to be lower than the top surface of the active region, and the top surface of the field oxide 202 in the word line structure coverage area to be higher than the top surface of the field oxide 202 outside the word line structure coverage area, thereby forming the side surface of the field oxide 202 at the bottom of the word line structure. FIG. 4B As shown, the groove formed by the first etching is indicated by the dashed frame 301.

[0067] In some embodiments, the first etching is achieved directly using the word line etching; in this case, after the tunneling dielectric layer 205 is etched, the field oxygen 202 can be etched downwards.

[0068] The etching amount of the first etching on the field oxygen 202 is:

[0069] Step 2: A protective sidewall 207 is formed by self-alignment on the side of the character line structure. The material of the protective sidewall 207 and the field oxygen 202 have different etching rates.

[0070] In some preferred embodiments, the protective sidewall 207 is made of polymer 207a. Polymer 207a is primarily made of C2F4 or C4F6.

[0071] The steps for forming the protective sidewall 207 include:

[0072] like FIG. 5A As shown, after the gate etching is completed, the polymer 207a is deposited directly in the etching machine used for gate etching. FIG. 5BAs shown, in the region of the field oxygen 202, the polymer 207a also extends to the side of the field oxygen 202 at the bottom of the word line structure. More preferably, the deposition thickness of the polymer 207a is...

[0073] like FIG. 6A As shown, after the polymer 207a is deposited, it is directly subjected to self-aligned etching in the gate etching machine to form the protective sidewall 207. The self-aligned etching removes the polymer 207a from the top surface of the control gate 204 and the surfaces outside the word line structure. The polymer 207a remaining on the side of the word line structure forms the protective sidewall 207. FIG. 6B As shown, in the region of the field oxygen 202, the protective sidewall 207 also extends to the side of the field oxygen 202 at the bottom of the letter line structure.

[0074] Step 3, as follows FIG. 7B As shown, isotropic etching is used to etch the field oxygen 202, causing the top surface of the field oxygen 202 both within and outside the coverage area of ​​the word line structure to be lowered, thereby forming an active region air gap 208 between the active regions, and the word line structure spans the active region air gap 208; in the isotropic etching, the etching rate of the protective sidewall 207 is lower than the etching rate of the field oxygen 202; after the isotropic etching is completed, the protective sidewall 207 remains on the side of the word line structure to protect the word line structure.

[0075] FIG. 7A The corresponding region is located within the active region, therefore the field oxygen 202 is absent. FIG. 7A and FIG. 7B As shown, the word line structure is protected by the protective sidewall 207 and will not be damaged. In this embodiment of the invention, the tunneling dielectric layer 204 in the word line structure is an oxide layer, and the inter-gate dielectric layer 206 also uses an oxide layer. Without the protective sidewall 207, when isotropically etching the field oxide 202, which is also an oxide layer, etching damage will occur to the tunneling dielectric layer 204 and the inter-gate dielectric layer 206.

[0076] In some preferred embodiments, the isotropic etching amount on the field oxide 202 is half the width of the word line structure. The word line structure corresponds to the channel length of the device cell. Corresponding to the etching of the field oxide 202 at the bottom of the word line structure, the isotropic etching proceeds from the side of the word line structure towards the center. When the space formed by the etching on both sides of the word line structure is continuous, the etching amount on the field oxide 202 is exactly half the width of the word line structure. The resulting active region air gap 208 is sufficient to reduce interference between the channel regions of two laterally adjacent device cells. In other embodiments, the isotropic etching amount on the field oxide 202 may also be less than or greater than half the width of the word line structure.

[0077] Step 4, as follows FIG. 8A As shown, the protective sidewall 207 is removed. FIG. 8B The active zone air gap 208 is shown after the protective sidewall 207 has been removed.

[0078] like FIG. 9 As shown, along FIG. 3 Along the direction of the dashed line AA, the gate structure spans the active region and the field oxygen 202. After forming the active region air gap 208, from... FIG. 9 It can be seen that the active region air gap 208 is located between the remaining field oxygen 202 and the gate structure, and the bottom surface of the tunneling dielectric layer 204 of the gate structure can also include a portion of the unremoved field oxygen 202.

[0079] In some embodiments, the protective sidewall 207 is removed by wet etching.

[0080] In this embodiment of the invention, after word line etching, a step is added to form a protective sidewall 207 by self-alignment on the side of the word line structure and to perform isotropic etching of the field oxide 202. This not only removes the field oxide 202 outside the word line structure coverage area, but also effectively removes the field oxide 202 below the word line structure coverage area, thereby forming an active region air gap 208. This effectively reduces the coupling capacitance between active regions and improves crosstalk. When this invention is applied to NANS flash memory, it can improve the programming and erasing windows and reliability.

[0081] In this embodiment of the invention, the etching region of field oxygen 202 is formed by self-alignment of the protective sidewall 207, which has the characteristics of simple process and easy implementation.

[0082] The protective sidewall 207 of this invention can also effectively protect the word line structure during the isotropic etching of field oxygen 202, so that the constituent structures of the word line structure will not be damaged.

[0083] The application has been described in detail by specific embodiments above, but these do not constitute limitation of the application. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the application, and these should also be considered as within the protection scope of the application.

Claims

1. A method for manufacturing an active region air gap, characterized in that, The method comprises the following steps: Step 1: forming a plurality of word line structures on a semiconductor substrate by word line etching, wherein a plurality of field oxides are formed on the semiconductor substrate and a plurality of active regions are isolated by the field oxides, and each word line structure crosses each field oxide and each active region; Step 2: forming a protective side wall in a self-aligned manner on the side surface of the word line structure, wherein the material of the protective side wall and the field oxide have different etching rates; Step 3: etching the field oxide by isotropic etching, so that the top surface of the field oxide in the covered area and the uncovered area of the word line structure is lowered, and thus an active region air gap is formed between the active regions, and the word line structure crosses the active region air gap; in the isotropic etching, the etching rate of the protective side wall is lower than the etching rate of the field oxide; after the isotropic etching is completed, the protective side wall is retained on the side surface of the word line structure, thereby protecting the word line structure; Step 4: removing the protective side wall.

2. The method of claim 1, wherein: Before step 2, the method further comprises a first etching of the field oxide in the uncovered area of the word line structure, wherein the first etching is anisotropic etching, the first etching lowers the top surface of the field oxide in the uncovered area of the word line structure to below the top surface of the active region, and the top surface of the field oxide in the covered area of the word line structure is higher than the top surface of the field oxide in the uncovered area of the word line structure, thereby forming a side surface of the field oxide at the bottom of the word line structure; In step 2, the protective side wall further extends to the side surface of the field oxide at the bottom of the word line structure in the region of the field oxide.

3. The method of claim 2, wherein: The first etching is directly implemented by the word line etching.

4. The method of claim 3, wherein: The covered area of the word line structure on the top of the active region constitutes a gate structure of a device unit; the gate structures of each device unit on the same word line structure are connected together and constitute a row structure.

5. The method of claim 4, wherein: Each device unit on the same active region constitutes a column structure, and the row structure and the column structure constitute an array structure.

6. The method of claim 5, wherein: In the formation region of the array structure, the length directions of each active region are parallel to each other.

7. The method of claim 6, wherein: The length direction of each word line structure is perpendicular to the length direction of the active region.

8. The method of claim 5, wherein: The device unit comprises a memory cell of a NAND flash memory, and the array structure constitutes a memory array of the NAND flash memory.

9. The method of claim 8, wherein: The gate structure of the memory cell comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate which are sequentially stacked.

10. The method of claim 9, wherein: The structure of the word line structure covering the top of the field oxide comprises the inter-gate dielectric layer and the control gate which are sequentially stacked; The tunneling dielectric layer and the floating gate are located in the overlapping region of the control gate and the active region.

11. The method of claim 4, wherein: The etching amount of the first etching on the field oxide is 200-500 angstrom.

12. The method of claim 11, wherein: The material of the protective side wall is a polymer.

13. The method of claim 12, wherein: The polymer is deposited in the etching machine table of the gate etching after the gate etching is completed; The self-aligned etching is performed in the etching machine table of the gate etching after the polymer deposition is completed, thereby forming the protective side wall.

14. The method of claim 13, wherein: The deposition thickness of the polymer is 10-30 angstrom.

15. The method of claim 1, wherein: The isotropic etching in step three etches the field oxide to 1 / 2 of the width of the word line structure.

16. The method of claim 12, wherein: The protective side wall is removed by wet etching in step four.

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