Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The semiconductor structure has a cell array region and a peripheral circuit region; the semiconductor structure comprises: a substrate; a connection layer located above the substrate and comprising a first part located in the cell array region and a second part located in the peripheral circuit region; wherein the thickness of the second part is greater than the thickness of the first part. The first part and / or the second part comprises a plurality of connection portions; the width of the connection portions gradually decreases in a direction away from the substrate. The semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure can improve the process reliability of the semiconductor structure, reduce the resistance of each connection portion in the peripheral circuit region, and effectively reduce the risk of short circuit or open circuit between each adjacent connection portion, thereby facilitating the improvement of the production yield of the semiconductor structure and the reduction of RC-Delay effect.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. After semiconductor processes entered the deep submicron stage, Dynamic Random Access Memory (DRAM), a commonly used semiconductor structure in computers and other electronic devices, is becoming increasingly smaller. Correspondingly, the size of each component in DRAM and the spacing between adjacent components are also decreasing. This allows for the widespread application of high aspect ratio ion etching techniques during the semiconductor structure fabrication process.

[0003] However, when fabricating semiconductor structures using high aspect ratio ion etching technology, the dimensions of the deep trench bottom are extremely difficult to control. Furthermore, due to various factors in the actual semiconductor fabrication process, the morphology of the deep trench bottom is prone to change, leading to the risk of short circuits or open circuits between adjacent interconnect structures located at the bottom of the deep trench, thus causing the corresponding circuits to fail. Moreover, as the dimensions of interconnect structures in semiconductor structures continue to decrease, these interconnect structures tend to have larger resistance values, thereby increasing the resistive-capacitive delay (RC-Delay) effect of the semiconductor structure. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can improve the process reliability of the semiconductor structure, reduce the resistance of each connection in the peripheral circuit area, and effectively reduce the risk of short circuit or open circuit between adjacent connections, thereby improving the production yield of the semiconductor structure and reducing the RC-Delay effect.

[0005] To achieve the above objectives, in one aspect, some embodiments of this disclosure provide a semiconductor structure. The semiconductor structure has a cell array region and a peripheral circuit region. The semiconductor structure includes a substrate and a connection layer. The connection layer is located above the substrate and includes a first portion located in the cell array region and a second portion located in the peripheral circuit region. The thickness of the second portion is greater than the thickness of the first portion.

[0006] In some embodiments of this disclosure, the thickness of the second portion is greater than or equal to twice the thickness of the first portion.

[0007] In some embodiments of this disclosure, the thickness of the second portion ranges from 60 nm to 80 nm.

[0008] In some embodiments of this disclosure, the first portion and / or the second portion includes a plurality of connecting portions; the connecting portions extend along a first direction; a second direction is perpendicular to the first direction in a plane parallel to the substrate. The dimension of the connecting portion in the second direction is the width of the connecting portion. The width of the connecting portion gradually decreases along a direction away from the substrate. The semiconductor structure further includes a first dielectric layer covering the connecting portions and used to insulate adjacent connecting portions.

[0009] In some embodiments of this disclosure, the width of the connection portion decreases proportionally along the direction away from the substrate.

[0010] In some embodiments of this disclosure, the minimum width of the connecting portion ranges from 100nm ± 20nm.

[0011] In some embodiments of this disclosure, the semiconductor structure further includes a second dielectric layer and a conductive via. The second dielectric layer covers the first dielectric layer. The conductive via penetrates both the second dielectric layer and the first dielectric layer and is correspondingly connected to the connection portion.

[0012] In some embodiments of this disclosure, the thickness of the second dielectric layer ranges from 2000nm to 500nm.

[0013] In some embodiments of this disclosure, the substrate includes: a unit transistor located within the unit array region, and a peripheral transistor located within the peripheral circuit region; wherein, the first portion is connected to the unit transistor; and the second portion is connected to the peripheral transistor.

[0014] In some embodiments of this disclosure, the substrate includes: a unit transistor and a memory module located within the unit array region, and a peripheral transistor located within the peripheral circuit region; wherein the memory module is located above the unit transistor and connected to the unit transistor; the first portion is correspondingly connected to the memory module; and the second portion is correspondingly connected to the peripheral transistor.

[0015] On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, including the following steps.

[0016] A substrate is provided, the substrate having a cell array region and a peripheral circuit region.

[0017] A connection layer is formed above the substrate; the connection layer includes a first portion located in the cell array region and a second portion located in the peripheral circuit region; the thickness of the second portion is greater than the thickness of the first portion.

[0018] In some embodiments of this disclosure, forming a bonding layer over the substrate includes the following steps.

[0019] A bonding material is deposited on the substrate.

[0020] A first mask is formed over the connecting material. The first mask has a first pattern that defines the cell array region.

[0021] Based on the first pattern, a portion of the connecting material is removed to form the first portion located in the cell array region and the second portion located in the peripheral circuit region.

[0022] In some embodiments of this disclosure, the step of removing a portion of the connecting material based on the first pattern to form a first portion located in the cell array region and a second portion located in the peripheral circuit region includes the following steps.

[0023] Based on the first pattern, the portion of the connecting material located in the unit array region is removed to form an initial second part.

[0024] Based on the first pattern, the connecting material of the target thickness is deposited again in the cell array region to form the initial first part.

[0025] Remove the first mask.

[0026] A second mask is formed covering the initial second portion and the initial first portion, the second mask having a second pattern.

[0027] Based on the second pattern, the initial first portion is etched to form the first portion, and the initial second portion is etched to form the second portion.

[0028] In some embodiments of this disclosure, the etching method for the initial first portion and the initial second portion includes: lateral etching using a fluorine-containing gas, wherein the etching rate gradually decreases as the etching depth increases.

[0029] In some embodiments of this disclosure, the reaction chamber pressure for etching the initial first portion and the initial second portion ranges from 3 mTorr to 6 mTorr. The RF source power ranges from 500 W to 600 W. The RF bias power ranges from 100 W to 150 W.

[0030] In some embodiments of this disclosure, the first portion and / or the second portion includes a plurality of connecting portions; there is a gap between adjacent connecting portions. The preparation method further includes the following steps.

[0031] A first dielectric layer is formed, which covers the connection portion and fills the gap.

[0032] A second dielectric layer is formed, which covers the first dielectric layer.

[0033] A via is formed that penetrates the second dielectric layer and the first dielectric layer, so that a portion of the second portion is exposed within the via.

[0034] The through-hole is filled with conductive material to form a conductive hole.

[0035] The semiconductor structure and its fabrication method provided in this disclosure are as described above. In the semiconductor structure provided in this disclosure, by setting the thickness of the first portion of the interconnect layer located in the cell array region to be different from the thickness of the second portion located in the peripheral circuit region—for example, making the thickness of the second portion greater than the thickness of the first portion—the smaller thickness of the first portion of the interconnect layer can be used to form the interconnection portion within the cell array region, and the larger thickness of the second portion of the interconnect layer can be used to form the interconnection portion within the peripheral circuit region. This reduces the resistance of each interconnection portion within the peripheral circuit region, thereby reducing the RC-Delay effect of the semiconductor structure.

[0036] Furthermore, in this embodiment, each connection extends along a first direction, and the width of each connection in a second direction gradually decreases in the direction away from the substrate. This allows the longitudinal cross-sectional shape of the spacing between adjacent connections along the second direction to be an inverted trapezoid. This facilitates the filling of an insulating medium between adjacent connections to form a first dielectric layer that covers the connections and insulates adjacent connections, ensuring a larger upper surface area of ​​the first dielectric layer in the portion between adjacent connections. Moreover, the thickness of the second portion of the connection layer is greater than the thickness of the first portion, allowing for a larger upper surface area of ​​the first dielectric layer in the portion between adjacent connections within the peripheral circuit region. This also helps ensure the morphological stability of each connection and the deep trench structure when fabricating a deep trench structure above the connections. In this embodiment, the above structure for each connection facilitates increasing the size of the connection contact window, enabling stable fabrication of the deep trench structure above the connection and effectively reducing the risk of short circuits or open circuits between adjacent connections. This improves the fabrication stability and production yield of the semiconductor structure. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0039] Figure 2 This is a schematic cross-sectional view of a partial region of a semiconductor structure provided in one embodiment;

[0040] Figure 3 This is a schematic cross-sectional view of a local region of a semiconductor structure provided in one embodiment;

[0041] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0042] Figure 5 This is a schematic flowchart of a method for fabricating another semiconductor structure provided in one embodiment;

[0043] Figure 6 for Figure 5 A schematic diagram of step S230 in the method for fabricating the semiconductor structure shown.

[0044] Figures 7a to 19 for Figure 5 The diagram shows the structural schematics of the semiconductor structure obtained in each step of the fabrication method.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1-Substrate, 11-Shallow trench isolation structure, 12-Device layer, S1-Unit array region, S2-Peripheral circuit region

[0047] C - Storage module, 2 - Connection layer, 20 - Connection material.

[0048] 21 - First part, 211 - Connecting part of the first part, T1 - Thickness of the first part

[0049] W1 - Width of the first part, 22 - Second part, 221 - Connecting part of the second part, T2 - Thickness of the second part

[0050] W2 - Width of the second part, G - Spacing, 21A - Initial first part, 22A - Initial second part.

[0051] 3-First dielectric layer, 4-Second dielectric layer, 5-Conductive via, H-Through via

[0052] Y1 - First mask, M1 - First pattern, Y2 - Second mask, Y21 - First hard mask layer, Y22 - First anti-reflection layer

[0053] Y3 - Third mask, Y21 - Second hard mask layer, Y22 - Second anti-reflection layer, M3 - Third pattern.

[0054] PR - Photoresist layer, K - Opening. Detailed Implementation

[0055] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0057] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0060] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0061] Furthermore, embodiments of the invention are described herein with reference to schematic diagrams that serve as preferred embodiments (and intermediate structures) of this disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this disclosure.

[0062] With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. As semiconductor processes have entered the deep submicron stage, the size of DRAM is decreasing. Correspondingly, the size of each component in DRAM and the spacing between adjacent components are also decreasing. This allows for the widespread application of high aspect ratio ion etching techniques in the fabrication of semiconductor structures.

[0063] However, when fabricating semiconductor structures using high aspect ratio ion etching technology, the dimensions of the deep trench bottom are extremely difficult to control. Furthermore, due to various factors in the actual semiconductor fabrication process, the morphology of the deep trench bottom is prone to change, leading to the risk of short circuits or open circuits between adjacent interconnect structures located at the bottom of the deep trench, thus causing the corresponding circuits to fail. Moreover, as the dimensions of interconnect structures in semiconductor structures continue to decrease, these interconnect structures tend to have larger resistance values, thereby increasing the resistive-capacitive delay (RC-Delay) effect of the semiconductor structure.

[0064] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can improve the process reliability of the semiconductor structure, reduce the resistance of each connection in the peripheral circuit area, and effectively reduce the risk of short circuit or open circuit between adjacent connections, thereby improving the production yield of the semiconductor structure and reducing the RC-Delay effect.

[0065] Please see Figure 1 and Figure 2 This disclosure provides a semiconductor structure in some embodiments. The semiconductor structure has a cell array region S1 and a peripheral circuit region S2. The semiconductor structure includes a substrate 1 and a connection layer 2. The connection layer 2 is located above the substrate 1 and includes a first portion 21 located in the cell array region S1 and a second portion 22 located in the peripheral circuit region S2. The thickness of the second portion 22 is greater than the thickness of the first portion 21.

[0066] It can be understood that the cell array region S1 refers to the region in a semiconductor structure used to form a cell array, such as the region forming a memory cell array. In DRAM, each memory cell in the memory cell array includes a transistor and a storage capacitor. The transistors in the cell array region S1 are disposed within the substrate 1, and the storage capacitors can be stacked on top of the substrate 1 and connected to the aforementioned transistors. The peripheral circuit region S2 is located on at least one side of the cell array region S1, such as the side or periphery, and refers to the region in the semiconductor structure used to form peripheral circuits. In DRAM, the peripheral circuits can be connected by multiple transistors and other electronic components (such as capacitors, resistors, etc.) according to design requirements to achieve specific functions.

[0067] For ease of distinction, in some of the following embodiments, transistors located in the cell array region S1 are defined as cell transistors, and transistors located in the peripheral circuit region S2 are defined as peripheral transistors. The cell transistors and peripheral transistors can have the same structure; for example, they can each be gate all around transistors (GAA transistors) and buried in the corresponding regions of the substrate 1. This disclosure will not elaborate further on this aspect.

[0068] Please continue reading. Figure 1 and Figure 2In some embodiments, substrate 1 may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multi-layer structure. For example, substrate 1 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0069] In some embodiments, such as Figure 2 As shown, a trench isolation structure 11 is provided in the substrate 1, which can be used to divide multiple active regions in the substrate 1 so that each transistor can be formed in the corresponding active region.

[0070] It is worth noting that the interconnect layer 2 is located above the substrate 1. The interconnect layer 2 can be used to realize electrical connections between the transistor and other devices above the interconnect layer 2, or to realize electrical connections between devices connected to the transistor and other devices above the interconnect layer 2, but it is not limited to these uses. The interconnect layer 2 is formed of a conductive material and can be a single-layer structure or a multi-layer structure. For example, the interconnect layer 2 is a conductive metal layer, such as a tungsten metal layer or a copper metal layer.

[0071] In some embodiments of this disclosure, the substrate 1 includes: a unit transistor located in the unit array region S1, and a peripheral transistor located in the peripheral circuit region S2; wherein, the first part 21 of the connection layer 2 is correspondingly connected to the unit transistor; and the second part 22 of the connection layer 3 is correspondingly connected to the peripheral transistor.

[0072] In other embodiments of this disclosure, the substrate 1 includes: a unit transistor and a memory module located within a unit array region S1, and a peripheral transistor located within a peripheral circuit region S2. The memory module is located above and connected to the unit transistor. A first portion 21 of the connection layer 2 is correspondingly connected to the memory module; a second portion 22 of the connection layer 2 is correspondingly connected to the peripheral transistor.

[0073] For example, such as Figure 1 and Figure 2As shown, a device layer 12 is also formed on the surface of the substrate 1. The device layer 12 can be, for example, a layer structure for forming bit lines or bit line contact structures that are connected to the transistor, or it can be another functional dielectric thin film located on top of the transistor. The device layer 12 may include, for example, multiple thin films such as conductive layers and dielectric layers, which can be selected and configured according to actual needs. A connection layer 2 is disposed on the surface of the device layer 12 facing away from the substrate 1, and can be connected to the transistor through or via the device layer 12.

[0074] For example, both the unit transistors and peripheral transistors employ GAA (Gas-Aligned Array), which helps to effectively increase the memory integration density of the semiconductor structure. Furthermore, to match the placement of each transistor, the first portion 21 and / or the second portion 22 of the connection layer 2 include multiple connection portions. Specifically, the connection portion 211 of the first portion 21 can be connected to the unit transistor, and the connection portion of the second portion 22 can be connected to the peripheral transistor.

[0075] Please refer to [link / reference needed] for further information. Figure 2 In the connecting layer 2, the thickness T2 of the second part 22 is greater than the thickness T1 of the first part 21. The thickness T2 of the second part 22 and the thickness T1 of the first part 21 can be selected and set according to requirements.

[0076] In some embodiments, the thickness T2 of the second portion 22 in the connecting layer 2 is greater than or equal to twice the thickness T1 of the first portion 21. However, it is not limited to this. For example, the thickness T2 of the second portion 22 in the connecting layer 2 is three, four, or five times the thickness T1 of the first portion 21.

[0077] In some embodiments, the thickness T2 of the second portion 22 in the connection layer 2 ranges from 60 nm to 80 nm. For example, the thickness T2 of the second portion 22 in the connection layer 2 is 60 nm, 65 nm, 70 nm, 75 nm, or 80 nm.

[0078] In addition, please continue to refer to Figure 2 In some embodiments of this disclosure, the first portion 21 and the second portion 22 of the interconnect layer 2 include a plurality of interconnects (including 211 and 221). Each interconnect (including 211 and 221) extends along a first direction (e.g., the Y direction); and the dimension of each interconnect (including 211 and 221) in a second direction (e.g., the X direction) is the width of the interconnect (including 211 and 221). The second direction (e.g., the X direction) is perpendicular to the first direction (e.g., the Y direction) in a plane parallel to the substrate 1. Furthermore, the width of each interconnect (including 211 and 221) gradually decreases along the direction away from the substrate 1.

[0079] In some embodiments, the width of each connection portion (including 211 and 221) is reduced proportionally along the direction away from the substrate 1.

[0080] In some embodiments, the minimum width of each connecting portion (including 211 and 221) ranges from 100nm ± 20nm; for example, 80nm, 90nm, 100nm, 110nm, or 120nm. Here, the minimum width of the connecting portion is the width of its top surface.

[0081] In some embodiments of this disclosure, such as Figure 2 As shown, there is a gap G between adjacent connecting portions. In the first part 21, the width W1 of the connecting portion 211 gradually decreases along the direction away from the substrate 1, so that the longitudinal cross-sectional shape of the gap G between adjacent connecting portions 211 along the second direction (e.g., the X direction) is an inverted trapezoid (i.e., the top side length is greater than the bottom side length). Similarly, in the second part 22, the width W2 of the connecting portion 221 gradually decreases along the direction away from the substrate 1, so that the longitudinal cross-sectional shape of the gap G between adjacent connecting portions 221 along the second direction (e.g., the X direction) is an inverted trapezoid.

[0082] Based on the above embodiments, please refer to Figures 1-3 It is understood that the semiconductor structure also includes a first dielectric layer 3 that covers each connection portion and serves to insulate adjacent connections portions.

[0083] In some embodiments, the first dielectric layer 3 is formed of a nitride material, which may be a nitride layer, such as a silicon nitride (Si3N4) layer.

[0084] In some embodiments of this disclosure, please refer to Figures 1-3 The semiconductor structure also includes a second dielectric layer 4 and a conductive via 5. The second dielectric layer 4 covers the first dielectric layer 3. The conductive via 5 penetrates both the second dielectric layer 4 and the first dielectric layer 3, and is correspondingly connected to the connection portion in the connection layer 2.

[0085] In some embodiments, such as Figure 1 As shown, the semiconductor structure also includes a memory module C disposed within the cell array region S1. Figure 1 The diagram only illustrates the location of the storage module C, without describing its structure or quantity. That is, the storage module C can be located on the surface of the first dielectric layer 3 opposite to the first part 2, and connected to the connecting portion 211 in the first part 21. It can be understood that the storage module C, for example, is a storage capacitor, which can have a columnar structure and be stacked vertically. Furthermore, the storage capacitors can be positioned one-to-one above the unit transistors, indirectly connected to them via the connecting portion 211 in the first part 21.

[0086] From the above, please continue reading Figure 1The second dielectric layer 4 can be formed within the peripheral circuit region S2 and cover the surface of the first dielectric layer 3 facing away from the second portion 22. Since the memory module C has a certain height, the second dielectric layer 4 can have a large thickness so that the top surface of the second dielectric layer 4 is flush with the top surface of the memory module C. Alternatively, in addition to being formed in the peripheral circuit region S2, the second dielectric layer 4 can also include a portion formed in the cell array region S1 to cover the memory module C. This ensures a flat semiconductor structure.

[0087] In some embodiments, the second dielectric layer 4 is an oxide layer, such as a boro-phospho-silicate-Glass (BPSG) layer.

[0088] In addition, in some embodiments, according to the wiring requirements of the semiconductor structure and the connection requirements between the semiconductor structure and external devices, at least one interconnection structure can be provided above the second dielectric layer 4 to be connected to the connection layer 2 through the conductive hole 5, thereby realizing the peripheral wiring of the semiconductor structure and the bonding connection between the semiconductor structure and external devices.

[0089] In some embodiments, the thickness of the second dielectric layer 4 may range from 2000nm ± 500nm; for example, 1500nm, 1800nm, 2000nm, 2200nm, or 2500nm. However, it is not limited to these values.

[0090] As can be seen, the second dielectric layer 4 has a relatively large thickness. Thus, forming conductive holes 5 in the second dielectric layer 4 and the first dielectric layer 3 typically requires high aspect ratio ion etching. The first dielectric layer 3 is a nitride layer, and the second dielectric layer 4 is an oxide layer. Therefore, compared to the second dielectric layer 4, the first dielectric layer 3 has greater hardness, which can protect the connecting layer 2 during the etching process.

[0091] In summary, in the semiconductor structure provided by the embodiments of this disclosure, by setting the thickness T1 of the first portion 21 of the connection layer 2 in the cell array region S1 to be different from the thickness T2 of the second portion 22 in the peripheral circuit region S2, for example, making the thickness T2 of the second portion 22 greater than the thickness T1 of the first portion 21, the smaller thickness of the first portion 21 in the connection layer 2 can be used to form the connection portion 211 in the cell array region S1, and the larger thickness of the second portion 22 in the connection layer 2 can be used to form the connection portion 221 in the peripheral circuit region S2. In this way, the resistance of each connection portion 221 in the peripheral circuit region S2 can be reduced, thereby reducing the RC-Delay effect of the semiconductor structure.

[0092] Furthermore, in this embodiment, each connecting portion (including 211 and 221) extends along a first direction (e.g., the Y direction), and the width of each connecting portion (including 211 and 221) in a second direction (e.g., the X direction) gradually decreases in the direction away from the substrate 1, which makes the longitudinal cross-sectional shape of the interval G between adjacent connecting portions inverted trapezoidal. This facilitates the filling of an insulating medium between adjacent connecting portions to form a first dielectric layer 3 that covers the connecting portions and insulates the adjacent connecting portions, and ensures that the upper surface area of ​​the first dielectric layer 3 located between adjacent connecting portions is large. In addition, the thickness T2 of the second portion 22 in the connecting layer 2 is greater than the thickness T1 of the first portion 21, which makes the upper surface area of ​​the first dielectric layer 3 located between adjacent connecting portions 221 in the peripheral circuit region S2 larger, and also helps to ensure the morphological stability of each connecting portion and the deep trench structure when fabricating a deep trench structure (e.g., conductive hole 5) above the connecting portion 221.

[0093] As can be seen, in this embodiment, the connection portions (including 211 and 221) adopt the above structure, which facilitates increasing the size of the contact windows of the connection portions (including 211 and 221), so as to stably fabricate deep trench structures above the connection portions and effectively reduce the risk of short circuits or open circuits between adjacent connection portions. In this way, the fabrication stability and production yield of semiconductor structures can be improved.

[0094] Based on the same inventive concept, please refer to Figure 4 This disclosure provides a method for fabricating a semiconductor structure, using some embodiments thereof, for preparing the semiconductor structures described in the above embodiments. The semiconductor fabrication method provided by this disclosure is used to prepare the semiconductor structures described in the above embodiments. This fabrication method also possesses the technical advantages of the above-described semiconductor structures, and will not be detailed here. The fabrication method includes the following steps.

[0095] S100 provides a substrate having a cell array region and a peripheral circuit region.

[0096] S200, a connection layer is formed above the substrate. The connection layer includes a first portion located in the cell array region and a second portion located in the peripheral circuit region. The thickness of the second portion is greater than the thickness of the first portion.

[0097] In some embodiments of this disclosure, the first portion and / or the second portion includes a plurality of connecting portions; adjacent connecting portions are spaced apart. See also... Figure 5 The preparation method further includes the following steps.

[0098] S300, a first dielectric layer is formed, which covers the connection portion and fills the gap.

[0099] S400, forming a second dielectric layer, the second dielectric layer covering the first dielectric layer.

[0100] S500, forming a via through the second dielectric layer and the first dielectric layer, so that a portion of the second portion is exposed within the via.

[0101] S600, the through hole is filled with conductive material to form a conductive hole.

[0102] In addition, please continue to refer to Figure 5 In some embodiments of this disclosure, step S200, forming a connection layer over the substrate, includes the following steps.

[0103] S210, depositing bonding material on top of the substrate.

[0104] S220, a first mask is formed over the bonding material. The first mask has a first pattern, which is used to define the cell array region.

[0105] S230, based on the first pattern, remove part of the connecting material to form a first part located in the cell array region and a second part located in the peripheral circuit region.

[0106] And, please see Figure 6 In some embodiments of this disclosure, step S230 involves removing a portion of the connecting material based on the first pattern to form a first portion located in the cell array region and a second portion located in the peripheral circuit region, including the following steps.

[0107] S231, based on the first pattern, remove the portion of the connecting material located in the unit array region to form an initial second part.

[0108] S232, based on the first pattern, a connecting material of the target thickness is deposited again in the cell array region to form the initial first part.

[0109] S233, remove the first mask.

[0110] S234, forming a second mask covering the initial second part and the initial first part, the second mask having a second pattern.

[0111] S235, based on the second pattern, etch an initial first portion to form a first portion, and etch an initial second portion to form a second portion.

[0112] To more clearly illustrate the semiconductor structure and its fabrication method provided in the embodiments of this disclosure, the following embodiments are combined with... Figures 4 to 19 The preparation method and the resulting structure are described in detail, but are not limited to this. Figure Xb is a partial cross-sectional view of the structure shown in Figure Xa along the A-A' direction, and should not be interpreted as a strictly corresponding cross-sectional view.

[0113] In step S100, please refer to Figure 7a and Figure 7b A substrate 1 is provided, which has a cell array region S1 and a peripheral circuit region S2.

[0114] Here, cell array region S1 refers to the region in a semiconductor structure used to form a cell array, such as the region forming a memory cell array. In DRAM, each memory cell in the memory cell array includes a transistor and a storage capacitor. The transistors in cell array region S1 are disposed within the substrate 1, and the storage capacitors can be stacked on top of the substrate 1 and connected to the aforementioned transistors. Peripheral circuit region S2 is located on at least one side of cell array region S1, such as the side or periphery, and refers to the region in the semiconductor structure used to form peripheral circuits. In DRAM, peripheral circuits can be connected by multiple transistors and other electronic components (such as capacitors, resistors, etc.) according to design requirements to achieve specific functions.

[0115] In some embodiments, a trench isolation structure 11 is provided in the substrate 1, which can be used to divide multiple active regions in the substrate 1 so that each transistor can be formed in the corresponding active region.

[0116] In some embodiments, a device layer 12 is further formed on the surface of the substrate 1. The device layer 12 may be, for example, a layer structure for forming bit lines or bit line contact structures and other devices connected to the transistor, or it may be other functional dielectric films located on top of the transistor. The device layer 12 may include, for example, multiple thin films such as conductive layers and dielectric layers, and the specific configuration can be selected according to actual needs.

[0117] In step S200, please refer to Figure 8a and Figures 8b to 13a and Figure 13b A connection layer 2 is formed above the substrate 1. The connection layer 2 includes a first portion 21 located in the cell array region S1 and a second portion 22 located in the peripheral circuit region S2. The thickness of the second portion 22 is greater than the thickness of the first portion 21.

[0118] Step S200 can be achieved, for example, through the following steps.

[0119] In step S210, please refer to Figure 8a and Figure 8b Connecting material 20 is deposited on top of substrate 1.

[0120] Here, matching the structure on substrate 1 in some of the aforementioned embodiments, the connection material 20 can be deposited on the surface of device layer 12 facing away from substrate 1. The connection material 20 is formed of a conductive material, such as tungsten metal or copper metal.

[0121] In step S220, please refer to Figure 9a and Figure 9b A first mask Y1 is formed over the connecting material 20. The first mask Y1 has a first pattern M1, which is used to define the cell array region S1.

[0122] In some embodiments, the first mask Y1 is a photoresist layer.

[0123] In step S230, please refer to Figure 10a and Figures 10b to 13a and Figure 13b Based on the first pattern M1, a portion of the connecting material 20 is removed to form a first portion 21 located in the unit array region S1 and a second portion 22 located in the peripheral circuit region S2.

[0124] In some embodiments of this disclosure, step S230 involves removing a portion of the connecting material based on the first pattern to form a first portion located in the cell array region and a second portion located in the peripheral circuit region, including the following steps.

[0125] In step S231, please refer to Figure 10a and Figure 10b Based on the first pattern M1, the portion of the connecting material 20 located in the unit array region S1 is removed to form the initial second part 22A.

[0126] In step S232, please continue reading. Figure 10a and Figure 10b Based on the first pattern M1, a connecting material of the target thickness is deposited again in the cell array region S1 to form the initial first part 21A.

[0127] Here, it is understood that the initial first portion 21A can also be formed by removing a portion of the connecting material 20 located in the cell array region S1. Compared to directly forming the initial first portion 21A by removing a portion of the connecting material 20, the present embodiment of the present disclosure, by removing a portion of the connecting material 20 and then depositing the same material again, can precisely control the formation thickness of the initial first portion 21A. This ensures that the formation thickness of the first portion 21 meets the usage requirements while reducing the thickness of the first portion 21 relative to the thickness of the second portion 22 in the connecting layer 2.

[0128] In step S233, the first mask Y1 is removed.

[0129] Here, after the initial first part 21A and the initial second part 22A are formed, a suitable method can be selected to peel off and remove them according to the material properties of the first mask Y1.

[0130] In step S234, please refer to Figure 11a and Figure 11bA second mask Y2 is formed covering the initial second portion 22A and the initial first portion 21A, the second mask Y2 having a second pattern ( Figure 11a and Figure 11b (Not shown in the image).

[0131] Here, the second pattern in the second mask Y2 matches the pattern design to be formed in the connecting layer 2.

[0132] In some embodiments, the first portion 21 and / or the second portion 22 of the connection layer 2 include multiple connection portions, and there is a gap between adjacent connection portions, in accordance with the placement positions of the transistors within the matching substrate 1. Correspondingly, the second pattern in the second mask Y2 can match the spacing design between adjacent connection portions. Specifically, the connection portion 211 of the first portion 21 can be connected to a corresponding unit transistor, and the connection portion of the second portion 22 can be connected to a corresponding peripheral transistor.

[0133] In some embodiments, compared to the first mask Y1, the second mask Y2 is used for finer etching, such as for achieving dual-pattern self-aligned etching. The second mask Y2 may include a first hard mask Y21 and a first anti-reflective layer Y22 stacked together. Furthermore, to match the different thicknesses of the first portion 21 and the second portion 22 in the connecting layer 2, the second mask Y2 is also used to level the surface height. The second hard mask Y2 may also include a spin-coated hard mask to ensure the top surface of the second mask Y2 is flat; alternatively, a chemical mechanical polishing process can be used to ensure the top surface of the second mask Y2 is flat. This facilitates etching on a flat surface, allowing for precise control of the etching depth.

[0134] In step S235, please refer to Figure 12a and Figures 12b to 13a and Figure 13b Based on the second pattern in the second mask, an initial first portion 21A is etched to form the first portion 21, and an initial second portion 22A is etched to form the second portion 22.

[0135] It is understood that the etching of the initial first portion 21A and the initial second portion 22A can be performed simultaneously or in separate steps. This disclosure does not limit this process.

[0136] In addition, please see Figure 12b and Figure 13bIn some embodiments, the connecting portion 211 in the first portion 21 and the connecting portion 221 in the second portion 22 may extend along a first direction (e.g., the Y direction), and the width of each connecting portion (including 211 and 221) gradually decreases along the direction away from the substrate 1. The dimension of each connecting portion (including 211 and 221) in the second direction (e.g., the X direction) is the width of the connecting portion (including 211 and 221). The second direction (e.g., the X direction) is perpendicular to the first direction (e.g., the Y direction) in a plane parallel to the substrate 1. Further, in some embodiments, the width of each connecting portion (including 211 and 221) decreases proportionally along the direction away from the substrate 1.

[0137] Thus, there is a gap G between adjacent connecting portions. In the first part 21, the width W1 of the connecting portion 211 gradually decreases along the direction away from the substrate 1, so that the longitudinal cross-sectional shape of the gap G between adjacent connecting portions 211 along the second direction (e.g., the X direction) is an inverted trapezoid. Similarly, in the second part 22, the width W2 of the connecting portion 221 gradually decreases along the direction away from the substrate 1, so that the longitudinal cross-sectional shape of the gap G between adjacent connecting portions 221 along the second direction (e.g., the X direction) is an inverted trapezoid.

[0138] Accordingly, in some embodiments of this disclosure, the etching method for the initial first portion 21A and the initial second portion 22A includes: lateral etching using a fluorine-containing gas, wherein the etching rate gradually decreases as the etching depth increases.

[0139] Here, using a fluorine-containing gas for lateral etching means that the etching intensity in the direction parallel to substrate 1 (i.e., lateral, including the X and Y directions) is greater than the etching intensity in the direction perpendicular to substrate 1 (e.g., the Z direction). Furthermore, by gradually decreasing the etching rate as the etching depth increases, a spacing G with an inverted trapezoidal cross-sectional shape along the second direction (e.g., the X direction) can be formed between adjacent connections.

[0140] It should be added that the etching methods for the initial first portion 21A and the initial second portion 22A described above can be implemented under specific process conditions, and can be specifically designed according to requirements. In some embodiments of this disclosure, the reaction chamber pressure of the initial first portion 21A and the initial second portion 22A can be controlled within the range of 3 mTorr to 6 mTorr; for example, 3 mTorr, 3.5 mTorr, 4 mTorr, 4.5 mTorr, 5 mTorr, 5.5 mTorr, or 6 mTorr. That is, it can be performed under a relatively low reaction chamber pressure environment.

[0141] In some embodiments, the power of the radio frequency source ranges from 500W to 600W; for example, 500W, 520W, 540W, 560W, 580W, or 600W.

[0142] In some embodiments, the RF bias power ranges from 100W to 150W; for example, 100W, 110W, 120W, 130W, 140W, or 150W. Furthermore, the RF bias direction is chosen to be perpendicular to the substrate 1 and downwards, meaning that the initial first portion 21A and the initial second portion 22A can be performed under a relatively weak downward bias environment.

[0143] It should be added that the angle formed by the sides of each connector (including 211 and 221) relative to the substrate 1 can be adjusted by controlling the etching rate and etching time. Furthermore, after the initial structure of the connector is formed, the morphology of each connector can be refined to precisely control the angle formed by the sides of each connector (including 211 and 221) relative to the substrate 1.

[0144] In step S300, please refer to Figure 14 A first dielectric layer 3 is formed, which covers the connecting portion (including 211 and 221) and fills the interval G.

[0145] In some embodiments, the first dielectric layer 3 is formed of a nitride material, such as silicon nitride.

[0146] After etching to form multiple connections (including 211 and 221) and the spacing G between adjacent connections, the longitudinal cross-sectional shape of the spacing between adjacent connections along the second direction (e.g., the X direction) is an inverted trapezoid. This facilitates the filling of insulating medium between adjacent connections to form a first dielectric layer 3 that covers the connections and insulates adjacent connections, and ensures that the upper surface area of ​​the first dielectric layer 3 located between adjacent connections is large. Furthermore, the thickness of the second portion 22 in the connection layer 2 is greater than the thickness of the first portion 21, which allows the upper surface area of ​​the first dielectric layer 3 located within the peripheral circuit region S2 between adjacent connections to be even larger.

[0147] In step S400, please refer to Figure 15 A second dielectric layer 4 is formed, which covers the first dielectric layer 3.

[0148] In some embodiments, to match the structure on the first dielectric layer 3, the second dielectric layer 4 may partially cover the first dielectric layer 3. For example, the second dielectric layer 4 may be formed within the peripheral circuit region S2 and cover the surface of the first dielectric layer 3 opposite to the second portion 22.

[0149] In some embodiments, the second dielectric layer 4 may be formed of an oxide material, such as boro-phospho-silicate glass (BPSG).

[0150] In some embodiments, the second dielectric layer 4 has a relatively large thickness. For example, the thickness of the second dielectric layer 4 may range from 2000nm ± 500nm; for example, 1500nm, 1800nm, 2000nm, 2200nm, or 2500nm.

[0151] In step S500, please refer to Figures 16-18 A through-hole H is formed that penetrates the second dielectric layer 4 and the first dielectric layer 3, so that a portion of the second portion 22 is exposed within the through-hole H.

[0152] As can be seen from the above embodiments, the second dielectric layer 4 has a relatively large thickness. Therefore, forming conductive holes 5 in the second dielectric layer 4 and the first dielectric layer 3 typically requires high aspect ratio ion etching. The first dielectric layer 3 is a nitride layer, and the second dielectric layer 4 is an oxide layer. Thus, compared to the second dielectric layer 4, the first dielectric layer 3 has greater hardness, which can protect the interconnect layer 2 during etching. Furthermore, in the example where each interconnection and adjacent interconnection in the interconnect layer 2 adopts the aforementioned structure, the longitudinal cross-sectional shape of the portion of the first dielectric layer 3 filling the gap G between adjacent interconnections can be inverted trapezoidal, i.e., having a larger top surface area. This facilitates increasing the size of the contact windows of the interconnections (including 211 and 221), enabling the stable fabrication of deep trench structures (e.g., the subsequently formed conductive holes 5) above the interconnections. This ensures the morphological stability of the deep trench structure and effectively reduces the risk of short circuits or open circuits between adjacent interconnections. In this way, the fabrication stability and production yield of the semiconductor structure can be improved.

[0153] For example, please refer to Figure 16 A third mask Y3 and a photoresist layer PR are stacked on the second dielectric layer 4; wherein, the photoresist layer PR has an opening K, which is used to define the third pattern; the third mask Y3 includes a second hard mask Y31 and a second anti-reflection layer Y32 stacked on top of each other.

[0154] Please see Figure 17 The third mask Y3 is etched based on the opening K in the photoresist layer PR, and a third pattern M3 can be formed in the third mask Y3. After the third pattern M3 is formed, the photoresist layer PR can be stripped away.

[0155] Please see Figure 18 Based on the third pattern M3 in the third mask Y3, the second dielectric layer 4 and the first dielectric layer 3 are etched to form a via H that penetrates the second dielectric layer 4 and the first dielectric layer 3, so that a portion of the second portion 22 (e.g., a portion of the connecting portion 221) is exposed in the via H. After forming the via H, the third mask Y3 is stripped away.

[0156] In step S600, please refer to Figure 19Conductive material is filled into the through hole H to form a conductive hole 5.

[0157] In some embodiments, the conductive material may be tungsten metal or copper metal, etc. The conductive hole 5 penetrates the second dielectric layer 4 and the first dielectric layer 3, and is correspondingly connected to the connecting portion in the connecting layer 2.

[0158] In addition, in some embodiments, according to the wiring requirements of the semiconductor structure and the connection requirements between the semiconductor structure and external devices, at least one interconnection structure can be provided above the second dielectric layer 4 to be connected to the connection layer 2 through the conductive hole 5, thereby realizing the peripheral wiring of the semiconductor structure and the bonding connection between the semiconductor structure and external devices.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a cell array region and a peripheral circuit region; A bonding layer is formed above the substrate; The connection layer includes a first portion located in the cell array region and a second portion located in the peripheral circuit region; The thickness of the second part is greater than the thickness of the first part; The step of forming a connection layer over the substrate includes: depositing a connection material over the substrate; A first mask is formed over the connecting material; the first mask has a first pattern, which is used to define the cell array region. Based on the first pattern, a portion of the connecting material is removed to form the first portion located in the unit array region and the second portion located in the peripheral circuit region; The step of removing a portion of the connecting material based on the first pattern to form the first portion located in the cell array region and the second portion located in the peripheral circuit region includes: Based on the first pattern, the portion of the connecting material located in the unit array region is removed to form an initial second part; Based on the first pattern, the connecting material of the target thickness is deposited again in the cell array region to form the initial first part; Remove the first mask; A second mask is formed covering the initial second portion and the initial first portion, the second mask having a second pattern; Based on the second pattern, the initial first portion is etched to form the first portion, and the initial second portion is etched to form the second portion.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching method for the initial first part and the initial second part includes: using a fluorine-containing gas for lateral etching, and the etching rate gradually decreases as the etching depth increases.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The range of reaction chamber pressure for etching the initial first part and the initial second part is 3mTorr to 6mTorr; the range of RF source power is 500W to 600W; and the range of RF bias power is 100W to 150W.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that, The first part and / or the second part includes a plurality of connecting portions; there is a gap between adjacent connecting portions; the manufacturing method further includes: A first dielectric layer is formed, which covers the connection portion and fills the gap; A second dielectric layer is formed, which covers the first dielectric layer; A via is formed that penetrates the second dielectric layer and the first dielectric layer, so that a portion of the second portion is exposed within the via; The through-hole is filled with conductive material to form a conductive hole.

5. A semiconductor structure, characterized in that, The semiconductor structure has a cell array region and a peripheral circuit region. The semiconductor structure is prepared by the method for preparing a semiconductor structure according to claim 1. The semiconductor structure includes: a substrate; a connection layer located above the substrate, including a first portion located in the cell array region and a second portion located in the peripheral circuit region; wherein the thickness of the second portion is greater than the thickness of the first portion.

6. The semiconductor structure according to claim 5, characterized in that, The thickness of the second part is greater than or equal to twice the thickness of the first part.

7. The semiconductor structure according to claim 6, characterized in that, The thickness of the second part ranges from 60nm to 80nm.

8. The semiconductor structure according to claim 5, characterized in that, The first portion and / or the second portion includes a plurality of connecting portions; the connecting portions extend along a first direction; a second direction is perpendicular to the first direction in a plane parallel to the substrate, and the dimension of the connecting portion in the second direction is the width of the connecting portion; wherein, the width of the connecting portion gradually decreases along the direction away from the substrate; the semiconductor structure further includes: a first dielectric layer covering the connecting portions and used to insulate adjacent connecting portions.

9. The semiconductor structure according to claim 8, characterized in that, The width of the connection portion decreases proportionally along the direction away from the substrate.

10. The semiconductor structure according to claim 8, characterized in that, The minimum width of the connecting part ranges from 100nm to 20nm.

11. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes: a second dielectric layer covering the first dielectric layer; and a conductive via penetrating the second dielectric layer and the first dielectric layer, and correspondingly connected to the connection portion.

12. The semiconductor structure according to claim 11, characterized in that, The thickness of the second dielectric layer ranges from 2000nm to 500nm.

13. The semiconductor structure according to claim 5, characterized in that, The substrate includes: a unit transistor located in the unit array region, and a peripheral transistor located in the peripheral circuit region; wherein, the first part is connected to the unit transistor; and the second part is connected to the peripheral transistor.

14. The semiconductor structure according to claim 5, characterized in that, The substrate includes: a unit transistor and a memory module located within the unit array region, and a peripheral transistor located within the peripheral circuit region; The storage module is located above the unit transistor and is connected to the unit transistor; the first part is connected to the storage module; and the second part is connected to the peripheral transistor.

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