Method of forming deep trench capacitor
By using low-temperature etching and a specific gas combination, the problem of polymer deposition in contact holes was solved, the defect rate of deep trench capacitors was reduced, and the stability and reliability of the devices were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2023-09-27
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, when forming contact holes for deep trench capacitors, polymer deposits are deposited on the bottom and sidewalls of the contact holes, which are difficult to remove, leading to capacitor defects.
A low-temperature etching process is adopted, using etching gases C5F8, O2 and Ar, followed by the introduction of CF4, Ar and CO, and finally O2. The etching temperature is controlled at 35℃~45℃ to form contact holes, and the polymer is removed by the combination of CF4 and CO gases to protect the sidewalls of the contact holes.
It effectively removes polymer from the bottom and sidewalls of the contact holes, reduces the defect rate of deep trench capacitors, and improves the stability and reliability of the devices.
Smart Images
Figure CN117219624B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a deep trench capacitor. Background Technology
[0002] With the rapid development of various application fields, the performance requirements for semiconductor integrated circuit devices are becoming increasingly demanding, leading to higher integration density and smaller individual device sizes. This necessitates even smaller device dimensions. Consequently, deep trench capacitors (DTCs) were developed, shifting the planar chip area footprint to a vertical design within the silicon wafer. Deep trench capacitors (DTCs) are widely used in antenna matching, RF filtering, and IC decoupling, especially in applications with height and size constraints. They exhibit very high stability and extremely low leakage current even under high bias voltages, playing a crucial role in some industrial sectors.
[0003] Existing deep trench capacitors stack an oxide layer and a gate polysilicon layer within a deep trench, both extending to the surface of the substrate. Sidewalls are also present on the substrate, covering the gate polysilicon layer and the oxide layer. Interconnect structures are also present on the substrate, including contact holes connected to the substrate or the gate polysilicon layer, and metal layers connected to the contact holes. The existing deep trench capacitor formation method involves first providing a substrate, forming a deep trench within the substrate, and then forming stacked oxide and gate polysilicon layers within the deep trench, both extending to a portion of the substrate surface. Next, sidewalls are formed to cover the gate polysilicon layer and oxide layer on the substrate surface. Then, an interlayer dielectric layer is formed on the surface of the substrate and the surface of the gate polysilicon layer. An anti-reflection layer and a photoresist layer are sequentially formed on the interlayer dielectric layer, with a patterned photoresist layer exposing the surface of the bottom anti-reflection coating to be etched. Next, a patterned photoresist layer is used to etch the interlayer dielectric layer to form multiple contact holes. The contact holes have a depth of 1.2 μm, a width of 0.3 μm, and an aspect ratio greater than 4. Then, the photoresist layer and the bottom anti-reflective coating are removed using O2 ashing and organic solvent wet etching at a temperature greater than 200°C. The etching of the interlayer dielectric layer to form contact holes is completed within an etching chamber, and the gases introduced during etching are C5F8, O2, and Ar, at a temperature of 0°C.
[0004] However, when forming contact holes using existing techniques, polymers are deposited on the bottom and sidewalls of the contact holes. Furthermore, due to the large depth-to-width ratio of the contact holes, the polymer at the bottom is difficult to remove. After subsequent wet removal of the photoresist layer and the bottom anti-reflective coating using organic solvents, the polymer at the bottom of the contact hole migrates to the substrate surface, potentially causing defects in deep trench capacitors. Summary of the Invention
[0005] The purpose of this invention is to provide a method for forming a deep trench capacitor, which can remove the polymer deposited on the bottom and sidewalls of the contact hole when forming the contact hole by etching the interlayer dielectric layer, thereby reducing the probability of defects in the deep trench capacitor.
[0006] To achieve the above objectives, the present invention provides a deep trench capacitor, comprising:
[0007] A substrate is provided in which deep trenches are formed;
[0008] Stacked oxide layers and gate polysilicon layers are formed within the deep trench, and the stacked oxide layers and gate polysilicon layers extend to a portion of the surface of the substrate.
[0009] An interlayer dielectric layer, a bottom anti-reflection coating, and a patterned photoresist layer are sequentially formed on the surface of the substrate and the surface of the gate polysilicon on the substrate;
[0010] Using a patterned photoresist layer, etching gases C5F8, O2 and Ar are introduced into the etching chamber, and the etching temperature is set to 35℃~45℃. The bottom anti-reflective coating and the interlayer dielectric layer are etched sequentially to form contact holes in the interlayer dielectric layer and the bottom anti-reflective coating. The aspect ratio of the contact holes is greater than 4.
[0011] Continue to introduce gases CF4, Ar and CO into the etching chamber at a temperature of 35℃~45℃. The flow rate of gas CF4 is 5sccm~10sccm, the flow rate of gas Ar is 100sccm~500sccm, the flow rate of gas CO is 50sccm~200sccm, the pressure is 10mT~30mT, and the power is 500W~800W.
[0012] Continue to introduce O2 into the etching cavity at a temperature of 35℃~45℃.
[0013] Optionally, in the method for forming the deep trench capacitor, the substrate comprises a wafer.
[0014] Optionally, in the method for forming the deep trench capacitor, the interlayer dielectric layer includes a silicon nitride layer or a silicon oxide layer.
[0015] Optionally, in the method for forming the deep trench capacitor, the depth of the contact hole is 1.2 μm to 1.3 μm and the width is 0.25 μm to 0.3 μm.
[0016] Optionally, in the method for forming the deep trench capacitor, the method of sequentially forming an interlayer dielectric layer, a bottom anti-reflective coating, and a patterned photoresist layer on the surface of the substrate and the surface of the gate polysilicon on the substrate includes:
[0017] An interlayer dielectric layer, a bottom anti-reflection coating, and a photoresist layer are sequentially formed on the surface of the substrate and on the surface of the gate polysilicon on the substrate.
[0018] The photoresist layer is exposed to obtain a patterned photoresist layer.
[0019] Optionally, in the method for forming a deep trench capacitor, after continuing to introduce O2 into the etching cavity, the method further includes:
[0020] Remove the patterned photoresist layer and the bottom anti-reflective coating.
[0021] Optionally, in the method for forming the deep trench capacitor, the method for removing the patterned photoresist layer and the bottom anti-reflective coating includes:
[0022] At a temperature of 130℃~200℃, O2 ashing was used to remove part of the photoresist layer and the bottom anti-reflective coating;
[0023] The photoresist layer and the bottom anti-reflective coating were removed using a wet method with organic solvents.
[0024] Optionally, in the method for forming the deep trench capacitor, after removing the patterned photoresist layer and the bottom anti-reflective coating, the method further includes:
[0025] Fill the contact hole with metal.
[0026] Optionally, in the method for forming the deep trench capacitor, after filling the contact hole with metal, the method further includes:
[0027] A metal layer is formed on the interlayer dielectric layer and the contact hole, the contact hole connecting the contact layer to the substrate or the gate polysilicon layer.
[0028] The method for forming a deep trench capacitor provided by the present invention includes: providing a substrate; forming a deep trench in the substrate, forming a stacked oxide layer and a gate polysilicon layer in the deep trench, wherein the stacked oxide layer and the gate polysilicon layer extend to a portion of the surface of the substrate; sequentially forming an interlayer dielectric layer, a bottom anti-reflection coating, and a patterned photoresist layer on the surface of the substrate and the surface of the gate polysilicon on the substrate; using the patterned photoresist layer, introducing etching gases C5F8, O2, and Ar into an etching chamber, and setting the etching temperature to 35°C to 45°C, sequentially etching the bottom anti-reflection coating and the... An interlayer dielectric layer is formed to create contact holes in the interlayer dielectric layer and the bottom anti-reflective coating. The aspect ratio of the contact holes is greater than 4. Gases CF4, Ar, and CO are continuously introduced into the etching chamber at a temperature of 35°C to 45°C. The flow rate of CF4 is 5 sccm to 10 sccm, the flow rate of Ar is 100 sccm to 500 sccm, and the flow rate of CO is 50 sccm to 200 sccm. The pressure is 10 mT to 30 mT, and the power is 500 W to 800 W. O2 is then introduced into the etching chamber at the same temperature. This invention uses etching gases at 35°C to 45°C to form contact holes in the interlayer dielectric layer, making the polymer generated during etching more volatile. After etching, CF4, Ar, and CO are continued to be introduced. CF4 makes the remaining polymer more porous and easier to remove, while CO protects the sidewalls of the contact holes and also helps the polymer to be removed more easily. Finally, pure O2 is introduced to completely remove the polymer. The removal of polymer deposited at the bottom and sidewalls of the contact hole during the etching of the interlayer dielectric layer reduces the likelihood of defects in deep trench capacitors. Attached Figure Description
[0029] Figure 1 This is a flowchart of a method for forming a deep trench capacitor according to an embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of a deep trench capacitor after deep trenches have been formed according to an embodiment of the present invention;
[0031] Figure 3 This is a schematic diagram of a deep trench capacitor after forming a stacked oxide layer and a gate polysilicon layer according to an embodiment of the present invention;
[0032] Figure 4 This is a schematic diagram of a deep trench capacitor after the contact holes are formed according to an embodiment of the present invention;
[0033] Figure 5 This is a schematic diagram of a deep trench capacitor after removing the bottom anti-reflective coating and photoresist layer according to an embodiment of the present invention;
[0034] Figure 6 This is a schematic diagram of a deep trench capacitor after the metal layer has been formed according to an embodiment of the present invention;
[0035] In the figure: 110-substrate, 120-deep trench, 131-first oxide layer, 141-first polysilicon layer, 132-second oxide layer, 142-second polysilicon layer, 133-third oxide layer, 143-third polysilicon layer, 150-sidewall, 160-interlayer dielectric layer, 170-contact hole, 180-bottom anti-reflective coating, 190-photoresist layer, 200-metal layer. Detailed Implementation
[0036] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0037] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0038] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0039] Please refer to Figure 1 The present invention provides a method for forming a deep trench capacitor, comprising:
[0040] S11: Provide a substrate in which a deep trench is formed;
[0041] S12: A stacked oxide layer and a gate polysilicon layer are formed in the deep trench, and the stacked oxide layer and the gate polysilicon layer extend to a portion of the surface of the substrate.
[0042] S13: An interlayer dielectric layer, a bottom anti-reflection coating, and a patterned photoresist layer are sequentially formed on the surface of the substrate and the surface of the gate polysilicon on the substrate;
[0043] S14: Using a patterned photoresist layer, etching gases C5F8, O2 and Ar are introduced into the etching chamber, and the etching temperature is set to 35℃~45℃. The bottom anti-reflective coating and the interlayer dielectric layer are etched sequentially to form contact holes in the interlayer dielectric layer and the bottom anti-reflective coating. The aspect ratio of the contact holes is greater than 4.
[0044] S15: Continue to introduce gases CF4, Ar and CO into the etching chamber at a temperature of 35℃~45℃. The flow rate of gas CF4 is 5sccm~10sccm, the flow rate of gas Ar is 100sccm~500sccm, the flow rate of gas CO is 50sccm~200sccm, the pressure is 10mT~30mT, and the power is 500W~800W.
[0045] S16: Continue to introduce O2 into the etching cavity at a temperature of 35℃~45℃.
[0046] For details, please refer to Figure 2 First, a substrate 110 is provided. The substrate 110 can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate can also be silicon, germanium, gallium arsenide, or a silicon-germanium compound. In this embodiment of the invention, the substrate material is silicon, for example, a wafer can be selected.
[0047] Next, a plurality of deep trenches 120 are formed in the substrate 110. The specific steps for forming the deep trenches 120 may be as follows: a patterned mask layer is formed on the surface of the substrate 110, the patterned mask layer defines the width, depth and position of the deep trenches, etc., and then the substrate 110 is etched with the patterned mask layer as a mask to form the deep trenches 120 located in the substrate 110.
[0048] Next, please refer to Figure 3Stacked oxide and polysilicon layers are formed in a deep trench 120, including a first oxide layer 131, a first polysilicon layer 141, a second oxide layer 132, a second polysilicon layer 142, a third oxide layer 133, and a third polysilicon layer 143 sequentially stacked on the bottom and sidewalls of the deep trench 120. The stacked oxide and polysilicon layers extend to a portion of the surface of the substrate 110, that is, the first oxide layer 131, the first polysilicon layer 141, the second oxide layer 132, the second polysilicon layer 142, the third oxide layer 133, and the third polysilicon layer 143 are sequentially stacked starting from a portion of the surface of the substrate 110. The first polysilicon layer 141, the second polysilicon layer 142, and the third polysilicon layer 143 can also be referred to as capacitor electrodes. Each polysilicon layer can be formed using plating, physical vapor deposition (PVD), ALD, CVD, or a combination thereof. Sidewalls 150 are formed at both ends of the first polysilicon layer 141, the second polysilicon layer 142, and the third polysilicon layer 143 on the substrate 110, respectively. The sidewalls 150 cover the sidewalls of the first polysilicon layer 141 and the first oxide layer 131, the second polysilicon layer 142 and the second oxide layer 132, and the third polysilicon layer 143 and the third oxide layer 133, respectively. In this embodiment, the sidewalls 150 are made of silicon oxide or silicon nitride. Preferably, silicon oxide or silicon nitride is deposited using ALD or CVD in a blanket deposition process.
[0049] Next, please refer to Figure 4 An interlayer dielectric layer 160 is deposited on the substrate 110, which is not covered by the polycrystalline silicon layer, and on the polycrystalline silicon layer. In this embodiment of the invention, the interlayer dielectric layer 160 is borophosphosilicate glass (BPSG), which can be formed by a variety of suitable methods, such as spin coating, CVD, PECVD, and ALD.
[0050] Next, please continue to refer to Figure 4The interlayer dielectric layer 160 is etched to form the contact hole 170. The etching method for the interlayer dielectric layer 160 is as follows: a bottom anti-reflective coating 180 and a photoresist layer 190 are sequentially formed on the interlayer dielectric layer 160. The thickness of the bottom anti-reflective coating 180 is 960 angstroms, and the thickness of the photoresist layer 190 is 10,000 angstroms. Next, the photoresist layer 190 is patterned, exposing a portion of the surface of the bottom anti-reflective coating 180. The exposed portion is subsequently used for etching to form the contact hole 170. Next, the bottom anti-reflective coating 180 and the interlayer dielectric layer 160 are sequentially etched downwards from the surface of the bottom anti-reflective coating 180, which is not covered by the patterned photoresist layer 190, to form a contact hole 170 located within the bottom anti-reflective coating 180 and the interlayer dielectric layer 160. The contact hole 170 exposes the surface of the substrate 110. The depth of the contact hole 170 is 1.2 μm to 1.3 μm, and the width of the contact hole 170 is 0.25 μm to 0.3 μm. If the cross-section of the contact hole 170 is circular, then the diameter of the circle is 0.25 μm to 0.3 μm. Therefore, the aspect ratio of the contact hole 170 is greater than 4, which is a large aspect ratio. During etching, polymers are generated and tend to deposit on the bottom and sidewalls. Due to the large aspect ratio of the contact hole 170, the polymer at the bottom of the contact hole 170 is very difficult to remove. The method for etching the interlayer dielectric layer 160 in this embodiment of the invention involves simultaneously introducing etching gases C5F8, O2, and Ar into the etching chamber, and setting the etching temperature to 30°C–50°C, for example, 40°C, to etch the interlayer dielectric layer 160. After etching is complete, gases CF4, Ar, and CO are continuously introduced into the etching chamber. The flow rate of CF4 is 5 sccm–10 sccm, the flow rate of Ar is 100 sccm–500 sccm, the flow rate of CO is 50 sccm–200 sccm, the pressure of each is 10 mT–30 mT, and the power is 500 W–800 W. This embodiment of the invention changes the temperature of the etching equipment from 0°C in the prior art to 40°C, and after etching is complete, gases CF4, Ar, and CO are continuously introduced into the etching chamber. CF4 loosens the polymer at the bottom of the contact hole, making it easier to remove, while CO provides oxygen to help remove the polymer while providing sidewall protection for the contact hole. Finally, most of the polymer is removed by rinsing with pure O2.
[0051] Next, please refer to Figure 5 The photoresist layer 190 and the bottom anti-reflective coating 180 are removed by O2 ashing at a temperature of 130°C to 200°C. Finally, the remaining photoresist layer 190 and bottom anti-reflective coating 180 are further removed using an organic solvent to clean the surface of the interlayer dielectric layer 160.
[0052] Next, please refer to Figure 6The contact hole 170 is filled with metal. In this embodiment, the contact hole 170 includes a contact hole formed above the substrate 110 and a contact hole formed above the polysilicon layer. The metal can be copper, aluminum, tungsten, a combination thereof, or an alloy thereof. Next, a metal layer 200 is formed on the surface of the interlayer dielectric layer 160 and the contact hole 170. In this embodiment, the metal layer 200 is connected to the substrate 110 or the polysilicon layer through the contact hole 170.
[0053] In summary, the method for forming a deep trench capacitor provided in this embodiment of the invention includes: providing a substrate; forming a deep trench in the substrate, forming a stacked oxide layer and a gate polysilicon layer in the deep trench, wherein the stacked oxide layer and the gate polysilicon layer extend to a portion of the substrate surface; sequentially forming an interlayer dielectric layer, a bottom anti-reflection coating, and a patterned photoresist layer on the surface of the substrate and the surface of the gate polysilicon on the substrate; using the patterned photoresist layer, introducing etching gases C5F8, O2, and Ar into an etching chamber, and setting the etching temperature to 35°C to 45°C, sequentially etching the bottom anti-reflection layer. The etching process involves creating contact holes in the interlayer dielectric layer and the bottom anti-reflective coating, with an aspect ratio greater than 4. Gases CF4, Ar, and CO are continuously introduced into the etching chamber at a temperature of 35°C–45°C. The flow rates of CF4, Ar, and CO are 50–200 sccm, 10–30 mT, and 500–800 W, respectively. O2 is also continuously introduced into the etching chamber at the same temperature. This invention utilizes etching gases at 35°C–45°C to form contact holes in the interlayer dielectric layer during etching, making the polymer produced during etching more volatile. After etching, CF4, Ar, and CO are continued to be introduced. CF4 makes the remaining polymer more porous and easier to remove, while CO protects the sidewalls of the contact holes and also facilitates polymer removal. Finally, pure O2 is introduced to completely remove the polymer. This removes the polymer deposited at the bottom and sidewalls of the contact holes during the etching process to form the contact holes, reducing the likelihood of defects in deep trench capacitors.
[0054] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a deep trench capacitor, characterized in that, include: A substrate is provided in which deep trenches are formed; Stacked oxide layers and gate polysilicon layers are formed within the deep trench, and the stacked oxide layers and gate polysilicon layers extend to a portion of the surface of the substrate. An interlayer dielectric layer, a bottom anti-reflection coating, and a patterned photoresist layer are sequentially formed on the surface of the substrate and the surface of the gate polysilicon on the substrate; Using a patterned photoresist layer, etching gases C5F8, O2 and Ar are introduced into the etching chamber, and the etching temperature is set to 35℃~45℃. The bottom anti-reflective coating and the interlayer dielectric layer are etched sequentially to form contact holes in the interlayer dielectric layer and the bottom anti-reflective coating. The aspect ratio of the contact holes is greater than 4. Continue to introduce gases CF4, Ar and CO into the etching chamber at a temperature of 35℃~45℃. The flow rate of gas CF4 is 5sccm~10sccm, the flow rate of gas Ar is 100sccm~500sccm, the flow rate of gas CO is 50sccm~200sccm, the pressure is 10mT~30mT, and the power is 500W~800W. Continue to introduce O2 into the etching cavity at a temperature of 35℃~45℃.
2. The method for forming a deep trench capacitor as described in claim 1, characterized in that, The substrate includes a wafer.
3. The method for forming a deep trench capacitor as described in claim 1, characterized in that, The interlayer dielectric layer includes a silicon nitride layer or a silicon oxide layer.
4. The method for forming a deep trench capacitor as described in claim 1, characterized in that, The depth of the contact hole is 1.2μm to 1.3μm, and the width is 0.25μm to 0.3μm.
5. The method for forming a deep trench capacitor as described in claim 1, characterized in that, A method for sequentially forming an interlayer dielectric layer, a bottom anti-reflective coating, and a patterned photoresist layer on the surface of the substrate and the surface of the gate polysilicon on the substrate includes: An interlayer dielectric layer, a bottom anti-reflection coating, and a photoresist layer are sequentially formed on the surface of the substrate and on the surface of the gate polysilicon on the substrate. The photoresist layer is exposed to obtain a patterned photoresist layer.
6. The method for forming a deep trench capacitor as described in claim 1, characterized in that, After continuing to introduce O2 into the etching cavity, the process also includes: Remove the patterned photoresist layer and the bottom anti-reflective coating.
7. The method for forming a deep trench capacitor as described in claim 6, characterized in that, Methods for removing the patterned photoresist layer and the underlying anti-reflective coating include: At a temperature of 130℃~200℃, O2 ashing was used to remove part of the photoresist layer and the bottom anti-reflective coating; The photoresist layer and the bottom anti-reflective coating were removed using a wet method with organic solvents.
8. The method for forming a deep trench capacitor as described in claim 6, characterized in that, After removing the patterned photoresist layer and the bottom anti-reflective coating, the process also includes: Fill the contact hole with metal.
9. The method for forming a deep trench capacitor as described in claim 8, characterized in that, After filling the contact hole with metal, the process further includes: A metal layer is formed on the interlayer dielectric layer and the contact hole, the contact hole connecting the contact layer to the substrate or the gate polysilicon layer.