Scan driving circuit, driving method and display panel

Abstract

The application provides a scan driving circuit, a driving method and a display panel. The scan driving circuit comprises a gate driving circuit connected in cascade. The gate driving circuit comprises a first input module, a first control module, a second control module, a first output module and a switching module. The first input module is configured to transmit a first input signal to a first node under the control of a first clock signal. The first control module is configured to transmit a first power supply potential to a second node under the control of the first clock signal. The second control module is configured to adjust the potentials of the first node and the second node. The first output module is configured to output a gate driving signal under the control of the potentials of the first node and the second node. The switching module comprises a first switching unit configured to transmit a second power supply potential to the first node under the control of a switching signal. The scan driving circuit can realize refresh frequency partition control at any position on a full screen.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a scanning driving circuit, driving method, and display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display devices are characterized by their light weight, small size, thinness, and low power consumption, and are widely used in terminal display devices such as mobile phones and computers.

[0003] In scenarios such as split-screen displays, multiple display scenarios may exist on the same screen. If the refresh rate of some display areas can be reduced without affecting the display effect, the power consumption of electronic devices can be reduced. Current technologies can only achieve full-screen refresh rate adjustment or fixed-position partition refresh rate control, neither of which can meet the needs of the above scenarios. Therefore, how to achieve partitioned refresh rate control at any position on the full screen has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a scanning driving circuit, a driving method, and a display panel. The various aspects involved in the embodiments of this application are described below.

[0005] In a first aspect, a scan driving circuit is provided, including cascaded gate driving circuits; the gate driving circuit includes: a first input module, a first control module, a first output module, and a switching module; the first input module is connected to a first signal input terminal and a first node, and is used to transmit a first input signal to the first node under the control of a first clock signal; the first control module is connected to a first power supply terminal and a second node, and is used to transmit a first power supply potential to the second node under the control of the first clock signal; the first output module is connected to the first node and the second node, and is used to output a gate driving signal under the control of the potentials of the first node and the second node; the switching module includes a first switching unit, the first switching unit is connected to the first node and the second power supply terminal, and is used to transmit a second power supply potential to the first node under the control of a first switching signal.

[0006] Optionally, the scanning drive circuit further includes a second control module, which is connected to the first node, the second node, and the second power supply terminal, and is used to adjust the potential of the first node and / or the second node.

[0007] Optionally, the switching module further includes a second switching unit, which is connected to the second control module; when the potential of the first node is pulled low by the first input module, the second switching unit transmits the second power supply potential to the first node under the control of the second switching signal.

[0008] Optionally, the system further includes multiple cascaded backup circuits, each corresponding one-to-one with the gate drive circuit. The backup signal output by the preceding backup circuit serves as the second input signal of the following backup circuit and the first input signal of the following gate drive circuit. Each backup circuit includes: a second input module, a third control module, a fourth control module, and a second output module. The second input module is connected to a second signal input terminal and a third node, and is used to transmit a second input signal to the third node under the control of the first clock signal. The third control module is connected to a first power supply terminal and a fourth node, and is used to transmit a first power supply potential to the fourth node under the control of the first clock signal. The fourth control module is connected to the third node, the fourth node, and the second power supply terminal, and is used to adjust the potentials of the third node and the fourth node. The second output module is connected to the third node and the fourth node, and is used to output the backup signal under the control of the potentials of the third node and the fourth node.

[0009] Optionally, the scan driving circuit further includes multiple cascaded backup circuits, each corresponding one-to-one with the gate driving circuit. The corresponding backup circuits are interconnected with the gate driving circuit. The backup signal output by the preceding backup circuit is the second input signal of the following backup circuit and the first input signal of the following gate driving circuit. Each backup circuit includes a second input module, a fourth control module, and a second output module. The second input module is connected to a second signal input terminal and a third node, and is used to transmit a second input signal to the third node under the control of the first clock signal. The fourth control module is connected to the third node, the second node, and the second power supply terminal, and is used to adjust the potential of the third node. The second output module is connected to the third node and the second node, and is used to output the backup signal under the control of the potentials of the third node and the second node.

[0010] Optionally, the first input module includes a first transistor, a first terminal of the first transistor is connected to the first signal input terminal, a second terminal of the first transistor is connected to the first node and the second control module, and a control terminal of the first transistor is connected to the first clock signal.

[0011] Optionally, the first control module includes a second transistor; the first end of the second transistor is connected to the first power supply terminal, the second end of the second transistor is connected to the second node, and the control terminal of the second transistor is connected to the first clock signal.

[0012] Optionally, the first output module includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor; the first terminal of the third transistor is connected to a second power supply terminal, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, and the connection point is the output terminal of the gate drive signal; the second terminal of the fourth transistor is connected to the second clock signal; the control terminal of the third transistor is connected to the second node; the control terminal of the fourth transistor is connected to the first node; the two ends of the first capacitor are respectively connected to the first terminal of the fourth transistor and the first node; the two ends of the second capacitor are respectively connected to the first terminal of the third transistor and the second node.

[0013] Optionally, the first switching unit includes a fifth transistor, the first end of which is connected to a second power supply terminal, the second end of which is connected to the first node, and the control terminal of the fifth transistor receives the first switching signal.

[0014] Optionally, the second control module includes a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the sixth transistor is connected to the first clock signal, the second terminal of the sixth transistor is connected to the second node, and the control terminal of the sixth transistor is connected to the first node; the first terminal of the seventh transistor is connected to a second power supply terminal, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, the control terminal of the seventh transistor is connected to the second node, the control terminal of the eighth transistor is connected to the second clock signal, and the second terminal of the eighth transistor is connected to the first node; the second switching unit includes a ninth transistor, the first terminal of the ninth transistor is connected to a second power supply terminal, the second terminal of the ninth transistor is connected to the second terminal of the seventh transistor, and the control terminal of the ninth transistor receives the second switching signal.

[0015] Optionally, the gate drive circuit further includes a current stabilization module, which is used to stabilize the current flowing to the first output module.

[0016] Optionally, the current stabilization module includes a tenth transistor, the first terminal of which is connected to the second control module, the second terminal of which is connected to the first node, and the control terminal of which is connected to the first power supply terminal.

[0017] Optionally, the second input module includes an eleventh transistor, the first terminal of which is connected to a second signal input terminal, the second terminal of which is connected to the third node, and the control terminal of which is connected to the first clock signal.

[0018] Optionally, the fourth control module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; the first terminal of the twelfth transistor is connected to the first clock signal, the second terminal of the twelfth transistor is connected to the fourth node or the second node, and the control terminal of the twelfth transistor is connected to the third node; the first terminal of the thirteenth transistor is connected to the second power supply terminal, the second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor, and the control terminal of the thirteenth transistor is connected to the fourth node or the second node; the control terminal of the fourteenth transistor is connected to the second clock signal, and the second terminal of the fourteenth transistor is connected to the third node.

[0019] Optionally, the second output module includes a fifteenth transistor, a sixteenth transistor, and a third capacitor; the first terminal of the fifteenth transistor is connected to the second power supply terminal, the second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor, and the connection point is the output terminal of the backup signal; the control terminal of the fifteenth transistor is connected to the fourth node or the second node; the second terminal of the sixteenth transistor is connected to the second clock signal; and the control terminal of the sixteenth transistor is connected to the third node; the two ends of the third capacitor are respectively connected to the second terminal of the sixteenth transistor and the third node.

[0020] Optionally, the third control module includes a seventeenth transistor, the first terminal of which is connected to the first power supply terminal, the control terminal of which is connected to the first clock signal, and the second terminal of the thirteenth transistor is connected to the fourth node.

[0021] In a second aspect, a driving method is provided, applied to a scan driving circuit as described in the first aspect, the method comprising: enabling the first switching unit and controlling the potential of the first node so that the gate driving signal output by the first output module is the second power supply potential.

[0022] Optionally, the scan driving circuit further includes a second switching unit connected to the second control module; the method further includes: when the potential of the first node is pulled low by the first input module, controlling the second switching unit to enable, so as to maintain the potential of the first node at the second power supply potential; optionally, the scan driving circuit further includes a plurality of cascaded backup circuits, the plurality of backup circuits corresponding one-to-one with the gate driving circuit, wherein the output signal of the previous backup circuit is the input signal of the next backup circuit and the next gate driving circuit; each backup circuit includes: a second input module, a third control module, a fourth control module, and a second output module; The second input module is connected to the second signal input terminal and the third node, and is used to transmit a second input signal to the third node under the control of the first clock signal; the third control module is connected to the first power supply terminal and the fourth node, and is used to transmit a first power supply potential to the fourth node under the control of the first clock signal; the fourth control module is connected to the third node, the fourth node and the second power supply terminal, and is used to adjust the potentials of the third node and the fourth node; the fourth output module is connected to the third node and the fourth node, and is used to output a backup signal under the control of the potentials of the third node and the fourth node.

[0023] Thirdly, a display panel is provided, including the scanning drive circuit as described in the first aspect.

[0024] According to the scanning driving circuit provided in the embodiments of this application, by enabling the switching unit of the target gate driving circuit in a plurality of cascaded gate driving circuits, the frequency of the target gate driving signal output by the target gate driving circuit is adjusted, thereby controlling the refresh frequency of the target row pixel corresponding to the target gate driving circuit and the first display area thereafter; since the target gate driving circuit can be any one of the plurality of gate driving circuits, the refresh frequency partition control at any position in the full screen can be realized by using the scanning driving circuit. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a foldable screen device in related technologies.

[0026] Figure 2 This is a schematic diagram of a gate drive circuit that implements fixed partition frequency control in related technologies.

[0027] Figure 3 yes Figure 1 This is a diagram illustrating how a foldable screen device can display multiple applications in a split-screen format.

[0028] Figure 4This is a schematic diagram of a scanning drive circuit provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram of a gate driving circuit provided in another embodiment of this application.

[0031] Figure 7 This is a schematic diagram of a scanning drive circuit provided in another embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the backup circuit provided in an embodiment of this application.

[0033] Figure 9 This is a schematic diagram of a backup circuit provided in another embodiment of this application.

[0034] Figures 10A-10C This is an example diagram of the gate drive signal output by the scan drive circuit.

[0035] Figure 11 This is a circuit diagram of the gate driving circuit provided in an embodiment of this application.

[0036] Figure 12 This is a circuit diagram of a gate drive circuit provided in another embodiment of this application.

[0037] Figure 13 This is a circuit diagram of a backup circuit provided in one embodiment of this application.

[0038] Figure 14 This is a circuit diagram of a backup circuit provided in another embodiment of this application.

[0039] Figure 15 yes Figure 4 The circuit diagram of a gate drive circuit in the scan drive circuit.

[0040] Figure 16 yes Figure 12 Example diagram of the input and output signals of the gate drive circuit.

[0041] Figure 17 This is a schematic diagram of the display panel that is reasonably provided in this application.

[0042] Figure 18 This is a schematic flowchart of the driving method provided in the embodiments of this application. Detailed Implementation

[0043] The display quality of an OLED screen is related to its refresh rate, which is determined by the control signals input to the pixel driving circuit. For example, if the control signal input to the pixel driving circuit is 60Hz, the screen will refresh 60 times per second; if the control signal input is 120Hz, the screen will refresh 120 times per second. For dynamic scenes, increasing the refresh rate can improve display quality. For relatively static scenes, since high-frequency refresh is unnecessary, reducing the refresh rate can save power.

[0044] In related technologies, the control signals input to the pixel driving circuit are usually generated by a scan driving circuit, which includes multiple driving units for generating and outputting scan signals respectively. The first-level scan signal is provided to the scan lines of the first row of pixels, the second-level scan signal is provided to the scan lines of the second row of pixels, and so on, with the nth-level scan signal provided to the scan lines of the nth row of pixels.

[0045] In a scanning drive circuit, multiple drive units are typically cascaded in sequence according to pixel rows. The output signal of the previous drive unit serves as the input signal of the next stage, while the output signal of each drive unit serves as the scanning signal in the pixel circuit to control the light emission of the pixel circuit. The output signals of adjacent drive units have a fixed time relationship. The frequency of the output signals of these multiple drive units is the same as the frequency of the initial input signal of the first drive unit, thereby making the refresh frequency of each pixel row the same and ensuring a consistent screen refresh rate for the display device.

[0046] With the development of flexible OLED technology, adjusting the full-screen refresh rate is gradually becoming insufficient to meet user needs. For example, in Figure 1 In the application scenario of the foldable laptop 100 shown, the upper first display area 110 serves as the normal display area, displaying the system interface or the interface of the currently running application; the lower second display area 120 can serve as a keyboard area, displaying virtual keyboard keys, where users can perform touch operations such as typing. Understandably, in this scenario, the image displayed in the second display area usually does not change, while the image in the first display area is in a state of real-time change. At this time, if the refresh rate of the second display area can be reduced, the power consumption of the screen can be reduced without affecting the use. For example, the refresh rate of the first display area 110 can be 120Hz, and the refresh rate of the second display area 120 can be 1Hz.

[0047] Therefore, in some related technologies, in order to reduce the refresh rate of the second display area, it can be solved by providing gate drive signals with different frequencies for the two display areas respectively.

[0048] As one implementation method, please refer to Figure 2 , Figure 2 for Figure 1 The screen gate driving circuit of the foldable laptop computer includes a first display area where m rows of pixel circuits are cascaded with multiple GIP circuits (GIP circuits a, ..., GIP circuit m shown in the figure). The GIP circuit a corresponding to the first row of pixels receives a first input signal SIN1. The frequency of the first input signal can be, for example, 120Hz. At this time, the multiple GIP circuits in the first display area all output a 120Hz signal, thereby keeping the refresh rate of the GIP circuits in the first display area at 120Hz. Figure 2 The pixels in the second display area are connected to GIP circuits m+1, m+2, ..., n respectively. The GIP circuit m+1 corresponding to the (m+1)th row pixel receives the second input signal SIN2. At this time, multiple GIP circuits cascaded with GIP circuit m+1 in the second display area output signals with the same frequency as the second input signal SIN2. In order to achieve the partition refresh frequency, the frequency of the second input signal can be reduced, for example, to 1Hz. Then, the refresh frequency of all pixels in the second display area is 1Hz.

[0049] In the above technical solution, the screen is divided into a first display area and a second display area with a higher refresh rate. By reducing the frequency of the output signal of the GIP circuit in the second display area, the refresh rate of the pixels in the second display area is reduced, thereby reducing the power of the entire display panel.

[0050] Figure 1 and Figure 2 The technical solution shown can achieve fixed-position partitioned frequency control, but in some scenarios, such as... Figure 1 When a computer unfolds into tablet mode, it may be necessary to display multiple applications in split-screen mode, such as... Figure 3 As shown, when the first display area 310 of the foldable screen device 300 plays a video, the second display area 320 displays a fixed image, and the third display area 330 displays an instant messaging application, the refresh rate of the first display area 310 and the third display area 330 can be set to a higher level (e.g., 120Hz), while the refresh rate of the second display area 320 can be set to a lower level (e.g., 1Hz). This can reduce the power consumption of the entire screen without affecting the display effect of each area.

[0051] However, in the above technical solution, because the GIP circuit of the display panel can only achieve frequency partitioning at fixed positions, that is, it cannot achieve frequency partitioning at any position on the full screen, it cannot be applied to... Figure 3 In the scene shown.

[0052] Therefore, how to achieve multiple partitions within the display panel and support different refresh rates has become an urgent problem to be solved.

[0053] In view of the above problems, embodiments of this application provide a scanning driving circuit and driving method, a display panel, and a display device.

[0054] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0055] Figure 4 This is a schematic structural diagram of a scan driving circuit 400 provided in one embodiment of this application. Figure 4 The scanning drive circuit includes multiple gate drive circuits 410A, ..., 410N, wherein the output signal of the previous stage gate drive circuit is the input signal of the next stage gate drive circuit.

[0056] Figure 5 yes Figure 4 The diagram shows the structure of the gate drive circuit in the scan drive circuit. Figure 5 The gate drive circuit in the diagram can be any one of multiple gate drive circuits. The following section discusses... Figure 5 The various modules in this gate drive circuit are described below.

[0057] Figure 5 The gate drive circuit includes: a first input module 510, a first control module 520, a first output module 530, and a switching module 540.

[0058] The first input module 510 is connected to the first signal input terminal and the first node N1, and is used to transmit the first input signal SIN to the first node N1 under the control of the first clock signal SCK1.

[0059] The first control module 520 is connected to the first power supply terminal and the second node N2. The first power supply terminal is used to provide the first power supply potential VGL to the first control module 520. The first control module is used to transmit the first power supply potential VGL to the second node N2 under the control of the first clock signal SCK1.

[0060] The first output module 530 is connected to the first node N1 and the second node N2, and is used to output a gate drive signal under the control of the potentials of the first node N1 and the second node N2.

[0061] In this embodiment, one end of the first output module 530 is connected to the second power supply terminal to receive the second power supply potential VGH, and the other end is connected to the second clock signal. Under the control of the first node N1 and the second node N2, the first output module 530 outputs the aforementioned second clock signal SCK2 and / or the second power supply potential VGH as a gate drive signal.

[0062] The switching module 540 includes a first switching unit 541, which is connected to the first node N1 and the second power supply terminal. Under the control of the first switching signal, the first switching unit 541 transmits the second power supply potential VGH to the first node N1. At this time, the potential of the first node N1 is pulled up to VGH, thereby keeping the gate drive signal output by the first output module 530 at a high potential to reduce the frequency of the output gate drive signal.

[0063] In the gate driving circuit 500, when the switching module 540 is not in operation, the gate driving signal Gout output by the first output module 530 changes according to the changes of the first clock signal SCK1, the second clock signal SCK2, and the first input signal SIN, and the frequency gate driving signal Gout is the same as the first input signal SIN. For the cascaded gate driving circuits, the gate driving signal Gout_1 output by the first-stage gate driving circuit is used to drive the first row of pixels in the display screen. When Gout_1 is low, the pixels in that row are lit, and when it is high, they are turned off. The refresh frequency of the pixels in that row is the same as the frequency of the driving signal Gout_1. At the same time, the gate driving signal Gout_1 also serves as the input signal of the next-stage gate driving circuit, so that the next-stage gate driving circuit obtains a driving signal Gout_2 with the same frequency as the driving signal Gout_1. And so on. When none of the switching modules in the cascaded gate driving circuits are in operation, the frequency of the driving signals output by each gate driving circuit is the same, so that each row of pixels in the display screen maintains the same refresh frequency.

[0064] When it is necessary to perform partitioned frequency control on the display screen, for example, when it is necessary to reduce the refresh rate of the first display area below the first target row, the first switching unit 541 in the first target gate driving circuit corresponding to the first target row can be enabled, the potential of the first node N1 in the first target gate driving circuit can be raised, so that the first target gate driving signal output by the first target gate driving circuit is kept at a high potential. At the same time, the output signals of multiple gate driving circuits cascaded after the first target gate driving circuit also output a high potential. At this time, the pixels in the first display area maintain the current display frame. By controlling the frequency of the first switching unit 541 to enable, the refresh rate of the first display area can be reduced.

[0065] When the first switching unit 541 is deactivated, the output signal of the first target gate driving circuit changes again with the changes of the first input signal, the first clock signal, and the second clock signal, and at this time the frequency of the output signal is the same as that of the input signal. The frequency of the output signals of the multiple gate driving circuits cascaded with the first target gate driving circuit also returns to synchronization with the first input signal, and the refresh rate of the entire screen is consistent.

[0066] By controlling the enable time of the first switching unit 541, the refresh frequency of the first display area can be controlled. For example, if the first switching unit 541 is enabled for 1ms every 1ms interval, the refresh frequency of the first display area is 30Hz. Or, for another example, if the first switching unit 541 is enabled for 59ms every 1ms interval, the refresh frequency of the first display area is 1Hz.

[0067] It is understood that the first target row can be any row on the display screen; in other words, in the embodiments of this application, the frequency of the output signal of any one of the cascaded gate drive circuits can be controlled by the switching module in the gate drive circuit, thereby realizing the refresh frequency partition control at any position on the full screen.

[0068] In some embodiments, such as Figure 6 As shown, the gate drive circuit also includes a second control module 550, which is connected to the first node N1, the second node N2, and the second power supply terminal. The second power supply terminal is used to provide a second power supply potential VGH. It should be noted that in this embodiment, the second power supply potential VGH is higher than the first power supply potential VGL. The second control module 550 is used to adjust the potential of the first node N1 and / or the second node N2 under the control of the first clock signal SCK1 and the second clock signal SCK2.

[0069] The aforementioned switching module 540 also includes a second switching unit 542, which is connected to the second control module 550. After the first switching unit 541 is deactivated, the second power supply potential VGH is transmitted to the first node according to the control of the second switching signal, so that the potential of the first node N1 is kept at a high potential, thereby preventing the signal input by the first input module 510 from interfering with the voltage of the first node N1.

[0070] In some embodiments, such as Figure 7 As shown, the scan driving circuit 400 provided in this embodiment further includes multiple backup circuits 420A, ..., 420N, which correspond one-to-one with multiple gate driving circuits 410A, ..., 410N. The backup signal output by the previous stage backup circuit is the second input signal of the next stage backup circuit and the first input signal of the next stage gate driving circuit. The initial input signal of the first stage backup circuit 420A and the first stage gate driving circuit 410A is SIN; the input signals of the nth stage backup circuit and the nth stage gate driving circuit are both the output signal backup_n-1 of the (n-1)th stage backup circuit.

[0071] Figure 8 This is a schematic diagram of the backup circuit in the scan drive circuit provided in the embodiment of this application. Figure 8 The backup circuit in the diagram can be any one of multiple backup circuits. The following section discusses... Figure 8 The various modules in the backup circuit are described.

[0072] Figure 8 The backup circuit includes: a second input module 710, a fourth control module 720, a second output module 730, and a third control module 740.

[0073] The second input module 710 is connected to the second signal input terminal and the third node N3, and is used to transmit the second input signal to the third node N3 under the control of the first clock signal SCK1.

[0074] It is understandable that when the backup circuit is the first of multiple backup circuits, the second input signal is the initial input signal SIN; when the backup circuit is not the first backup circuit, the second input signal is the output signal of the backup circuit preceding it.

[0075] The fourth control module 720 is connected to the third node N3, the fourth node N4 and the second power supply terminal, and is used to adjust the potential of the third node N3 and / or the fourth node N4.

[0076] The second output module 730 is connected to the third node N3 and the fourth node N4 and is used to output a backup signal under the control of the potentials of the third node N3 and the fourth node N4.

[0077] The third control module 740 is connected to the first power supply terminal and the fourth node N4, and is used to transmit the first power supply potential VGL to the fourth node N4 under the control of the first clock signal SCK1.

[0078] In some embodiments, one end of the second output module 730 is connected to the second power supply terminal to receive the second power supply potential VGH, and the other end is connected to the second clock signal. Under the potential control of the third node N3 and the fourth node N4, the second output module 730 outputs the aforementioned second clock signal SCK2 and / or the second power supply potential VGH as backup signals.

[0079] Figure 9 This is a schematic diagram of another backup circuit provided in an embodiment of this application. The backup circuit includes: a second input module 710, a fourth control module 720, and a second output module 730.

[0080] The second input module 710 is connected to the second signal input terminal and the third node N3. The second input module 710 is used to transmit the second input signal to the third node N3 under the control of the first clock signal SCK1.

[0081] The fourth control module 720 is connected to the third node N3, the second node N2, and the second power supply terminal, and is used to adjust the potential of the third node N3.

[0082] The second output module 730 is connected to the third node N3 and the second node N2, and is used to output a backup signal under the control of the potentials of the third node N3 and the second node N2. In some embodiments, in addition to using the above-mentioned switching module to realize the refresh frequency partition control at any position in the full screen, the above-mentioned cascaded backup circuits can also be used to further perform multi-partition control of the refresh frequency.

[0083] Taking a display panel comprising n rows of pixels as an example, the switching modules in the first to mth gate driving circuits are enabled, reducing the refresh rate of the pixels in the first to mth rows. Simultaneously, the switching modules in the kth to nth gate driving circuits are also enabled, further reducing the refresh rate of the pixels in the kth to nth rows. The input signal of each gate driving circuit in the (k+1)th to (n-1)th gate driving circuits is the output signal of its preceding backup circuit. In this embodiment, the frequency of the backup signal output by the backup circuit is only related to the input signal of the first-level backup circuit. Therefore, the refresh rate of the pixels in the (k+1)th to (n-1)th rows remains unchanged. In other words, the scanning driving circuit provided in this application can achieve segmented refresh rate control for multiple areas of the entire screen.

[0084] It is also understood that, in some implementations, the enable time of the switching unit in the gate drive circuit corresponding to different display areas can be controlled, thereby further adjusting the segmented frequency of each display area.

[0085] Figures 10A-10C An example diagram is shown showing the output of the gate drive signals for each row using the scan drive circuit described above. Figure 10A The frequency of the gate drive signals in rows 5-8 is lower than that of the other rows. Correspondingly, the refresh rate of the display area corresponding to this part is also lower than that of the other display areas. Figure 10B Lines 7-10 and Figure 10C The refresh rate of the display area corresponding to rows 3-6 is lower than that of other display areas. From Figures 10A-10C It can be seen that the scanning drive circuit provided in this application embodiment can realize segmented frequency control of multiple display areas.

[0086] The following is combined Figure 11 The circuit diagram shown further illustrates the gate drive circuit in the embodiments of this application.

[0087] The first input module 510 includes a first transistor M1.

[0088] The first terminal of the first transistor M1 is connected to the first signal input terminal, the second terminal of the first transistor M1 is connected to the first node N1 and the second control module 550, and the control terminal of the first transistor M1 is connected to the first clock signal SCK1.

[0089] Optionally, the first control module 520 includes a second transistor M2.

[0090] The first terminal of the second transistor M2 is connected to the first power supply terminal, which provides the first power supply potential VGL. The second terminal is connected to the second node N2, and the control terminal is connected to the first clock signal SCK1.

[0091] Optionally, the first output module 530 includes a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2.

[0092] The first terminal of the third transistor M3 is connected to the second power supply terminal. The second terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4, and the connection point is the output terminal of the gate drive signal. The second terminal of the fourth transistor M4 is connected to the second clock signal SCK2. The control terminal of the third transistor M3 is connected to the second node N2. The control terminal of the fourth transistor M4 is connected to the first node N1.

[0093] The two ends of the first capacitor C1 are connected to the first terminal of the fourth transistor M4 and the first node N1, respectively.

[0094] The two ends of the second capacitor C2 are connected to the first terminal and the second node N2 of the third transistor M3, respectively.

[0095] Optionally, the first switching unit 541 includes a fifth transistor M5. The first end of the fifth transistor M5 is connected to the second power supply terminal, and the second end of the fifth transistor M5 is connected to the first node N1. The control terminal of the fifth transistor M5 receives a first switching signal SW1. When the fifth transistor M5 is turned on under the control of the first switching signal SW1, the potential of the first node N1 is pulled up to the second power supply potential VGH.

[0096] Figure 12 This is a circuit diagram of a gate drive circuit provided in another embodiment of this application. See also... Figure 12 Optionally, the gate drive circuit further includes a second control module 550, which is connected to the first node N1, the second node N2, and the second power supply terminal. The second power supply terminal is used to provide a second power supply potential VGH. It should be noted that in this embodiment, the second power supply potential VGH is higher than the first power supply potential VGL. The second control module 550 is used to adjust the potential of the first node N1 and / or the second node N2 under the control of the first clock signal SCK1 and the second clock signal CSK2.

[0097] Optionally, the second control module 550 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

[0098] The first terminal of the sixth transistor M6 is connected to the first clock signal SCK1, the second terminal is connected to the second node N2, and the control terminal is connected to the first node N1.

[0099] The first terminal of the seventh transistor M7 is connected to the second power supply terminal, which provides the second power supply potential VGH. The second terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8. The control terminal of the seventh transistor M7 is connected to the second node N2. The control terminal of the eighth transistor M8 is connected to the second clock signal SCK2. The second terminal of the eighth transistor M8 is connected to the first node N1.

[0100] The second switching unit 542 includes a ninth transistor M9. The first terminal of the ninth transistor M9 is connected to the second power supply terminal, and the second terminal of the ninth transistor M9 is connected to the second terminal of the seventh transistor M7. The control terminal of the ninth transistor M9 receives the second switching signal SW2. For a period of time after the fifth transistor M5 is turned off, the ninth transistor M9 can remain in the on state under the control of the second switching signal SW2, keeping the potential of the first node N1 at a high potential VGH.

[0101] To further improve signal stability, the gate drive circuit 500 may optionally include a current stabilization module 560 for stabilizing the current flowing to the first output module 530.

[0102] Optionally, the current stabilization module 560 includes a tenth transistor M10, the first terminal of which is connected to the second control module 550, the second terminal of which is connected to the control terminal of the fourth transistor M4, and the control terminal of which is connected to the first power supply terminal.

[0103] In some embodiments, the tenth transistor M10 can be considered as a unidirectional conducting transistor, so that current flows only from the second terminal of the first transistor M1 or the second terminal of the eighth transistor M8 into the control terminal of the fourth transistor M4, without backflow, further improving the signal stability in the entire gate drive circuit. It is understood that since the tenth transistor M10 remains in a conducting state throughout the operation of the gate drive circuit, therefore... Figure 12 and Figure 12 Both the first and second terminals of the tenth transistor M10 can be referred to as the first node N1.

[0104] The following is combined Figure 13 and Figure 14 The circuit diagram shown further illustrates the backup circuit in the embodiments of this application.

[0105] See Figure 13 , Figure 13 This is a circuit diagram of a backup circuit provided in one embodiment of this application.

[0106] like Figure 13 As shown, the second input module 710 includes an eleventh transistor M11. The first terminal of the eleventh transistor M11 is connected to the second signal input terminal, the second terminal of the eleventh transistor M11 is connected to the third node N3, and the control terminal of the eleventh transistor M11 is connected to the first clock signal SCK1.

[0107] Optionally, the fourth control module 720 includes a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

[0108] The first terminal of the twelfth transistor M12 is connected to the first clock signal SCK1, the second terminal of the twelfth transistor M12 is connected to the fourth node N4, and the control terminal of the twelfth transistor M12 is connected to the third node N3.

[0109] The first terminal of the thirteenth transistor M13 is connected to the second power supply terminal, the second terminal of the thirteenth transistor M13 is connected to the first terminal of the fourteenth transistor M14, and the control terminal of the thirteenth transistor M13 is connected to the fourth node N4.

[0110] The control terminal of the fourteenth transistor M14 is connected to the second clock signal SCK2, and the second terminal of the fourteenth transistor M14 is connected to the third node N3.

[0111] Optionally, the second output module 730 includes a fifteenth transistor M15, a sixteenth transistor M16, and a third capacitor C3.

[0112] The first terminal of the fifteen transistor M15 is connected to the second power supply terminal, the second terminal of the fifteen transistor M15 is connected to the first terminal of the sixteenth transistor M16, and the connection point is the output terminal of the backup signal. The control terminal of the fifteen transistor M15 is connected to the fourth node N4.

[0113] The second terminal of the sixteenth transistor M16 is connected to the second clock signal SCK2, and the control terminal is connected to the third node N3.

[0114] The two ends of the third capacitor C3 are connected to the second terminal of the sixteenth transistor M16 and the third node N3, respectively.

[0115] Optionally, the third control module 720 includes a seventeenth transistor M17.

[0116] The first terminal of the seventeen-transistor M17 is connected to the first power supply terminal, the control terminal of the seventeen-transistor M17 is connected to the first clock signal SCK1, and the second terminal of the seventeen-transistor M17 is connected to the fourth node N4.

[0117] See Figure 14 , Figure 14 This is a circuit diagram of a backup circuit provided in another embodiment of this application. Figure 13 The difference is that, in Figure 14 The backup circuit shown does not include the third control module 730, and the second terminal of the twelfth transistor M12, the control terminal of the thirteenth transistor M13, and the control terminal of the fifteenth transistor M15 are all connected to the second node.

[0118] As mentioned above, the scanning circuit provided in this application embodiment includes multiple cascaded gate driving circuits and multiple backup circuits, and the number of multiple gate driving circuits and multiple backup circuits is the same; each row of pixels in the display panel or display screen corresponds to a gate driving circuit and a backup circuit, and the gate driving circuit and the backup circuit constitute a scanning driving circuit unit in the scanning driving circuit.

[0119] Figure 15 The following is a circuit diagram of a gate driving circuit in a scan driving circuit provided in an embodiment of this application. Figure 15 A detailed description is provided. The gate drive circuit includes, for example: Figure 12 and Figure 14 The gate drive circuit and backup circuit are included.

[0120] It is also understandable that, Figure 12 and Figure 13 In the circuit shown, the second transistor M2 in the gate drive circuit and the seventeenth transistor M17 in the backup circuit are both connected to the first power supply terminal, and their control terminals are both connected to the first clock signal SCK1. Therefore, they can be merged into one. At the same time, the fourth node N4 in the backup circuit and the second node N2 in the gate drive circuit can be merged to obtain... Figure 15 The circuit diagram shown.

[0121] Figure 16 It shows Figure 15 An example of the input and output signals of the gate drive circuit in the example, from Figure 16 As can be seen from the diagram, the gate drive circuit can output a backup signal and a gate drive signal with the same frequency and phase according to the input signal and the clock signal.

[0122] The following example illustrates the principle of implementing partition refresh frequency control using the scan drive circuit provided in the embodiments of this application. Figure 17 This is a schematic diagram of a display panel. Figure 17 The display panel in the image consists of n rows of pixels, where each row of pixels has a driving circuit. Figure 15 The scanning drive circuit in the display panel is divided into three areas: the first display area consists of rows 1 to m-1, the second display area consists of rows m to k-1, and the third display area consists of rows k to n. The refresh rates of the first and third display areas are higher than those of the second display area.

[0123] In the initial display state, the refresh rates of the multiple display areas are the same, for example, all 120Hz. When it is necessary to reduce the refresh rate of the second display area, the first switching signal SW1 is input to the fifth transistor M5 in the multiple scan drive circuits corresponding to the m-th to k-1-th rows of pixels, causing the potential of the first node N1 to be pulled high to VGH, thereby turning off the fourth transistor M4 and preventing the output of the second clock signal SCK2. When the next first input signal SIN is transmitted at a low level, the fourth transistor M4 remains off, and the gate drive signal output by the gate drive circuit continues to maintain a high potential VGH until the next valid first input signal SIN is input. Then, the first switching signal SW1 and the second switching signal SW2 are disconnected, and the potential of the first node N1 is pulled low by the valid first input signal SIN. The fourth transistor M4 turns on, and the second clock signal SCK2 is output as the valid gate drive signal under the low refresh rate. The refresh rate of the second display area is reduced through the first switching unit and the second switching unit.

[0124] When the refresh rate of the second display area is readjusted to 120Hz, the gate of the fourth transistor M4 needs to be pulled low to ensure that M4 is turned on, so that the scan drive circuit can output a signal with the same frequency as the input signal. Since the voltage of the first node N1 can only be lowered by the input signal SIN of the first transistor M1, if SW1 is turned off after the low level of the SIN signal is transmitted to the gate of the fourth transistor M4, it cannot be guaranteed that the gate potential of the fourth transistor M4 can be pulled low enough to ensure that M4 is turned on normally. Therefore, SW1 needs to be turned off in advance to ensure that the voltage of the first node N1 is easily lowered. At this time, the voltage of the first node N1 is maintained by the first capacitor C1. If the SIN signal is input at this time, it will pull down the voltage of the first node N1, causing M4 to be unable to be in a stable off state, and the output result of Gout cannot be guaranteed to still be VGH, resulting in unstable output results. To maintain the voltage of the first node N1 while ensuring that M4 is turned on in time when switching to a higher frequency, the SW2 signal is input to the tenth transistor M10 during the switching process. The SW2 signal is later than the SW1 signal, so that the N1 node can still be kept at a high level for a period of time after M5 is turned off, so as to avoid the interference of the low level of the SIN signal on the voltage of the N1 node and ensure that the output of Gout is still VGH. When the next SIN signal is input, the SW2 signal is turned off, and the SW1 signal is also turned off. The voltage of the N1 node is easily pulled down by the SIN signal, turning on M4, and the output of Gout is SCK2.

[0125] The above text combined Figures 1-17 The scanning drive circuit provided in the embodiments of this application is described in detail below. Figure 18 This document describes the method embodiments of this application; it should be understood that the description of the method embodiments corresponds to the device embodiments, therefore, any parts not described in detail can be referred to the device embodiments above.

[0126] Figure 18 This is a schematic flowchart of a driving method provided in an embodiment of this application. The driving method is applied to a scan driving circuit, which can be... Figure 4 The scan drive circuit 400 is shown in the figure. Figure 18 The method includes step S1810.

[0127] In step S1810, the first switching unit is enabled, and the potential of the first node is controlled so that the gate drive signal output by the first output module is the second power supply potential.

[0128] When it is necessary to perform partitioned frequency control on the display screen, for example, when it is necessary to reduce the refresh rate of the first display area below the first target row, the first switching unit in the first target gate driving circuit corresponding to the first target row can be enabled, the potential of the first node in the first target gate driving circuit can be raised, and the first target gate driving signal output by the first target gate driving circuit can be kept at the second power supply potential VGH; at the same time, the output signals of multiple gate driving circuits cascaded after the first target gate driving circuit also output a high potential, and at this time the pixels in the first display area maintain the current display frame.

[0129] When the first switching unit is deactivated, the output signal of the first target gate drive circuit changes again in accordance with the changes of the first input signal, the first clock signal, and the second clock signal, and at this time the frequency of the output signal is the same as that of the input signal. The frequency of the output signals of the multiple gate drive circuits cascaded with the first target gate drive circuit also returns to synchronization with the first input signal, and the refresh rate of the entire screen is consistent.

[0130] By controlling the enable time of the first switching unit using the above method, the refresh rate of the first display area can be controlled.

[0131] Optionally, the scanning drive circuit further includes a second switching unit connected to the second control module; the method further includes: when the potential of the first node is pulled low by the first input module, controlling the second switching unit to enable so as to maintain the potential of the first node at the second power supply potential.

[0132] Optionally, the scan driving circuit further includes multiple cascaded backup circuits, each of which corresponds to the gate driving circuit. The output signal of the previous backup circuit is the input signal of the next backup circuit and the next gate driving circuit.

[0133] Optionally, each backup circuit includes: a second input module, a third control module, a fourth control module, and a second output module; the second input module is connected to a second signal input terminal and a third node, and is used to transmit a second input signal to the third node under the control of the first clock signal; the third control module is connected to a first power supply terminal and a fourth node, and is used to transmit a first power supply potential to the fourth node under the control of the first clock signal; the fourth control module is connected to the third node, the fourth node, and the second power supply terminal, and is used to adjust the potentials of the third node and the fourth node; the fourth output module is connected to the third node and the fourth node, and is used to output a backup signal under the control of the potentials of the third node and the fourth node.

[0134] This application also provides a display panel that includes a scanning drive circuit as described in one of the above embodiments.

[0135] This application also provides a display device, which includes a scanning driving circuit or a display panel as described in one of the above embodiments.

[0136] It should be noted that the display device can be various electronic display products, specifically including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptops, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices. Furthermore, depending on actual needs, the display device may also include other structures such as a touch function layer, a polarizer, and a cover plate.

[0137] It should be noted that, in the embodiments of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0138] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0139] It should be understood that the term "and / or" used in the embodiments of this application is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In addition, the character " / " in the embodiments of this application generally indicates that the preceding and following associated objects have an "or" relationship.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A scanning drive circuit, characterized in that, Including cascaded gate drive circuits; The gate drive circuit includes: a first input module, a first control module, a first output module, and a switching module; The first input module is connected to the first signal input terminal and the first node. The first input module is used to transmit the first input signal to the first node under the control of the first clock signal. The first control module is connected to the first power supply terminal and the second node. The first control module is used to transmit the first power supply potential to the second node under the control of the first clock signal. The first output module is connected to the first node and the second node, and is used to output a gate drive signal under the control of the potentials of the first node and the second node; The switching module includes a first switching unit, which is connected to the first node and the second power supply terminal. Under the control of the first switching signal, the first switching unit transmits the second power supply potential to the first node so that the gate drive signal is kept at a high level. The scanning drive circuit further includes a second control module, which is connected to the first node, the second node, and the second power supply terminal, and is used to adjust the potential of the first node and / or the second node. The switching module further includes a second switching unit, which is connected to the second control module. When the potential of the first node is pulled low by the first input module, the second switching unit transmits the second power supply potential to the first node under the control of the second switching signal, so as to keep the potential of the first node at a high potential and avoid the signal input by the first input module from interfering with the voltage of the first node.

2. The scanning drive circuit according to claim 1, characterized in that, It also includes multiple cascaded backup circuits, each of which corresponds to the gate drive circuit. The backup signal output by the previous backup circuit is the second input signal of the next backup circuit and the first input signal of the next gate drive circuit. Each of the backup circuits includes: a second input module, a third control module, a fourth control module, and a second output module; The second input module is connected to the second signal input terminal and the third node. The second input module is used to transmit the second input signal to the third node under the control of the first clock signal. The third control module is connected to the first power supply terminal and the fourth node. The third control module is used to transmit the first power supply potential to the fourth node under the control of the first clock signal. The fourth control module is connected to the third node, the fourth node and the second power supply terminal, and is used to adjust the potential of the third node and the fourth node; The second output module is connected to the third node and the fourth node, and is used to output the backup signal under the control of the potential of the third node and the fourth node.

3. The scanning drive circuit according to claim 1, characterized in that, It also includes multiple cascaded backup circuits, each of which corresponds to the gate driving circuit. The backup circuits and the gate driving circuits are interconnected. The backup signal output by the previous backup circuit is the second input signal of the next backup circuit and the first input signal of the next gate driving circuit. Each of the backup circuits includes: a second input module, a fourth control module, and a second output module; The second input module is connected to the second signal input terminal and the third node. The second input module is used to transmit the second input signal to the third node under the control of the first clock signal. The fourth control module is connected to the third node, the second node and the second power supply terminal, and is used to adjust the potential of the third node; The second output module is connected to the third node and the second node, and is used to output the backup signal under the control of the potential of the third node and the second node.

4. The scanning drive circuit according to claim 1, characterized in that, The first input module includes a first transistor, a first terminal of the first transistor is connected to the first signal input terminal, a second terminal of the first transistor is connected to the first node and the second control module, and a control terminal of the first transistor is connected to the first clock signal.

5. The scanning drive circuit according to claim 1, characterized in that, The first control module includes a second transistor; The first terminal of the second transistor is connected to the first power supply terminal, the second terminal of the second transistor is connected to the second node, and the control terminal of the second transistor is connected to the first clock signal.

6. The scanning drive circuit according to claim 5, characterized in that, The first output module includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor; The first terminal of the third transistor is connected to the second power supply terminal, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, and the connection point is the output terminal of the gate drive signal. The second terminal of the fourth transistor is connected to the second clock signal. The control terminal of the third transistor is connected to the second node, and the control terminal of the fourth transistor is connected to the first node. The two ends of the first capacitor are respectively connected to the first end of the fourth transistor and the first node; The two ends of the second capacitor are respectively connected to the first end of the third transistor and the second node.

7. The scanning drive circuit according to claim 5, characterized in that, The first switching unit includes a fifth transistor, the first end of which is connected to a second power supply terminal, the second end of which is connected to the first node, and the control terminal of the fifth transistor receives the first switching signal.

8. The scanning drive circuit according to claim 1, characterized in that, The second control module includes a sixth transistor, a seventh transistor, and an eighth transistor; The first terminal of the sixth transistor is connected to the first clock signal, the second terminal of the sixth transistor is connected to the second node, and the control terminal of the sixth transistor is connected to the first node; The first terminal of the seventh transistor is connected to the second power supply terminal, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, the control terminal of the seventh transistor is connected to the second node, the control terminal of the eighth transistor is connected to the second clock signal, and the second terminal of the eighth transistor is connected to the first node. The second switching unit includes a ninth transistor, the first terminal of which is connected to a second power supply terminal, the second terminal of which is connected to the second terminal of the seventh transistor, and the control terminal of the ninth transistor receives the second switching signal.

9. The scanning drive circuit according to claim 8, characterized in that, The gate drive circuit further includes a current stabilization module, which is used to stabilize the current flowing to the first output module.

10. The scanning drive circuit according to claim 9, characterized in that, The current stabilization module includes a tenth transistor, the first terminal of which is connected to the second control module, the second terminal of which is connected to the first node, and the control terminal of which is connected to the first power supply terminal.

11. The scanning drive circuit according to claim 2 or 3, characterized in that, The second input module includes an eleventh transistor, the first terminal of which is connected to a second signal input terminal, the second terminal of which is connected to the third node, and the control terminal of which is connected to the first clock signal.

12. The scanning drive circuit according to claim 11, characterized in that, The fourth control module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The first terminal of the twelfth transistor is connected to the first clock signal, the second terminal of the twelfth transistor is connected to the fourth node or the second node, and the control terminal of the twelfth transistor is connected to the third node; The first terminal of the thirteenth transistor is connected to the second power supply terminal, the second terminal of the thirteenth transistor is connected to the first terminal of the fourteenth transistor, and the control terminal of the thirteenth transistor is connected to the fourth node or the second node; The control terminal of the fourteenth transistor is connected to the second clock signal, and the second terminal of the fourteenth transistor is connected to the third node.

13. The scanning drive circuit according to claim 11, characterized in that, The second output module includes a fifteenth transistor, a sixteenth transistor, and a third capacitor; The first terminal of the fifteenth transistor is connected to the second power supply terminal, the second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor, and the connection point is the output terminal of the backup signal. The control terminal of the fifteenth transistor is connected to the fourth node or the second node. The second terminal of the sixteenth transistor is connected to the second clock signal. The control terminal of the sixteenth transistor is connected to the third node. The two ends of the third capacitor are respectively connected to the second end of the sixteenth transistor and the third node.

14. The scanning drive circuit according to claim 12, characterized in that, When the backup circuit includes a second input module, a third control module, a fourth control module, and a second output module, the third control module includes a seventeenth transistor, the first terminal of the seventeenth transistor is connected to the first power supply terminal, the control terminal of the seventeenth transistor is connected to the first clock signal, and the second terminal of the thirteenth transistor is connected to the fourth node.

15. A driving method applied to the scanning driving circuit as described in claim 1, the method comprising: Enable the first switching unit and control the potential of the first node so that the gate drive signal output by the first output module is the second power supply potential; The scanning drive circuit further includes a second switching unit, which is connected to the second control module. The driving method further includes: when the potential of the first node is pulled low by the first input module, controlling the second switching unit to enable so as to maintain the potential of the first node at the second power supply potential.

16. The driving method according to claim 15, characterized in that, The scanning drive circuit also includes multiple cascaded backup circuits, each of which corresponds to the gate drive circuit. The output signal of the previous backup circuit is the input signal of the next backup circuit and the next gate drive circuit. Each backup circuit includes a second input module, a third control module, a fourth control module, and a second output module. The second input module is connected to the second signal input terminal and the third node. The second input module is used to transmit the second input signal to the third node under the control of the first clock signal. The third control module is connected to the first power supply terminal and the fourth node. The third control module is used to transmit the first power supply potential to the fourth node under the control of the first clock signal. The fourth control module is connected to the third node, the fourth node and the second power supply terminal, and is used to adjust the potential of the third node and the fourth node; The second output module is connected to the third node and the fourth node, and is used to output a backup signal under the control of the potential of the third node and the fourth node.

17. A display panel, characterized in that, Includes the scan drive circuit as described in any one of claims 1-14.

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