Transistor process corner detection method, apparatus, and electronic device

Abstract

The present disclosure provides a transistor process corner detection method, device and electronic equipment, which is applied to the field of integrated circuit manufacturing technology. The transistor process corner detection method is realized by a ring oscillator composed of a transistor to be detected, the transistor to be detected including a P-type transistor and an N-type transistor, and the method includes: obtaining an oscillation period of an output signal of the ring oscillator; obtaining an amplitude average value of the output signal of the ring oscillator; determining a process corner of the N-type transistor and the P-type transistor in the ring oscillator according to a ratio of the amplitude average value to a power supply voltage of the ring oscillator and a comparison result of the oscillation period with a first threshold value and a second threshold value, wherein the first threshold value is greater than the second threshold value. The embodiment of the present disclosure can improve the speed of detecting the transistor process corner.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit testing technology, and more specifically, to a method, apparatus, and electronic device for transistor process corner testing. Background Technology

[0002] In the manufacturing process of integrated circuits, different process deviations, such as doping concentration, manufacturing temperature, and etching degree, will have varying degrees of impact on different areas of the same wafer, thus creating different process corners on the wafer. The process corners of transistors affect the device's response speed and are an important indicator in the process monitoring process.

[0003] In related technologies, a ring oscillator (RO) is typically used to measure the process corner of a transistor. The process corner of the transistor forming the ring oscillator is determined by comparing the oscillation period of the RO's output signal with a preset value. However, using only the oscillation period of the output signal cannot distinguish between the process corners of P-type and N-type transistors. Furthermore, existing techniques for detecting the process corners of P-type and N-type transistors involve significant computation and control, resulting in low efficiency during high-volume testing.

[0004] Therefore, a method is needed to quickly detect transistor process corners.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a method, apparatus, and electronic device for detecting process corners of transistors, which at least to some extent overcomes the problem of low detection efficiency of process corners for P-type and N-type transistors due to limitations and defects in related technologies.

[0007] According to a first aspect of the present disclosure, a method for detecting the process corner of a transistor is provided, implemented by a ring oscillator composed of transistors under test, the transistors under test including P-type transistors and N-type transistors, the method comprising: acquiring the oscillation period of the output signal of the ring oscillator; acquiring the average amplitude of the output signal of the ring oscillator; and determining the process corner of the N-type transistor and the P-type transistor in the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator, and a comparison result of the oscillation period with a first threshold and a second threshold, wherein the first threshold is greater than the second threshold.

[0008] In an exemplary embodiment of this disclosure, the step of determining the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator and the comparison result of the oscillation period with a first threshold and a second threshold includes: when the oscillation period is greater than the first threshold and the ratio is equal to 0.5, determining that the ring oscillator is in a slow NMOS / slow PMOS process corner; when the oscillation period is greater than the first threshold and the ratio is less than 0.5, determining that the ring oscillator is in a standard NMOS / slow PMOS process corner; and when the oscillation period is greater than the first threshold and the ratio is greater than 0.5, determining that the ring oscillator is in a slow NMOS / standard PMOS process corner.

[0009] In an exemplary embodiment of this disclosure, the step of determining the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator and the comparison result of the oscillation period with a first threshold and a second threshold includes: when the oscillation period is less than the second threshold and the ratio is equal to 0.5, determining that the ring oscillator is in a fast NMOS / fast PMOS process corner; when the oscillation period is less than the second threshold and the ratio is less than 0.5, determining that the ring oscillator is in a fast NMOS / standard PMOS process corner; and when the oscillation period is less than the second threshold and the ratio is greater than 0.5, determining that the ring oscillator is in a standard NMOS / fast PMOS process corner.

[0010] In an exemplary embodiment of this disclosure, the step of determining the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator and the comparison result of the oscillation period with a first threshold and a second threshold includes: when the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is equal to 0.5, determining that the ring oscillator is in a standard NMOS / standard PMOS process corner; when the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is less than 0.5, determining that the ring oscillator is in a fast NMOS / slow PMOS process corner; when the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is greater than 0.5, determining that the ring oscillator is in a slow NMOS / fast PMOS process corner.

[0011] In one exemplary embodiment of this disclosure, the output terminal of the ring oscillator is connected to a frequency divider, and obtaining the oscillation period of the output signal of the ring oscillator includes: using the frequency divider to perform frequency division processing on the output signal to obtain a first frequency divided signal, measuring the period of the first frequency divided signal, and determining the oscillation period based on the ratio of the period of the first frequency divided signal to the frequency division factor of the frequency divider.

[0012] In one exemplary embodiment of this disclosure, the output terminal of the ring oscillator is connected to a low-pass filter circuit, and obtaining the average amplitude of the output signal of the ring oscillator includes: obtaining the average amplitude based on the output signal of the low-pass filter circuit.

[0013] In one exemplary embodiment of this disclosure, the method further includes: determining the duty cycle of the output signal based on the average amplitude; calculating a first propagation delay time corresponding to the N-type transistor and a second propagation delay time corresponding to the P-type transistor based on the duty cycle of the output signal and the oscillation period; determining the process angle of the N-type transistor based on the first propagation delay time and the standard delay time of the N-type transistor; and determining the process angle of the P-type transistor based on the comparison result of the second propagation delay time and the standard delay time of the P-type transistor.

[0014] In one exemplary embodiment of this disclosure, determining the duty cycle of the output signal based on the average amplitude includes setting the ratio of the average amplitude to the power supply voltage of the ring oscillator as the duty cycle of the output signal.

[0015] In one exemplary embodiment of this disclosure, the ring oscillator includes a starting unit and an even number of cascaded oscillation units. The output terminal of the starting unit is connected to the input terminal of the first-stage oscillation unit, the output terminal of the last-stage oscillation unit is connected to the first input terminal of the starting unit, and the second input terminal of the starting unit receives the start-up signal.

[0016] In an exemplary embodiment of this disclosure, the transmission delay time of the starting unit and the oscillation unit is a first transmission delay time or a second transmission delay time. When the first input terminal of the starting unit and the input terminal of the oscillation unit receive a high-level signal, the transmission delay time of the starting unit and the oscillation unit is the first transmission delay time; when the first input terminal of the starting unit and the input terminal of the oscillation unit receive a low-level signal, the transmission delay time of the starting unit and the oscillation unit is the second transmission delay time.

[0017] In an exemplary embodiment of this disclosure, calculating the first transmission delay time corresponding to the N-type transistor and the second transmission delay time corresponding to the P-type transistor based on the duty cycle of the output signal and the oscillation period includes: determining the first transmission delay time according to a first formula, the first formula including trf=T*D-(N-1)*tPD; determining the second transmission delay time according to a second formula, the second formula including tfr=T*(1-D)-(N-1)*tPD; where trf is the first transmission delay time, tfr is the second transmission delay time, T is the oscillation period, D is the duty cycle, N is the total number of oscillation units and start-up units in the ring oscillator, 2tPD is the sum of the transmission delay times of two adjacent oscillation units, and tPD=T / (2*N)=(trf+tfr) / 2=(trf+tfr) / 2.

[0018] In one exemplary embodiment of this disclosure, the starting unit includes a NAND gate, and the oscillation unit includes an inverter.

[0019] According to a second aspect of the present disclosure, a transistor process corner detection device is provided, connected to a ring oscillator composed of transistors under test, the transistors under test including P-type transistors and N-type transistors, the device comprising: an oscillation period acquisition module configured to acquire the oscillation period of the output signal of the ring oscillator; and an amplitude average value acquisition module configured to acquire the amplitude average value of the output signal of the ring oscillator.

[0020] According to a third aspect of this disclosure, an electronic device is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to perform the method as described in any of the preceding methods based on instructions stored in the memory.

[0021] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a program stored thereon that, when executed by a processor, implements the transistor process corner detection method as described in any of the preceding claims.

[0022] This embodiment of the invention determines the process corners of P-type and N-type transistors in a ring oscillator by judging only the average amplitude and oscillation period of the output signal of the ring oscillator, without the need for calculation and control, thus effectively improving the efficiency of mass production testing.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 This is a flowchart of a transistor process corner detection method in an exemplary embodiment of this disclosure.

[0026] Figure 2 This is a schematic diagram of a ring oscillator in an embodiment of this disclosure.

[0027] Figure 3 This is a schematic diagram of the comparison results of step S3 in one embodiment of this disclosure.

[0028] Figure 4 This is a schematic diagram of the process corner in one embodiment of this disclosure.

[0029] Figure 5 This is a flowchart of a transistor process corner detection method in another embodiment of this disclosure.

[0030] Figure 6 This is a schematic diagram of the first transmission delay time trf and the second transmission delay time tfr in the embodiments of this disclosure.

[0031] Figure 7 This is a block diagram of a transistor process corner detection device according to an exemplary embodiment of the present disclosure.

[0032] Figure 8 This is a block diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0034] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a flowchart of a transistor process corner detection method in an exemplary embodiment of this disclosure.

[0037] refer to Figure 1 The transistor process corner detection method 100 may include:

[0038] Step S1: Obtain the oscillation period of the output signal of the ring oscillator;

[0039] Step S2: Obtain the average amplitude of the output signal of the ring oscillator;

[0040] Step S3: Based on the ratio of the average amplitude to the power supply voltage of the ring oscillator, and the comparison result of the oscillation period with the first threshold and the second threshold, determine the process angle of the N-type transistor and the P-type transistor in the ring oscillator, wherein the first threshold is greater than the second threshold.

[0041] This embodiment of the invention determines the process corners of P-type and N-type transistors in a ring oscillator by judging only the average amplitude and oscillation period of the output signal of the ring oscillator, without the need for calculation and control, thus effectively improving the efficiency of mass production testing.

[0042] The method provided in this disclosure is implemented by a ring oscillator composed of transistors under test, including P-type transistors and N-type transistors.

[0043] Figure 2 This is a schematic diagram of a ring oscillator in an embodiment of this disclosure.

[0044] refer to Figure 2The ring oscillator 200 may include a starting unit 21 and an even number of oscillation units 22 connected in series. The input terminal of each oscillation unit 22 is connected to the output terminal of the previous oscillation unit 21. The input terminal of the first oscillation unit 22 is connected to the output terminal of the starting unit 21, and the output terminal of the last oscillation unit 22 is connected to the input terminal of the starting unit 21. The starting unit 21 has two input terminals: one input terminal is used to connect to the output terminal of the last oscillation unit 22, and the other input terminal is used to connect to the start-up signal. To prevent the ring oscillator from being in a continuous working state, the working state of the ring oscillator is controlled by the start-up signal.

[0045] In addition, the output of the ring oscillator 200 can be connected to a frequency divider 23 and a low-pass filter circuit 24 to measure the oscillation period and average amplitude of the output signal.

[0046] In one embodiment, the startup unit 21 may include a NAND gate; the oscillation unit 22 may include an inverter. The inverters are composed of N-type and P-type transistors. The source of the N-type transistor is connected to the power supply voltage Vcc, its gate serves as the input terminal of the oscillation unit 22, and its drain serves as the output terminal of the oscillation unit 22. The source of the P-type transistor is connected to zero potential Vss, its gate serves as the input terminal of the oscillation unit 22 connected to the gate of the N-type transistor, and its drain serves as the output terminal of the oscillation unit 22 connected to the drain of the N-type transistor. The NAND gate is also composed of the same number of N-type and P-type transistors. It should be noted that the ring oscillator has many oscillation stages. The delay of the startup unit and the delay of the oscillation unit, after being divided by the number of stages, have a very small impact. Furthermore, the size of the startup unit is designed according to the size of the oscillation unit, so the delay time of the startup unit is equivalent to the delay time of the oscillation unit.

[0047] In other embodiments, the startup unit 21 and the oscillation unit 22 can also be implemented by other circuits capable of signal inversion, as long as the number of P-type transistors in the startup unit 21 and the oscillation unit 22 can be equal to the number of N-type transistors, which will not be elaborated here.

[0048] The steps of the transistor process corner detection method 100 will be described in detail below.

[0049] In step S1, the oscillation period of the output signal of the ring oscillator is obtained.

[0050] In one embodiment, since the oscillation period T of the ring oscillator 200 is small and difficult to time, when measuring the oscillation period of the output signal of the ring oscillator 200, the output signal can first be divided by the frequency divider 23 to obtain a frequency-divided pulse signal. The period of the frequency-divided pulse signal is measured to obtain the first period nT. Then, the oscillation period T is obtained according to the ratio of the first period nT to the frequency division factor n of the frequency divider 23. The frequency division factor n of the frequency divider can be determined according to the minimum accuracy that the machine tool can measure.

[0051] In step S2, the average amplitude of the output signal of the ring oscillator is obtained.

[0052] In this embodiment, the average amplitude can be obtained from the output signal of the low-pass filter circuit 24 connected to the output terminal of the ring oscillator 200. The low-pass filter circuit 24 filters the pulse signal output by the ring oscillator 200 to output an approximate DC signal with a level equal to the average amplitude of the pulse signal. The average amplitude of the output signal of the ring oscillator 200 can then be obtained based on the level of this approximate DC signal. The low-pass filter circuit 24 can be of various types, such as an RC low-pass filter circuit. The capacitance value in the RC low-pass filter circuit can be determined based on the amplitude of the output signal of the ring oscillator 200, and this disclosure does not impose any special limitations on this.

[0053] In step S3, the process angles of the N-type transistor and the P-type transistor in the ring oscillator are determined based on the ratio of the average amplitude to the power supply voltage of the ring oscillator and the comparison results of the oscillation period with the first threshold and the second threshold, wherein the first threshold is greater than the second threshold.

[0054] At different process corners, NMOS and PMOS transistors can exhibit different gate oxide thicknesses, threshold voltages, transistor drive currents, and conduction speeds. The transistor drive current refers to the source-drain current of the transistor, which represents the carrier mobility of the MOS transistor. Carrier mobility is the average drift velocity of carriers under a unit electric field. Therefore, embodiments of the present invention can determine the respective process corners of NMOS and PMOS transistors by detecting their conduction speeds.

[0055] Figure 3 This is a schematic diagram of the comparison results of step S3 in one embodiment of this disclosure.

[0056] Figure 4 This is a schematic diagram of the process corner in one embodiment of this disclosure.

[0057] refer to Figure 3In one embodiment, the oscillation period is first compared with a first threshold and a second threshold. The first threshold and the second threshold can be preset values ​​used to measure the oscillation period. If the first threshold is greater than the second threshold, it indicates that the oscillation period is too long and the overall response speed of the component is too slow. If the oscillation period is greater than the second threshold, it indicates that the oscillation period is too short and the overall response speed of the component is too fast. If the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, it indicates that the overall response speed of the component is within the standard range.

[0058] However, the overall response speed of a device is affected by the response speeds of both the P-type and N-type transistors. Therefore, after determining the overall response speed, it is also necessary to determine the independent response speeds of the P-type and N-type transistors.

[0059] In this embodiment, the relative conduction durations of the N-type and P-type transistors are quickly determined by the average amplitude of the output signal. When the ratio of the average amplitude V to the power supply voltage Vcc is equal to 0.5, it indicates that the durations of the low and high levels in the output signal are equal. When the ratio is less than 0.5, it indicates that the conduction duration of the N-type transistor is less than that of the P-type transistor, and the response speed of the P-type transistor is slower than that of the N-type transistor. When the ratio is greater than 0.5, it indicates that the conduction duration of the N-type transistor is greater than that of the P-type transistor, and the response speed of the P-type transistor is faster than that of the N-type transistor.

[0060] The following explanation uses T (Typical) as the identifier for the standard process corner, S (Slow) as the identifier for the slow process corner, and F (Fast) as the identifier for the fast process corner to explain the determination process of the embodiments of this disclosure. It can be understood that TN represents an N-type transistor with a standard process corner, SN represents an N-type transistor with a slow process corner, FN represents an N-type transistor with a fast process corner, TP represents a P-type transistor with a standard process corner, SP represents a P-type transistor with a slow process corner, and FP represents a P-type transistor with a fast process corner. These six transistor combinations can yield nine process corner measurement results for the ring oscillator.

[0061] refer to Figure 4 The nine process corners SF, TF, FF, ST, TT, FT, SS, TS, and FS are determined based on the device response speed. Combining the process corners of N-type and P-type transistors can form... Figure 4 The diagram shows the relationship.

[0062] refer to Figure 3 and Figure 4 The judgment process in step S3 may specifically include:

[0063] When the oscillation period T is greater than the first threshold Tth1 and the ratio A is equal to 0.5, the ring oscillator is determined to be in the slow NMOS slow PMOS process corner, that is, the ring oscillator composed of SNSP is located in the SS process corner.

[0064] When the oscillation period T is greater than the first threshold Tth1 and the ratio A is less than 0.5, the ring oscillator is determined to be in the standard NMOS slow PMOS process corner, that is, the ring oscillator composed of TNSP is located in the TS process corner.

[0065] When the oscillation period T is greater than the first threshold Tth1 and the ratio A is greater than 0.5, the ring oscillator is determined to be in the slow NMOS standard PMOS process corner, that is, the ring oscillator composed of SNTP is located in the ST process corner.

[0066] When the oscillation period T is less than the second threshold Tth2 and the ratio A is equal to 0.5, the ring oscillator is determined to be in the fast NMOS fast PMOS process corner, that is, the ring oscillator composed of FNFP is located in the FF process corner.

[0067] When the oscillation period T is less than the second threshold Tth2 and the ratio A is less than 0.5, the ring oscillator is determined to be at the fast NMOS standard PMOS process corner, that is, the ring oscillator composed of FNTP is located at the FT process corner.

[0068] When the oscillation period T is less than the second threshold Tth2 and the ratio A is greater than 0.5, the ring oscillator is determined to be at the standard NMOS fast PMOS process corner, that is, the ring oscillator composed of TNFP is located at the TF process corner.

[0069] When the oscillation period T is greater than or equal to the second threshold Tth2 and less than or equal to the first threshold Tth1, and the ratio A is equal to 0.5, the ring oscillator is determined to be at the standard NMOS standard PMOS process corner, that is, the ring oscillator composed of TNTP is located at the TT process corner.

[0070] When the oscillation period T is greater than or equal to the second threshold Tth2 and less than or equal to the first threshold Tth1, and the ratio A is less than 0.5, the ring oscillator is determined to be in the fast NMOS slow PMOS process corner, that is, the ring oscillator composed of FNSP is located in the FS process corner.

[0071] When the oscillation period T is greater than or equal to the second threshold Tth2 and less than or equal to the first threshold Tth1, and the ratio A is greater than 0.5, the ring oscillator is determined to be in the slow NMOS fast PMOS process corner, that is, the ring oscillator composed of SNFP is located in the SF process corner.

[0072] When the transmission delay time of the starting unit 21 and the oscillation unit 22 is the same, the process corner judgment result can also be obtained by direct calculation.

[0073] Figure 5 This is a flowchart of a transistor process corner detection method in another embodiment of this disclosure.

[0074] refer to Figure 5 Transistor process corner detection methods may also include:

[0075] Step S51: Determine the duty cycle of the output signal based on the average amplitude.

[0076] Step S52: Calculate the first propagation delay time corresponding to the N-type transistor and the second propagation delay time corresponding to the P-type transistor based on the duty cycle of the output signal and the oscillation period;

[0077] Step S53: Determine the process angle of the N-type transistor based on the first transmission delay time and the standard delay time of the N-type transistor, and determine the process angle of the P-type transistor based on the comparison result of the second transmission delay time and the standard delay time of the P-type transistor.

[0078] exist Figure 5 In the illustrated embodiment, the propagation delay time of the N-type transistor and the P-type transistor can be directly calculated, and then the process angle judgment result of the N-type transistor and the P-type transistor can be directly obtained by comparing the calculated propagation delay time with the preset standard propagation delay time (corresponding to the TT process angle).

[0079] In some embodiments, in step S51, the ratio of the average amplitude V to the power supply voltage Vcc of the ring oscillator can be set as the duty cycle D of the output signal, i.e., the duty cycle is determined according to the following formula:

[0080] D = V / Vcc (1)

[0081] Next, in step S52, the first propagation delay time trf corresponding to the N-type transistor and the second propagation delay time tfr corresponding to the P-type transistor can be determined according to the following formula:

[0082] trf=T*D-(N-1)*tPD (2)

[0083] tfr=T*(1-D)-(N-1)*tPD (3)

[0084] Where T is the oscillation period, N is the total number of starting units and oscillation units in the ring oscillator (i.e., the number of stages), and tPD is the propagation delay time of the starting unit and each oscillation unit, determined according to the following formula:

[0085] tPD=T / (2*N)=(trf+tfr) / 2 (4)

[0086] Formula (2) means that, firstly, the duration of the high level within one cycle is obtained according to T*D. The duration of the high level begins with the output of the last stage oscillation unit at a high level and ends with the output of the last stage oscillation unit at a low level. This includes the time it takes for the high-level output signal to be transmitted between the start-up unit and the oscillation unit after returning to the input of the start-up unit until the output signal of the last stage oscillation unit flips to a low level. That is, the total transmission delay time of the start-up unit and the oscillation unit is equal to the delay time of (N+1) / 2 N-type transistors and (N-1) / 2 P-type transistors. Formula (3) is the opposite. The duration of the low level within one cycle is obtained according to T*(1-D). That is, the time between the low level output of the last stage oscillation unit returning to the input of the start-up unit, the delay time of (N-1) / 2 N-type transistors and (N+1) / 2 P-type transistors, and the output of the high level of the last stage oscillation unit.

[0087] Since the stages within the ring oscillator are connected in a ring series, and each stage inverts the output signal of the preceding stage, the propagation delay time of the starting unit 21 and the oscillation unit 22 within one cycle is either a first propagation delay time trf or a second propagation delay time tfr. When the first input terminal of the starting unit and the input terminal of the oscillation unit receive a high-level signal, the propagation delay time of the starting unit and the oscillation unit is the first propagation delay time trf, which is the propagation delay time of the N-type transistor; when the first input terminal of the starting unit and the input terminal of the oscillation unit receive a low-level signal, the propagation delay time of the starting unit and the oscillation unit is the second propagation delay time tfr, which is the propagation delay time of the P-type transistor.

[0088] Figure 6 This is a schematic diagram of the first transmission delay time trf and the second transmission delay time tfr in the embodiments of this disclosure.

[0089] refer to Figure 6 Assume that the total number of starting units and oscillation units in the ring oscillator is 3, the duty cycle is D, and the output signal of one period T includes high level and low level. The total duration of the high level is T*D, and the total duration of the low level is T*(1-D).

[0090] The initial high-level signal received at the input of the startup unit is inverted three times and then output as a low level by the second oscillation unit. This high level includes the propagation delay time of the N-type transistor in the startup unit, the propagation delay time of the P-type transistor in the first oscillation unit, and the propagation delay time of the N-type transistor in the second oscillation unit. Since the transistor parameters in each unit are the same, the total duration T*D of the high level includes the first propagation delay time trf, the second propagation delay time tfr, and the first propagation delay time trf.

[0091] The sum of the propagation delay times of two adjacent oscillation units is trf + tfr = 2 * tPD. Therefore, the first propagation time trf = T * D - (N-1) * tPD, which is the first propagation delay time trf corresponding to an N-type transistor.

[0092] Similarly, formula (3) can be obtained to calculate the second propagation delay time tfr corresponding to a P-type transistor.

[0093] By directly calculating the propagation delay time of N-type and P-type transistors based on the power supply voltage, the efficiency of obtaining the process corner determination results for N-type and P-type transistors can also be improved.

[0094] Corresponding to the above method embodiments, this disclosure also provides a transistor process corner detection device, which can be used to execute the above method embodiments.

[0095] Figure 7 This is a block diagram of a transistor process corner detection device according to an exemplary embodiment of the present disclosure.

[0096] refer to Figure 7 The transistor process corner detection device 700 is connected to a ring oscillator composed of transistors under test, including P-type transistors and N-type transistors. The device 700 may include:

[0097] The oscillation period acquisition module 71 is configured to acquire the oscillation period of the output signal of the ring oscillator;

[0098] The amplitude average value acquisition module 72 is configured to acquire the amplitude average value of the output signal of the ring oscillator;

[0099] The data comparison module 73 is configured to determine the process angle of the N-type transistor and the P-type transistor in the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator, and the comparison result of the oscillation period with the first threshold and the second threshold, wherein the first threshold is greater than the second threshold.

[0100] In an exemplary embodiment of this disclosure, the data comparison module 73 is configured to: determine that the ring oscillator is in a slow NMOS / slow PMOS process corner when the oscillation period is greater than a first threshold and the ratio is equal to 0.5; determine that the ring oscillator is in a standard NMOS / slow PMOS process corner when the oscillation period is greater than the first threshold and the ratio is less than 0.5; and determine that the ring oscillator is in a slow NMOS / standard PMOS process corner when the oscillation period is greater than the first threshold and the ratio is greater than 0.5.

[0101] In an exemplary embodiment of this disclosure, the data comparison module 73 is configured to: determine that the ring oscillator is in a fast NMOS / fast PMOS process corner when the oscillation period is less than a second threshold and the ratio is equal to 0.5; determine that the ring oscillator is in a fast NMOS / standard PMOS process corner when the oscillation period is less than the second threshold and the ratio is less than 0.5; and determine that the ring oscillator is in a standard NMOS / fast PMOS process corner when the oscillation period is less than the second threshold and the ratio is greater than 0.5.

[0102] In an exemplary embodiment of this disclosure, the data comparison module 73 is configured to: determine that the ring oscillator is in a standard NMOS / standard PMOS process corner when the oscillation period is greater than or equal to a second threshold and less than or equal to a first threshold, and the ratio is equal to 0.5; determine that the ring oscillator is in a fast NMOS / slow PMOS process corner when the oscillation period is greater than or equal to a second threshold and less than or equal to a first threshold, and the ratio is less than 0.5; and determine that the ring oscillator is in a slow NMOS / fast PMOS process corner when the oscillation period is greater than or equal to a second threshold and less than or equal to a first threshold, and the ratio is greater than 0.5.

[0103] In an exemplary embodiment of this disclosure, the output terminal of the ring oscillator is connected to a frequency divider, and the oscillation period acquisition module 71 is configured to: use the frequency divider to perform frequency division processing on the output signal to obtain a first frequency divided signal, measure the period of the first frequency divided signal, and determine the oscillation period based on the ratio of the period of the first frequency divided signal to the frequency division multiple of the frequency divider.

[0104] In one exemplary embodiment of this disclosure, the output terminal of the ring oscillator is connected to a low-pass filter circuit, and the amplitude average value acquisition module 72 is configured to acquire the amplitude average value based on the output signal of the low-pass filter circuit.

[0105] In one exemplary embodiment of this disclosure, the ring oscillator includes a starting unit and an even number of cascaded oscillation units. The output terminal of the starting unit is connected to the input terminal of the first-stage oscillation unit, the output terminal of the last-stage oscillation unit is connected to the first input terminal of the starting unit, and the second input terminal of the starting unit receives the start-up signal.

[0106] In an exemplary embodiment of this disclosure, the transmission delay time of the startup unit and the oscillation unit is a first transmission delay time or a second transmission delay time. When the first input terminal of the startup unit and the input terminal of the oscillation unit receive a high-level signal, the transmission delay time of the startup unit and the oscillation unit is the first transmission delay time; when the first input terminal of the startup unit and the input terminal of the oscillation unit receive a low-level signal, the transmission delay time of the startup unit and the oscillation unit is the second transmission delay time.

[0107] In one exemplary embodiment of this disclosure, a transmission delay time calculation module 74 is further included. The transmission delay time calculation module 74 is configured to: determine the duty cycle of the output signal based on the average amplitude; calculate the first transmission delay time corresponding to the N-type transistor and the second transmission delay time corresponding to the P-type transistor based on the duty cycle and oscillation period of the output signal; determine the process angle of the N-type transistor based on the first transmission delay time and the standard delay time of the N-type transistor; and determine the process angle of the P-type transistor based on the comparison result of the second transmission delay time and the standard delay time of the P-type transistor.

[0108] In one exemplary embodiment of this disclosure, the transmission delay time calculation module 74 is configured to set the ratio of the average amplitude to the power supply voltage of the ring oscillator as the duty cycle of the output signal.

[0109] In an exemplary embodiment of this disclosure, the transmission delay time of the starting unit and the oscillation unit are the same. The transmission delay time calculation module 74 is configured to: determine the first transmission delay time according to a first formula, the first formula including trf=T*D-(N-1)*tPD; and determine the second transmission delay time according to a second formula, the second formula including tfr=T*(1-D)-(N-1)*tPD; where trf is the first transmission delay time, tfr is the second transmission delay time, T is the oscillation period, D is the duty cycle, N is the total number of oscillation units and starting units in the ring oscillator, and 2tPD is the sum of the transmission delay times of two adjacent oscillation units, and tPD=T / (2*N)=(trf+tfr) / 2.

[0110] In one exemplary embodiment of this disclosure, the startup unit includes a NAND gate, and the oscillation unit includes an inverter and a NAND gate.

[0111] Since the functions of the device 700 have been described in detail in their respective method embodiments, they will not be repeated here.

[0112] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0113] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0114] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0115] The following reference Figure 8 To describe an electronic device 800 according to this embodiment of the present invention. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0116] like Figure 8 As shown, the electronic device 800 is manifested in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, and a bus 830 connecting different system components (including storage unit 820 and processing unit 810).

[0117] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 810 can perform the method shown in the embodiments of this disclosure.

[0118] Storage unit 820 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 8201 and / or cache memory 8202, and may further include a read-only memory (ROM) 8203.

[0119] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0120] Bus 830 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0121] Electronic device 800 can also communicate with one or more external devices 900 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0122] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0123] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0124] The program product for implementing the above-described method according to embodiments of the present invention may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0126] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0127] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0128] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0129] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0130] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method for detecting transistor process corners, characterized in that, This is achieved using a ring oscillator composed of transistors under test, including P-type and N-type transistors. The method includes: Obtain the oscillation period of the output signal of the ring oscillator; Obtain the average amplitude of the output signal of the ring oscillator; Based on the ratio of the average amplitude to the power supply voltage of the ring oscillator, and the comparison results of the oscillation period with the first threshold and the second threshold, the process angles of the N-type transistor and the P-type transistor in the ring oscillator are determined, wherein the first threshold is greater than the second threshold.

2. The transistor process corner detection method as described in claim 1, characterized in that, The comparison of the average amplitude with the power supply voltage of the ring oscillator, and the comparison of the oscillation period with the first threshold and the second threshold, includes: When the oscillation period is greater than the first threshold and the ratio is equal to 0.5, it is determined that the ring oscillator is in a slow NMOS slow PMOS process corner. When the oscillation period is greater than the first threshold and the ratio is less than 0.5, the ring oscillator is determined to be in a standard NMOS slow PMOS process corner. When the oscillation period is greater than the first threshold and the ratio is greater than 0.5, the ring oscillator is determined to be in a slow NMOS standard PMOS process corner.

3. The transistor process corner detection method as described in claim 1, characterized in that, The comparison of the average amplitude with the power supply voltage of the ring oscillator, and the comparison of the oscillation period with the first threshold and the second threshold, includes: When the oscillation period is less than the second threshold and the ratio is equal to 0.5, the ring oscillator is determined to be in a fast NMOS or fast PMOS process corner. When the oscillation period is less than the second threshold and the ratio is less than 0.5, the ring oscillator is determined to be in a fast NMOS standard PMOS process corner. When the oscillation period is less than the second threshold and the ratio is greater than 0.5, the ring oscillator is determined to be in a standard NMOS fast PMOS process corner.

4. The transistor process corner detection method as described in claim 1, characterized in that, The comparison of the average amplitude with the power supply voltage of the ring oscillator, and the comparison of the oscillation period with the first threshold and the second threshold, includes: When the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is equal to 0.5, the ring oscillator is determined to be in a standard NMOS or standard PMOS process corner. When the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is less than 0.5, the ring oscillator is determined to be in a fast NMOS slow PMOS process corner. When the oscillation period is greater than or equal to the second threshold and less than or equal to the first threshold, and the ratio is greater than 0.5, the ring oscillator is determined to be in a slow NMOS fast PMOS process corner.

5. The transistor process corner detection method as described in claim 1, characterized in that, The output terminal of the ring oscillator is connected to a frequency divider, and the oscillation period of the output signal of the ring oscillator includes: The output signal is divided using the frequency divider to obtain a first frequency-divided signal, and the period of the first frequency-divided signal is measured. The oscillation period is determined based on the ratio of the period of the first frequency-divided signal to the frequency division factor of the frequency divider.

6. The transistor process corner detection method as described in claim 1, characterized in that, The output terminal of the ring oscillator is connected to a low-pass filter circuit, and obtaining the average amplitude of the output signal of the ring oscillator includes: The average amplitude is obtained based on the output signal of the low-pass filter circuit.

7. The transistor process corner detection method as described in claim 1, characterized in that, Also includes: The duty cycle of the output signal is determined based on the average amplitude. The first propagation delay time corresponding to the N-type transistor and the second propagation delay time corresponding to the P-type transistor are calculated based on the duty cycle of the output signal and the oscillation period. The process angle of the N-type transistor is determined based on the first propagation delay time and the standard delay time of the N-type transistor, and the process angle of the P-type transistor is determined based on the comparison result of the second propagation delay time and the standard delay time of the P-type transistor.

8. The transistor process corner detection method as described in claim 7, characterized in that, Determining the duty cycle of the output signal based on the average amplitude includes: The ratio of the average amplitude to the power supply voltage of the ring oscillator is set as the duty cycle of the output signal.

9. The transistor process corner detection method as described in claim 7, characterized in that, The ring oscillator includes a starting unit and an even number of cascaded oscillation units. The output of the starting unit is connected to the input of the first-stage oscillation unit, the output of the last-stage oscillation unit is connected to the first input of the starting unit, and the second input of the starting unit receives the start-up signal.

10. The transistor process corner detection method as described in claim 9, characterized in that, The transmission delay time of the starting unit and the oscillation unit is a first transmission delay time or a second transmission delay time. When the first input terminal of the starting unit and the input terminal of the oscillation unit receive a high-level signal, the transmission delay time of the starting unit and the oscillation unit is the first transmission delay time. When the first input terminal of the start-up unit and the input terminal of the oscillation unit receive a low-level signal, the transmission delay time of the start-up unit and the oscillation unit is the second transmission delay time.

11. The transistor process corner detection method as described in claim 10, characterized in that, The calculation of the first propagation delay time corresponding to the N-type transistor and the second propagation delay time corresponding to the P-type transistor based on the duty cycle of the output signal and the oscillation period includes: The first transmission delay time is determined according to the first formula, which includes trf = T*D - (N-1)*tPD; The second transmission delay time is determined according to the second formula, which includes tfr=T*(1-D)-(N-1)*tPD; Where trf is the first transmission delay time, tfr is the second transmission delay time, T is the oscillation period, D is the duty cycle, N is the total number of oscillation units and start-up units in the ring oscillator, and 2tPD is the sum of the transmission delay times of two adjacent oscillation units, and tPD = T / (2*N) = (trf + tfr) / 2.

12. The transistor process corner detection method as described in claim 10, characterized in that, The starting unit includes a NAND gate, and the oscillation unit includes an inverter.

13. A transistor process corner detection device, characterized in that, A ring oscillator composed of transistors under test is connected, the ring oscillator including a startup unit and an even number of cascaded oscillation units, the output of the last oscillation unit being connected to an input of the startup unit, the transistors under test including P-type transistors and N-type transistors, the device comprising: The oscillation period acquisition module is configured to acquire the oscillation period of the output signal of the ring oscillator; The amplitude average value acquisition module is configured to acquire the amplitude average value of the output signal of the ring oscillator; The data comparison module is configured to determine the process angle of the N-type transistor and the P-type transistor in the ring oscillator based on the ratio of the average amplitude to the power supply voltage of the ring oscillator and the comparison result of the oscillation period with a first threshold and a second threshold, wherein the first threshold is greater than the second threshold.

14. An electronic device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the transistor process corner detection method as described in any one of claims 1-12 based on instructions stored in the memory.

15. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the transistor process corner detection method as described in any one of claims 1-12.

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