A delay circuit and electronic device

Abstract

The present application provides a delay circuit and electronic equipment, and relates to the field of circuit delay technology. The delay circuit includes an input module, a trigger module, an AND gate, and a delay module, the input module is used to receive an input signal, and the output end of the input module is respectively connected to the trigger module and the first input end of the AND gate, the output end of the trigger module is respectively electrically connected to the second input end of the AND gate and the delay module, and the delay module is respectively electrically connected to the input module and the third input end of the AND gate; wherein, when the input module receives a delay signal, the input module and the delay module are used to delay the delay signal, and output the delayed signal through the AND gate. The delay circuit and electronic equipment provided by the present application have the advantages of reducing a large amount of capacitor area and reducing the chip production cost.

Description

Technical Field

[0001] The present application relates to the field of circuit delay technology, and in particular to a delay circuit and an electronic device. Background Art

[0002] A large number of delay circuits are needed in the operation of the chip. The delay circuit controls the components in the circuit to allow the chip to delay the analog and digital signals generated, thereby controlling the action time of the circuit. At the same time, the delay circuit can also ensure the stability and reliability of the chip and avoid interference from noise signals.

[0003] Although the ordinary RC delay circuit has a simple structure, it has the disadvantages of low precision, high noise and inconvenient frequency adjustment. Since there is no negative feedback, the output amplitude is not stable enough, and the delay time is limited. To obtain a longer delay, a larger capacitor is required, which will waste a lot of area and increase the cost. Summary of the invention

[0004] The purpose of the present application is to provide a delay circuit and an electronic device to solve the problems existing in the prior art such as high cost of the delay circuit and unstable output amplitude.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] On the one hand, an embodiment of the present application provides a delay circuit, which includes an input module, a trigger module, an AND gate, and a delay module, wherein the input module is used to receive an input signal, and the output end of the input module is respectively connected to the trigger module and the first input end of the AND gate, the output end of the trigger module is respectively electrically connected to the second input end of the AND gate and the delay module, and the delay module is respectively electrically connected to the input module and the third input end of the AND gate; wherein,

[0007] When the input module receives a delayed signal, the input module and the delay module are used to perform delay processing on the delayed signal and output the delayed signal through the AND gate.

[0008] Optionally, the input module includes a first switch tube, a second switch tube, a Schmitt trigger, a first inverter and a power supply module. The control end of the first switch tube is used to receive an input signal, the control end of the second switch tube is electrically connected to the delay module, the first ends of the first switch tube and the second switch tube are respectively electrically connected to the power supply module and the Schmitt trigger, the second ends of the first switch tube and the second switch tube are grounded, the output end of the Schmitt trigger is electrically connected to the first inverter, and the output ends of the first inverter are respectively electrically connected to the trigger module and the first input end of the AND gate.

[0009] Optionally, the power module includes a plurality of switch tubes connected in series, and the input module also includes a first transmission gate, the first transmission gate is connected in parallel with one or more of the switch tubes, and when the first transmission gate is turned on, the switch tubes connected in parallel with the first transmission gate are short-circuited.

[0010] Optionally, the delay module includes a first capacitor, a second inverter, a third switch tube, a third capacitor and a connection unit, one end of the first capacitor is electrically connected to the input module, and the other end of the first capacitor is grounded; the input end of the second inverter is electrically connected to the output end of the trigger module, the output end of the second inverter is electrically connected to the first input end of the connection unit and the control end of the third switch tube respectively, the third switch tube and the first end of the capacitor are respectively connected to the second input end of the connection unit, the power supply and the third input end of the AND gate, and the second end of the third switch tube and the capacitor are grounded; wherein,

[0011] When the input module receives the delay signal, the connecting unit is used to output a driving signal to the input module.

[0012] Optionally, the delay module further includes a second transmission gate and a second capacitor, the second transmission gate and the second capacitor are connected in series and then connected in parallel with the first capacitor, and the second transmission gate and the second capacitor are connected in series and then grounded.

[0013] Optionally, when the first capacitor is charged and turned on, the third switch tube is turned on;

[0014] When the first capacitor is charged to a corresponding flip voltage, the third switch tube is turned off, the third capacitor is charged, and the first capacitor is discharged through the input module;

[0015] When the third capacitor is charged to reach the corresponding flip voltage, the input module charges the first capacitor again.

[0016] Optionally, the connection unit includes an NOR gate and a first OR gate, the first input end of the NOR gate is electrically connected to the output end of the second inverter, the second input end of the NOR gate is electrically connected to the third switch tube and the first end of the capacitor, the output end of the NOR gate is electrically connected to the first input end of the first OR gate, the second input end of the first OR gate is used to receive an enable signal, and the output end of the first OR gate is electrically connected to the input module.

[0017] Optionally, the delay circuit also includes a trigger control module, the trigger module includes an RS trigger, the R end of the RS trigger is electrically connected to the trigger control module, the S end of the RS trigger is electrically connected to the input module, and the Q end of the RS trigger is electrically connected to the delay module and the second input end of the AND gate, respectively.

[0018] Optionally, the trigger control module includes a second OR gate, a first input end of the second OR gate is used to receive a trigger signal, a second input end of the second OR gate is used to receive an enable signal, and an output end of the second OR gate is electrically connected to the R end of the RS trigger.

[0019] On the other hand, an embodiment of the present application further provides an electronic device, which includes the above-mentioned delay circuit.

[0020] Compared with the prior art, this application has the following beneficial effects:

[0021] The embodiment of the present application provides a delay circuit and an electronic device, the delay circuit includes an input module, a trigger module, an AND gate and a delay module, the input module is used to receive an input signal, and the output end of the input module is respectively connected to the trigger module and the first input end of the AND gate, the output end of the trigger module is respectively electrically connected to the second input end of the AND gate and the delay module, and the delay module is respectively electrically connected to the input module and the third input end of the AND gate; wherein, when the input module receives a delay signal, the input module and the delay module are used to delay the delay signal and output the delayed signal through the AND gate. The delay circuit structure provided by the present application is relatively simple, and fewer devices are used. Compared with an RC circuit with the same delay duration, a large amount of capacitor area is reduced, and the chip production cost is reduced.

[0022] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A module schematic diagram of a delay circuit provided in an embodiment of the present application.

[0025] Figure 2 A circuit diagram of a delay circuit provided in an embodiment of the present application.

[0026] Figure 3 A waveform diagram corresponding to the delay circuit provided in an embodiment of the present application.

[0027] In the figure:

[0028] 110-input module; 111-Schmitt trigger; 112-first inverter; 113-power module; 114-first transmission gate; 115-second transmission gate; NM1-first switch tube; NM2-second switch tube; C1-first capacitor; C2-second capacitor; 120-trigger module; 130-AND gate; 140-delay module; 141-NOR gate; 142-first OR gate; NM3-third switch tube; C3-third capacitor; 150-second OR gate. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0031] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0032] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0033] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0034] As described in the background technology, the current delay circuit generally adopts the RC delay circuit, which has the problems of high delay circuit cost and unstable output amplitude.

[0035] In view of this, in order to solve the above problems, an embodiment of the present application provides a delay circuit, which achieves the effect of reducing costs and making the delay more stable by setting a simple delay circuit structure.

[0036] The following is an exemplary description of the delay circuit provided in this application:

[0037] As an alternative implementation, see Figure 1 The delay circuit includes an input module 110, a trigger module 120, an AND gate 130 and a delay module 140. The input module 110 is used to receive an input signal, and the output end of the input module 110 is respectively connected to the trigger module 120 and the first input end of the AND gate 130, the output end of the trigger module 120 is respectively electrically connected to the second input end of the AND gate 130 and the delay module 140, and the delay module 140 is respectively electrically connected to the input module 110 and the third input end of the AND gate 130; wherein, when the input module 110 receives a delay signal, the input module 110 and the delay module 140 are used to delay the delay signal and output the delayed signal through the AND gate 130.

[0038] On the one hand, through the delay circuit provided by the present application, when the signal needs to be delayed, the delay module 140 and the input module 110 can be used to perform delay processing to achieve the delay effect. On the other hand, the delay circuit structure provided by the present application is relatively simple, and fewer components are used. Compared with the RC circuit with the same delay time, a large amount of capacitor area is reduced, thereby reducing the chip production cost.

[0039] It should be noted that the delay described in the present application means that after the input module 110 receives the delay signal, the signal is not directly output through the AND gate 130, but is output from the AND gate 130 after a certain period of time after a series of processing. For example, if the delay of the delay circuit is 100us, then when the input module 110 receives the signal, the signal is output from the AND gate 130 after 100us; similarly, if the delay of the delay circuit is 500us, then when the input module 110 receives the signal, the signal is output from the AND gate 130 after 500us, thereby realizing delayed processing of the signal.

[0040] As an alternative implementation, see Figure 2The input module 110 includes a first switch tube NM1, a second switch tube NM2, a Schmitt trigger 111, a first inverter 112 and a power module 113. The control end of the first switch tube NM1 is used to receive the input signal VIN. The control end of the second switch tube NM2 is electrically connected to the delay module 140. The first ends of the first switch tube NM1 and the second switch tube NM2 are electrically connected to the power module 113 and the Schmitt trigger 111 respectively. The second ends of the first switch tube NM1 and the second switch tube NM2 are grounded. The output end of the Schmitt trigger 111 is electrically connected to the first inverter 112. The output end of the first inverter 112 is electrically connected to the first input end of the trigger module 120 and the AND gate 130 respectively.

[0041] Among them, the control end of the first switch tube NM1 can be connected to a comparator, so the input signal VIN is the signal output by the comparator, and the delay circuit provided in this application can generate a delay between the flip point of the comparator and the output end VOUT of the AND gate 130.

[0042] exist Figure 2 In order to facilitate the explanation, different nodes are marked in the circuit, namely net0 to net5, where net0 is the node of the control end of the first switch tube NM1, and net1 is the node input to the Schmitt trigger 111. Optionally, the first switch tube NM1 and the second switch tube NM2 provided in the present application are both NMOS tubes. Of course, in other examples, the first switch tube NM1 and the second switch tube NM2 can also be P-type tubes, which is not limited here.

[0043] When the comparator does not flip, net0 is at a high level, the first switch tube NM1 is turned on, the voltage of the net1 node is pulled down, and the voltage of the net2 node is also pulled down, and then a low level is output through the AND gate 130. Therefore, when the comparator does not flip, the delay circuit can also output normally, but does not provide a delay function; and when the comparator flips, the delay circuit outputs a delayed signal.

[0044] The delay module includes a first capacitor C1 , one end of the first capacitor C1 is electrically connected to the input end of the Schmitt trigger 111 , and the other end of the first capacitor C1 is grounded.

[0045] The capacitor provided in the present application may be a capacitor device, or may be implemented by using the parasitic capacitance of a switch tube, such as Figure 2 In this case, the switching tube device is used as a capacitor.

[0046] By setting the first capacitor C1, when the power module 113 supplies power to the subsequent stage, the first capacitor C1 needs to be charged first, thereby realizing the delay function. In addition, the power module 113 includes a plurality of switch tubes connected in series, and the input module 110 also includes a first transmission gate 114, the first transmission gate 114 is connected in parallel with one or more of the switch tubes, and when the first transmission gate 114 is turned on, the switch tube connected in parallel with the first transmission gate 114 is short-circuited. In the figure, the plurality of switch tubes connected in series all use PMOS tubes, such as the figure including the switch tubes PM1 and PM2 connected in series, and the first transmission gate 114 is connected in parallel with the switch tube PM2, when the first transmission gate 114 is turned off, the power supply supplies power to the first capacitor C1 through the switch tubes PM1 and PM2; and when the first transmission gate 114 is turned on, the switch tube PM2 is short-circuited, and the power supply supplies power to the subsequent stage through the switch tube PM1. It can be understood that, due to the different numbers of switch tubes, the equivalent width-to-length ratios are different, the current changes, and then different biases are selected through the first transmission gate 114 to adjust the length of the delay time.

[0047] In one implementation, the third capacitor C3 can also be powered by the power module 113. On this basis, the power module also includes a switch tube PM3, and the gates of the switch tubes PM3, PM1, and PM2 are all connected to the bias voltage Vbp, one end of the switch tube PM3 is connected to the power supply VDD, and the other end of the switch tube PM3 is connected to the third capacitor C3, thereby powering the third capacitor C3.

[0048] In addition, the delay module 140 also includes a second transmission gate 115 and a second capacitor C2, one end of the second transmission gate 115 and the second capacitor C2 connected in series is connected to the input end of the Schmitt trigger 111, and the other end is grounded. When the second transmission gate 115 is turned off, the second capacitor C2 has no effect on the capacitor; and when the second transmission gate 115 is turned on, the second capacitor C2 is connected to the circuit, and the size of the capacitor can be changed at this time, thereby achieving the purpose of adjusting the length of the delay time. Among them, the second capacitor C2 is connected in parallel with the first capacitor C1, and when the second transmission gate 115 is turned on, the first capacitor C1 and the second capacitor C2 jointly realize the delay. In one implementation, the delay circuit also includes a trigger control module, and the trigger module 120 includes an RS trigger, the R end of the RS trigger is electrically connected to the trigger control module, the S end of the RS trigger is electrically connected to the input module 110, and the Q end of the RS trigger is electrically connected to the second input end of the delay module 140 and the gate 130 respectively. The trigger control module includes a second OR gate 150, a first input end of the second OR gate 150 is used to receive a trigger signal, a second input end of the second OR gate 150 is used to receive an enable signal, and an output end of the second OR gate 150 is electrically connected to the R end of the RS trigger.

[0049] In the present application, the enable signal is a low level signal, and the trigger signal is also a low level signal.

[0050] As an optional implementation, the delay module 140 includes a second inverter, a third switch tube NM3, a third capacitor C3 and a connecting unit, the input end of the second inverter is electrically connected to the output end of the trigger module 120, the output end of the second inverter is electrically connected to the first input end of the connecting unit and the control end of the third switch tube NM3, respectively, the third switch tube NM3 and the first end of the capacitor are respectively connected to the second input end of the connecting unit, the power supply and the third input end of the AND gate 130, and the third switch tube NM3 and the second end of the capacitor are grounded; wherein, when the input module 110 receives the delay signal, the connecting unit is used to output a driving signal to the input module 110.

[0051] Among them, the connection unit includes an NOR gate 141 and a first OR gate 142, the first input end of the NOR gate 141 is electrically connected to the output end of the second inverter, the second input end of the NOR gate 141 is electrically connected to the third switch tube NM3 and the first end of the capacitor, the output end of the NOR gate 141 is electrically connected to the first input end of the first OR gate 142, the second input end of the first OR gate 142 is used to receive an enable signal, and the output end of the first OR gate 142 is electrically connected to the input module 110.

[0052] Specifically, the output end of the first OR gate 142 is electrically connected to the control end of the second switch tube NM2, and the second switch tube NM2 adopts an NMOS tube, so when the first OR gate 142 outputs a low level, the second switch tube NM2 is turned off; and when the first OR gate 142 outputs a high level, the second switch tube NM2 is turned on.

[0053] It can be understood that the working principle of the delay circuit provided in this application is:

[0054] When the comparator does not flip, the signal of net0 is high level, the first switch tube NM1 is turned on, net1 is pulled low, and the voltage of net2 node is also pulled low, and then a low level is output through the AND gate 130 without delay.

[0055] When the comparator flips, that is, the VIN signal is at a low level, net0 becomes low, the first switch tube NM1 is turned off, the power module 113 starts to charge the first capacitor C1, and net1 starts to change from low to high. When net1 exceeds the flip point of the Schmitt trigger 111, net2 becomes high. At this time, the net3 signal line at the Q end of the RS trigger is high, and net4 is low. Because the power supply ibp charges the third capacitor C3 at this time, net5 changes from low to high, but the logic judgment is still low. In addition, at this time, both input ends of the NOR gate 141 are 0, and the output is 1. Because the en_b signal is always low, the output signal con of the first OR gate 142 is high, and con is connected to the gate end of the second switch tube NM2, thereby causing the second switch tube NM2 to turn on, and the first capacitor C1 is discharged through the resistors R1 and NM2, so net1 is quickly pulled down. When the third capacitor C3 is charged, the voltage of net5 gradually increases. When the net5 signal increases to the flip voltage, the output of the NOR gate 141 is 0, the output signal con of the first OR gate 142 also becomes 0, the second switch tube NM2 is turned off, and the power module 113 charges the first capacitor C1 again. Net1 changes from low to high. When net1 exceeds the flip point of the Schmitt trigger 111, net2 becomes high. At this time, the net2, net3 and net5 signal lines are all high, and the VOUT output is high. Through two transmission gates, the length of the delay time can be determined by selecting different biases and capacitor sizes.

[0056] It should be noted that the "0" and "1" described in this application refer to low level and high level, respectively, which will not be elaborated here. In addition, according to the above working principle, when the signal is flipped, that is, when the input signal is at a low level, the first capacitor C1, the third capacitor C3 and the driving signal con are used to add a delay function to the entire circuit. The applicant has verified that the delay circuit provided in this application can provide a delay of 50us to 500us.

[0057] Specifically, for the first capacitor C1 and the third capacitor C3, there are three stages in total. First, when the first capacitor C1 is charged and turned on, the third switch tube (NM3) is turned on, and the third capacitor C3 is not charged at this time; then, when the first capacitor C1 is charged to reach the corresponding flip voltage, the third switch tube NM3 is turned off, the third capacitor C3 is charged, and the first capacitor is discharged through the circuit of the resistor R1 and the second switch tube NM2; finally, when the third capacitor C3 is charged to reach the corresponding flip voltage, the input module charges the first capacitor C1 again. That is, in this application, the first capacitor C1 is charged first, and then the third capacitor C3 is charged. At this time, the first capacitor C1 is discharged, and finally the first capacitor C1 is charged again, and then the delay effect is achieved through the first capacitor C1 and the third capacitor C3.

[0058] See also Figure 3, which is a schematic diagram of the simulation waveform corresponding to the delay circuit provided in this application. In the figure, net0 to net5 correspond to Figure 2 As can be seen from the figure, the waveform of the response node includes the stages of charging the first capacitor C1, charging the third capacitor and discharging the first capacitor, and charging the first capacitor again, that is, the time period t1 to t3 in the figure. Specifically, during the t1 period, the first capacitor C1 is charged, C1 is charged, and a delay is generated. During the charging process, the net1 voltage continues to rise. When it rises to the flip point of the Schmitt trigger, the third switch tube NM3 is turned off, the third capacitor C3 begins to charge, and the con signal flips. At this time, the second switch tube NM2 is turned on, and the first capacitor C1 is discharged through the resistor R1. As the third capacitor C3 continues to charge, the net5 voltage continues to rise. When the voltage reaches the flip voltage, the con signal flips again. At this time, the second switch tube NM2 is turned off and continues to charge the first capacitor C1.

[0059] Therefore, in the stage t1, the delay is achieved by charging the first capacitor C1; in the stage t2, the delay is achieved by charging the third capacitor C3; and in the stage t3, the delay is achieved again by charging the first capacitor C1.

[0060] Based on the above working principle, the delay circuit provided by this application mainly has the following effects:

[0061] 1. The delay circuit provided in the present application has a simple structure. It uses the first capacitor C1, the third capacitor C3 and the driving signal con to realize the delay function. At the same time, fewer devices are used. Compared with the RC circuit with the same delay time, a large amount of capacitor area is reduced, thereby reducing the chip production cost.

[0062] 2. The delay circuit provided by the present application adds two transmission gates and an adjustment resistor R1. By controlling the on and off of the transmission gates, selecting different biases and capacitors, and adjusting the size of the resistor R1, the length of the delay time can be flexibly adjusted. The resistor R1 can also be replaced by a current mirror, and the delay time can be adjusted by controlling the discharge time of C1.

[0063] Based on the above implementation, an embodiment of the present application further provides an electronic device, which includes the above delay circuit.

[0064] In summary, the embodiment of the present application provides a delay circuit and an electronic device, the delay circuit includes an input module 110, a trigger module 120, an AND gate 130 and a delay module 140, the input module 110 is used to receive an input signal, and the output end of the input module 110 is respectively connected to the trigger module 120 and the first input end of the AND gate 130, the output end of the trigger module 120 is respectively electrically connected to the second input end of the AND gate 130 and the delay module 140, and the delay module 140 is respectively electrically connected to the input module 110 and the third input end of the AND gate 130; wherein; when the input module 110 receives the delay signal, the input module 110 and the delay module 140 are used to delay the delay signal and output the delayed signal through the AND gate 130. The delay circuit structure provided by the present application is relatively simple, and fewer devices are used. Compared with the RC circuit with the same delay time, a large amount of capacitor area is reduced, and the chip production cost is reduced.

[0065] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0066] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A delay circuit, characterized in that: The delay circuit comprises an input module (110), a trigger module (120), an AND gate (130) and a delay module (140); the input module (110) is used to receive an input signal, and the output end of the input module (110) is respectively connected to the trigger module (120) and the first input end of the AND gate (130); the output end of the trigger module (120) is respectively electrically connected to the second input end of the AND gate (130) and the delay module (140); the delay module (140) is respectively electrically connected to the input module (110), the trigger module (120) and the third input end of the AND gate (130); wherein: When the input module (110) receives a delayed signal, the input module (110) and the delay module (140) are used to perform delay processing on the delayed signal and output the delayed signal through the AND gate (130); The delay module (140) comprises a first capacitor (C1), a second inverter, a third switch tube (NM3), a third capacitor (C3) and a connection unit, one end of the first capacitor (C1) is electrically connected to the input module (110), and the other end of the first capacitor (C1) is grounded; the input end of the second inverter is electrically connected to the output end of the trigger module (120), the output end of the second inverter is electrically connected to the first input end of the connection unit and the control end of the third switch tube (NM3), the first end of the third switch tube (NM3) and the third capacitor are respectively connected to the second input end of the connection unit, the power module (113) and the third input end of the AND gate (130), and the second end of the third switch tube (NM3) and the third capacitor are grounded; wherein, When the input module (110) receives the delay signal, the connection unit is used to output a drive signal to the input module (110).

2. The delay circuit according to claim 1, characterized in that: The input module (110) comprises a first switch tube (NM1), a second switch tube (NM2), a Schmitt trigger (111), a first inverter (112) and a power module (113); the control end of the first switch tube (NM1) is used to receive an input signal; the control end of the second switch tube (NM2) is electrically connected to the delay module (140); the first ends of the first switch tube (NM1) and the second switch tube (NM2) are respectively electrically connected to the power module (113) and the Schmitt trigger (111); the second ends of the first switch tube (NM1) and the second switch tube (NM2) are grounded; the output end of the Schmitt trigger (111) is electrically connected to the first inverter (112); the output end of the first inverter (112) is respectively electrically connected to the first input end of the trigger module (120) and the AND gate (130).

3. The delay circuit according to claim 2, characterized in that: The power module (113) comprises a plurality of switch tubes connected in series, and the input module (110) further comprises a first transmission gate (114), wherein the first transmission gate (114) is connected in parallel with one or more of the switch tubes, and when the first transmission gate (114) is turned on, the switch tubes connected in parallel with the first transmission gate (114) are short-circuited.

4. The delay circuit according to claim 1, characterized in that: The delay module (140) further comprises a second transmission gate (115) and a second capacitor (C2); the second transmission gate (115) and the second capacitor (C2) are connected in series and then connected in parallel with the first capacitor (C1); and the second transmission gate (115) and the second capacitor (C2) are connected in series and then grounded.

5. The delay circuit according to claim 1, characterized in that: When the first capacitor (C1) is charged and turned on, the third switch tube (NM3) is turned on; When the first capacitor (C1) is charged to reach a corresponding flip voltage, the third switch tube (NM3) is turned off, the third capacitor (C3) is charged, and the first capacitor is discharged through the input module (110); When the third capacitor (C3) is charged to reach the corresponding flip voltage, the input module charges the first capacitor (C1) again.

6. The delay circuit according to claim 1, characterized in that: The connection unit comprises a NOR gate (141) and a first OR gate (142); a first input end of the NOR gate (141) is electrically connected to an output end of the second inverter; a second input end of the NOR gate (141) is electrically connected to the third switch tube (NM3) and a first end of the third capacitor; an output end of the NOR gate (141) is electrically connected to a first input end of the first OR gate (142); a second input end of the first OR gate (142) is used to receive an enable signal; and an output end of the first OR gate (142) is electrically connected to the input module (110).

7. The delay circuit according to claim 1, characterized in that: The delay circuit also includes a trigger control module, the trigger module (120) includes an RS trigger, the R end of the RS trigger is electrically connected to the trigger control module, the S end of the RS trigger is electrically connected to the input module (110), and the Q end of the RS trigger is electrically connected to the delay module (140) and the second input end of the AND gate (130), respectively.

8. The delay circuit according to claim 7, characterized in that: The trigger control module comprises a second OR gate (150), a first input end of the second OR gate (150) is used to receive a trigger signal, a second input end of the second OR gate (150) is used to receive an enable signal, and an output end of the second OR gate (150) is electrically connected to an R end of the RS trigger.

9. An electronic device, characterized in that: The electronic device comprises the delay circuit according to any one of claims 1 to 8.

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