Selectively biased magnetoresistive random access memory cell

Abstract

A magnetoresistive random access memory (MRAM) cell is provided. The MRAM cell (500) includes a top contact (502), a hard mask layer (504) below the top contact, and a magnetic tunnel junction (MTJ) (506) below the hard mask layer. The MRAM cell further includes a diffusion barrier (508) below the MTJ, a bottom contact (510) below the diffusion barrier, and a magnetic liner (512) disposed around the bottom contact.

Description

Background Technology

[0001] This disclosure relates to the electrical, electronic, and computer fields. In particular, the present invention relates to a magnetoresistive random-access memory (MRAM) cell manufactured to selectively bias the cell.

[0002] MRAM is a type of non-volatile memory used to store data in computers and other electronic devices. Unlike conventional read-access memory (DRAM), which uses charge or current (e.g., capacitors) to store data, MRAM uses magnetic storage elements to store data in a magnetic field. The magnetic storage element is formed by two ferromagnetic plates, each of which can be kept magnetized and separated by a thin insulating layer. The magnetization of the plates can be changed to match the magnetization of the external field of the memory. Summary of the Invention

[0003] Embodiments of this disclosure include a magnetoresistive random access memory (MRAM) cell. The MRAM cell includes a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further includes a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner disposed around the bottom contact.

[0004] Advantageously, embodiments of this disclosure include a magnetic liner surrounding the bottom contact. The magnetic liner may be formed to have a specific size for selectively biasing the resulting MRAM cells. For example, the MRAM cells may be biased to make it easier to write to high or low values, depending on the size of the magnetic liner. This can be advantageous in certain applications, such as by allowing artificial intelligence models written to memory to be pre-biased or by storing security keys in memory.

[0005] In some embodiments, the size of the bottom contacts and the liner is based on the desired bias conditions of the MRAM cells. This allows for hardware biasing of each MRAM cell in the memory array based on the intended use of the memory device containing the memory array.

[0006] Additional embodiments of the present invention include an MRAM cell. The MRAM cell includes a top contact, a hard mask layer below the top contact, and an MTJ below the hard mask layer. The MRAM cell further includes a diffusion barrier below the MTJ and a bottom contact below the diffusion barrier. The bottom contact includes a ferromagnetic filler.

[0007] Advantageously, embodiments of this disclosure include a magnetic filler in the bottom contact. The magnetic filler may be formed to have a specific size for selectively biasing the resulting MRAM cells. For example, the MRAM cells may be biased to make it easier to write to high or low values, depending on the size of the bottom contact. This can be advantageous in certain applications, such as by allowing artificial intelligence models to be pre-biased for writing into memory or by storing security keys in memory.

[0008] In some embodiments, the sizes of the bottom contact and MTJ are based on the desired bias conditions of the MRAM cell. This allows for hardware biasing of each MRAM cell in the memory array based on the intended use of the memory device containing the memory array. Additionally, controlling the sizes of the MTJ and bottom contact, rather than just the bottom contact, allows for a wider range of pre-biases and a simpler manufacturing process.

[0009] Additional embodiments of the present invention include methods, systems, and computer program products for forming an MRAM device, wherein individual MRAM cells are selectively biased. The method includes determining a set of MRAM cells to be hardware biased in a memory array. The method further includes determining bias conditions for each MRAM cell in the set of MRAM cells. The method further includes determining a critical dimension for each MRAM cell in the set of MRAM cells based on the bias conditions of the MRAM cell and the structure type of the MRAM cell. The method further includes fabricating the memory array using the determined critical dimension of each MRAM cell in the set of MRAM cells.

[0010] Advantageously, embodiments of this disclosure allow individual MRAM cells to be pre-biased to a specific state. For example, MRAM cells can be biased to make it easier to write to high or low values, depending on the critical size of the manufactured MRAM cell. This can be advantageous in certain applications, such as by allowing artificial intelligence models written to memory to be pre-biased or by storing security keys in memory.

[0011] In some embodiments, the set of MRAM cells to be hardware biased is determined based on the intended use of the MRAM device. This allows the MRAM device to be more specifically tailored to a particular application. For example, an MRAM device used for an artificial intelligence model can be selectively biased, making it particularly suitable for pre-biasing an artificial intelligence model.

[0012] The above overview is not intended to describe every illustrated embodiment or implementation of this disclosure.

[0013] Brief description of the attached figures

[0014] The accompanying drawings, which are included in and form a part of this disclosure, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are merely illustrative of exemplary embodiments and do not limit the scope of the disclosure.

[0015] Figure 1 An example memory device according to an embodiment of the present disclosure is shown, wherein each memory cell is selectively biased to one of three bias conditions.

[0016] Figure 2 A second example memory device according to an embodiment of the present disclosure is shown, wherein each memory cell is selectively biased to one of three bias conditions.

[0017] Figure 3 This is a diagram illustrating an example deep neural network including a set of bias nodes according to an embodiment of the present disclosure.

[0018] Figure 4 This is a diagram illustrating a bias weight matrix that can be used to transform an input vector into an output vector via matrix multiplication, according to an embodiment of the present disclosure.

[0019] Figure 5 This is a cross-sectional view illustrating a first example MRAM cell structure for selectively biasing MRAM cells according to an embodiment of the present disclosure.

[0020] Figure 6 This is a cross-sectional view illustrating a second example MRAM cell structure for selectively biasing MRAM cells according to an embodiment of the present disclosure.

[0021] Figure 7 This is a cross-sectional view illustrating a third example MRAM cell structure for selectively biasing MRAM cells according to an embodiment of the present disclosure.

[0022] Figure 8 This is a diagram illustrating the effect of different bottom contact sizes on the programming voltage of an MRAM cell in a first example MRAM cell structure according to an embodiment of the present disclosure.

[0023] Figure 9 The magnetic field lines of an MRAM cell according to an embodiment of the present disclosure are shown, the MRAM cell having an external magnetic underlayer (EMU) liner on the bottom contact.

[0024] Figure 10 The magnetic field lines of an MRAM cell having EMU filling for a bottom contact are shown according to an embodiment of the present disclosure.

[0025] Figure 11AThis is a graph illustrating experimental results showing that adding Co DAL does not alter the effective vertical anisotropy field of the free layer in a magnetic tunnel junction (MTJ) element according to an embodiment of the present disclosure.

[0026] Figure 11B The figure shows experimental results illustrating how adding Co DAL according to an embodiment of the present disclosure reduces the stray magnetic field from the fixed layer to the free layer in an MTJ element to approximately zero.

[0027] Figure 12 A flowchart of an example method for selectively biasing an MRAM cell array according to an embodiment of the present disclosure is shown.

[0028] Figure 13 A high-level block diagram of an exemplary computer system, according to embodiments of the present disclosure, is shown that can be used to implement one or more of the methods, tools, modules, and any associated functions described herein.

[0029] While the embodiments described herein are subject to various modifications and alternatives, their details have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the specific embodiments described are not intended to be limiting. Rather, the invention is intended to cover all modifications, equivalents, and substitutions that fall within the scope of the invention. Detailed Implementation

[0030] This invention relates generally to the electrical, electronic, and computer fields, and more particularly to magnetoresistive random access memory (MRAM) cells and methods of manufacturing the same, wherein the MRAM cells are manufactured to selectively bias the cells. While this disclosure is not necessarily limited to such applications, various aspects of this disclosure can be understood through the discussion of different examples using this context.

[0031] Various embodiments of this disclosure are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of this disclosure. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) are illustrated between elements in the following description and drawings. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and this disclosure is not intended to limit this aspect. Thus, the connection of entities may refer to direct or indirect connections, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the reference in this specification to forming layer "A" on layer "B" includes one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B," provided that the intermediate layers substantially do not alter the relevant characteristics and functions of layer "A" and layer "B."

[0032] The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms “comprises,” “compri sing,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0033] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives will refer to the structures and methods described in the orientation shown in the figures. The terms “cover,” “top,” “on top,” “positioned on,” or “positioned on top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an insert element (such as an interface structure) may be present between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer. It should be noted that the term “selective,” such as “the first element is selectively used for the second element,” means that the first element can be etched, and the second element can act as an etching barrier.

[0034] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein. In particular, the steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known; therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0035] Generally speaking, the various processes used to form microchips that will be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / photolithography.

[0036] Deposition is any process that grows, coats, or otherwise transfers materials onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), which is a process that uses energy within a plasma to initiate a reaction at the wafer surface, where the reaction would otherwise require the higher temperatures associated with conventional CVD. The energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0037] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and more. One example of a removal process is ion beam etching (IBE). Typically, IBE (or milling) refers to a dry plasma etching method that uses a long-range, wide-beam ion / plasma source to remove substrate material through a device containing physically inert gases and / or chemically reactive gases. Similar to other dry plasma etching techniques, IBE offers benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). RIE typically uses chemically reactive plasma to remove material deposited on a wafer. With RIE, plasma is generated under low pressure (vacuum) via an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove the material.

[0038] Semiconductor doping alters electrical properties by doping (e.g., transistor source and drain), typically through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (“RTA”). Annealing is used to activate the implanted dopant. Films of conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate the transistors and their components. Selective doping of individual regions of a semiconductor substrate allows the substrate's conductivity to change with the application of voltage. By creating structures of these different components, millions of transistors can be built and wired together to form the complex circuitry of modern microelectronic devices.

[0039] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. To build the numerous wires that make up the complex structure of transistors and the interconnecting circuits of millions of transistors, the lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0040] Turning now to a more specific overview of the technology relating to aspects of the invention, generally, an MRAM cell refers to any material or combination of materials capable of storing one bit of information using magnetic storage elements. An MRAM cell value (which can be binary (1 or 0) or analog (e.g., 0.65)) is stored in the memory cell as a function of the cell's resistance, similar to how values ​​are stored in resistive random access memory (ReRAM or RRAM) cells and / or memristors. In other words, the relative orientation of the magnetization of the plates within the MRAM cell affects the resistance of the MRAM cell. This resistance can be measured by passing current through the MRAM cell, and the measured resistance can be converted into a value.

[0041] In magnetic tunnel junction (MTJ) devices, current-induced magnetization is a key phenomenon of interest for MRAM cells / devices. Recognizing that some applications benefit from biasing individual memory cells, the inventors have identified a need for variability in the switching of MTJ cells in STT-MRAM with current (or write voltage) differences. For example, the inventors have recognized that in STT-MRAM arrays, there are unintentional variations at the edges of the array, such as MTJ size and asymmetry from the physical location of the cells. These result in a suboptimal array, as some cells behave differently from others based on their position within the array. Furthermore, as recognized by the inventors, the intentional biasing of MRAM cells can be used as a building block for AI applications or for security purposes.

[0042] Embodiments of this disclosure address the above and other problems of current MRAM technology. Embodiments of this disclosure include methods and structures for intentionally hardware biasing individual memory cells in a memory array. Biasing MRAM cells alters the ease with which MRAM cells can be programmed into a specific state (e.g., a state associated with a 0 or 1 bit value). In some embodiments, one or more MRAM cells may be biased such that they can only have a specific memory state (e.g., always 0 or always 1).

[0043] Hardware biasing of selected memory cells can be used in applications where artificial intelligence (AI) models are embedded in memory arrays, such that certain memory cells containing the values ​​of selected portions of the AI ​​model (e.g., specific weights in a deep neural network (DNN) model) are pre-biased to favor a particular state. This allows the AI ​​model to be pre-biased before training and computer learning occur. Other example implementations of embodiments of this disclosure include: when security keys are being programmed into separate arrays (such as for security applications and / or system controller applications), and when specific MRAM cells are intentionally biased to mitigate known problems of memory arrays related to manufacturing processes (e.g., to reduce the number of virtual bits and increase the density of the memory device).

[0044] Embodiments of this disclosure include a method for intentionally pre-biasing MRAM cells of a memory array. The method may include determining which MRAM cells in the memory array should be biased. The memory array may be biased based on a specific implementation of the memory array that will be used (e.g., an AI model or a security key). The method may also include determining a bias condition for each of the MRAM cells in the memory array. The bias condition for an MRAM cell may be a type or level of hardware bias for the MRAM cell. In some embodiments, there may be two different bias conditions, while in other embodiments, there may be more than two different bias conditions.

[0045] The MRAM cells to be biased and the bias conditions to be applied to them can depend on the specific application / implementation of the memory array. For example, in some embodiments, MRAM cells may be biased to reduce design problems associated with the MRAM array (especially along the edges of the array), while in other embodiments, individual cells may be biased to pre-bias the AI ​​model or security key to the memory array. The number of MRAM cells to be biased, which MRAM cells to be biased, and which bias conditions (and how many bias conditions) to use can all depend on the specific embodiment. For example, different AI models may have different pre-bias conditions, such that different MRAM cells are hardware biased for each AI model.

[0046] Once the MRAM cells to be biased are determined and bias conditions are defined for each such MRAM cell, the method may include fabricating an MRAM array. Fabricating the MRAM array can utilize known or conventional manufacturing processes or operations to produce MRAM cell structures with specific hardware biases. The bias conditions may be determined by the volume of magnetic material in the underlying bottom contacts or interconnects. In other words, the relative volume of the magnetic material beneath the pre-programmed lithography of the bottom contacts (assuming a fixed magnetic substrate thickness) determines how the MRAM cells are biased. Embodiments include biasing an MRAM circuit or array for pre-programming based on the volume of the bottom electrode magnetic material and using it itself within the MRAM array. Some embodiments modify the bias of individual MRAM cells by performing one or more of the following: a) changing the microscale size beneath the MTJ by the size of the magnetic substrate; b) increasing the Co substrate thickness by the same microscale size; and / or c) changing the size of the MTJ cell. Several example MRAM cell structures for selectively biasing MRAM cells are disclosed herein.

[0047] Some embodiments of this disclosure utilize a liner added to the bottom contacts of an MRAM cell, the MRAM cell including a magnetic tunnel junction (MTJ). The liner includes magnetic materials (e.g., cobalt, iron, nickel, magnetic metal alloys (e.g., nickel alloys), and / or rare earth alloys (e.g., neodymium alloys (e.g., NdFeB) and samarium-cobalt alloys)). These embodiments can be used by varying the size of the bottom contacts and the magnetic liner (e.g., as shown in the original text). Figure 5 (as shown), by changing the size of the magnetic liner without changing the size of the bottom contact and / or by changing the dimensions of the entire MTJ stack and the bottom contact (e.g., as shown). Figure 6 (As shown in the figure) to control (e.g., tune) the bias conditions of the MRAM cell.

[0048] In certain embodiments of the present invention, the typical bottom contact of an MRAM cell is replaced or substantially replaced with a magnetic material. For example, in some embodiments, the entire bottom contact may be made of a magnetic material, while in other embodiments, the body of the bottom contact may be made of a magnetic material (e.g., having a Cu liner for increased conductivity). These embodiments can be used to control the bias conditions of an MRAM cell by carrying the size of the bottom magnetic contact. Examples of this embodiment are shown in... Figure 7 The diagram illustrates an MRAM cell with three different bias conditions. In some embodiments, two or more of the three methods of biasing the MRAM cells in the memory array are included in the same array. For example, some MRAM cells in the array may utilize a substrate, while other MRAM cells in the memory array may utilize a magnetic bottom contact (e.g., magnetic fill).

[0049] It should be understood that the above advantages are exemplary and should not be construed as limiting. Embodiments of this disclosure may include all, some, or not include the above advantages while remaining within the spirit and scope of this disclosure.

[0050] Now turn to the attached diagram. Figure 1 An example memory device 100 according to an embodiment of the present disclosure is shown, wherein each memory cell is selectively biased to one of three bias conditions. The memory device 100 includes a memory array 102 and peripheral circuitry 104 and 106. The memory array 102 includes a plurality of MRAM cells, each storing individual data bits, and the peripheral circuitry 104, 106 includes different integrated circuits for reading data from and writing data to the memory array 102. The MRAM array 102 may include a plurality of hardware-biased MRAM cells, and Figure 1 The arrangement of the biased cells shown can be particularly useful for counteracting problems caused by MRAM manufacturing, which result in some MRAM cells along the edge of memory array 102 being biased differently from the MRAM cells in the middle of memory array 102.

[0051] like Figure 1 As shown, each MRAM cell in memory array 102 is subject to one of three different bias conditions. MRAM cell 108A at the center of MRAM array 102 is hardware biased to the first bias condition. Similarly, MRAM cells 108B along the edges of memory array 102 are hardware biased to the second bias condition, while MRAM cells 108C between edge MRAM cells 108B and inner MRAM cells 108A are hardware biased to the third bias condition. Each bias condition determines the ease with which an MRAM cell can be written to a specific value. For example, MRAM cell 108A with the first bias condition is effectively unbiased, making it equally easy to write the cell to 0 as to write it to 1. Meanwhile, MRAM cell 108B with the second bias condition is easier to write to 1 than to 0, and MRAM cell 108C with the third bias condition is easier to write to 0 than to 1.

[0052] See now Figure 2 This paper depicts a second example memory device 200 according to embodiments of the present disclosure, wherein each memory cell is selectively biased to one of three bias conditions. The memory device 200 includes a memory array 202 and peripheral circuitry 204 and 206. The memory array 202 includes a plurality of MRAM cells, each storing individual data bits, and the peripheral circuitry 204, 206 includes different integrated circuits for reading data from and writing data to the memory array 202. The MRAM array 202 may include a plurality of hardware-biased MRAM cells.

[0053] Similar to Figure 1 The memory array 102 shown is described above, and each MRAM cell in the memory array 202 is subject to one of three different bias conditions. Furthermore, each bias condition determines the ease with which an MRAM cell can be written to a specific value. For example, an MRAM cell 208A with a first bias condition is effectively unbiased, making it equally easy to write the cell to 0 as to write it to 1. Meanwhile, an MRAM cell 208B with a second bias condition is easier to write to 1 than to 0, and an MRAM cell 208C with a third bias condition is easier to write to 0 than to 1.

[0054] However, unlike memory array 102, MRAM cells with the same bias conditions in memory array 202 are not grouped together. Instead, each bias condition 108A-C is more dispersed across the array. This is because... Figure 2 The arrangement of biased cells shown corresponds to an example hardware bias of MRAM cells to pre-bias the AI ​​model or embed a security key into memory array 202. Accordingly, the bias condition of each MRAM cell does not correspond to its location in memory array 202 (as is the case with memory array 102), but rather the bias condition of each MRAM cell is based on what information will be stored in that MRAM cell (e.g., which node of the AI ​​model or part of the security key is stored in that MRAM cell).

[0055] See now Figure 3 The diagram illustrates an example deep neural network (DNN) 300 including a set of biased nodes according to embodiments of the present disclosure. The DNN 300 includes a plurality of nodes 310. The nodes 310 are grouped into an input layer, three hidden layers 304, 306, and an output layer 308. One of the hidden layers 304 includes a biased node, wherein each of the three bias conditions of the node 310 is associated with a different pattern on the node 310. The biased nodes in the biased hidden layers 304 can be hardware biased by physically biasing the MRAM cells that hold the values ​​(e.g., weights) of the biased nodes. Figure 4 As shown in Figure 400, the weight matrix 402 can be biased by biasing the nodes in the biased hidden layer 304. For example, the first cell 408 in the bias weight matrix 402 can be biased to a value of 0, while the second cell 410 in the weight matrix 402 can be biased low (e.g., shown as 1), and the third cell 412 in the weight matrix 402 can be biased high (e.g., shown as 9). Therefore, as Figure 4 As shown, the transformation of input vector 404 into output vector 406 via matrix multiplication can be hardware biased.

[0056] See now Figure 5 The diagram shown is a cross-sectional view depicting a first example MRAM cell structure for selectively biasing MRAM cells according to embodiments of the present disclosure. Specifically, Figure 5 Three different MRAM cells 500 with the same basic structure are shown, each of which has a different bias condition. Figure 5 The embodiment shown includes a structure with an external magnetic substrate (EMU) liner beneath MTJs of different sizes on a microstud. The bottom contact liner comprises a ferromagnetic liner, and different magnetic fields are applied to the MTJs, thus applying different write / read voltages.

[0057] Each MRAM cell 500 includes a top contact 502, a hard mask 504, an MTJ 506, a barrier 508 (also known as a diffusion barrier), a bottom contact 510, and a magnetic liner 512. Generally, the MTJ 506 comprises two ferromagnetic bodies separated by an insulator, also known as a tunnel barrier. Each of these components may actually consist of one or more individual material layers, and other material layers may be found within the MTJ 506, directly on top of the MTJ 506, or directly beneath the MTJ 506.

[0058] For example, the MTJ 506 may include a free layer, a tunnel barrier beneath the free layer, and a reference layer beneath the tunnel barrier. The free layer and reference layer may be made of a ferromagnetic material, while the tunnel barrier may be an insulating material. For example, in some embodiments, the tunnel barrier may include one or more epitaxial (crystalline) MgO layers. In other embodiments, other suitable materials (e.g., amorphous alumina) may be used as the tunnel barrier. The free layer may be connected to the top contact of the MRAM cell, while the reference layer may be connected to the bottom contact. In some embodiments, a heavy metal layer (e.g., Pt, Ta) separates the free layer and / or reference layer from the contacts. The MTJ 506 may further include a dielectric material to isolate the MTJ from components other than the contacts. For example, a dielectric package using a low-k material may be formed on the lateral edges of the MTJ 506 to encapsulate the MTJ 506.

[0059] In some embodiments, the hard mask 504 may be, but is not limited to, a slow IBE etched conductor. For example, the hard mask 504 may include one or more Ta, TaN, Ru, and / or W layers.

[0060] MRAM cell 500 can be hardware biased by changing the critical dimensions (e.g., size or area) of the bottom contact 510 and magnetic substrate 512. For example, a first MRAM cell 500A may have a first bias condition based on its relatively large bottom contact 510 and magnetic substrate 512. (See below for more details.) Figure 8 In more detail, the first MRAM cell 500A may be biased to make it easier to write to a high state (e.g., 1). Meanwhile, the third MRAM cell 500C, having the smallest bottom contact 510 and magnetic substrate 512, may be the MRAM cell 500 most easily written to a low state (e.g., 0), while the second MRAM cell 500B, having a critical size somewhere between the first MRAM cell 500A and the third MRAM cell 500C, may fall somewhere between the other two. In other words, the second MRAM cell 500B may be easier to write low but harder to write high than the first MRAM cell 500A, and easier to write high but harder to write low than the third MRAM cell 500C.

[0061] See now Figure 6 The diagram shows a cross-sectional view depicting a second example MRAM cell structure for selectively biasing an MRAM cell 600 according to an embodiment of the present disclosure. Specifically, Figure 6 Three different MRAM cells 600 with the same basic structure are shown, each of which has a different bias condition. Figure 6 The embodiment shown includes a structure with an external magnetic underlayer (EMU) liner beneath the MTJ, incorporating different critical sizes of the MTJ. The bottom contact liner comprises a ferromagnetic liner, and the variations in the MTJ critical size, along with the different sizes of the EMU, require different currents or voltages for writing / reading each cell.

[0062] The MRAM cell 600 can be broadly similar to the one about Figure 5 The MRAM cell 500 discussed. Specifically, each MRAM cell 600 includes a top contact 602, a hard mask 604, an MTJ 606, a diffusion barrier 608, a bottom contact 610, and a magnetic liner 612. Each of these components can be coupled with... Figure 5 The corresponding components are substantially similar or identical. For example, in some embodiments, MTJ 606 includes the same sub-components and their arrangement as MTJ 506 discussed above.

[0063] However, unlike MRAM cell 500, MRAM cell 600 can be hardware biased by changing the critical dimensions (e.g., size or area) of the entire stack rather than the top contact. In other words, MRAM cell 500 can be biased by changing the size of the hard mask 604, MTJ 606, diffusion barrier 608, bottom contact 610, and magnetic liner 612 (collectively referred to herein as the MRAM stack). For example, first MRAM cell 600A may have a first bias condition based on its relatively large MRAM stack. Thus, first MRAM cell 600A may be biased to make it relatively easy to write to a high state (e.g., 1). Meanwhile, third MRAM cell 600C with the smallest MRAM stack may be the MRAM cell 600 most easily written to a low state (e.g., written to 0), while second MRAM cell 600B with a critical dimension somewhere between first MRAM cell 600A and third MRAM cell 600C may fall somewhere between the other two. In other words, the second MRAM cell 600B is easier to write low but harder to write high than the first MRAM cell 600A, and easier to write high but harder to write low than the third MRAM cell 600C.

[0064] See now Figure 7 The image shown is a cross-sectional view depicting a third example MRAM cell structure for selectively biasing MRAM cells according to embodiments of the present disclosure. Specifically, Figure 7 Three different MRAM cells 700 with the same basic structure are shown, each of which has a different bias condition. Figure 6 The illustrated embodiment includes a structure with an EMU having magnetic filler beneath an MTJ. The bottom contact metal filler is made of a ferromagnetic material and applies a magnetic field to the MTJ. Changing the size of the magnetic filler also changes the magnetic bias applied to each MTJ, thereby biasing each cell differently. This results in each MRAM cell having a different write / read voltage for programming the MRAM cell.

[0065] The MRAM cell 700 can be broadly similar to the one about Figure 5 The MRAM cell 700 discussed herein. Specifically, each MRAM cell 700 includes a top contact 702, a hard mask 704, an MTJ 706, a diffusion barrier 708, and a bottom contact 610. Each of these components can interact with... Figure 5 The corresponding components are substantially similar or identical. For example, in some embodiments, MTJ 706 includes the same sub-components and their arrangement as MTJ 506 discussed above.

[0066] However, it is noteworthy that, unlike MRAM cell 500, MRAM cell 700 may not have a different magnetic liner. Instead, the entire bottom contact 710 may be made of a ferromagnetic material. In some embodiments, the ferromagnetic material used in the bottom contact 710 may form the body of the bottom contact 710, and may also contain some other metals (e.g., for conductivity).

[0067] MRAM cells 700 can be hardware biased by changing the critical dimensions (e.g., size or area) of the bottom contact 710. For example, a first MRAM cell 700A may have a first bias condition based on its relatively large bottom contact 710. Thus, the first MRAM cell 700A can be biased to make it relatively easy to write to a high state (e.g., 1). Meanwhile, a third MRAM cell 700C with the smallest bottom contact 710 may be the MRAM cell 700 that is easiest to write to a low state (e.g., write to 0), while a second MRAM cell 700B with a critical dimension somewhere between the first MRAM cell 700A and the third MRAM cell 700C may fall somewhere between the other two. In other words, the second MRAM cell 700B may be easier to write low but harder to write high than the first MRAM cell 700A, and easier to write high but harder to write low than the third MRAM cell 700C.

[0068] See now Figure 8 This illustration depicts the effect of different bottom contact dimensions on the programming voltage of an MRAM cell 800, illustrating a first example MRAM cell structure according to an embodiment of the present disclosure. The MRAM cell 800 may be generally similar to... Figure 5 The MRAM cell 500 shown is or is related to Figure 5 The MRAM cell 500 shown is identical. Specifically, each MRAM cell 800 includes a top contact 802, a hard mask 804, an MTJ 806, a diffusion barrier 808, a bottom contact 810, and a magnetic liner 812. Each of these components can be coupled with... Figure 5 The corresponding components are substantially similar or identical. For example, in some embodiments, the MTJ806 includes the same sub-components and their arrangement as the MTJ 506 discussed above.

[0069] Each MRAM cell 800 has a corresponding graph illustrating how easy it is to write the MRAM cell 800 to a low state and a high state. For example, a first graph 850A shows the voltages required to write the first MRAM cell 800A to high and low, a second graph 850B shows the voltages required to write the second MRAM cell 800B to high and low, and a third graph 850C shows the voltages required to write the third MRAM cell 800C to high and low.

[0070] As shown in the first pattern 850, the large magnetic pad 812 of the first MRAM cell 800A relative to the second MRAM cell 800B shifts the voltage curve to the left. This makes it easier to write the first MRAM cell 800A to a high state. Similarly, the small magnetic pad 812 of the third MRAM cell 800C relative to the second MRAM cell 800B shifts the voltage curve in the third pattern 850C to the right, resulting in an MRAM cell 800C biased towards a low state. These changes are a result of the bias field applied to the MTJ by the magnetic pad 812. Therefore, adjusting the size of the magnetic pad 812 can be used to adjust the voltage bias of the MRAM cell 800, with or without a corresponding change in the bottom contact 810.

[0071] See now Figure 9 The illustration shows the magnetic field lines 925 of an MRAM cell 900 according to an embodiment of the present disclosure. The MRAM cell 900 has an external magnetic underlayer (EMU) liner 912 on a bottom contact 910. The MRAM cell 900 may be generally similar to Figure 5 The MRAM cell 500 shown is or is related to Figure 5 The MRAM cell 500 shown is identical. Specifically, the MRAM cell 900 includes a top contact 902, a hard mask 904, an MTJ 906, a barrier 908 (also known as a diffusion barrier), a bottom contact 910, and a magnetic liner 912. Each of these components can be coupled with... Figure 5 The corresponding components are substantially similar or identical. For example, in some embodiments, MTJ 906 includes the same sub-components and their arrangement as MTJ 506 discussed above.

[0072] As shown in magnetic field diagrams 920 and 950, the magnetic layers in the stack are affected by the magnetic dipole interactions between the layers. In particular, the fields of the free layer and / or the reference layer are influenced by the external magnetic sublayer.

[0073] The first magnetic field diagram 920 shows magnetic field lines 925 when the magnetic liner 912 is magnetized such that the magnetic poles are on the inner side (e.g., negative pole) and outer side (e.g., positive pole) of the liner 912. Figure 9 As shown, in this case, the magnetic field 925 exits from the pin of the magnetic liner 912, passes through the MTJ 906, and returns to the same pin of the magnetic liner 912. The field alignment direction is upward (i.e., towards the MTJ 906), and the net field influence 930 of the EMU is opposite to the alignment direction (i.e., downward, away from the MTJ 906). The magnetic field strength (Hdipole) of the dipole is approximately 10-1000 Oersted (Oe). Therefore, the thickness dl of the diffusion barrier 908 needs to be less than approximately 10 nm.

[0074] Conversely, the second magnetic field diagram 950 shows magnetic field lines 925 when the magnetic liner 912 is magnetized such that the magnetic poles are on the left and right sides of the liner 912. In other words, each vertical pin of the liner 912 is a different pole, with the left pin being the positive pole and the right pin being the negative pole. Figure 9 As shown, the effect of this dipole arrangement is that the magnetic field lines 925 move from one magnetic pole (i.e., left, positive) to the other magnetic pole (i.e., right, negative). This results in the net field influence 930 of the EMU being perpendicular to the field alignment direction (e.g., in this case, the net field influence 930 is to the right). Again assuming the magnetic field strength (Hdipole) of the dipole is approximately 10-1000 Oersted (Oe), the thickness d2 of the diffusion barrier 908 needs to be less than approximately 5 times the thickness of the liner 912.

[0075] See now Figure 10 The diagram illustrates a magnetic field line 1025 of an MRAM cell 1000 having EMU filling for a bottom contact 1012, according to an embodiment of the present disclosure. The MRAM cell 1000 may be substantially similar to... Figure 7 The MRAM cell 700 shown is or is related to Figure 7 The MRAM cell 700 shown is identical. Specifically, the MRAM cell 1000 includes a top contact 1002, a hard mask 1004, an MTJ 1006, a diffusion barrier 1008, and a bottom contact 1010. Each of these components can be coupled with... Figure 7 The corresponding components are substantially similar or identical. For example, in some embodiments, MTJ 1006 includes the same sub-components and their arrangement as MTJ 706 discussed above.

[0076] As shown in magnetic field diagrams 1020 and 1050, the magnetic layers in the stack are affected by the magnetic dipole interactions between the layers. In particular, the field of the free layer and / or the reference layer is affected by the external magnetic underlayer (e.g., a bottom contact with magnetic filling).

[0077] The first magnetic field diagram 1020 shows magnetic field lines 1025 when the magnetic bottom contact 1010 is magnetized such that the magnetic poles are at the bottom (e.g., negative pole) and top (e.g., positive pole) of the bottom contact 1010. Figure 10 As shown, in this case, the magnetic field 1025 exits from the top of the bottom contact 1010, passes through the MTJ 1006, and returns to the bottom of the bottom contact 1010. The field alignment direction rises (i.e., towards the MTJ 1006), and the net field influence 930 of the EMU is also in the same direction as the alignment direction (i.e., upward, towards the MTJ 1006). The magnetic field strength of the dipole (H) dipoleThe value is approximately 10-1000 Oersted (Oe). Therefore, the thickness d3 of the diffusion barrier 1008 needs to be approximately 5 times less than the thickness of the magnetic filler of the bottom contact.

[0078] Conversely, the second magnetic field diagram 1050 shows magnetic field lines 1025 when the magnetic bottom contact 1010 is magnetized such that the magnetic poles are on the left and right sides of the bottom contact. In other words, each horizontal side of the bottom contact 1010 has a different pole, with the left side being positive and the right side being negative. Figure 10 As shown, the effect of this dipole arrangement is that the magnetic field lines 1025 move from one pole (i.e., the left, positive side) to the other pole (i.e., the right, negative side). This results in the net field influence 1030 of the EMU being perpendicular to the field alignment direction (e.g., in this case, the net field influence 1030 is to the right). Again, assuming the magnetic field strength (H) of the dipole... dipole The diffusion barrier is approximately 10-1000 Oersted (Oe), and the thickness d4 of the diffusion barrier 1008 needs to be less than about 5 times the critical size of the bottom contact.

[0079] See now Figure 11A Figure 1100 shows experimental results illustrating that the addition of a Co dielectric adhesion layer (DAL) does not alter the effective vertical anisotropic field of the free layer in an MTJ element, according to embodiments of the present disclosure. In Figure 1100, a Co DAL is added to the MTJ in the stack shown in box 1102, while the stack shown in box 1104 includes a non-magnetic liner. As can be seen from Figure 1100, including the Co DAL does not alter the field strength of the vertical anisotropic field (H_C) of the free layer, compared to those with only a non-magnetic liner.

[0080] See now Figure 11B Figure 1110 illustrates experimental results showing that adding CoDAL reduces the stray magnetic field from the fixed layer to the free layer in an MTJ element to approximately zero, according to embodiments of the present disclosure. In Figure 1110, CoDAL is added to the MTJ in the stack shown in box 1112, while the stack shown in box 1114 includes a non-magnetic liner. As can be seen from Figure 1100, including CoDAL significantly reduces the strength of the stray magnetic field (H_cpl) compared to those with only a non-magnetic liner.

[0081] As from Figure 11A and 11B As can be seen, including the magnetic liner, in this example Co DAL, has the desired effect of reducing stray magnetic fields without reducing the strength of the effective perpendicular anisotropic field.

[0082] See now Figure 12A flowchart of an example method 1200 for selectively biasing an array of MRAM cells according to embodiments of the present disclosure is shown. One or more operations of method 1200 may be performed automatically by a computer system. Therefore, at least a portion of method 1200 may be implemented in software, hardware, firmware, or any combination thereof. The method begins at operation 1202, wherein a set of MRAM cells to be biased is determined.

[0083] As disclosed herein, the MRAM cells to be biased can be determined based on the intended application or use of the resulting MRAM device. For example, if the MRAM device will be used to store an AI model, some of the MRAM cells can be hardware biased to pre-bias the AI ​​model stored therein. For instance, if one or more nodes in the AI ​​model will be biased, the corresponding MRAM cell (i.e., the cell that will store the data (e.g., its weights) of the biased node) can be determined at operation 1202. Similarly, if the MRAM device will store a security key, individual MRAM cells can be selectively biased based on what value or portion of the security key will be contained in the individual MRAM cell.

[0084] At operation 1204, the bias condition for each MRAM cell in the group of MRAM cells is determined. In some embodiments, only MRAM cells that will be hardware biased are considered to have a bias condition. In other embodiments, all MRAM cells (including those that will be normally manufactured) are considered to have a bias condition. In some embodiments, the bias condition for each MRAM cell can be determined or selected from a predetermined list based on the intended use of the MRAM device (e.g., automatically by the processor). For example, if the MRAM device is to contain an AI model, there can be multiple bias nodes in the AI ​​model. However, each bias node may not be biased in the same way. For example, some bias nodes may be biased high (i.e., more likely a larger number), while other nodes may be biased low (i.e., less likely a smaller number). Thus, some of the corresponding MRAM cells may be biased in one direction (e.g., low), while other MRAM cells may be biased in another direction (e.g., high).

[0085] In some embodiments, determining the bias conditions of MRAM cells includes grouping the MRAM cells into multiple subsets. Each subset may correspond to a specific bias condition. For example, a first subset of MRAM cells may contain those cells that will be biased toward a high value, while a second subset of MRAM cells may contain those cells that will be biased toward a low value.

[0086] At operation 1206, the structure type of the MRAM cell is determined. The structure type corresponds to the physical structure of the MRAM cell and how the MRAM cell is tuned (e.g., which parts of the MRAM cell are changed to bias it). For example, a first structure type may include an MTJ stack on top of a bottom contact including a liner. In this structure type, the MRAM cell can be tuned by changing the size of the bottom contact and the magnetic liner, by changing only the size (e.g., thickness) of the magnetic liner, or by changing the size of the entire MTJ stack and the bottom contact / liner. A second structure type may include an MTJ stack on top of a bottom contact that is substantially made of magnetic material (e.g., has a magnetic material filler). As above, the MRAM cell having the second structure type can be tuned (e.g., selectively biased) by changing the size of the magnetic bottom contact (with or without a corresponding change in the size of the MTJ).

[0087] At operation 1208, one or more physical properties (e.g., critical dimensions) of each MRAM cell to be manufactured are determined. These physical properties may be based on the bias conditions and structural type of the MRAM cell. One or more physical properties may correspond to different portions of the MRAM cell under different bias conditions. For example, in embodiments dependent on a magnetic liner, one or more physical properties may include the thickness of the magnetic liner and the bottom contact. In this example, and as... Figure 8 As shown, an MRAM cell to be biased high can have a larger thickness than an MRAM cell to be biased low.

[0088] In operation 1210, an MRAM device is manufactured. Manufacturing the MRAM device may involve forming MRAM cells with different critical dimensions using known manufacturing methods and processes based on corresponding bias conditions. After manufacturing the MRAM device, method 1200 ends.

[0089] See now Figure 13 This diagram illustrates a high-level block diagram of an example computer system 1301 that can be used to implement one or more and any associated functions of the methods, tools, and modules described herein (e.g., using one or more processor circuits of a computer or a computer processor) according to embodiments of the present disclosure. In some embodiments, the main components of the computer system 1301 may include one or more CPUs 1302, a memory subsystem 1304, a terminal interface 1312, a storage interface 1316, an I / O (input / output) device interface 1314, and a network interface 1318, all of which may be directly or indirectly communicatively coupled to enable inter-component communication via a memory bus 1303, an I / O bus 1308, and an I / O bus interface unit 1310.

[0090] Computer system 1301 may include one or more general-purpose programmable central processing units (CPUs) 1302A, 1302B, 1302C, and 1302D, collectively referred to herein as CPU 1302. In some embodiments, computer system 1301 may include multiple processors typical of a relatively large system; however, in other embodiments, computer system 1301 may alternatively be a single CPU system. Each CPU 1302 may execute instructions stored in memory subsystem 1304 and may include one or more levels of on-board cache.

[0091] System memory 1304 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1322 or cache memory 1324. Computer system 1301 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1326 may be provided for reading from and writing to non-removable, non-volatile magnetic media (such as a "hard disk drive"). Although not shown, a disk drive may be provided for reading from or writing to a removable non-volatile disk (e.g., a "floppy disk"), or an optical disk drive may be provided for reading from or writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical media). Additionally, memory 1304 may include flash memory, such as a flash memory stick drive or a flash drive. The memory device may be connected to memory bus 1303 via one or more data media interfaces. Memory 1304 may include at least one program product having a set (e.g., at least one) of program modules configured to perform functions of different embodiments.

[0092] One or more programs / utilities 1328, each having at least one set of program modules 1330, may be stored in memory 1304. Programs / utilities 1328 may include a management program (also known as a virtual machine monitor), one or more operating systems, one or more applications, other program modules, and program data. Each or some combination of the operating system, one or more applications, other program modules, and program data may include an implementation of a network environment. Program modules 1330 generally perform functions or methods of different embodiments.

[0093] Although the memory bus 1303 is Figure 13While shown as a single bus structure providing a direct communication path between CPU 1302, memory subsystem 1304, and I / O bus interface 1310, in some embodiments, memory bus 1303 may include multiple different buses or communication paths, which may be arranged in any of a variety of forms, such as point-to-point links in hierarchical, star, or network configurations, multiple hierarchical buses, parallel and redundant paths, or any other suitable type of configuration. Furthermore, although I / O bus interface 1310 and I / O bus 1308 are shown as a single corresponding unit, in some embodiments, computer system 1301 may include multiple I / O bus interface units 1310, multiple I / O buses 1308, or both. Further, although multiple I / O interface units separating I / O bus 1308 from different communication paths running to different I / O devices are shown, in other embodiments, some or all I / O devices may be directly connected to one or more system I / O buses.

[0094] In some embodiments, computer system 1301 may be a multi-user mainframe computer system, a single-user system, a server computer, or a similar device that has little or no direct user interface but receives requests from other computer systems (clients). Further, in some embodiments, computer system 1301 may be implemented as a desktop computer, portable computer, laptop or notebook computer, tablet computer, pocket computer, telephone, smartphone, network switch or router, or any other suitable type of electronic device.

[0095] It is important to note that Figure 13 This description aims to depict representative major components of an exemplary computer system 1301. However, in some embodiments, individual components may have more... Figure 13 The greater or lesser complexity represented in the text can exist differently from... Figure 13 Those components shown or excluding Figure 13 Components other than those shown, and the number, type, and configuration of such components may vary. Furthermore, modules are listed and described illustratively according to embodiments and do not imply the necessity of a particular module or the exclusivity of other potential modules (or functions / purposes applied to a particular module).

[0096] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0097] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0099] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information from the computer-readable program instructions in order to perform aspects of this invention.

[0100] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0101] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0102] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the figures. For example, two blocks shown consecutively may actually be completed as a single step, executed simultaneously, substantially simultaneously, or with partial or complete temporal overlap, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0104] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “includes” and / or “including” are used in this specification, they specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. In the preceding detailed description of exemplary embodiments of the various embodiments, reference has been made to the accompanying drawings (in which like numerals denote like elements), which form a part of the description and illustrate specific exemplary embodiments in which the various embodiments may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, but other embodiments may be used and logical, mechanical, electrical, and other changes may be made without departing from the scope of the different embodiments. In the preceding description, numerous specific details have been set forth to provide a thorough understanding of the various embodiments. However, the various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the embodiments.

[0105] As used in this article, when referring to a project as “multiple,” it means one or more projects. For example, “multiple different types of networks” means one or more different types of networks.

[0106] When different reference numbers include a common number followed by different letters (e.g., 100a, 100b, 100c) or punctuation followed by different numbers (e.g., 100-1, 100-2, or 100.1, 100.2), the reference character without a letter or a following number (e.g., 100) may refer to the group of elements as a whole, any subset of that group, or an example sample of that group.

[0107] Furthermore, when used with a series of items, the phrase "at least one" indicates that different combinations of one or more of the listed items can be used, and only one item from each of the listed items may be required. In other words, "at least one" means that any combination of items and multiple items from the list can be used, but not all items from the list. Items can be specific objects, things, or categories.

[0108] For example, but not limited to, "at least one of Item A, Item B, or Item C" can include Item A, Item A and Item B, or Item B. The example could also include Item A, Item B, and Item C, or Item B and Item C. Of course, any combination of these items can exist. In some illustrative examples, "at least one" can be, for example, but not limited to, two of Item A; one of Item B; and ten of Item C; four of Item B and seven of Item C; or other suitable combinations.

[0109] In the foregoing, reference has been made to various embodiments. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the features and elements described is contemplated for implementation and practice of this disclosure, regardless of whether they are associated with different embodiments. Many modifications, alterations, and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit this disclosure. Therefore, the described aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly stated in the claims. Moreover, the following claims are intended to be construed as covering all such changes and modifications falling within the true spirit and scope of the invention.

[0110] Example implementation:

[0111] The following provides a non-limiting enumeration of exemplary embodiments to illustrate some aspects of this disclosure.

[0112] Example embodiment 1 is a magnetoresistive random access memory (MRAM) cell. The MRAM cell includes a top contact, a hard mask layer below the top contact, a magnetic tunnel junction (MTJ) below the hard mask layer, a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner disposed around the bottom contact.

[0113] Example embodiment 2 includes the MRAM cell of example embodiment 1, with or without optional features. In this example embodiment, the size of the bottom contact and magnetic liner of the MRAM cell is based on the required bias conditions of the MRAM cell.

[0114] Example embodiment 3 includes an MRAM cell from any of the example embodiments 1 to 2, with or without optional features. In this exemplary embodiment, the sizes of the MTJ, bottom contact, and magnetic liner of the MRAM cell are stacked based on the desired bias conditions of the MRAM cells.

[0115] Example embodiment 4 includes an MRAM cell from any of Example embodiments 1 to 3, including or excluding optional features. In this example embodiment, the MRAM cell is part of a memory array comprising a plurality of MRAM cells. The plurality of MRAM cells includes a first group of MRAM cells having a bottom contact and a magnetic liner with a first critical size, and a second group of MRAM cells having a bottom contact and a magnetic liner with a second critical size. Optionally, the first and second critical sizes are different.

[0116] Example embodiment 5 includes an MRAM cell from any of example embodiments 1 to 4, with or without optional features. In this exemplary embodiment, the MTJ includes a free layer, a reference layer, and a tunnel barrier disposed between the free layer and the reference layer. Optionally, the tunnel barrier is an MgO layer.

[0117] Example embodiment 6 is a magnetoresistive random access memory (MRAM) cell. The MRAM cell includes a top contact, a hard mask layer below the top contact, a magnetic tunnel junction (MTJ) below the hard mask layer, a diffusion barrier below the MTJ, and a bottom contact below the diffusion barrier. The bottom contact includes a ferromagnetic material filler.

[0118] Example embodiment 7 includes the MRAM cell of example embodiment 6, with or without optional features. In this exemplary embodiment, the sizes of the MTJ and the bottom contact are based on the bias conditions of the MRAM cell.

[0119] Example embodiment 8 includes an MRAM cell from any of example embodiments 6 to 7, including or excluding optional features. In this example embodiment, the MRAM cell is part of a memory array comprising a plurality of MRAM cells. The plurality of MRAM cells includes a first group of MRAM cells having a bottom contact and a magnetic liner with a first critical dimension, and a second group of MRAM cells having a bottom contact and a magnetic liner with a second critical dimension. Optionally, the first and second critical dimensions are different.

[0120] Example embodiment 9 includes an MRAM cell of any one of Example embodiments 6 to 8, with or without optional features. In this exemplary embodiment, the MTJ includes a free layer, a reference layer, and a tunneling barrier disposed between the free layer and the reference layer. Optionally, the tunneling barrier is an MgO layer.

[0121] Example embodiment 10 is a method of forming a magnetoresistive random access memory (MRAM) device, wherein individual MRAM cells are selectively biased. The method includes determining a set of MRAM cells in a memory array to be hardware biased. The method further includes determining bias conditions for each MRAM cell in the set of MRAM cells. The method further includes determining a critical size for each MRAM cell in the set of MRAM cells based on the bias conditions of the MRAM cell and the structure type of the MRAM cell. The method further includes fabricating the memory array using the determined critical size of each MRAM cell in the set of MRAM cells.

[0122] Example embodiment 11 includes the method of example embodiment 10, with or without optional features. In this example embodiment, the set of MRAM cells to be hardware biased is determined based on the intended use of the MRAM device. Optionally, the intended use of the MRAM device is selected from the group consisting of: memory for artificial intelligence (AI) models and memory containing security keys.

[0123] Example embodiment 12 includes the method of any one of example embodiments 10 to 11, with or without optional features. In this example embodiment, determining the bias conditions of the set of MRAM cells includes dividing the set of MRAM cells into multiple subsets. Each subset contains MRAM cells with specific bias conditions.

[0124] Example embodiment 13 includes the method of any one of Examples 10 to 12, with or without optional features. In this example embodiment, manufacturing an MRAM device includes forming a top contact for each MRAM cell in the MRAM device. Manufacturing an MRAM device further includes forming a hard mask below the top contact. Manufacturing an MRAM device further includes forming an MTJ below the hard mask. Manufacturing an MRAM device further includes forming a diffusion barrier below the MTJ. Manufacturing an MRAM device further includes forming a bottom contact below the diffusion barrier. Manufacturing an MRAM device further includes forming a magnetic liner around the bottom contact. The size of the bottom contact and magnetic liner for each respective MRAM cell is based on the bias conditions of the respective MRAM cell.

[0125] Example embodiment 14 includes the method of any one of Example embodiments 10 to 13, including or excluding optional features. In this example embodiment, manufacturing an MRAM apparatus includes forming a top contact for each MRAM cell in the MRAM apparatus. Manufacturing an MRAM apparatus further includes forming a hard mask below the top contact. Manufacturing an MRAM apparatus further includes forming an MTJ below the hard mask. Manufacturing an MRAM apparatus further includes forming a diffusion barrier below the MTJ. Manufacturing an MRAM apparatus further includes forming a bottom contact below the diffusion barrier. Manufacturing an MRAM apparatus further includes forming a magnetic liner around the bottom contact. The size of the MTJ, bottom contact, and magnetic liner for each respective MRAM cell is based on the bias conditions of the respective MRAM cell.

[0126] Example embodiment 15 includes the method of any one of Example embodiments 10 to 14, including or excluding optional features. In this example embodiment, manufacturing an MRAM device includes forming a top contact for each MRAM cell in the MRAM device. Manufacturing an MRAM device further includes forming a hard mask below the top contact. Manufacturing an MRAM device further includes forming an MTJ below the hard mask. Manufacturing an MRAM device further includes forming a diffusion barrier below the MTJ. Manufacturing an MRAM device further includes forming a bottom contact below the diffusion barrier, wherein the bottom contact is at least substantially made of a ferromagnetic material. The size of the MTJ and the bottom contact for each respective MRAM cell is based on the bias conditions of the respective MRAM cell.

Claims

1. A magnetoresistive random access memory (MRAM) cell, the MRAM cell comprising: Top contact element; The hard mask layer beneath the top contact element; The magnetic tunnel junction (MTJ) beneath the hard mask layer; The diffusion barrier beneath the MTJ; The bottom contact below the diffusion barrier; as well as A magnetic liner is arranged around at least a portion of the bottom contact element. The MRAM cell is part of a memory array comprising multiple MRAM cells, including a first group of MRAM cells having a bottom contact and a magnetic liner with a first critical size, and a second group of MRAM cells having a bottom contact and a magnetic liner with a second critical size different from the first critical size.

2. The MRAM cell of claim 1, wherein the size of the bottom contact and the magnetic liner of the MRAM cell is based on the required bias conditions of the MRAM cell, wherein the bias conditions are the type or level of hardware bias of the MRAM cell.

3. The MRAM cell of claim 1, wherein the size of the MTJ, bottom contact and magnetic liner of the MRAM cell is based on the required bias conditions of the MRAM cell, wherein the bias conditions are the type or level of hardware bias of the MRAM cell.

4. The MRAM cell according to claim 1, wherein, The MTJ includes: Free layer; Reference layer; and A tunnel barrier is disposed between the free layer and the reference layer.

5. The MRAM cell according to claim 4, wherein, The tunnel barrier is a MgO layer.

6. A magnetoresistive random access memory (MRAM) cell, the MRAM cell comprising: Top contact element; The hard mask layer beneath the top contact element; The magnetic tunnel junction (MTJ) beneath the hard mask layer; The diffusion barrier beneath the MTJ; The bottom contact below the diffusion barrier includes a ferromagnetic material filler. A magnetic liner is arranged around at least a portion of the bottom contact element. The MRAM cell is part of a memory array comprising multiple MRAM cells, including a first group of MRAM cells having a bottom contact and a magnetic liner with a first critical size, and a second group of MRAM cells having a bottom contact and a magnetic liner with a second critical size different from the first critical size.

7. The MRAM cell of claim 6, wherein the size of the MTJ and the bottom contact is based on the bias conditions of the MRAM cell, wherein the bias conditions are the type or level of hardware bias of the MRAM cell.

8. The MRAM cell according to claim 6, wherein, The MTJ includes: Free layer; Reference layer; and A tunnel barrier is disposed between the free layer and the reference layer.

9. The MRAM cell according to claim 8, wherein, The tunnel barrier is a MgO layer.

10. A method for forming a magnetoresistive random access memory (MRAM) device, wherein, Each MRAM cell is selectively biased, the method comprising: Identify a set of MRAM cells in the memory array to be hardware biased; For each MRAM cell in the set of MRAM cells, determine the bias condition; For each MRAM cell in the set of MRAM cells, a critical size is determined based on the bias condition of the MRAM cell and the structure type of the MRAM cell, wherein the bias condition is the type or level of hardware bias of the MRAM cell; and The MRAM device is manufactured using a defined critical size for each MRAM cell in the set of MRAM cells, wherein manufacturing the MRAM device comprises: A top contact is formed for each MRAM cell in the MRAM device; A hard mask is formed below the top contact element; An MTJ is formed beneath the hard mask; A diffusion barrier is formed below the MTJ; A bottom contact is formed below the diffusion barrier; and A magnetic liner is formed around the bottom contact element. The MRAM cell is part of a memory array comprising multiple MRAM cells, including a first group of MRAM cells having a bottom contact and a magnetic liner with a first critical size, and a second group of MRAM cells having a bottom contact and a magnetic liner with a second critical size different from the first critical size.

11. The method according to claim 10, wherein, The set of MRAM cells to be hardware biased is determined based on the intended use of the MRAM device.

12. The method according to claim 11, wherein, The intended use of the MRAM device is selected from the group consisting of memory for artificial intelligence (AI) models and memory containing security keys.

13. The method of claim 10, wherein determining the bias conditions of the set of MRAM cells comprises: The group of MRAM cells is divided into multiple subsets, each subset including MRAM cells with specific bias conditions.

14. The method of claim 10, wherein the size of the bottom contact and magnetic liner of each respective MRAM cell is based on the bias conditions of the respective MRAM cell.

15. The method of claim 10, wherein the size of the MTJ, bottom contact, and magnetic liner of each respective MRAM cell is based on the bias conditions of the respective MRAM cell.

16. The method of claim 10, wherein, The bottom contact element is at least substantially made of a ferromagnetic material, and The size of the MTJ and bottom contact of each corresponding MRAM cell is based on the bias conditions of the corresponding MRAM cell.

Images