Method for writing mapping relationship applied to memory and memory

Abstract

A method for writing mapping relationship applied to a memory and the memory are disclosed. The method comprises: obtaining a first linked list corresponding to a first logical address set to which a first logical address in the mapping relationship to be written belongs from a first mapping table in a cache unit according to the first logical address; updating a first logical address range in a case that the first logical address is continuous with a first logical address range stored in a first node in the first linked list and a first physical address in the mapping relationship to be written is continuous with a first physical address range stored in the first node in the first linked list; and releasing a second node in the first linked list in a case that an updated first logical address range covers a second logical address range stored in the second node in the first linked list. The method can timely determine an invalid node in an L2P mapping table and release the invalid node, thereby reducing a cache space occupied by the L2P mapping table.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method for writing mapping relationships in a memory and a memory. Background Technology

[0002] Solid-state drives (SSDs) are storage hard drives made using solid-state electronic storage chips. A storage hard drive includes a controller and storage media. Currently, the most common SSDs use flash memory as the storage medium to store data, such as non-volatile memory like NAND flash.

[0003] Solid-state drives (SSDs) are widely used in various applications. When writing data to an SSD, a mapping table from the Flash Translation Layer (FTL) is required to record the mapping relationship between the host logical space address and the physical address of the flash storage medium. Therefore, SSDs not only store the data written by the user, but also the mapping table that maintains the mapping relationship of the written data.

[0004] Currently, mainstream solid-state drives (SSDs) generally have two hardware designs: one with DRAM as a cache unit, and the other without DRAM (called DRAM-Less SSDs). Because DRAM-Less SSDs have limited cache unit capacity, they typically use a two-level mapping table to store the mapping relationship between host logical space addresses and physical addresses on the storage medium. During write operations, the second-level mapping table is first written to the cache unit, and then flushed to the storage medium when conditions are met. During read operations, the second-level mapping table in the cache unit is first searched; if the corresponding data cannot be found, the required second-level mapping table is loaded from the storage medium into the cache unit. Therefore, the write design of the second-level mapping table also affects subsequent read performance. Summary of the Invention

[0005] The purpose of this invention is to provide a writing method and memory for mapping relationships, which improves the read and write performance of the host through mapping table design and management.

[0006] According to a first aspect of the present invention, a method for writing a mapping relationship applied to a memory is provided, the method comprising:

[0007] Based on the first logical address in the mapping relationship to be written, the first linked list corresponding to the first logical address set to which the first logical address belongs is obtained from the first-level mapping table in the cache unit. The first-level mapping table includes the correspondence between the index addresses of N logical address sets and N linked lists. The N linked lists are stored in the write cache area in the cache unit, where N is a positive integer.

[0008] If the first logical address is continuous with the first logical address range stored in the first node of the first linked list, and the first physical address in the mapping relationship to be written is continuous with the first physical address range stored in the first node of the first linked list, then update the first logical address range; and

[0009] If the updated first logical address range covers the second logical address range stored in the second node of the first linked list, then release the second node in the first linked list.

[0010] In some embodiments, after updating the first logical address range, the method further includes:

[0011] If the first logical address and the previously written third logical address do not belong to the same linked list, the invalid node in the second linked list corresponding to the second logical address set to which the third logical address belongs is released. The range of logical addresses stored in the invalid node is a subset of the range of logical addresses stored in the preceding node, and the preceding node is in the second linked list and is located before the invalid node.

[0012] In some embodiments, releasing the invalid node in the second linked list corresponding to the second logical address set to which the third logical address belongs includes:

[0013] Traverse the second linked list;

[0014] If the logical address range stored by the current node traversed in the second linked list covers the logical address range stored by the subsequent nodes of the current node, the subsequent nodes of the current node are treated as invalid nodes and released.

[0015] In some embodiments, if the first logical address is not contiguous with the range of the first logical address stored in the first node of the first linked list, and / or the first physical address in the mapping relationship to be written is not contiguous with the range of the first physical address stored in the first node of the first linked list, then a new empty node is requested from the cache unit, and the mapping relationship to be written is written into the new empty node.

[0016] In some embodiments, each node in the first linked list uses a starting logical address, a starting physical address, and a count value to store a correspondence between a logical address range and a physical address range.

[0017] In some embodiments, it is determined whether the first logical address and the range of the first logical address are continuous by the following method:

[0018] Determine whether the first logical address is equal to the sum of the starting logical address in the first node, the count value, and 1. If yes, then it is continuous; otherwise, it is not continuous.

[0019] The determination of whether the first physical address is continuous with the range of the first physical address is made in the following way:

[0020] Determine whether the first physical address is equal to the sum of the starting physical address in the first node, the count value, and 1. If yes, then it is continuous; otherwise, it is not continuous.

[0021] In some embodiments, the number of nodes that the cache unit can apply for is limited, and the writing method further includes: when the number of nodes applied for in the cache unit is greater than a first threshold, refreshing the data of each linked list to the storage medium.

[0022] In some embodiments, the writing method further includes: if a null pointer is obtained from the first-level mapping table based on the first logical address in the mapping relationship to be written, then a new null node is requested from the cache unit, and the mapping relationship to be written is written into the new null node, and the null pointer is modified to point to the new null node.

[0023] According to a second aspect of the present invention, a controller for a memory is provided, coupled to an external storage medium, the controller further comprising a cache unit, the controller performing the write method described in any of the preceding claims.

[0024] According to a third aspect of the present invention, a memory is provided, comprising:

[0025] Coupled controller and storage medium;

[0026] The controller further includes a cache unit, and the controller is used to execute the write method described in any of the preceding claims.

[0027] In some embodiments, the storage medium is a flash memory chip.

[0028] The mapping table writing method provided in this disclosure promptly identifies and releases invalid nodes occupied by the L2P mapping table, thereby reducing the cache space occupied by the L2P mapping table. This approach helps improve the read and write performance of sequential read and write operations. Furthermore, by using a counter value, a single node can store multiple mapping relationship data, allowing the entire cache unit to store more mapping relationships. Attached Figure Description

[0029] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0030] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown;

[0031] Figure 2 This is a block diagram illustrating a two-level mapping table in a DRAM-less solid-state drive;

[0032] Figure 3 A flowchart illustrating a method for writing mapping relationship data to a memory according to an embodiment of this disclosure is shown;

[0033] Figure 4 A flowchart is shown, illustrating another embodiment of the present disclosure, of a method for writing mapping data to a memory. Detailed Implementation

[0034] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0035] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0036] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0038] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown.

[0039] like Figure 1 As shown, the computer system 100 includes a host 110 and a solid-state drive (SSD). The SSD includes a controller 120 and a storage medium 130. The controller 120 is connected to the host 110 and is used to exchange data with the host 110. The controller 120 connects the host 110 and the storage medium 130 and stores the write data of the host 110 into the storage medium 130.

[0040] The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a memory controller 128. The host interface 121 of the control system 120 is connected to the host 110 to transmit data and read / write commands. The processor 123 is connected to the host interface 121, the cache unit 124, and the memory controller 128. The processor 123 parses read / write commands and executes read / write operations. The cache unit 124, for example, is SRAM, used to store a mapping table. The memory controller 128 controls the transmission and storage of write data. The processor 123 also implements the core software layer for memory control, namely the FTL (flash translation layer). The FTL consists of several programs. The processor 123 executes these programs, enabling it to translate read / write commands upon receipt, thereby completing access to the storage medium 130. Therefore, the host 110's file system and operating system can access the storage medium as if it were their own memory. The FTL also features, for example, support for bad block management, wear leveling, garbage collection, power-off recovery, and write balancing technologies.

[0041] Storage medium 130 is, for example, a flash memory chip array. To improve data read and write performance, the memory controller 128 of controller 120 can read and write to the flash memory chips of storage medium 130 via multiple channels (e.g., CH0 and CH2), with each channel connected to a group of flash memory chips.

[0042] Cache unit 124 can use SRAM and / or DRAM. Comparatively, SRAM offers speed advantages as a cache, but it is more expensive and has a smaller storage capacity per unit space. Accordingly, to improve cache space utilization, DRAM-less solid-state drives (SDS) employ a two-level mapping table for address management.

[0043] Figure 2 This is a block diagram illustrating a two-level mapping table in a DRAM-less solid-state drive. For example... Figure 2As shown, cache unit 124 includes a cache area 1241 for storing the first-level mapping table and a write cache area 1242 for storing the second-level mapping table. First, all logical addresses (LAA) are equally divided into (n+1) groups (0 to n). Then, the first-level mapping table can be viewed as an array L1[n] with (n+1) elements (index starting from 0). Array L1[n] stores (n+1) index addresses, which respectively point to multiple second-level mapping tables stored on storage medium 130 (equivalent to the first-level mapping table including the correspondence between the (n+1) logical address set and the index addresses of (n+1) linked lists). Furthermore, since the secondary mapping table is first written to the write buffer 1242 and then flushed to the storage medium 130 during the write operation, before the secondary mapping table is flushed to the storage medium 130, the secondary mapping table is first organized into a linked list, such as linked list 1243, and stored in the write buffer 1242. At this time, the index address of linked list 1243 is added to the corresponding element of array L1[n]. The index address of linked list 1243 is the index address of the first node of linked list 1243. After linked list 1243 is flushed to the storage medium 130, the index address corresponding to the storage medium 130 is also added to the corresponding element of array L1[n].

[0044] As shown in the figure, linked list 1242 consists of one or more nodes. Each node contains an L2P mapping consisting of LAA, PAA, SEQ, and NEXT. LAA represents the starting logical address of at least one mapping stored in the current node; PAA represents the starting physical address of at least one mapping stored in this node; SEQ indicates that there are SEQ consecutive mapping data entries starting from the initial LAA; and NEXT represents the index address pointing to the next node. Because of SEQ, a node can store (SEQ+1) mapping data entries. When a user reads data, controller 120 queries the first-level mapping table. If it finds that the logical address of the data the host wants to read is within the LAA range of a certain node, the physical address corresponding to this logical address can be calculated using the node's LAA, FAA, and SEQ. When a user writes data, the controller 120 generates new mapping data based on the write command. This new mapping data is added to the corresponding linked list. However, if the controller 120 repeatedly writes data to a logical address with an existing mapping, an invalid mapping will occur. For example, if the newly written logical address range according to the user's write command is 99-101, and the previously written logical address range according to the user's write command is 99-100, then the former logical address range (99-101) and the latter logical address range (99-100) overlap. Therefore, the mapping corresponding to the overlapping logical address range in the latter logical address range becomes an invalid mapping. If it is necessary to read multiple invalid nodes containing only invalid mappings before reading the valid mapping, more read time is consumed, thus affecting the system's read performance.

[0045] Figure 3 A flowchart illustrating a method for writing mapping relationships to a memory according to a first embodiment of this disclosure is shown. In this embodiment, the memory uses a two-level mapping table to store the mapping relationships. The second-level mapping table also uses linked lists for storage, and each entry in the first-level mapping table stores the index addresses of multiple linked lists. Each node in each linked list stores the correspondence between logical address ranges and physical address ranges, and stores an index address pointing to the next node. It should be emphasized that although... Figure 2 In this implementation, each node uses a start logical address (LAA), a start physical address (PAA), and a count value to store the correspondence between a logical address range and a physical address range. However, this implementation is not mandatory. For example, a data structure such as start logical address, end logical address, start physical address, and end physical address can be used to store the correspondence between logical address ranges and physical address ranges.

[0046] refer to Figure 3 As shown, the flowchart includes the following steps.

[0047] In step S301, the index address of the first node of the first linked list to which the logical address in the mapping relationship to be written belongs is obtained from the corresponding entry of the first-level mapping table.

[0048] refer to Figure 2 As mentioned above, in its original state, the array space corresponding to the first-level mapping table stores null pointers (NULL). When a mapping relationship to be written is received, it is determined that the logical address in the mapping relationship corresponds to a certain element in the array space, and the index address is retrieved from that element. Then, it is determined whether the index address points to a node (i.e., whether the index address is not a null pointer). If it does, the node it points to is called the first node of the first linked list, and the following steps S302 to S307 are executed. If it is a null pointer, a null node is allocated, the mapping relationship to be written is written to the null node, and the corresponding entry in the first-level mapping table is updated to point to the null node.

[0049] In step S302, data is retrieved from the first node of the first linked list, and the logical address range and physical address range of the first node of the first linked list are determined based on the data.

[0050] In step S303, it is determined whether the logical address range of the mapping relationship to be written is continuous with the logical address range of the first node of the first linked list, and whether the physical address range of the mapping relationship to be written is continuous with the physical address range of the first node of the first linked list. If both are continuous, step S304 is executed; otherwise, step S307 is executed.

[0051] Specifically, it is determined whether the logical address in the mapping relationship to be written is continuous with the logical address range of the first node of the first linked list. This includes: if the logical address in the mapping relationship to be written equals the starting logical address of the first node plus a count value plus 1, then the logical address in the mapping relationship to be written is continuous with the logical address range of the first node; otherwise, they are not continuous. It is also determined whether the physical address in the mapping relationship to be written is continuous with the physical address range of the first node. This includes: if the physical address in the mapping relationship to be written equals the starting physical address of the first node plus a count value plus 1, then the physical address in the mapping relationship to be written is continuous with the physical address range of the first node; otherwise, they are not continuous.

[0052] In step S304, the mapping relationship to be written is written to the first node of the first linked list. Specifically, the count value in the first node is incremented by 1.

[0053] In step S305, it is determined whether the logical address range of the first node of the updated first linked list covers the logical address range stored in the second node of the first linked list. If so, step S306 is executed; otherwise, the program terminates. Specifically, it is determined whether the logical address range stored in the second node is a subset of the logical address range in the updated first node. If so, it is determined to be an overlay. If the logical address range of the first node of the updated first linked list covers the logical address range stored in the second node of the first linked list, step S306 is executed.

[0054] In step S306, the second node of the first linked list is released.

[0055] In step S307, an empty node is requested, the mapping relationship to be written is written to the empty node, the index address stored in the empty node is set to point to the first node of the first linked list, and the corresponding entry of the first-level mapping table is updated to point to the empty node.

[0056] Examples are given for steps S302 to S307.

[0057] Step 1: Assuming the initial state, the first node old_node of the first linked list stores data as LAA=100, PAA=100, SEQ=1, Next=NULL, with LAA ranging from [100, 101]. The first mapping to be written is LAA=100, PAA=200, which is not contiguous with the LAA and PAA stored in old_node. From steps S301, S302, S303, S307 to END, a new node new_node will be allocated, and the mapping to be written will be written into new_node. Finally, new_node stores LAA=100, PAA=200, seq=0, next="index address of old_node", and the index address of old_node that the first-level mapping table originally pointed to is redirected to new_node, but old_node is not released. Thus, when reading LAA=100, the node data is read sequentially from front to back according to the linked list. The mapping relationship of LAA=100 will be found in the new_node first, without needing to read the nodes further, so the reading will not be wrong.

[0058] Step 2: The second mapping to be written is LAA=101, PAA=201, which is contiguous with both LAA and PAA stored in new_node. From steps S301 to S306 and then to END, the data in new_node is first updated to LAA=100, PAA=200, seq=1, next=“index address of old_node”. At this time, the logical address range of old_node [100,101] is covered by the logical address range of new_node [100,101]. All L2P mappings stored in old_node are invalid mappings, so step S305 will jump to S306, that is, old_node is released. The L2P mappings stored in the linked list are: LAA=100, PAA=200, seq=1, next=null.

[0059] Step 3: If the two mapping relationships to be written after Step 1 are: LAA=99 and PAA=300, and LAA=100 and PAA=301, then these two mapping relationships are not contiguous with the LAA and PAA stored in old_node(LAA=100, PAA=100, SEQ=1, Next=NULL). Therefore, through steps S301, S302, S303, S307 to END, a new node new_node1 will be allocated. Finally, new_node1 stores LAA=99, PAA=300, seq=1, and next=“the index address of old_node”. Thus, when reading LAA=99 or 100, the node data is read sequentially from front to back according to the linked list. The mapping relationship is first found in the new_node1 node, eliminating the need to read nodes further, thus preventing errors during the read.

[0060] Step 4: If the mapping relationship to be written after Step 3 is: LAA = 101 and PAA = 302, then refer to the above steps and update this mapping relationship to new_node1. The updated new_node1 becomes: LAA = 99, PAA = 300, seq = 2, next = "index address of old_node", that is, the seq of new_node1 is increased by 1. At this time, the LAA range of new_node1 is: [99, 101], which covers the logical address range of old_node [100, 101], and old_node needs to be released.

[0061] In summary, the mapping table writing method provided in the above embodiments can promptly identify and release nodes occupied by invalid L2P mapping tables, thereby reducing the occupation of nodes by invalid L2P mappings and also reducing the frequency of table flushing due to insufficient node quantity. This method is particularly effective in improving the performance of sequential read and write operations. Moreover, using the counter value SEQ allows a single node to store multiple mapping relationships, enabling the entire cache unit to store more L2P mapping relationships, which can further improve the performance of sequential write and sequential read operations.

[0062] In some embodiments, since the number of nodes that the controller's cache unit can request is limited, when the number of requested nodes is greater than a set first threshold, or the number of remaining requestable nodes is less than a set second threshold, the node data is refreshed to the storage medium. This reduces the occupation of nodes by the L2P mapping table updated when the user performs sequential write operations, thereby reducing the frequency of table flushing due to insufficient number of nodes and improving sequential write performance.

[0063] In summary, by reducing the number of nodes occupied by invalid mappings, read performance in read scenarios can be improved. Furthermore, since the latest mapping is always at the front of the linked list, it can also be guaranteed that the correct mapping is read.

[0064] Figure 4 A flowchart illustrating a method for writing mapping relationships to a memory according to another embodiment of this disclosure is shown. In this embodiment, the memory uses a two-level mapping table to store the mapping relationships. The second-level mapping table also uses linked lists for storage, and each entry in the first-level mapping table stores the index addresses of multiple linked lists. Each node in each linked list stores the correspondence between logical address ranges and physical address ranges, and stores an index address pointing to the next node. It should be emphasized that, although... Figure 2 In this implementation, each node uses a start logical address (LAA), a start physical address (PAA), and a count value to store the correspondence between a logical address range and a physical address range. However, this implementation is not mandatory. For example, a data structure such as start logical address, end logical address, start physical address, and end physical address can be used to store the correspondence between logical address ranges and physical address ranges.

[0065] Referring to the diagram above, the flowchart includes steps S301-S304, S307, S308, and S309. Specifically, steps S301-S304 and S307 can be found in the previous section. Figure 3 The description of the corresponding steps will not be repeated here.

[0066] In step S308, it is determined whether the logical address in the mapping relationship to be written belongs to the same linked list as the logical address written previously. If not, step S309 is executed to perform a node merging operation on the linked list to which the logical address written previously belongs. This reduces the overhead caused by excessively frequent execution of step S306, which could negatively impact firmware code execution efficiency. For the node merging operation in step S309, the following two methods are currently provided:

[0067] The first method: perform a merging operation on the linked list pointed to by the logical page set of the first-level mapping table corresponding to the last updated LAA: traverse the linked list pointed to by the logical page set of the first-level mapping table corresponding to the last updated LAA, and if the LAA range stored in the currently traversed node covers the LAA range of its subsequent nodes, then release its subsequent invalid nodes.

[0068] The second method: Check if the SEQ CNT in the first node reaches the maximum value of the SEQ CNT stored in the node (this maximum value is the maximum value of the LAA range corresponding to an element in L1[n]). If so, all subsequent nodes are invalid nodes, and all subsequent invalid nodes are released directly. The judgment condition of this method is more difficult to achieve than that of the first method, but it does not require traversing all nodes, making it more efficient and with better performance than the first method.

[0069] Will Figure 4 Implementation examples and Figure 3 A comparison of the embodiments reveals that, in the scenario of sequential write operations (i.e., the logical addresses generated by the write command are consecutive), Figure 3 In some implementations, S306 may need to be executed multiple times to release multiple nodes occupied by invalid mappings. Figure 4 The implementation only requires releasing multiple invalid nodes in the same linked list together when writing to different linked lists, reducing the frequency of releasing invalid nodes, and therefore the performance is relatively good.

[0070] It should be understood that sequential write operations are more common on solid-state drives (SSDs) compared to random write operations. Therefore, the core idea of ​​this disclosure is to improve sequential write and read performance by promptly identifying and releasing nodes occupied by invalid L2P mapping tables, thereby improving the overall read and write performance of the SSD. Through random sample experiments, we found that the technical solution provided in the embodiments of this disclosure can improve the overall read performance of the SSD.

[0071] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for writing mapping relationships applied to memory, characterized in that, The method includes: Based on the first logical address in the mapping relationship to be written, the first linked list corresponding to the first logical address set to which the first logical address belongs is obtained from the first-level mapping table in the cache unit. The first-level mapping table includes the correspondence between the index addresses of N logical address sets and N linked lists. The N linked lists are stored in the write cache area in the cache unit, where N is a positive integer. If the first logical address is continuous with the first logical address range stored in the first node of the first linked list, and the first physical address in the mapping relationship to be written is continuous with the first physical address range stored in the first node of the first linked list, then update the first logical address range; and If the updated first logical address range covers the second logical address range stored in the second node of the first linked list, then release the second node in the first linked list.

2. The writing method according to claim 1, characterized in that, After updating the first logical address range, the method further includes: If the first logical address and the previously written third logical address do not belong to the same linked list, the invalid node in the second linked list corresponding to the second logical address set to which the third logical address belongs is released. The range of logical addresses stored in the invalid node is a subset of the range of logical addresses stored in the preceding node, and the preceding node is in the second linked list and is located before the invalid node.

3. The writing method according to claim 2, characterized in that, Releasing the invalid nodes in the second linked list corresponding to the second logical address set to which the third logical address belongs includes: Traverse the second linked list; If the logical address range stored by the current node traversed in the second linked list covers the logical address range stored by the subsequent nodes of the current node, the subsequent nodes of the current node are treated as invalid nodes and released.

4. The writing method according to claim 1, characterized in that, If the first logical address is not contiguous with the range of the first logical address stored in the first node of the first linked list, and / or the first physical address in the mapping relationship to be written is not contiguous with the range of the first physical address stored in the first node of the first linked list, then a new empty node is requested from the cache unit, and the mapping relationship to be written is written into the new empty node.

5. The writing method according to any one of claims 1 to 4, characterized in that, Each node in the first linked list uses a starting logical address, a starting physical address, and a count value to store a correspondence between a logical address range and a physical address range.

6. The writing method according to claim 5, characterized in that, The determination of whether the first logical address is continuous with the first logical address range is made in the following way: Determine whether the first logical address is equal to the sum of the starting logical address in the first node, the count value, and 1. If yes, then it is continuous; otherwise, it is not continuous. The determination of whether the first physical address is continuous with the range of the first physical address is made in the following way: Determine whether the first physical address is equal to the sum of the starting physical address in the first node, the count value, and 1. If yes, then it is continuous; otherwise, it is not continuous.

7. The writing method according to any one of claims 1 to 4, characterized in that, The number of nodes that can be requested by the cache unit is limited, and the writing method further includes: when the number of requested nodes in the cache unit is greater than a first threshold, refreshing the data of each linked list to the storage medium.

8. The writing method according to claim 1, characterized in that, Also includes: If a null pointer is obtained from the first-level mapping table based on the first logical address in the mapping relationship to be written, a new null node is requested from the cache unit, the mapping relationship to be written is written into the new null node, and the null pointer is modified to point to the new null node.

9. A controller for a memory coupled to an external storage medium, the controller further comprising a cache unit, the controller performing a write method as described in any one of 1 to 8.

10. A memory comprising: Coupled controller and storage medium; The controller further includes a cache unit, and the controller is used to execute the write method according to any one of claims 1-8.

11. The memory according to claim 10, wherein the storage medium is a flash memory chip.

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