Semiconductor interconnect reliability structure and method of forming the same

Abstract

A semiconductor interconnect reliability structure and a forming method thereof, the semiconductor interconnect reliability structure comprises: a plurality of metal lines extending along a first direction and arranged in parallel along a second direction, comprising a non-lead area along the first direction, and a first lead area and a second lead area located on both sides of the non-lead area respectively, comprising a first metal line and a second metal line arranged alternately and spaced apart along the second direction; a first partition layer penetrating the first metal line near the second lead area in the non-lead area, each first metal line has a plurality of first partition layers, and the plurality of first partition layers are arranged along the first direction; a second partition layer penetrating the second metal line near the first lead area in the non-lead area, each second metal line has a plurality of second partition layers, and the plurality of second partition layers are arranged along the first direction; a via interconnect structure is located on top of the first metal line in the first lead area and on top of the second metal line in the second lead area respectively. The present application improves the accuracy of test results.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor interconnect reliability structure and a method for forming the same. Background Technology

[0002] In the semiconductor device manufacturing process, reliability testing is frequently required. Especially with the advancement of semiconductor process technology, semiconductor devices are becoming increasingly integrated, and their dimensions are shrinking proportionally. Their critical dimensions (CD) are also becoming smaller. For semiconductor devices with increasingly smaller CDs, the interlayer dielectric (ILD) in the back-end of line (BEOL) process is also becoming thinner, making performance testing of the circuit structure manufactured using BEOL crucial.

[0003] In this field, time-dependent dielectric breakdown (TDDB) testing is commonly used for reliability testing. It can be used to predict the lifespan of semiconductor devices. Typically, a constant voltage is applied to a metal line, causing the device to accumulate voltage; this is what is commonly referred to as TDDB. After a period of time, the dielectric material will break down. The time elapsed from the application of a constant voltage to the point where the dielectric material breaks down is the dielectric lifespan under that condition. Summary of the Invention

[0004] The problem solved by this invention is to provide a semiconductor interconnect reliability structure and its formation method, which improves the accuracy of test results.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor interconnect reliability structure, comprising: multiple metal lines extending along a first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; the metal lines along the first direction including a lead region and a non-lead region; the lead region including a first lead region and a second lead region located on both sides of the non-lead region, both the first and second lead regions being used to load test signals; the metal lines along the second direction including alternating first and second metal lines; and a first partition layer penetrating the first metal line near the second lead region in the non-lead region and used to divide the first metal line in the first direction. Each first metal wire has multiple first partition layers, and the multiple first partition layers are arranged along a first direction; a second partition layer penetrates the second metal wire in the non-lead area near the first lead area and is used to divide the second metal wire in the first direction, each second metal wire has multiple second partition layers, and the multiple second partition layers are arranged along the first direction; a through-hole interconnect structure is located on the top of the first metal wire in the first lead area and the top of the second metal wire in the second lead area, respectively, the through-hole interconnect structure in the first lead area is used as the test signal loading end of the first metal wire, and the through-hole interconnect structure in the second lead area is used as the test signal loading end of the second metal wire.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor interconnect reliability structure, comprising: providing a substrate, on which a first dielectric layer is formed, the first dielectric layer including a non-lead region and a lead region along a first direction, the lead region including a first lead region and a second lead region located on both sides of the non-lead region, the first lead region and the second lead region both being used to load test signals; forming a core layer covering the first dielectric layer; forming a first trench and a second trench extending along the first direction and arranged alternately in parallel along a second direction in the core layer, wherein, in the first direction, the first trench has a plurality of first intervals for dividing the first trench into a plurality of first sub-trenches, the plurality of first intervals being located in the non-lead region near the second lead region, and, in the first direction, the second trench has a plurality of first intervals for dividing the first trench into a plurality of first sub-trenches, the plurality of first intervals being located in the non-lead region near the second lead region, and, in the first direction, the second trench has a plurality of first intervals for dividing the first trench into a plurality of first sub-trenches. Multiple second intervals are used to divide the second trench into multiple second sub-trenches, and the multiple second intervals are located in the non-lead area near the first lead area; the first dielectric layer at the bottom of the first trench and the second trench is etched to form interconnect openings; metal lines are formed in the interconnect openings; after the metal lines are formed, a second dielectric layer is formed on the first dielectric layer and the metal lines; through-hole interconnect structures are formed in the second dielectric layers of the first lead area and the second lead area respectively, the through-hole interconnect structure of the first lead area is located on the top of the metal line corresponding to the first trench and is in contact with the metal line, and is used as the test signal loading end of the metal line, and the through-hole interconnect structure of the second lead area is located on the top of the metal line corresponding to the second trench and is in contact with the metal line, and is used as the test signal loading end of the metal line.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor interconnect reliability structure provided in this embodiment of the invention, each first metal line has multiple first isolation layers, and the multiple first isolation layers are arranged along a first direction; each second metal line has multiple second isolation layers, and the multiple second isolation layers are arranged along the first direction. When the semiconductor interconnect reliability structure of this embodiment of the invention is used to test time-dependent dielectric breakdown lifetime (TDDB) or to test breakdown voltage (VBD), the dielectric breakdown lifetime with the minimum spacing is used as the test lifetime. Since multiple second isolation layers completely isolate the second metal line near the first lead area in the non-lead area, and multiple first isolation layers completely isolate the first metal line near the second lead area in the non-lead area, during testing, the portion of each first metal line that loads a signal through the via interconnect structure can be isolated from the portion located in the second lead area by the non-connected metal lines with a large spacing, thereby facilitating the loading of each first metal line. The larger distance between the signal-carrying portion and the portion located in the second lead region helps avoid mistaking the dielectric breakdown lifetime between the signal-carrying portion of each first metal line and the portion located in the second lead region as the test result when testing the dielectric breakdown lifetime between adjacent first and second metal lines due to the influence of the via interconnect structure in the second lead region. Similarly, the second metal line is treated the same way as the first metal line, thereby reducing the impact of via interconnect structures on the semiconductor interconnect reliability structure and thus facilitating the acquisition of more accurate test results. Attached Figure Description

[0009] Figure 1 This is a top view of a semiconductor interconnect reliability structure;

[0010] Figures 2 to 4 This is a schematic diagram of an embodiment of the semiconductor interconnect reliability structure of the present invention;

[0011] Figures 5 to 25 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a reliable semiconductor interconnect structure of the present invention. Detailed Implementation

[0012] Currently, with the continuous shrinking of technology nodes, improving the accuracy of test results has become a challenge, resulting in a need to improve the accuracy of test results. This paper analyzes the reasons why the accuracy of test results needs improvement, using a semiconductor interconnect reliability structure as an example.

[0013] Figure 1 This is a top view of a semiconductor interconnect reliability structure.

[0014] The semiconductor interconnect reliability structure includes: a dielectric layer 10, wherein the dielectric layer 10 is along a first direction (e.g., Figure 1 The non-lead region 10T (in the X direction) includes a non-lead region 10T, a first lead region 10V1 located on one side of the non-lead region 10T, and a second lead region 10V2 located on the other side of the non-lead region 10T. Both the first lead region 10V1 and the second lead region 10V2 are used to load test signals. Multiple metal wires (not shown) are formed in the dielectric layer 10, extending along a first direction and along a second direction (e.g., ...). Figure 1 The first metal wires are arranged in parallel in the Y direction, and the second direction is perpendicular to the first direction. The metal wires along the second direction include alternating and equally spaced first metal wires 21 and second metal wires 22. The first through-hole interconnect structure 31 is located on top of the first metal wire 21 in the first lead area 10V1 and is used as the test signal loading end of the first metal wire 21. The second through-hole interconnect structure 32 is located on top of the second metal wire 22 in the second lead area 10V2 and is used as the test signal loading end of the second metal wire 22.

[0015] Typically, when forming the first via interconnect structure 31 and the second via interconnect structure 32, the dimensions of the first via interconnect structure 31 and the second via interconnect structure 32 expand along the second direction, such that the spacing w1 between the first via interconnect structure 31 at the top of the first metal line 21 and the adjacent second metal line 22 is smaller than the spacing d1 between the adjacent first metal line 21 and the second metal line 22. Similarly, the spacing w2 between the second via interconnect structure 32 on the second metal line 22 and the adjacent first metal line 21 is smaller than the spacing d1 between the adjacent first metal line 21 and the second metal line 22. When the semiconductor interconnect reliability structure is used to test time-dependent dielectric breakdown lifetime or to test breakdown voltage, the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime. Therefore, when testing adjacent... When testing the dielectric layer 10 between the first metal line 21 and the second metal line 22, the breakdown lifetime of the dielectric layer 10 between adjacent first metal lines 21 and second metal lines 22 is difficult to accurately detect because the spacings w1 and w2 are smaller than the spacing d1 between adjacent first metal lines 21 and second metal lines 22. Furthermore, the actual breakdown lifetime obtained may be the breakdown lifetime of the dielectric layer 10 between the first via interconnect structure 31 at the top of the first metal line 21 and the adjacent second metal line 22, or the breakdown lifetime of the dielectric layer 10 between the second via interconnect structure 32 on the second metal line 22 and the adjacent first metal line 21. This results in a large error in the test results and significantly affects their accuracy.

[0016] To address the technical problem, this invention provides a semiconductor interconnect reliability structure, comprising: multiple metal lines extending along a first direction and arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction; each metal line along the first direction including a lead region and a non-lead region; the lead region including a first lead region and a second lead region located on either side of the non-lead region, both the first and second lead regions being used to load test signals; and the metal lines along the second direction including alternating first and second metal lines; and a first partition layer penetrating the first metal line near the second lead region in the non-lead region and used to divide the first metal line in the first direction. Each first metal wire has multiple first partition layers arranged along a first direction; a second partition layer penetrates the second metal wire near the first lead area in the non-lead area and is used to divide the second metal wire in the first direction, each second metal wire having multiple second partition layers arranged along the first direction; and through-hole interconnect structures are respectively located on the top of the first metal wire in the first lead area and on the top of the second metal wire in the second lead area, the through-hole interconnect structure in the first lead area being used as a test signal loading end for the first metal wire, and the through-hole interconnect structure in the second lead area being used as a test signal loading end for the second metal wire.

[0017] When the semiconductor interconnect reliability structure of this embodiment is used to test time-dependent dielectric breakdown lifetime or breakdown voltage, the dielectric breakdown lifetime with the minimum spacing is used as the test lifetime. Since multiple second isolation layers completely isolate the second metal lines near the first lead area in the non-lead area, and multiple first isolation layers completely isolate the first metal lines near the second lead area in the non-lead area, during testing, the portion of each first metal line that loads a signal through the via interconnect structure is isolated from the portion located in the second lead area by the non-connected metal lines with a large spacing. This facilitates signal loading on each first metal line. The larger distance between the portion of the first metal line and the portion located in the second lead area helps to avoid mistaking the dielectric breakdown lifetime between the portion of the first metal line carrying the signal and the portion located in the second lead area as the test result when testing the dielectric breakdown lifetime between adjacent first and second metal lines due to the influence of the via interconnect structure in the second lead area. Similarly, the second metal line is treated the same way as the first metal line, thereby reducing the impact of the via interconnect structure on the semiconductor interconnect reliability structure, and thus facilitating the acquisition of more accurate test results.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Figures 2 to 4This is a schematic diagram of an embodiment of the semiconductor interconnect reliability structure of the present invention, wherein, Figure 2 It is a top view. Figure 3 a is Figure 2 Cross-sectional view along the BB direction. Figure 3 b is Figure 2 A cross-sectional view along the B'B' direction. Figure 4 yes Figure 2 A sectional view along the CC direction.

[0020] Semiconductor interconnect reliability structures include: multiple metal lines (not shown), the metal lines being along a first direction (e.g., Figure 2 Extending in the X direction and along the second direction (e.g., the middle X direction) and along the second direction (e.g Figure 2 The metal wires are arranged parallel to each other in the Y direction, and the second direction is perpendicular to the first direction. Along the first direction, the metal wires include a non-lead region 101T and a lead region. The lead region includes a first lead region 101V1 and a second lead region 101V2 located on either side of the non-lead region 101T. Both the first lead region 101V1 and the second lead region 101V2 are used to load test signals. Along the second direction, the metal wires include alternating first metal wires 211 and second metal wires 221. A first partition layer 111 penetrates the first metal wire 211 near the second lead region 101V2 in the non-lead region 101T and is used to divide the first metal wire 211 in the first direction. Each first metal wire 211 has multiple first partition layers 111, and the multiple first partition layers 111 are arranged along the Y direction. Arranged in one direction; a second partition layer 121, penetrating the second metal wire 221 near the first lead area 101V1 in the non-lead area 101T, and used to divide the second metal wire 221 in the first direction, each second metal wire 221 having multiple second partition layers 121, and the multiple second partition layers 121 arranged along the first direction; through-hole interconnection structures 321, respectively located on the top of the first metal wire 211 in the first lead area 101V1 and the top of the second metal wire 221 in the second lead area 101V2, the through-hole interconnection structure 321 in the first lead area 101V1 is used as the test signal loading end of the first metal wire 211, and the through-hole interconnection structure 321 in the second lead area 101V2 is used as the test signal loading end of the second metal wire 221.

[0021] In this embodiment, the semiconductor interconnect reliability structure includes a TDDB test structure or a VBD test structure.

[0022] The TDDB (Time-Related Dielectric Breakdown) test structure is used to predict the lifespan of semiconductor devices. Typically, the breakdown lifetime of the dielectric material is determined by detecting the breakdown time. A constant voltage is applied to the metal line, causing the device to accumulate voltage. After a certain period, the dielectric material will break down. The time elapsed from the application of the constant voltage to the point where the dielectric material breaks down is the lifetime of the dielectric material under those conditions. The VBD (Voltage-Based Breakdown) test structure is a pre-test of the TDDB test, used to determine the breakdown lifetime of the dielectric material by detecting the breakdown voltage. A voltage is increased in a stepped manner on the metal line. After reaching a certain voltage, the dielectric material will break down. The voltage applied at the point where the dielectric material breaks down is the breakdown voltage of the dielectric material.

[0023] As an example, the test structure for semiconductor interconnect reliability is TDDB.

[0024] In this embodiment, the semiconductor interconnect reliability structure includes a substrate 131, which includes a substrate structure layer (not shown) and a substrate (not shown). Taking a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the semiconductor interconnect reliability structure is a three-dimensional semiconductor structure, the substrate can also be a substrate with fins.

[0025] The substrate structure layer may also include other structures, such as gate structures, doped regions, shallow trench isolation (STI) structures, and dielectric layers, etc., in which devices (e.g., MOS transistors or SRAM devices) are formed. Specifically, the substrate structure layer also includes an interlayer dielectric layer (not shown) formed on the substrate and contact plugs (CT) formed in the interlayer dielectric layer (not shown).

[0026] In this embodiment, a dielectric layer 101 is formed on the substrate 131.

[0027] In this embodiment, the dielectric layer 101 is an inter metal dielectric (IMD) layer, which is used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process.

[0028] Therefore, the dielectric layer 101 is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the dielectric layer 101 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the dielectric layer 101 is made of an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0029] Accordingly, in this embodiment, the metal lines are located in the dielectric layer 101, and along the second direction, adjacent first metal lines 211 and second metal lines 221 are separated by the dielectric layer 101.

[0030] It should be noted that the first metal line 211 and the second metal line 221 are interconnecting metal lines on the same layer.

[0031] In this embodiment, the metal wire includes a non-lead area 101T along the first direction, and a first lead area 101V1 and a second lead area 101V2 located on both sides of the non-lead area 101T. The first lead area 101V1 and the second lead area 101V2 are both used to load test signals, and the first metal wire 211 and the second metal wire 221 are arranged alternately.

[0032] In this embodiment, when testing the reliability of a semiconductor interconnect structure, test signals are applied to the first metal line 211 of the first lead region 101V1 and the second metal line 221 of the second lead region 101V2, respectively, to detect the dielectric breakdown lifetime between adjacent first metal lines 211 and second metal lines 221 located in the non-lead region 101T, thereby achieving reliability testing.

[0033] In this embodiment, the spacing between adjacent first metal lines 211 and second metal lines 221 is equal.

[0034] Since the dielectric breakdown lifetime of the minimum spacing is used as the TDDB test lifetime when the semiconductor interconnect reliability structure is used to test the time-related dielectric breakdown lifetime, in this embodiment, the spacing between adjacent first metal lines 211 and second metal lines 221 is equal. Therefore, when performing TDDB testing, the dielectric breakdown lifetime between adjacent first metal lines 211 and second metal lines 221 can be detected more accurately, and the situation of large error in the detection result caused by different spacing dimensions between adjacent first metal lines 211 and second metal lines 221 can be avoided to a large extent.

[0035] In this embodiment, the material of the metal wire includes one or more of copper, aluminum, and copper alloys, thereby enabling the first metal wire 211 and the second metal wire 221 to achieve better conductivity.

[0036] In this embodiment, the first metal line 211 and the second metal interconnect 221 are metal interconnects in the same layer, therefore, the first metal line 211 and the second metal interconnect 221 are made of the same material.

[0037] The second isolation layer 121 is used to separate the second metal wire 221 of the first lead area 101V1 and the non-lead area 101T in the first direction, thereby achieving physical and electrical isolation between the second metal wire 221 of the first lead area 101V1 and the non-lead area 101T. The first isolation layer 111 is used to separate the first metal wire 211 of the second lead area 101V2 and the non-lead area 101T in the first direction, thereby achieving physical and electrical isolation between the second lead area 101V2 and the first metal wire 211 of the non-lead area 101T.

[0038] When the semiconductor interconnect reliability structure of this embodiment is used to test time-dependent dielectric breakdown lifetime or breakdown voltage, the dielectric breakdown lifetime with the minimum spacing is used as the test lifetime. Since multiple second isolation layers 121 completely isolate the second metal line 221 near the first lead region 101V1 in the non-lead region 101T, and multiple first isolation layers 111 completely isolate the first metal line 211 near the second lead region 101V2 in the non-lead region 101T, during testing, the portion of each first metal line 211 that is loaded with a signal through the via interconnect structure 311 is isolated from the portion located in the second lead region 101V2 by the non-connected metal lines with a large spacing. This facilitates the loading of signals by each first metal line 211. The larger distance between the signal portion and the portion located in the second lead region helps to avoid mistaking the dielectric breakdown lifetime between the portion of the first metal line 211 loaded with the signal and the portion located in the second lead region 101V2 as the test result when testing the dielectric breakdown lifetime between adjacent first metal lines 211 and second metal lines 221 due to the influence of the via interconnect structure 311 located in the second lead region 101V2. Similarly, the second metal line 221 is treated the same as the first metal line 211, thereby reducing the impact of the via interconnect structure 311 on the first metal line 211 and the via interconnect structure 311 on the second metal line 221 on the semiconductor interconnect reliability structure, thus facilitating the acquisition of more accurate test results.

[0039] In this embodiment, the first partition layer 111 located in the first metal line 211 also extends to the sidewalls of the second metal line 221 along the second direction, thereby helping to ensure that the first partition layer 111 completely separates the first metal line 211 of the second lead area 101V2 and the non-lead area 101T.

[0040] In this embodiment, the second partition layer 121 located in the second metal line 221 also extends to the sidewalls of the first metal line 211 along the second direction, thereby helping to ensure that the second partition layer 121 completely separates the second metal line 221 of the first lead area 101V1 and the non-lead area 101T.

[0041] In this embodiment, in the second direction, adjacent first partition layers 111 are staggered in the first direction; in the second direction, adjacent second partition layers 121 are staggered in the first direction.

[0042] In the second direction, the adjacent first isolation layers 111 are staggered in the first direction, which helps to make the spacing between the adjacent first isolation layers 111 larger, thereby reducing the limitation on the length dimension of the first isolation layer 111 along the second direction, increasing the process window for forming the first isolation layer 111, and reducing the process difficulty of forming the first isolation layer 111. This helps to reduce the difficulty of forming a reliable semiconductor interconnect structure. Similarly, in the second direction, the adjacent second isolation layers 121 are staggered in the first direction, which also helps to reduce the difficulty of forming a reliable semiconductor interconnect structure.

[0043] In this embodiment, multiple first partition layers 111 in the same first metal wire 211 are located in the same row, and in the first direction, the distance between adjacent rows of first partition layers 111 is less than the spacing between adjacent first partition layers 111; multiple second partition layers 121 in the same second metal wire 221 are located in the same row, and in the first direction, the distance between adjacent rows of second partition layers 121 is less than the spacing between adjacent second partition layers 121.

[0044] The distance between the first partition layers 111 of adjacent rows is the distance between the first partition layers 111 at the far end of the same side of adjacent rows, and the distance between the second partition layers 121 of adjacent rows is the distance between the second partition layers 121 at the far end of the same side of adjacent rows.

[0045] In the first direction, the distance between the first partition layers 111 of adjacent rows is less than the spacing between adjacent first partition layers 111. That is, the first partition layers 111 of adjacent rows are sequentially interspersed, so that the spacing between the ends of adjacent rows is not too large. This is conducive to making the overall arrangement of the first partition layers 111 more reasonable and occupying less area. This is conducive to ensuring that the non-lead area 101T has a sufficient length of first metal line 211 for loading signals for testing. At the same time, it is also conducive to saving the overall area occupied by the semiconductor interconnect reliability structure. Similarly, in the first direction, the distance between the second partition layers 121 of adjacent rows is less than the spacing between adjacent second partition layers 121. This is conducive to ensuring that the non-lead area 101T has a sufficient length of second metal line 221 for loading signals for testing. At the same time, it is also conducive to saving the overall area occupied by the semiconductor interconnect reliability structure.

[0046] In this embodiment, two adjacent rows of first partition layers 111 are aligned; two adjacent rows of second partition layers 121 are aligned.

[0047] The first partition layer 111 is aligned with two adjacent rows, and the second partition layer 121 is aligned with two adjacent rows, so that the layout of the first partition layer 111 and the second partition layer 121 is relatively neat and symmetrical, making the formation of the first partition layer 111 and the second partition layer 121 simple and easy to operate.

[0048] In this embodiment, each first metal wire 211 has two first partition layers 111 arranged along the second direction; each second metal wire 221 has two second partition layers 121 arranged along the second direction.

[0049] Each first metal line 211 has two first isolation layers 111 arranged along the second direction. This allows the portion of each first metal line 211 that carries a signal through a via interconnect structure to be isolated from the portion located in the second lead region 101V2 by the non-connected portions of the first metal line 211. At the same time, using as few first isolation layers 111 as possible helps to reduce the area occupied by the first isolation layers 111, thereby saving the area occupied by the semiconductor interconnect reliability structure. Similarly, each second metal line 221 has two second isolation layers 121 arranged along the second direction. This helps to reduce the area occupied by the second isolation layers 121, thereby saving the area occupied by the semiconductor interconnect reliability structure.

[0050] In this embodiment, the materials of the first partition layer 111 and the second partition layer 121 include one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN and SiON.

[0051] In this embodiment, the first partition layer 111, the second partition layer 121 and the dielectric layer 101 are an integral structure.

[0052] In this embodiment, during the formation of the semiconductor interconnect reliability structure, the first metal line 211 and the second metal line 221 are formed in corresponding interconnect openings, which are formed in the dielectric layer 101. Typically, trenches are first formed in the core layer above the dielectric layer 101, and then the pattern of the trenches is transferred to the dielectric layer 101 to form interconnect openings. The interconnect openings of the first isolation layer 111 and the second isolation layer 121 are formed in the same step by transferring the pattern of the trenches to the dielectric layer 101. That is, an etching mask is typically formed on the top of the dielectric layer 101 at the positions corresponding to the first isolation layer 111 and the second isolation layer 121, so that the dielectric layer 101 at the positions corresponding to the first isolation layer 111 and the second isolation layer 121 can be retained after etching. Therefore, the first isolation layer 111, the second isolation layer 121 and the dielectric layer 101 are an integral structure. Moreover, in the process of forming a reliable semiconductor interconnect structure, there is no need to separately form the first isolation layer 111 and the second isolation layer 121, which reduces the process complexity and improves the process efficiency.

[0053] Therefore, in this embodiment, the first partition layer 111, the second partition layer 121, and the dielectric layer 101 are made of the same material.

[0054] In other embodiments, the first isolation layer, the second isolation layer, and the dielectric layer may also be independent structures.

[0055] It should be noted that the linewidth dimensions of the first partition layer 111 and the second partition layer 121 along the first direction should not be too small or too large. If the linewidth dimensions of the first partition layer 111 and the second partition layer 121 along the first direction are too small, the isolation effect of the first partition layer 111 and the second partition layer 121 will be weakened, making it difficult for the first partition layer 111 and the second partition layer 121 to completely isolate the first metal wire 211 and the second metal wire 221. If the linewidth dimensions of the first partition layer 111 and the second partition layer 121 along the first direction are too large, the first partition layer 111 and the second partition layer 121 will occupy too much space of the first metal wire 211 and the second metal wire 221, affecting the formation quality and performance of the first metal wire 211 and the second metal wire 221. At the same time, excessively large linewidth dimensions of the first partition layer 111 and the second partition layer 121 will also cause unnecessary process waste. Therefore, in this embodiment, the linewidth dimensions of the first partition layer 111 and the second partition layer 121 along the first direction are 20nm to 35nm.

[0056] It should also be noted that the length dimension s1 of the first isolation layer 111 and the second isolation layer 121 along the second direction should not be too small. If the length dimension s1 of the first isolation layer 111 and the second isolation layer 121 is too small, it is easy to cause the problem of incomplete isolation of the metal lines, and it is also easy to cause difficulties in the formation of the first isolation layer 111 and the second isolation layer 121 due to design guidelines, thereby affecting the test performance of the semiconductor interconnect reliability structure. Therefore, in this embodiment, the length dimension of the first isolation layer 111 and the second isolation layer 121 along the second direction is greater than or equal to 18 nm.

[0057] It should also be noted that, along the first direction, the spacing s4 between adjacent first isolation layers 111 in the same first metal line 211 and between adjacent second isolation layers 121 in the same second metal line 221 should not be too small. If the spacing s4 between adjacent first isolation layers 111 in the same first metal line 211 and between adjacent second isolation layers 121 in the same second metal line 221 is too small, it can easily lead to difficulties in forming adjacent first isolation layers 111 or second isolation layers 121 on the same metal line, and it can also be difficult to form adjacent first isolation layers 111 or second isolation layers 121 due to design constraints, thereby affecting the test performance of the semiconductor interconnect reliability structure. Therefore, in this embodiment, along the first direction, the spacing s4 between adjacent first isolation layers 111 in the same first metal line 211 and between adjacent second isolation layers 121 in the same second metal line 221 is greater than or equal to 100 nm.

[0058] It should also be noted that, in the second direction, the spacing s3 between adjacent first isolation layers 111 and adjacent second isolation layers 121 should not be too small. If the spacing s3 between adjacent first isolation layers 111 and adjacent second isolation layers 121 is too small, the head-to-head spacing between the first isolation layers 111 and the second isolation layers 121 will be too small, which may make it difficult to form the first isolation layers 111 and the second isolation layers 121 due to design constraints, thereby affecting the test performance of the semiconductor interconnect reliability structure. Therefore, in this embodiment, in the second direction, the spacing s3 between adjacent first isolation layers 111 and adjacent second isolation layers 121 is greater than or equal to 80 nm.

[0059] It should also be noted that the diagonal spacing s2 between adjacent first isolation layers 111 and adjacent second isolation layers 121 should not be too small. If the diagonal spacing s2 between adjacent first isolation layers 111 and adjacent second isolation layers 121 is too small, it will be difficult to form adjacent first isolation layers 111 and adjacent second isolation layers 121, and it will also be difficult to form the first isolation layers 111 and second isolation layers 121 due to design constraints, thereby affecting the test performance of the semiconductor interconnect reliability structure. Therefore, in this embodiment, the diagonal spacing s2 between adjacent first isolation layers 111 and adjacent second isolation layers 121 is greater than or equal to 50 nm.

[0060] In this embodiment, dielectric layer 101 is defined as first dielectric layer 101, and a second dielectric layer 301 covering the metal lines is also formed on the first dielectric layer 101.

[0061] The second dielectric layer 301 is also used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0062] Therefore, the material of the second dielectric layer 301 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). In this embodiment, the material of the second dielectric layer 301 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the material of the second dielectric layer 301 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0063] Correspondingly, the via interconnect structure 311 is located in the second dielectric layer 301.

[0064] Typically, when forming the via interconnect structure 311, the size of the via interconnect structure 311 expands along the second direction. Therefore, in this embodiment, along the second direction, the width of the via interconnect structure 311 is greater than the width of the metal line in which it is located.

[0065] In other words, the distance w1 between the through-hole interconnect structure 311 at the top of the first metal line 211 and the adjacent second metal line 221 is less than the distance d1 between the adjacent first metal line 211 and the second metal line 221. Similarly, the distance w2 between the through-hole interconnect structure 311 on the second metal line 221 and the adjacent first metal line 211 is less than the distance d1 between the adjacent first metal line 211 and the second metal line 221.

[0066] Since the first isolation layer 111 and the second isolation layer 121 achieve physical and electrical isolation between the second metal wire 221 of the first lead area 101V1 and the non-lead area 101T, and also achieve physical and electrical isolation between the first metal wire 211 of the second lead area 101V2 and the non-lead area 101T, even if the spacing w1 and w2 are both smaller than the spacing d1 between adjacent first metal wires and second metal wires, the probability of test error caused by the spacing w1 and w2 being smaller than the spacing d1 between adjacent first metal wires and second metal wires is reduced when testing the dielectric breakdown lifetime between adjacent first metal wires 211 and second metal wires 221 using TDDB.

[0067] Because the spacing w1 between the via interconnect structure 311 at the top of the first metal line 211 and the adjacent second metal line 221 is smaller than the spacing d1 between the adjacent first metal line 211 and the second metal line 221, during the manufacturing process, process errors may cause the via interconnect structure 311 at the top of the first metal line 211 to mistakenly contact the adjacent second metal line 221. This could easily cause the portion of the second metal line 221 located in the first lead region 101V1 to become energized during the operation of the semiconductor interconnect reliability structure. If the second metal line 221 has only one second isolation layer 121 along the first direction, it could easily lead to the dielectric breakdown between the ends of the second metal line 221 located on both sides of the second isolation layer 121 during the TDDB test of the dielectric breakdown lifetime between the adjacent first metal line 211 and the second metal line 221. Since lifetime is used as a test result, it affects the test accuracy of semiconductor interconnect reliability structure. Therefore, in this embodiment, along the first direction, the second metal line 221 has multiple second isolation layers 121. The portion of each second metal line 211 that is loaded with a signal through the via interconnect structure 311 is isolated from the portion located in the first lead region 101V1 by non-connected metal lines with a large spacing. This helps to avoid the situation where the dielectric breakdown lifetime between the portion of each first metal line 211 loaded with a signal and the portion located in the first lead region 101V1 is mistakenly taken as the test result due to the influence of the via interconnect structure 311 located in the first lead region 101V1. The same applies to the first metal line 211.

[0068] It should be noted that the number of via interconnect structures 311 at the top of each first metal line 211, in the first lead region 101V1 or the second lead region 101V2, cannot be too many or too few. If the number of via interconnect structures 311 is too many, and the feature size of the semiconductor interconnect reliability structure is decreasing, it will easily increase the process difficulty of forming the via interconnect structures 311, and cause unnecessary process waste; if the number of via interconnect structures 311 is too few, it will easily increase the probability of failure of the via interconnect structure 311 connection. Therefore, in this embodiment, the number of via interconnect structures 311 at the top of each first metal line 211, in the first lead region 101V1 or the second lead region 101V2, is 2 to 5.

[0069] In this embodiment, at the top of each first metal wire 211, in the first lead area 101V1 or the second lead area 101V2, there are 3 through-hole interconnect structures 311. Under the condition of ensuring simple formation process, as long as one of the through-hole interconnect structures 311 is electrically connected, the first metal wire 211 is electrically connected successfully. Therefore, by using 3 through-hole interconnect structures 311, the test signal loading of the first metal wire 211 can be guaranteed to a large extent.

[0070] In this embodiment, the material of the through-hole interconnect structure 311 is a metallic material. Metallic materials have good electrical conductivity, which is beneficial for improving the electrical connection performance between the first metal line 211 and the external interconnect structure, and consequently, for improving the accuracy of the test results.

[0071] In this embodiment, the material of the through-hole interconnect structure 311 includes one or more of copper, aluminum, and copper alloys.

[0072] In this embodiment, at the top of each second metal wire 221, in the first lead region 101V1 or the second lead region 101V2, the number of through-hole interconnect structures 311 is 1 to 5.

[0073] In this embodiment, at the top of each second metal wire 221, in the first lead area 101V1 or the second lead area 101V2, there are two through-hole interconnect structures 311.

[0074] In this embodiment, the via interconnection structure 311 at the top of each second metal wire 221 is similar to the via interconnection structure 211 at the top of each first metal wire 211, and will not be described again here.

[0075] Figures 5 to 25 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a reliable semiconductor interconnect structure of the present invention.

[0076] refer to Figure 5A substrate 130 is provided, on which a first dielectric layer 100 is formed, the first dielectric layer 100 being oriented along a first direction (e.g., ...). Figure 5 The X-direction region includes a non-lead region 100T and a lead region. The lead region includes a first lead region 100V1 and a second lead region 100V2 located on both sides of the non-lead region 100T. Both the first lead region 100V1 and the second lead region 100V2 are used to load test signals.

[0077] In this embodiment, the semiconductor interconnect reliability structure includes a TDDB test structure or a VBD test structure.

[0078] As an example, the semiconductor interconnect reliability structure is the TDDB test structure.

[0079] In this embodiment, the substrate 130 includes a substrate structure layer (not shown), and the substrate structure layer includes a substrate (not shown). Taking a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, when the semiconductor interconnect reliability structure is a three-dimensional semiconductor structure, the substrate can also be a substrate with fins.

[0080] The substrate structure layer may also include other structures, such as gate structures, doped regions, shallow trench isolation (STI) structures, and dielectric layers, etc., in which devices (e.g., MOS transistors or SRAM devices) are formed. Specifically, the substrate structure layer also includes a second dielectric layer (not shown) formed on the substrate and contact holes (CT) formed in the second dielectric layer (not shown).

[0081] In this embodiment, a first dielectric layer 100 is formed on the substrate 130.

[0082] In this embodiment, the first dielectric layer 100 is an inter-metal dielectric (IMD) layer, which is used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process.

[0083] Therefore, the material of the first dielectric layer 100 is a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, the material of the first dielectric layer 100 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the material of the first dielectric layer 100 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0084] The non-lead region 100T serves as the non-lead region of TDDB, while the first lead region 100V1 and the second lead region 100V2 are both used to load test signals.

[0085] Specifically, metal lines are subsequently formed in the first dielectric layer 100. During the TDDB test, test signals are applied to the metal lines of the first lead region 100V1 and the second lead region 100V2, and the dielectric breakdown lifetime between adjacent metal lines in the non-lead region 100T is tested.

[0086] refer to Figure 6 This forms a core layer 400 covering the first dielectric layer 100.

[0087] The core layer 400 provides a process platform for the subsequent formation of the first trench and the second trench, thereby utilizing the graphical core layer 400 to pass the pattern downwards. Specifically, the first trench defines the pattern and location of the subsequently formed first interconnect opening, and the second trench defines the pattern and location of the subsequently formed second interconnect opening, which correspondingly improves the pattern accuracy of the first and second interconnect openings.

[0088] In addition, side walls will be formed on the side walls of the core layer 400, and the core layer 400 will also provide support for the formation of the side walls.

[0089] The core layer 400 will be removed subsequently. Therefore, the material of the core layer 400 is one that is easy to remove, thereby reducing the difficulty of removing the core layer 400 and minimizing damage to other films located below the core layer 400. Therefore, the material of the core layer 400 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the core layer 400 is amorphous silicon (a-Si).

[0090] Reference Figures 7 to 18 In the core layer 400, a structure is formed along the first direction (e.g.) Figure 16 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 16The first trench 410 and the second trench 420 are arranged in parallel and alternately in the Y direction. In the first direction, the first trench 410 has a plurality of first intervals for dividing the first trench 410 into a plurality of first sub-trenches. The plurality of first intervals are located in the non-lead region 100T near the second lead region 100V2. In the first direction, the second trench 420 has a plurality of second intervals for dividing the second trench 420 into a plurality of second sub-trenches. The plurality of second intervals are located in the non-lead region 100T near the first lead region 100V1.

[0091] The first trench 410 is used to define the position for the subsequent formation of the first metal line, the first interval is used to define the position for the subsequent formation of the first partition layer, the second trench 420 is used to define the position for the subsequent formation of the second metal line, and the second interval is used to define the position for the subsequent formation of the second partition layer.

[0092] When the semiconductor interconnect reliability structure of this embodiment is used to test time-dependent dielectric breakdown lifetime or breakdown voltage, the dielectric breakdown lifetime with the minimum spacing is used as the test lifetime. Since multiple second isolation layers completely isolate the second metal lines near the first lead region 100V1 in the non-lead region 100T, and multiple first isolation layers completely isolate the first metal lines near the second lead region 100V2 in the non-lead region 100T, during testing, the portion of each first metal line that loads a signal through the via interconnect structure can be isolated from the portion located in the second lead region 100V2 by the non-connected metal lines with a large spacing. This facilitates the isolation of each first metal line from the portion of the signal loaded through the via interconnect structure. The large distance between the portion of the line-loaded signal and the portion located in the second lead region helps to avoid mistaking the dielectric breakdown lifetime between the portion of the first metal line and the portion located in the second lead region 100V2 as the test result when testing the dielectric breakdown lifetime between adjacent first and second metal lines due to the influence of the via interconnect structure located in the second lead region 100V2. Similarly, the second metal line is treated the same as the first metal line, thereby reducing the impact of the via interconnect structure 310 on the semiconductor interconnect reliability structure on the first and second metal lines, and thus facilitating the acquisition of more accurate test results.

[0093] In this embodiment, in the second direction, adjacent first intervals are staggered in the first direction; in the second direction, adjacent second intervals are staggered in the first direction.

[0094] In other words, in the second direction, the adjacent first isolation layers are staggered in the first direction, which helps to make the spacing between the adjacent first isolation layers larger, thereby reducing the limitation on the length dimension of the first isolation layer along the second direction, increasing the process window for forming the first isolation layer, and reducing the process difficulty of forming the first isolation layer. This helps to reduce the difficulty of forming a reliable semiconductor interconnect structure. Similarly, in the second direction, the adjacent second isolation layers are staggered in the first direction, which also helps to reduce the difficulty of forming a reliable semiconductor interconnect structure.

[0095] In this embodiment, multiple first intervals in the same first trench 410 are located in the same row, and in the first direction, the distance between the first intervals of adjacent rows is less than the distance between adjacent first intervals; multiple second intervals in the same second trench 420 are located in the same row, and in the first direction, the distance between the second intervals of adjacent rows is less than the distance between adjacent second intervals.

[0096] The distance at which the first interval between adjacent rows is staggered refers to the distance at which the first interval between the two ends on the same side of the adjacent rows is staggered, and the distance at which the second interval between adjacent rows is staggered refers to the distance at which the second interval between the two ends on the same side of the adjacent rows is staggered.

[0097] That is, in the first direction, the distance between the first partition layers of adjacent rows is less than the spacing between adjacent first partition layers; in the first direction, the distance between the second partition layers of adjacent rows is less than the spacing between adjacent second partition layers.

[0098] In the first direction, the distance between the first partition layers of adjacent rows is less than the spacing between adjacent first partition layers. That is, the first partition layers of adjacent rows are sequentially interspersed, so that the spacing between the ends of adjacent rows is not too large. This helps to make the overall arrangement of the first partition layers more reasonable and occupy less area. This helps to ensure that the non-lead area 100T has a sufficient length of first metal line for loading signals for testing. At the same time, it also helps to save the overall area occupied by the semiconductor interconnect reliability structure. Similarly, in the first direction, the distance between the second partition layers of adjacent rows is less than the spacing between adjacent second partition layers. This helps to ensure that the non-lead area 100T has a sufficient length of second metal line for loading signals for testing. At the same time, it also helps to save the overall area occupied by the semiconductor interconnect reliability structure.

[0099] In this embodiment, the first interval between two adjacent rows is aligned; the second interval between two adjacent rows is aligned.

[0100] In other words, in the clubhouse, the first partition layer of two adjacent rows is aligned; the second partition layer of two adjacent rows is aligned.

[0101] The first partition layer is aligned with two adjacent rows, and the second partition layer is aligned with two adjacent rows, so that the layout of the first and second partition layers is relatively neat and symmetrical, making the formation of the first and second partition layers simple and easy to operate.

[0102] In this embodiment, each first groove 410 has two first partitions arranged along the second direction; each second groove 420 has two second partitions arranged along the second direction.

[0103] That is, each first metal wire has two first partition layers arranged along the second direction; each second metal wire has two second partition layers arranged along the second direction.

[0104] Each first metal line has two first isolation layers arranged along the second direction. This allows the portion of each first metal line that carries a signal through a via interconnect structure to be isolated from the portion located in the second lead region 100V2 by the non-connected portion of the first metal line. At the same time, using as few first isolation layers as possible helps to reduce the area occupied by the first isolation layers, thereby saving the area occupied by the semiconductor interconnect reliability structure. Similarly, each second metal line has two second isolation layers arranged along the second direction. This helps to reduce the area occupied by the second isolation layers, thereby saving the area occupied by the semiconductor interconnect reliability structure.

[0105] The following is for reference only. Figures 7 to 18 The steps for forming the first trench 410 and the second trench 420 are described in detail.

[0106] Reference Figure 7 and Figure 8 , Figure 7 It is a top view. Figure 8 yes Figure 7 In the cross-sectional view along the B'B' direction, near the second lead region 100V2 in the non-lead region 100T, a plurality of first partition structures 710 are formed in the core layer 400. The plurality of first partition structures 710 are arranged in multiple rows in the second direction, and each row has a plurality of first partition structures 710 arranged along the first direction.

[0107] The first partition structure 710 is used as a mask for etching the first dielectric layer 100 when the pattern of the second trench 420 and the first trench 410 is subsequently transferred to the first dielectric layer 100.

[0108] In this embodiment, the material of the first partition structure 710 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the first partition structure 710 is titanium oxide.

[0109] The steps of forming the first isolation structure 710 include: forming a first mask layer 601 on the first dielectric layer 100, forming a first mask opening 610 in the first mask layer 601, and exposing the core layer 400 near the second lead region 100V2 in the non-lead region 100T.

[0110] The first mask layer 601 is used as a mask for forming the first partition structure 710.

[0111] The first mask layer 601 is made of a material that is easy to remove, and the process of removing the first mask layer 601 causes minimal damage to other film layers. In this embodiment, the material of the first mask layer 601 is spin-coated carbon (SOC) material. In other embodiments, the material of the first mask layer may also be ODL (organic dielectric layer) material or BARC (bottom anti-reflective coating) material.

[0112] In this embodiment, the core layer 400 exposed by the first mask opening 610 is removed, and a first groove (not shown) is formed in the core layer 400.

[0113] In this embodiment, a first partition structure 710 is formed in the first groove.

[0114] Compared with the scheme of directly patterning the core layer 400, forming the first mask opening 610 first helps to improve the pattern size accuracy and position accuracy of the first mask opening 610. Correspondingly, forming the first partition structure 710 in the first groove corresponding to the first mask opening 610 helps to improve the pattern size accuracy and position accuracy of the first partition structure 710.

[0115] Specifically, the step of forming the first partition structure in the first groove includes: filling the first mask opening 610 with a first partition material, the first partition material also covering the top of the first mask layer 601; performing a back etching process (e.g., dry etching process) on the first partition material, and retaining the first partition material located in the first mask opening 610 as the first partition structure 710.

[0116] The first partition structure 710 is formed in the first mask opening 610. Therefore, by reasonably setting the thickness of the first partition material and the etching amount of the first partition material, the height of the first partition structure 710 can easily meet the process requirements, and the process flexibility is high.

[0117] In this embodiment, after the first partition structure 710 is formed, the first mask layer 601 is removed.

[0118] Remove the first mask layer 601 to prepare for subsequent process steps.

[0119] Reference Figure 9 and Figure 10 , Figure 9 It is a top view. Figure 10 yes Figure 9 In the cross-sectional view along the BB direction, near the first lead region 100V1 in the non-lead region 100T, a second partition structure 720 is formed in the core layer 400. Multiple second partition structures 720 are arranged in multiple rows in the second direction. Each row has multiple second partition structures 720 arranged along the first direction. The first partition structure 710 and the second partition structure 720 are arranged alternately along the second direction.

[0120] The second isolation structure 720 is used together with the first isolation structure 710 as a mask for etching the first dielectric layer 100 when the pattern of the second trench 420 and the first trench 410 is subsequently transferred to the first dielectric layer 100.

[0121] In this embodiment, the material of the second partition structure 720 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the second partition structure 720 is titanium oxide.

[0122] The steps of forming the second partition structure 720 include: forming a second mask layer 602 on the first dielectric layer 100, forming a second mask opening 620 in the second mask layer 602, and exposing the core layer 400 at the junction of the first lead region 100V1 and the non-lead region 100T.

[0123] The second mask layer 602 is used as a mask for forming the second partition structure 720.

[0124] The material of the second mask layer 602 is easily removable, and the process of removing the second mask layer 602 causes minimal damage to other film layers. In this embodiment, the material of the second mask layer 602 is spin-coated carbon (SOC). In other embodiments, the material of the second mask layer may also be ODL (organic dielectric layer) or BARC (bottom anti-reflective coating).

[0125] In this embodiment, the core layer 400 exposed by the second mask opening 620 is removed, and a second groove (not shown) is formed in the core layer 400.

[0126] In this embodiment, a second partition structure 720 is formed in the second groove.

[0127] Compared with the scheme of directly patterning the core layer 400, forming the second mask opening 620 first helps to improve the pattern size accuracy and position accuracy of the second mask opening 620. Correspondingly, forming the second partition structure 720 in the second groove corresponding to the second mask opening 620 helps to improve the pattern size accuracy and position accuracy of the second partition structure 720.

[0128] Specifically, the step of forming the second partition structure 720 in the second groove includes: filling the second mask opening 620 with a second partition material, the second partition material also covering the top of the second mask layer 602; performing a back etching process (e.g., dry etching process) on the second partition material, retaining the second partition material located in the second mask opening 620 as the second partition structure 720.

[0129] The second partition structure 720 is formed in the second mask opening 620. Therefore, by reasonably setting the thickness of the second partition material and the etching amount of the second partition material, the height of the second partition structure 720 can easily meet the process requirements, and the process flexibility is high.

[0130] In this embodiment, after the second partition structure 720 is formed, the second mask layer 602 is removed.

[0131] It should be noted that in this embodiment, the first partition structure 710 and the second partition structure 720 are formed in different steps, and the order in which the first partition structure 710 and the second partition structure 720 are formed is not limited.

[0132] Reference Figure 11 and Figure 12 , Figure 11 It is a top view. Figure 12 yes Figure 11 Based on the cross-sectional view along the AA direction, after forming the first partition structure 710 and the second partition structure 720, a first groove 410 extending along the first direction and arranged parallel to the second direction is formed in the core layer 400. The first partition structure 710 divides the first groove 410 along the first direction, and in the second direction, the first groove 410 exposes the end of the second partition structure 720.

[0133] The first trench 410 is used to define the pattern and position of the subsequently formed first interconnect opening, which helps to improve the pattern accuracy of the first interconnect opening.

[0134] Reference Figures 13 to 15 , Figure 13 Based on Figure 12 sectional view, Figure 14 It is a top view. Figure 15 yes Figure 14 Based on the cross-sectional view along the AA direction, a mask sidewall 510 is formed on the sidewall of the first trench 410.

[0135] The mask sidewall 510 is used to subsequently isolate the second trench from the first trench 410, preventing the second trench from becoming connected to the first trench 410, and ensuring that the spacing between adjacent second trenches and first trenches 410 meets the designed minimum space. Furthermore, when the patterns of the second trench and first trench 410 are subsequently transferred to the first dielectric layer 100, the mask sidewall 510 serves as a mask for etching the first dielectric layer 100. In addition, the mask sidewall 510 is used to adjust the spacing between the second trench and first trench 410 in the second direction.

[0136] The mask sidewall 510 is made of a material that has etching selectivity with the core layer 400. The material of the mask sidewall 510 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the mask sidewall 510 is titanium oxide.

[0137] It should be noted that this embodiment only illustrates the length of the mask sidewalls 510 along the first direction and the number of the first trenches 410 along the second direction. In reality, the second direction may also include... Figure 14 The core layer 400 and mask sidewalls 510 extend in the Y direction.

[0138] refer to Figure 13 The step of forming the mask sidewall 510 includes: forming a mask sidewall material layer 500 that conformally covers the top of the core layer 400 and the bottom and sidewalls of the first trench 410.

[0139] The mask sidewall material layer 500 is used to form the mask sidewall 510.

[0140] In this embodiment, an atomic layer deposition process is used to form the mask sidewall material layer 500.

[0141] The mask sidewall material layer 500 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the mask sidewall material layer 500 to cover the top of the core layer 400, as well as the bottom and sidewall of the first trench 410 in good conformal manner.

[0142] In this embodiment, the material of the mask sidewall material layer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and is used to directly form the mask sidewall 510.

[0143] Reference Figure 14 and Figure 15Remove the mask sidewall material layer 500 located at the top of the core layer 400 and the bottom of the first trench 410, and retain the mask sidewall material layer 500 located on the sidewall of the first trench 410 as the mask sidewall 510.

[0144] Removing the mask sidewall material layer 500 located at the top of the core layer 400 and the bottom of the first trench 410 can better expose the top surface of the core layer 400, thereby reducing the difficulty of the subsequent removal of the core layer 400 and preparing for the subsequent pattern transfer using the mask sidewall 510 as an etching mask.

[0145] In this embodiment, a dry etching process is used to remove the mask sidewall material layer 500 located at the top of the core layer 400 and the bottom of the first trench 410.

[0146] Dry etching has the characteristics of anisotropic etching. Therefore, by selecting dry etching, it is beneficial to reduce the damage to the mask sidewall 510 and the first dielectric layer 100. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the mask sidewall 510.

[0147] Reference Figures 16 to 18 , Figure 16 It is a top view. Figure 17 yes Figure 16 Cross-sectional view based on the AA direction, Figure 18 a is Figure 16 Sectional view based on the BB direction. Figure 18 b is Figure 16 Based on the cross-sectional view in the B'B direction, after forming the mask sidewall 510, the core layer 400 is removed to form the second trench 420. The second partition structure 720 divides the second trench 420 along the first direction, and the adjacent second trench 420 is isolated from the first trench 410 by the mask sidewall 510.

[0148] The second trench 420 is used to define the shape, size, and position of the second interconnect opening subsequently formed in the first dielectric layer 100. In this embodiment, by first forming the first trench 410 in the core layer 400 and then using the mask sidewall 510 to form the second trench 420, the pattern accuracy of the first trench 410 and the second trench 420 is improved, thereby improving the pattern accuracy of the subsequently formed first interconnect opening and second interconnect opening, and correspondingly improving the accuracy of pattern transfer.

[0149] Furthermore, the formation of the first trench 410 and the second trench 420 in this embodiment is beneficial to improving the process window for forming the first trench 410 and the second trench 420 (e.g., improving the optical proximity effect or alleviating the limitation of photolithography process resolution), ensuring the pattern accuracy of the first trench 410 and the second trench 420, and reducing the spacing between adjacent first trench 410 and second trench 420.

[0150] In this embodiment, a maskless etching process is used to remove the core layer 400. The etching selectivity between the core layer 400, the mask sidewall 510, and the first dielectric layer 100 is relatively high. Therefore, the damage to other film layers is small during the removal of the core layer 400. Accordingly, a maskless etching process can be used to remove the core layer 400, thereby simplifying the process steps and reducing costs. Moreover, by using a maskless etching process, the process window for forming the second trench 420 is significantly increased.

[0151] In this embodiment, a wet etching process is used to remove the core layer 400. The wet etching process removes the core layer 400 through a chemical reaction, which helps reduce damage to the mask sidewalls 510 and the first dielectric layer 100, and also helps to completely remove the core layer 400. In this embodiment, the material of the core layer 400 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH solution.

[0152] In this embodiment, the first groove 410 and the second groove 420 are formed in different steps, and the order in which the first groove 410 and the second groove 420 are formed is not limited.

[0153] In this embodiment, the first partition structure 710 and the second partition structure 720 are formed first, and then the first trench 410 and the second trench 420 are formed. Forming the first partition structure 710 and the second partition structure 720 in the core layer 400 with high flatness first helps to make the formed first partition structure 710 and the second partition structure 720 of better quality and more accurate position, which is beneficial to the subsequent more accurate patterning of the first dielectric layer 100 as a mask.

[0154] In other embodiments, a first partition structure and a second partition structure may be formed in the first trench and the second trench respectively after the first trench and the second trench are formed; or, after the first trench is formed, a first partition structure may be formed in the first trench, and after the first partition structure is formed, a second trench may be formed, and after the second trench is formed, a second partition structure may be formed in the second trench; or, after the first partition structure is formed, a first trench may be formed, and after the first trench is formed, a second partition structure may be formed, and after the second partition structure is formed, a second trench may be formed.

[0155] It should be noted that in other embodiments, the specific steps for forming the first trench and the second trench are similar to those in this embodiment. Accordingly, the description of the first mask layer and the second mask layer can be referred to in conjunction with the relevant description of the mask layer in this embodiment, and will not be repeated here.

[0156] Reference Figure 19 and Figure 20 , Figure 19 It is a top view. Figure 20 a is Figure 19 Sectional view based on the BB direction. Figure 20 b is Figure 19 Based on the cross-sectional view along the B'B' direction, the first dielectric layer 100 at the bottom of the first trench 410 and the second trench 420 is etched to form interconnect openings. The interconnect openings include first interconnect openings 230 and second interconnect openings 240 arranged alternately along the second direction. The first interconnect opening 230 corresponds to the first trench 410, and the second interconnect opening 240 corresponds to the second trench 420.

[0157] In this embodiment, in the step of etching the first dielectric layer 100 at the bottom of the first trench 410 and the second trench 420, the first dielectric layer 100 is etched using the mask sidewall 510, the first partition structure 710 and the second partition structure 720 as masks.

[0158] In this embodiment, the interconnection opening corresponding to the first trench 410 is the first interconnection opening 230, the interconnection opening corresponding to the second trench 420 is the second interconnection opening 240, the portion of the first dielectric layer 100 retained by the first isolation structure 710 is the first isolation layer 110, and the portion of the first dielectric layer 100 retained by the second isolation structure 720 is the second isolation layer 120.

[0159] In other words, in this embodiment, the first partition layer 110 and the second partition layer 120 are integral with the first dielectric layer 100, eliminating the need for the steps of forming the first partition layer 110 and the second partition layer 120, thus simplifying the process and improving process efficiency.

[0160] In this embodiment, in the first direction, the first interconnection opening 230 of the second lead region 100V2 and the non-lead region 100T is isolated by the first isolation layer 110, and the second interconnection opening 240 of the first lead region 100V1 and the non-lead region 100T is isolated by the second isolation layer 120.

[0161] like Figure 19 As shown, Figure 19 The dashed boxes in the figure represent the outlines of the first partition layer 110 and the second partition layer 120.

[0162] The first interconnect opening 230 and the second interconnect opening 240 are used to provide spatial locations for the formation of metal interconnect lines.

[0163] In this embodiment, the first trench 410 and the second trench 420 have high morphological quality, dimensional accuracy and positional accuracy, thereby improving the accuracy of pattern transfer and correspondingly improving the pattern accuracy of interconnect openings. This ensures that the morphology and layout of the subsequently formed metal lines meet the design requirements and improves the performance of the metal lines.

[0164] In this embodiment, the first dielectric layer 100 is etched using the mask sidewall 510, the first partition structure 710, and the second partition structure 720 as masks to form interconnect openings. Compared with the scheme of directly forming interconnect openings in the first dielectric layer 100, this scheme is easier to form mask sidewalls 510 with smaller dimensions in the second direction, and the dimensions and positions of the mask sidewalls 510, the first partition structure 710, and the second partition structure 720 are more accurate. This is beneficial for accurately controlling the pattern accuracy of the interconnect openings and correspondingly improving the accuracy of pattern transmission.

[0165] In this embodiment, a dry etching process is used to etch the first dielectric layer 100 at the bottom of the first trench 410 and the second trench 420 to form interconnect openings.

[0166] Dry etching processes are characterized by anisotropic etching. Therefore, dry etching is more directional, which is beneficial for improving the sidewall morphology quality and dimensional accuracy of interconnect openings.

[0167] Reference Figure 21 and Figure 22 ,in, Figure 21 It is a top view. Figure 22 a is Figure 21 Cross-sectional view along the BB direction. Figure 22 b is Figure 21 A cross-sectional view along the B'B' direction shows metal lines formed in interconnect openings, wherein the metal line 210 is located in the first interconnect opening 230 and the metal line 220 is located in the second interconnect opening 240.

[0168] In this embodiment, the metal wire is made of one or more of copper, aluminum, and copper alloys to achieve better conductivity.

[0169] In this embodiment, the first metal line 210 and the second metal interconnect 220 are metal interconnects in the same layer, therefore, the first metal line 210 and the second metal interconnect 220 are made of the same material.

[0170] In this embodiment, the first dielectric layer 100 retained between adjacent first metal lines 210 and second metal lines 220 is transmitted through the mask sidewall 510, so the size of the interval d1 between adjacent first metal lines 210 and second metal lines 220 is equal.

[0171] Since the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime when the semiconductor interconnect reliability structure is used to test the time-related dielectric breakdown lifetime or the breakdown voltage, in this embodiment, the spacing d1 between adjacent first metal lines 210 and second metal lines 220 is equal. Therefore, during the test, the dielectric breakdown lifetime between adjacent first metal lines 210 and second metal lines 220 can be detected more accurately, and the situation of large error in the test result caused by different spacing dimensions between adjacent first metal lines 210 and second metal lines 220 is largely avoided.

[0172] Reference Figures 23 to 25 ,in, Figure 23 It is a top view. Figure 24 a is Figure 23 Cross-sectional view along the BB direction. Figure 24 b is Figure 23 A cross-sectional view along the B'B' direction. Figure 25 yes Figure 23 A cross-sectional view along the CC direction shows that after the metal line is formed, a second dielectric layer 300 is formed on the first dielectric layer 100 and the metal line.

[0173] The second dielectric layer 300 is used to achieve electrical isolation between metal interconnect structures (e.g., via interconnect structures) in the back-end process.

[0174] The description of the material of the second dielectric layer 300 can be found in the previous description of the first dielectric layer 100, and will not be repeated here.

[0175] Continue to refer to Figures 23 to 25 Through-hole interconnect structures 310 are formed in the second dielectric layer 300 of the first lead region 100V1 and the second lead region 100V2, respectively. The through-hole interconnect structure 310 of the first lead region 100V1 is located on the top of the metal line corresponding to the first trench 410 and is in contact with the metal line, and is used as the test signal loading end of the metal line. The through-hole interconnect structure 310 of the second lead region 100V2 is located on the top of the metal line corresponding to the second trench 420 and is in contact with the metal line, and is used as the test signal loading end of the metal line.

[0176] In this embodiment, the through-hole interconnect structure 310 is formed in the same step, which simplifies the process steps and improves the process efficiency.

[0177] Typically, when forming the via interconnect structure 310, the size of the via interconnect structure 310 expands along the second direction.

[0178] Therefore, in this embodiment, along the second direction, the width dimension of the through-hole interconnect structure 310 is greater than the width dimension of the metal line in which it is located.

[0179] In other words, the distance w1 between the via interconnect structure 310 at the top of the first metal line 210 and the adjacent second metal line 220 is less than the distance d1 between the adjacent first metal line 210 and the second metal line 220. Similarly, the distance w2 between the via interconnect structure 310 on the second metal line 220 and the adjacent first metal line 210 is less than the distance d1 between the adjacent first metal line 210 and the second metal line 220.

[0180] Since the first isolation layer 110 and the second isolation layer 120 achieve physical and electrical isolation between the first lead area 100V1 and the second metal line 220 in the non-lead area 100T, and also achieve physical and electrical isolation between the second lead area 100V2 and the first metal line 210 in the non-lead area 100T, even if the spacings w1 and w2 are both smaller than the spacing d1 between adjacent first metal lines and second metal lines, when testing the dielectric breakdown lifetime between adjacent first metal lines 210 and second metal lines 220, the probability of test errors caused by the spacings w1 and w2 being smaller than the spacing d1 between adjacent first metal lines and second metal lines is reduced.

[0181] Because the spacing w1 between the via interconnect structure 310 at the top of the first metal line 210 and the adjacent second metal line 220 is smaller than the spacing d1 between the adjacent first metal line 210 and the second metal line 220, during the manufacturing process, process errors may cause the via interconnect structure 310 at the top of the first metal line 210 to mistakenly contact the adjacent second metal line 220. This could easily cause the portion of the second metal line 220 located in the first lead region 100V1 to become energized during the operation of the semiconductor interconnect reliability structure. If the second metal line 220 has only one second isolation layer 120 along the first direction, it could easily lead to the dielectric breakdown between the ends of the second metal line 220 located on both sides of the second isolation layer 120 during the TDDB test of the dielectric breakdown lifetime between the adjacent first metal line 210 and the second metal line 220. Since lifetime is used as a test result, it affects the test accuracy of semiconductor interconnect reliability structure. Therefore, in this embodiment, along the first direction, the second metal line 220 has multiple second isolation layers 120. The portion of each second metal line 210 that is loaded with a signal through the via interconnect structure 310 can be isolated from the portion located in the first lead region 100V1 by non-connected metal lines with a large spacing. This helps to avoid the situation where the dielectric breakdown lifetime between the portion of each first metal line 210 loaded with a signal and the portion located in the first lead region 100V1 is mistakenly taken as the test result due to the influence of the via interconnect structure 310 located in the first lead region 100V1. The same applies to the first metal line 210.

[0182] In this embodiment, at the top of each first metal wire 210, in the first lead region 100V1 or the second lead region 100V2, the number of via interconnect structures 310 is 2 to 5. For an analysis of the number of via interconnect structures 310, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0183] In this embodiment, at the top of each first metal wire 210, in the first lead area 100V1 or the second lead area 100V2, there are 3 through-hole interconnect structures 310. Under the premise of ensuring simple formation process, as long as one of the through-hole interconnect structures 310 is electrically connected, the first metal wire 210 is electrically connected successfully. Therefore, by using 3 through-hole interconnect structures 310, the test signal loading of the first metal wire 210 can be guaranteed to a large extent.

[0184] In this embodiment, the material of the through-hole interconnect structure 310 is a metallic material. Metallic materials have good electrical conductivity, which is beneficial for improving the electrical connection performance between the first metal line 210 and the external interconnect structure, and consequently, for improving the accuracy of the test results.

[0185] In this embodiment, the material of the through-hole interconnect structure 310 includes one or more of copper, aluminum, and copper alloys.

[0186] In this embodiment, at the top of each second metal wire 220, in the first lead area 100V1 or the second lead area 100V2, the number of through-hole interconnect structures 310 is 2 to 5.

[0187] In this embodiment, at the top of each second metal wire 220, in the first lead area 100V1 or the second lead area 100V2, there are 3 through-hole interconnect structures 310.

[0188] In this embodiment, the via interconnect structure 310 at the top of each second metal line 220 is similar to the via interconnect structure 310 at the top of each first metal line 210 described above, and will not be repeated here.

[0189] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor interconnect reliability structure, characterized in that, include: Multiple metal wires extend along a first direction and are arranged parallel to each other along a second direction, the second direction being perpendicular to the first direction. The metal wires along the first direction include a lead area and a non-lead area. The lead area includes a first lead area and a second lead area located on both sides of the non-lead area. Both the first lead area and the second lead area are used to load test signals. The metal wires along the second direction include alternating first metal wires and second metal wires. A first partition layer extends through the first metal wire near the second lead area in the non-lead area and is used to divide the first metal wire in the first direction. Each first metal wire has multiple first partition layers, and the multiple first partition layers are arranged along the first direction. The second partition layer extends through the second metal wire near the first lead area in the non-lead area and is used to divide the second metal wire in the first direction. Each second metal wire has multiple second partition layers, and the multiple second partition layers are arranged along the first direction. Through-hole interconnect structures are respectively located on the top of the first metal wire in the first lead area and on the top of the second metal wire in the second lead area. The through-hole interconnect structure in the first lead area is used as the test signal loading end of the first metal wire, and the through-hole interconnect structure in the second lead area is used as the test signal loading end of the second metal wire.

2. The semiconductor interconnect reliability structure as described in claim 1, characterized in that, In the second direction, adjacent first partition layers are staggered in the first direction; in the second direction, adjacent second partition layers are staggered in the first direction.

3. The semiconductor interconnect reliability structure as described in claim 1, characterized in that, Multiple first partition layers in the same first metal wire are located in the same row, and in the first direction, the distance between the first partition layers in adjacent rows is less than the distance between adjacent first partition layers; Multiple second partition layers in the same second metal wire are located in the same row, and in the first direction, the distance between the second partition layers in adjacent rows is less than the distance between adjacent second partition layers.

4. The semiconductor interconnect reliability structure as described in claim 3, characterized in that, Alignment settings for two adjacent rows of first partition layers; alignment settings for two adjacent rows of second partition layers.

5. The semiconductor interconnect reliability structure as described in claim 1, characterized in that, Each first metal wire has two first partition layers arranged along the second direction; each second metal wire has two second partition layers arranged along the second direction.

6. The semiconductor interconnect reliability structure as described in claim 1, characterized in that, The semiconductor interconnect reliability structure also includes a dielectric layer; The metal lines are located in the dielectric layer and are spaced apart from each other along the second direction by the dielectric layer.

7. The semiconductor interconnect reliability structure as described in claim 6, characterized in that, The first partition layer, the second partition layer, and the dielectric layer are an integral structure.

8. The semiconductor interconnect reliability structure as described in claim 6, characterized in that, The dielectric layer material includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

9. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, Along the second direction, the length dimension of the first partition layer and the second partition layer is greater than or equal to 18 nm.

10. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, Along the first direction, the spacing between adjacent first partition layers in the same first metal line and the spacing between adjacent second partition layers in the same second metal line are both greater than or equal to 100 nm. In the second direction, the spacing between adjacent first partition layers with opposite ends and the spacing between adjacent second partition layers with opposite ends are both greater than or equal to 80 nm. The diagonal spacing between the first partition layers that are diagonally adjacent and the diagonal spacing between the second partition layers that are diagonally adjacent are both greater than or equal to 50 nm.

11. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, Along the second direction, the width dimension of the through-hole interconnect structure is greater than the width dimension of the metal line in which it is located.

12. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, The spacing between adjacent first and second metal lines is equal.

13. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, The materials of the first and second partition layers both include one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

14. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, The material of the metal wire includes one or more of copper, aluminum, and copper alloys.

15. The semiconductor interconnect reliability structure according to any one of claims 1 to 8, characterized in that, The semiconductor interconnect reliability structure includes the TDDB semiconductor interconnect reliability structure or the VBD semiconductor interconnect reliability structure.

16. A method for forming a reliable semiconductor interconnect structure, characterized in that, include: A substrate is provided, on which a first dielectric layer is formed. The first dielectric layer includes a non-lead region and a lead region along a first direction. The lead region includes a first lead region and a second lead region located on both sides of the non-lead region. Both the first lead region and the second lead region are used to load test signals. A core layer covering the first dielectric layer is formed; In the core layer, a first trench and a second trench are formed, extending along the first direction and arranged alternately in parallel along the second direction. In the first direction, the first trench has a plurality of first intervals for dividing the first trench into a plurality of first sub-trenches. The plurality of first intervals are located in the non-lead area near the second lead area. In the first direction, the second trench has a plurality of second intervals for dividing the second trench into a plurality of second sub-trenches. The plurality of second intervals are located in the non-lead area near the first lead area. The first dielectric layer at the bottom of the first trench and the second trench is etched to form interconnect openings; Metal wires are formed in the interconnection openings; After the metal line is formed, a second dielectric layer is formed on the first dielectric layer and the metal line; Through-hole interconnect structures are formed in the second dielectric layer of the first lead region and the second lead region, respectively. The through-hole interconnect structure of the first lead region is located on the top of the metal line corresponding to the first trench and is in contact with the metal line, and is used as the test signal loading end of the metal line. The through-hole interconnect structure of the second lead region is located on the top of the metal line corresponding to the second trench and is in contact with the metal line, and is used as the test signal loading end of the metal line.

17. The method for forming a semiconductor interconnect reliability structure as described in claim 16, characterized in that, In the second direction, adjacent first intervals are staggered in the first direction; in the second direction, adjacent second intervals are staggered in the first direction.

18. The method for forming a semiconductor interconnect reliability structure as described in claim 16, characterized in that, In the same first trench, multiple first intervals are located in the same row, and in the first direction, the distance between the first intervals of adjacent rows is less than the distance between adjacent first intervals; In the same second trench, multiple second intervals are located in the same row, and in the first direction, the distance between the second intervals of adjacent rows is less than the distance between adjacent second intervals.

19. The method for forming a semiconductor interconnect reliability structure as described in claim 16, characterized in that, Alignment settings at the first interval between two adjacent rows; alignment settings at the second interval between two adjacent rows.

20. The method for forming a semiconductor interconnect reliability structure as described in claim 16, characterized in that, Each first trench has two first partitions arranged along the second direction; each second trench has two second partitions arranged along the second direction.

21. The method for forming a semiconductor interconnect reliability structure as described in claim 16, characterized in that, The steps of forming the first trench and the second trench include: forming a plurality of first partition structures in the core layer near the second lead area in the non-lead area, the plurality of first partition structures being arranged in multiple rows in the second direction, and each row having a plurality of first partition structures arranged along the first direction; In the non-lead area near the first lead area, a second partition structure is formed in the core layer. Multiple second partition structures are arranged in multiple rows in the second direction. Each row has multiple second partition structures arranged along the first direction. The first partition structure and the second partition structure are arranged alternately along the second direction. After the first partition structure and the second partition structure are formed, a first groove is formed in the core layer that extends along the first direction and is arranged parallel to the second direction. The first partition structure divides the first groove along the first direction, and in the second direction, the first groove exposes the sidewall of the second partition structure. A mask sidewall is formed on the sidewall of the first trench; After the mask sidewall is formed, the core layer is removed to form a second trench. The second partition structure divides the second trench along the first direction, and adjacent second trenches are isolated from the first trench by the mask sidewall. In the step of etching the first dielectric layer at the bottom of the first trench and the second trench, the first dielectric layer is etched using the mask sidewall, the first partition structure and the second partition structure as masks.

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