A semiconductor structure and a method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a gate structure, a capping layer, and a first sacrificial structure. The substrate includes discrete semiconductor channels disposed on top of the substrate and extending vertically. The gate structure is disposed in the central region of the semiconductor channels and includes a ring structure and a bridge structure; the ring structure surrounds the semiconductor channels, and the bridge structure penetrates the semiconductor channels and extends along the penetration direction to the inner wall of the ring structure. The capping layer is located between adjacent semiconductor channels and includes a first connecting hole extending vertically. The first sacrificial structure is located above the capping layer and includes a second connecting hole extending vertically, the second connecting hole connecting to the top of the semiconductor channels through the first connecting hole, and the inner sidewall of the second connecting hole has an irregular shape. This disclosure improves the overall electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] Higher density efficiency can be achieved when using a vertical gate all around (VGAA) transistor structure as the access transistor for dynamic memory. However, in related technologies, the capacitor connected to the access transistor has a low capacitance, which affects the overall electrical performance of the semiconductor structure. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which can improve the overall electrical performance of the semiconductor structure.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a semiconductor structure, including:

[0007] A substrate, including discrete semiconductor channels; the semiconductor channels are disposed on the top of the substrate and extend in a vertical direction;

[0008] A gate structure, disposed in the middle region of the semiconductor channel, includes a ring structure and a bridge structure, wherein the ring structure surrounds the semiconductor channel, and the bridge structure penetrates the semiconductor channel and extends along the penetration direction to the inner wall of the ring structure;

[0009] A capping layer is located in the spacer region between adjacent semiconductor channels; the capping layer includes a first connecting hole extending along the vertical direction;

[0010] A first sacrificial structure is located above the cover layer; the first sacrificial structure includes a second connecting hole extending along the vertical direction, the second connecting hole connecting to the top of the semiconductor channel through the first connecting hole; the inner sidewall of the second connecting hole has an irregular shape.

[0011] In the above scheme, the first sacrificial structure further includes: an additional doped region and a bulk region; the doping concentration in the additional doped region is higher than the doping concentration in the bulk region;

[0012] In the first sacrificial structure, the diameter of the second connecting hole located in the additional doped region is larger than its diameter located in the body region.

[0013] In the above scheme, in the first sacrificial structure, the additional doped region and the body region are arranged alternately along the vertical direction.

[0014] In the above scheme, the thickness of the additional doped region along the vertical direction is less than the thickness of the body region along the vertical direction.

[0015] In the above scheme, the material of the first sacrificial structure is borosilicate glass, wherein the boron content of the additional doped region is higher than the boron content of the bulk region.

[0016] In the above scheme, the top of the first connecting hole is higher than the top of the semiconductor channel, and the top of the semiconductor channel and a portion of its sidewalls near the top are exposed by the first connecting hole; in the cover layer, the middle aperture of the first connecting hole is larger than its top aperture or bottom aperture.

[0017] In the above scheme, the length of the ring structure along the vertical direction is less than the length of the semiconductor channel along the vertical direction; the length of the bridge structure along the vertical direction is less than or equal to the length of the ring structure along the vertical direction.

[0018] In the above scheme, the semiconductor structure further includes: a dielectric layer; the dielectric layer includes: a first portion and a second portion; the first portion of the dielectric layer is located between the gate structure and the semiconductor channel; the second portion of the dielectric layer is located between the ring structure and the capping layer; the thickness of the second portion of the dielectric layer is greater than the thickness of the first portion of the dielectric layer.

[0019] In the above scheme, the width of the middle region of the semiconductor channel and the top width of the semiconductor channel are both smaller than the bottom width of the semiconductor channel.

[0020] In the above scheme, the semiconductor structure further includes: a first isolation layer located in the interval region and covered by the cover layer; the ring structure is located between the first isolation layer and the semiconductor channel.

[0021] In the above scheme, the semiconductor structure further includes: a bit line, located inside the substrate, and electrically connected to the bottom of the semiconductor channel.

[0022] This disclosure also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including discrete semiconductor channels; the semiconductor channels being disposed on the top of the substrate and extending in a vertical direction; forming a gate structure in a central region of the semiconductor channels, the gate structure including a ring structure and a bridge structure, wherein the ring structure surrounds the semiconductor channels, and the bridge structure penetrates the semiconductor channels and extends in a penetration direction to the inner wall of the ring structure; forming a capping layer; the capping layer being located in a spacer region between adjacent semiconductor channels, the capping layer including a first connecting hole extending in the vertical direction; forming a first sacrificial structure; the first sacrificial structure being located above the capping layer, the first sacrificial structure including a second connecting hole extending in the vertical direction, the second connecting hole communicating with the top of the semiconductor channels through the first connecting hole; the inner sidewall of the second connecting hole having an irregular shape.

[0023] In the above scheme, the steps of forming the capping layer and the first sacrificial structure include: depositing an initial capping layer; depositing a first sacrificial layer on the initial capping layer; forming a patterned first mask on the first sacrificial layer; the first mask includes a third via, the third via corresponding to the semiconductor channel; etching according to the third via until the top of the semiconductor channel, forming a second via in the first sacrificial layer, and forming the first via in the initial capping layer, thereby forming the first sacrificial structure and the capping layer respectively; wherein, the first sacrificial structure further includes an additional doped region and a body region; the aperture of the second via located in the additional doped region is larger than its aperture located in the body region.

[0024] In the above scheme, before etching according to the third connecting hole until the top of the semiconductor channel, the method further includes: ion implantation of the first sacrificial layer to form the additional doped region and the body region in the first sacrificial layer; the doping concentration in the additional doped region is higher than the doping concentration in the body region; the additional doped region and the body region are alternately arranged along the vertical direction, and the thickness of the additional doped region along the vertical direction is less than the thickness of the body region along the vertical direction.

[0025] In the above scheme, the step of forming the gate structure includes: forming a groove in the semiconductor channel; forming a second sacrificial layer in the groove; forming a filling layer in the groove, the filling layer being located on the second sacrificial layer and filling the remaining groove; removing the second sacrificial layer to form a through-hole; the through-hole penetrating the semiconductor channel; forming an initial dielectric layer on the sidewall of the central region of the semiconductor channel and the inner wall of the through-hole; the portion of the initial dielectric layer located in the central region forming a first portion of the dielectric layer, the first portion of the dielectric layer being located between the gate structure and the semiconductor channel; forming a gate layer around the sidewall of the initial dielectric layer and filling the through-hole; wherein the portion of the gate layer filling the through-hole forms the bridge structure; etching the portion of the gate layer surrounding the sidewall of the initial dielectric layer to form the ring structure.

[0026] Therefore, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a gate structure, a capping layer, and a first sacrificial structure. The substrate includes discrete semiconductor channels disposed on the top of the substrate and extending vertically. The gate structure is disposed in the middle region of the semiconductor channels and includes a ring structure and a bridge structure. The ring structure surrounds the semiconductor channels, and the bridge structure penetrates the semiconductor channels and extends to the inner wall of the ring structure in the penetration direction. The capping layer is located in the spacer region between adjacent semiconductor channels and includes a first connecting hole extending vertically. The first sacrificial structure is located above the capping layer and includes a second connecting hole extending vertically, which connects to the top of the semiconductor channels through the first connecting hole. The inner sidewall of the second connecting hole has an irregular shape. Because the inner sidewall of the second connecting hole has an irregular shape, a capacitor can be formed in the second connecting hole. The capacitor plate covers the inner sidewall of the second connecting hole, thus increasing the area of ​​the capacitor plate and improving the capacitance. Therefore, this disclosure improves the overall electrical performance of the semiconductor structure. Attached Figure Description

[0027] Figure 1 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 1 ;

[0028] Figure 2 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 2 ;

[0029] Figure 3 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 3 ;

[0030] Figure 4A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 4 ;

[0031] Figure 5 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 5 ;

[0032] Figure 6 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 6 ;

[0033] Figure 7 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 7 ;

[0034] Figure 8 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 8 ;

[0035] Figure 9 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 9 ;

[0036] Figure 10 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 10 ;

[0037] Figure 11 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 10 one;

[0038] Figure 12 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 1 ;

[0039] Figure 13 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 2 ;

[0040] Figure 14 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 3 ;

[0041] Figure 15 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 4 ;

[0042] Figure 16 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 5 ;

[0043] Figure 17 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 6 ;

[0044] Figure 18 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 7 ;

[0045] Figure 19 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 8 ;

[0046] Figure 20 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 9 ;

[0047] Figure 21 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 ;

[0048] Figure 22 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 one;

[0049] Figure 23 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 two;

[0050] Figure 24 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 three;

[0051] Figure 25 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 Four. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0053] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0054] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0056] Figure 1 This is an optional structural diagram of the semiconductor structure provided in the embodiments of this disclosure, such as... Figure 1 As shown, the semiconductor structure 80 includes: a substrate 00, a gate structure 10, a capping layer 20, and a first sacrificial structure 30. Wherein:

[0057] The substrate 00 includes discrete semiconductor channels 01; the semiconductor channels 01 are disposed on the top of the substrate 00 and extend in the vertical direction Z.

[0058] A gate structure 10 is disposed in the middle region of the semiconductor channel 01, including a ring structure 101 and a bridge structure 102, wherein the ring structure 101 surrounds the semiconductor channel 01, and the bridge structure 102 penetrates the semiconductor channel 01 and extends to the inner wall of the ring structure 101 in the penetration direction.

[0059] Cover layer 20 is located in the spacer region between adjacent semiconductor channels 01; cover layer 20 includes a first connecting hole 201 extending in the vertical direction Z;

[0060] The first sacrificial structure 30 is located above the cover layer 20; the first sacrificial structure 30 includes a second connecting hole 301 extending in the vertical direction Z, the second connecting hole 301 being connected to the top of the semiconductor channel 01 through the first connecting hole 201; the inner sidewall of the second connecting hole 301 is irregularly shaped.

[0061] The first sacrificial structure 30 also includes an additional doped region 302 and a bulk region 303; the doping concentration in the additional doped region 302 is higher than the doping concentration in the bulk region 303.

[0062] In this embodiment, the substrate 00 may include at least one semiconductor material, such as group IV elements like silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or group III-V compounds like gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), and indium gallium arsenide (InGaAs). The following description uses silicon as an example of substrate 00. The semiconductor channel 01 may contain doping elements to improve its conductivity. These doping elements may be p-type or n-type. The n-type doping element may be at least one of arsenic (As), phosphorus (P), or antimony (Sb), while the p-type doping element may be at least one of boron (B), indium (In), or gallium (Ga). The gate structure 10 may be made of titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), or tungsten (W), among other conductive materials. The following description uses titanium nitride as an example of titanium nitride.

[0063] Figure 2 The pattern of the second connecting hole 301 is shown from a top view. Figure 1 For along Figure 2 A cross-sectional view taken along line A-A1. By etching the first sacrificial structure 30 according to the mask, the following can be obtained: Figure 1 and Figure 2 The second connecting hole 301 is shown. Furthermore, in subsequent processes, capacitors can be formed in the first connecting hole 201 and the second connecting hole 301, with the capacitor plates covering the inner sidewalls of the first connecting hole 201 and the second connecting hole 301. It should be noted that... Figure 2 The first direction X and the second direction Y shown are both perpendicular to Figure 1 The vertical direction Z is shown. The first direction X and the second direction Y can be perpendicular to each other or form any angle. The following explanation uses the example of the first direction X being perpendicular to the second direction Y.

[0064] In this embodiment of the present disclosure, the inner wall of the second connecting hole 301 has an irregular shape, that is, the cross-sectional profile of the inner wall of the second connecting hole 301 is not composed of only straight lines. Figure 3 Another optional structural schematic diagram showing the cross-sectional profile of the inner wall of the second connecting hole 301, see reference. Figure 1 and Figure 3 With the length of the connecting hole remaining constant along the vertical direction Z, compared to connecting holes with regular shapes such as cylinders on their inner walls, Figure 1 and Figure 3 The inner wall of the second connecting hole 301 shown has a larger area.

[0065] It is understandable that a capacitor can be formed in the second connecting hole 301, with the capacitor plate covering the inner sidewall of the second connecting hole 301. In this way, the area of ​​the capacitor plate can be increased, the capacitance can be improved, and thus the overall electrical performance of the semiconductor structure 80 is improved.

[0066] In some embodiments of this disclosure, the first sacrificial structure 30 further includes an additional doped region 302 and a body region 303; the doping concentration in the additional doped region 302 is higher than the doping concentration in the body region 303. In the first sacrificial structure 30, the aperture of the second via 301 located in the additional doped region 302 is larger than its aperture located in the body region 303. In these embodiments, because the doping concentration in the additional doped region 302 is higher than that in the body region 303, the additional doped region 302 is easier to etch than the body region 303, and the additional doped region 302 is more likely to form an isotropic etched structure.

[0067] refer to Figure 4 The portion of the second connecting hole 301 located in the additional doped region 302 has an arc-shaped cross-sectional profile, thus forming an isotropic etching structure; while the portion of the second connecting hole 301 located in the body region 303 has a straight cross-sectional profile, thus forming an anisotropic etching structure; therefore, the cross-sectional profile of the inner wall of the second connecting hole 301 is wavy, that is, the aperture of the second connecting hole 301 located in the additional doped region 302 is larger than the aperture of its location in the body region 303.

[0068] In some embodiments of this disclosure, reference is made to Figure 4 The first sacrificial structure 30 can be made of boro-phospho-silicate glass (BPSG). Both the additional doped region 302 and the bulk region 303 are doped with boron, wherein the boron content of the additional doped region 302 is higher than that of the bulk region 303. In some embodiments, the bulk region 303 can also be undoped BPSG, while the additional doped region 302 is boron-doped BPSG.

[0069] In some embodiments of this disclosure, reference is made to Figure 4 In the first sacrificial structure 30, the additional doped region 302 and the bulk region 303 are arranged alternately along the vertical direction Z. The thickness of the additional doped region 302 along the vertical direction Z is less than the thickness of the bulk region 303 along the vertical direction Z.

[0070] In this embodiment of the disclosure, the first sacrificial structure 30 can be doped using an ion implantation (IMP) process to form an additional doped region 302. By controlling the ion implantation to use different energies, regions at different depths in the first sacrificial structure 30 can be doped, thereby forming alternating additional doped regions 302 and bulk regions 303.

[0071] Understandably, because the additional doped region 302 is easier to etch than the bulk region 303, the inner wall of the second connecting hole 301 has an irregular shape, such as... Figure 4 As shown in the example, the aperture of the second connecting hole 301 located in the additional doped region 302 is larger than that located in the body region 303, and the cross-sectional profile of the inner wall of the second connecting hole 301 is wavy. The capacitor formed in the second connecting hole 301 has its plates covering the inner wall of the second connecting hole 301; therefore, the area of ​​the capacitor plates can be increased, thereby improving the capacitance.

[0072] In some embodiments of this disclosure, reference is made to Figure 1 The top of the first connecting hole 201 is higher than the top of the semiconductor channel 01. The top of the semiconductor channel 01 and a portion of its sidewalls near the top are exposed by the first connecting hole 201.

[0073] In this embodiment of the present disclosure, capacitors can be formed in the first connecting hole 201 and the second connecting hole 301 in subsequent processes. The first connecting hole 201 exposes the top of the semiconductor channel 01 and a portion of the sidewall near the top, thereby increasing the contact area between the semiconductor channel 01 and the subsequently formed capacitor, thus reducing the contact resistance and improving the electrical performance.

[0074] In some embodiments of this disclosure, reference is made to Figure 1 In the cover layer 20, the central aperture of the first connecting hole 201 is larger than its top or bottom aperture. It should be noted that the central portion of the first connecting hole 201 refers to the area between its top and bottom. Since a capacitor plate can be formed in the first connecting hole 201, an excessively large top or bottom aperture would make it difficult to protect the capacitor and increase the risk of a short circuit. Therefore, the top or bottom aperture of the first connecting hole 201 should not be too large. Furthermore, increasing the central aperture of the first connecting hole 201, making it larger than its top or bottom aperture, not only avoids increasing the risk of a short circuit but also increases the surface area of ​​the electrode plate, thereby improving the capacitance.

[0075] In some embodiments of this disclosure, reference is made to Figure 1 The top of the capping layer 20 is higher than the top of the semiconductor channel 01. It can be understood that the top of the capping layer 20 is higher than the top of the semiconductor channel 01, thereby isolating the capacitor plates formed in the first through hole 201 from each other and preventing short circuits.

[0076] In some embodiments of this disclosure, Figure 1 The cover layer 20 shown may be made of boron nitride silicon (SiB). x N yWhere the ratio of x to y represents the ratio of the number of boron to nitrogen atoms in boron nitride silicon, and 4 ≥ y > x > 0, yx ≤ 2. In some embodiments, this boron nitride silicon SiB x N y It is SiB2N4 or SiB 2.6 N4. It should be noted that SiB... x N y The notation does not indicate that the number of silicon atoms is 1. Compared to general materials, boron nitride silicon has a higher etching rate, meaning it is easier to etch. Therefore, a boron nitride silicon capping layer 20 is used, which makes it easier to form a first connecting hole 201 with a larger central aperture, thereby increasing the surface area of ​​the electrode plate and improving capacitance.

[0077] In this embodiment, boron can be introduced into the cavity during silicon nitride formation to form boron silicon nitride. Simultaneously, the ratio of boron to nitrogen atoms in the boron silicon nitride can be adjusted by controlling the flow rate ratio of nitrogen and boron atoms. It should be noted that boron silicon nitride is easier to etch than silicon nitride. Furthermore, doping boron atoms into silicon nitride reduces its stress, meaning lower stress and weaker internal interactions, making it less prone to structural damage and thus improving device performance. When the difference between the number of nitrogen and boron atoms is less than or equal to 2, the nitrogen content in boron silicon nitride can be increased, thereby increasing the etching rate and reducing stress. Conversely, if the difference is greater than 2, the boron content is lower, resulting in a lower etching rate and higher stress.

[0078] Figure 5 This is a cross-sectional view showing a portion of the semiconductor structure located below the first sacrificial structure. In some embodiments of this disclosure, reference is made to... Figure 5 The semiconductor structure 80 further includes a dielectric layer 40. The dielectric layer 40 includes a first portion 401 and a second portion 402. The first portion 401 of the dielectric layer 40 is located between the gate structure 10 and the semiconductor channel 01, and the second portion 402 of the dielectric layer 40 is located between the ring structure 101 and the capping layer 20. The thickness of the second portion 402 of the dielectric layer 40 is greater than the thickness of the first portion 401 of the dielectric layer 40, and this thickness can be the thickness along a first direction X.

[0079] In this embodiment, the dielectric layer 40 may be made of silicon oxide (SiO). The semiconductor channel 01, the gate structure 10, and the first portion 401 of the dielectric layer 40 together constitute the first transistor. The central region of the semiconductor channel 01 forms a channel, the gate structure 10 serves as the gate of the first transistor, and the upper and lower portions of the central region of the semiconductor channel 01 form the source and drain, respectively. It should be noted that the central region of the semiconductor channel 01 is the middle portion of the semiconductor channel 01 along the vertical direction Z. The central region of the semiconductor channel 01 is located between the top and bottom of the semiconductor channel 01 and is at a certain distance from both the top and bottom. The first portion 401 of the dielectric layer 40 serves as the gate dielectric of the first transistor, while the second portion 402 of the dielectric layer 40 protects the gate structure 10 to prevent short circuits.

[0080] The first transistor is a VGAA transistor, meaning that the channel formed by the semiconductor channel 01 extends vertically, and the ring structure 101 of the gate structure 10 surrounds the channel. Therefore, under the same size, compared with transistor structures such as FinFET (Fin Field Effect Transistor), the gate of the first transistor can more fully cover the channel, thus providing stronger gate control capability.

[0081] Figure 6 and Figure 7 This shows a portion of the semiconductor structure located beneath the capping layer. Figure 7 This is a top view. Figure 6 For along Figure 7 The sectional view taken from the mid-section line A-A1.

[0082] In this embodiment of the disclosure, reference is made to Figure 7 From a top-down view, the dimensions of semiconductor channel 01 satisfy 4F. 2 (F: Minimum pattern size achievable under given process conditions), meaning that the distance between the center points of two adjacent semiconductor channels 01 in the first direction X is 2F, and the distance between the center points of two adjacent semiconductor channels 01 in the second direction Y is also 2F. Therefore, the integration density of the semiconductor structure 80 is improved. In some embodiments, when forming memory cells on the semiconductor channels 01, the memory cells can also be arranged according to 4F. 2 arrangement.

[0083] In this embodiment of the disclosure, combined with Figure 6 and Figure 7The bridge structure 102 of the gate structure 10 penetrates the semiconductor channel 01 and extends along the penetration direction (i.e., the second direction Y) to the inner wall of the ring structure 101. The semiconductor channel 01 is penetrated to form a through hole, which is filled by the bridge structure 102, meaning the inner wall of the through hole is covered by the bridge structure 102. In this way, the bridge structure 102 covers a portion of the channel, increasing the coverage area of ​​the gate structure 10 over the channel, making the channel easier to control. This further enhances the control capability of the gate of the formed first transistor and also improves the overall electrical performance of the semiconductor structure 80.

[0084] In some embodiments of this disclosure, reference is made to Figure 6 The length of the ring structure 101 along the vertical direction Z is less than the length of the semiconductor channel 01 along the vertical direction Z, and the length of the bridge structure 102 along the vertical direction Z is less than or equal to the length of the ring structure 101 along the vertical direction Z.

[0085] It is understandable that the length of the ring structure 101 along the vertical direction Z is less than the length of the semiconductor channel 01 along the vertical direction Z. The area of ​​the semiconductor channel 01 not surrounded by the ring structure 101 can form the source and drain of the transistor. Based on this, the length of the ring structure 101 along the vertical direction Z can be set to be longer. In this way, the coverage area of ​​the gate structure 10 over the channel is increased, thereby further improving the control capability of the gate of the formed first transistor.

[0086] In some embodiments of this disclosure, reference is made to Figure 6 The width of the middle region and the top width of the semiconductor channel 01 are both smaller than the bottom width of the semiconductor channel 01. It should be noted that the middle region of the semiconductor channel 01 is the middle part of the semiconductor channel 01 along the vertical direction Z. The middle region of the semiconductor channel 01 lies between the top and bottom of the semiconductor channel 01, and is at a certain distance from both the top and bottom.

[0087] It is understandable that if the width of the middle region of the semiconductor channel 01 is smaller than the bottom width of the semiconductor channel 01, then the ring structure 101 of the gate structure 10 can be made thicker, which helps to reduce the resistance of the ring structure 101, reduce the gate voltage loss of the formed first transistor, and further improve the gate control capability of the first transistor.

[0088] In some embodiments of this disclosure, reference is made to Figure 5 , Figure 6 and Figure 7 The semiconductor structure 80 also includes a first isolation layer 41. The first isolation layer 41 is located in the spacer region between adjacent semiconductor channels 01, and the first isolation layer 41 is covered by the capping layer 20. The ring structure 101 is located between the first isolation layer 41 and the semiconductor channels 01.

[0089] In this embodiment, the first isolation layer 41 extends along the second direction Y to isolate adjacent semiconductor channels 01. Additionally, the gate structure 10 arranged in the second direction Y is connected in series with word lines 50 extending along the second direction Y, and the first isolation layer 41 also serves to isolate adjacent word lines 50. The material of the first isolation layer 41 may be silicon nitride (SiN).

[0090] It is understandable that since the gate structure 10 is connected in series with word lines 50, the word lines 50 contact the semiconductor channel 01 through the gate structure 10. Simultaneously, due to the arrangement of the ring structure 101 and the bridge structure 102, the contact area between the gate structure 10 and the semiconductor channel 01 is increased. Therefore, the contact area between the word lines 50 and the semiconductor channel 01 is increased, the contact resistance between the word lines 50 and the semiconductor channel 01 is reduced, the electrical stability of the word lines 50 is improved, and in other words, the control capability of the word lines 50 over the first transistor is enhanced.

[0091] In some embodiments of this disclosure, such as Figure 8 As shown, the number of bridge structures 102 is at least two, and the at least two bridge structures 102 are stacked along the vertical direction Z. It can be understood that each bridge structure 102 covers the inner wall of a through hole on the semiconductor channel 01, that is, it covers a part of the channel. Using at least two bridge structures 102 can increase the coverage area of ​​the channel, thereby further improving the control capability of the gate of the formed first transistor.

[0092] In this embodiment of the disclosure, reference is made to Figure 8 Each bridge structure 102 has a width smaller than the width of the semiconductor channel 01. The semiconductor channel 01 is penetrated by the bridge structure 102, which covers the inner wall of the through hole. This increases the contact area between the gate structure 10 and the semiconductor channel 01, thereby increasing the channel length corresponding to the gate structure 10. This improves the control capability of the gate structure 10 over the semiconductor channel 01 and reduces the contact resistance between the gate structure 10 and the semiconductor channel 01.

[0093] In some embodiments of this disclosure, such as Figure 9As shown, the semiconductor structure 80 further includes a second gate structure 11. The second gate structure 11 is located above the gate structure 10. The second gate structure 11 may include a second ring structure 111 and a second bridge structure 112, wherein the second ring structure 111 surrounds the semiconductor channel 01, and the second bridge structure 112 penetrates the semiconductor channel 01. It can be understood that, since the second gate structure 11 includes the second ring structure 111 surrounding the semiconductor channel 01 and the second bridge structure 112 penetrating the semiconductor channel 01, the coverage area of ​​the second gate structure 11 over the semiconductor channel 01 is increased, thereby improving the control capability over the semiconductor channel 01 and improving the overall electrical performance of the semiconductor structure 80.

[0094] In this embodiment of the disclosure, reference is made to Figure 9 The semiconductor channel 01 and gate structure 10 can form a first transistor, with gate structure 10 serving as the gate of the first transistor. The semiconductor channel 01 and the second gate structure 11 can form a second transistor, with the second gate structure 11 serving as the gate of the second transistor. Both the first and second transistors can function as selection transistors, meaning that both the gates of the first and second transistors can receive control signals, and their control capabilities over the semiconductor channel 01 can compensate for each other. For example, if the gate of one transistor fails to completely turn off the semiconductor channel 01, the gate of the other transistor can compensate, achieving the turn-off of the semiconductor channel 01, thereby reducing leakage current in the semiconductor channel 01 and improving the overall electrical performance of the semiconductor structure 80.

[0095] In some embodiments of this disclosure, such as Figure 10 As shown, the semiconductor structure 80 further includes a third gate structure 12. The substrate 00 also includes a second semiconductor channel 03 and a third semiconductor channel 04 extending along the vertical direction Z, with the second semiconductor channel 03 and the third semiconductor channel 04 disposed at the top of each semiconductor channel 01. The third gate structure 12 is located above the gate structure 10 and is disposed in the middle region of the second semiconductor channel 03 and the third semiconductor channel 04. The third gate structure 12 includes a third ring structure 121 and a fourth ring structure 122, wherein the third ring structure 121 surrounds the second semiconductor channel 03, and the second ring structure 122 surrounds the third semiconductor channel 04.

[0096] In this embodiment of the disclosure, reference is made to Figure 10Semiconductor channel 01 and gate structure 10 can form a first transistor, second semiconductor channel 03 and third ring structure 121 can form a second transistor, and third semiconductor channel 04 and second ring structure 122 can form a third transistor. The gates of the first transistor, the second transistor, and the third transistor can all receive control signals. With the increase in the number of controlled structures, the control forces of each structure can compensate for each other, thereby improving the overall electrical performance of the semiconductor structure 80.

[0097] In some embodiments of this disclosure, such as Figure 11 As shown, the semiconductor structure 80 also includes a bit line 51. The bit line 51 is located inside the substrate 00, and the bottom of the semiconductor channel 01 is electrically connected to the bit line 51.

[0098] In this embodiment of the disclosure, reference is made to Figure 11 Bit line 51 extends along the first direction X. The substrate 00 may also include metal silicide structures 02 (area surrounded by a circular dashed box), and the various metal silicide structures 02 are connected to form bit line 51, which is electrically connected to the bottom of semiconductor channel 01.

[0099] In this embodiment of the disclosure, the material of the metal silicide structure 02 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0100] It is understandable that the metal silicide structure 02 has a relatively low resistivity compared to the unmetallized semiconductor material, which helps to reduce the resistance of bit line 51 and the contact resistance between bit line 51 and semiconductor channel 01, thereby further improving the electrical performance of semiconductor structure 80.

[0101] In this embodiment of the disclosure, combined with Figure 7 and Figure 11 The bottom of semiconductor channel 01 serves as one of the source and drain of the first transistor and can be electrically connected to bit line 51; gate structure 10 serves as the gate of the first transistor and can be connected in series with word line 50; the top of semiconductor channel 01 serves as the other of the source and drain of the first transistor and can be electrically connected to the subsequently formed capacitor structure. This forms a memory cell circuit that can be used in DRAM and other types of memory. Because the capacitor formed by semiconductor structure 80 has a larger capacitance and the gate control capability of the formed first transistor is stronger, the electrical performance of the formed memory cell circuit is improved, thereby enhancing the overall performance of the memory.

[0102] This disclosure also provides a method for manufacturing a semiconductor structure, including steps S101 to S103, which will be described in conjunction with each step.

[0103] It should be noted that, Figures 12 to 24 These are partial structural diagrams of the semiconductor structure in each step, used to describe and clearly illustrate the steps of the semiconductor structure manufacturing method. Figures 12 to 24 The first direction X and the second direction Y shown are both perpendicular to the vertical direction Z. The first direction X and the second direction Y can be perpendicular to each other or form any angle. The following explanation uses the example of the first direction X being perpendicular to the second direction Y.

[0104] S101, Provide the substrate. For example... Figure 12 As shown, the substrate 00 includes discrete semiconductor channels 01, which are disposed on the top of the substrate 00 and extend in the vertical direction Z.

[0105] In this embodiment of the disclosure, the substrate 00 may include at least one of the semiconductor materials, such as group IV elements such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), and indium gallium arsenide (InGaAs). The following description exemplifies the inclusion of silicon in the substrate 00.

[0106] Semiconductor channel 01 may contain doping elements to improve its conductivity. The doping elements may be P-type or N-type doping elements. The N-type doping element may be at least one of arsenic (As), phosphorus (P), or antimony (Sb), while the P-type doping element may be at least one of boron (B), indium (In), or gallium (Ga).

[0107] In this embodiment of the disclosure, reference is made to Figure 12 The substrate 00 also includes a bit line 51 extending along a first direction X. The substrate 00 further includes metal silicide structures 02 (area enclosed by a circular dashed frame), which are interconnected to form the bit line 51. The bottom of the semiconductor channel 01 is electrically connected to the bit line 51. The material of the metal silicide structure 02 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0108] refer to Figure 12 A mask layer 60 is also covered on the semiconductor channel 01. A first portion 601 of the mask layer 60 covers the sidewalls and top of the semiconductor channel 01, and a second portion 602 of the mask layer 60 fills the middle of the first portion 601. The first portion 601 and the second portion 602 of the mask layer 60 are made of different materials; for example, the first portion 601 is made of silicon oxide, while the second portion 602 is made of silicon nitride. Thus, combined with... Figure 13 and Figure 14The etching can be performed according to a certain selection ratio, removing only the second part 602 and the part of the semiconductor channel 01 it covers, forming a groove 61 in the middle of the semiconductor channel 01. Figure 15 A top view of a single semiconductor channel 01, as shown below. Figure 15 As shown, the groove 61 extends along the second direction Y and passes through the semiconductor channel 01.

[0109] In this embodiment of the disclosure, reference is made to Figure 13 Before etching to form the grooves, a first isolation layer 41 can be deposited. The first isolation layer 41 extends along the second direction Y and isolates adjacent semiconductor channels 01. The material of the first isolation layer 41 can be silicon nitride.

[0110] In this embodiment of the disclosure, combined with Figure 14 and Figure 16 After etching to form the groove 61, an epitaxial layer 62 can be formed on the inner wall of the groove 61 to reduce the width of the groove 61 and repair the defects on the inner wall of the groove 61.

[0111] In this embodiment of the disclosure, combined with Figure 16 and Figure 17 After the groove 61 is formed, a second sacrificial layer 63 can be formed within the groove 61. The material of the second sacrificial layer 63 can be silicon-germanium (SiGe), which makes it easy to remove in subsequent processes, providing a basis for the formation of the bridge structure in the gate structure in subsequent processes. Furthermore, referring to... Figure 17 A filling layer 64 can be formed in the groove 61, the filling layer 64 is located on the second sacrificial layer 63, and the filling layer 64 fills the remaining groove 61.

[0112] In this embodiment of the disclosure, combined with Figure 13 and Figure 18 The first portion 601 of the mask layer 60, which covers the sidewall portion of the semiconductor channel 01, can be etched down to the bottom region of the semiconductor channel 01, such as... Figure 18 As shown, this protects the sidewalls near the bottom of semiconductor channel 01 from short circuits.

[0113] S102, A gate structure is formed in the middle region of the semiconductor channel.

[0114] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 A wet etching process can be used to remove the second sacrificial layer 63 filled in the semiconductor channel 01, forming... Figure 19 Through hole 013.

[0115] In this embodiment of the disclosure, combined with Figure 19 and Figure 20After the through-hole 013 is formed, a chemical vapor deposition (CVD) process can be used to form an initial dielectric layer on the sidewall of the central region of the semiconductor channel 01 and the inner wall of the through-hole 013. The portion of the initial dielectric layer located in the central region forms the first portion 401 of the dielectric layer 40, which is located between the gate structure 10 and the semiconductor channel 01. The material of the initial dielectric layer can be silicon oxide.

[0116] In this embodiment of the disclosure, combined with Figure 19 and Figure 20 After forming the initial dielectric layer, a gate layer can be formed around the sidewalls of the initial dielectric layer and filling the through-hole 013. The portion of the gate layer filling the through-hole 013 forms a bridge structure 102. The gate layer can be made of conductive materials such as titanium nitride. Then, the portion of the gate layer surrounding the sidewalls of the initial dielectric layer can be etched back, and the remaining gate layer after etching back forms a ring structure 101. Thus, a gate structure 10 including the ring structure 101 and the bridge structure 102 is formed. The ring structure 101 surrounds the semiconductor channel 01, and the bridge structure 102 penetrates the semiconductor channel 01 and extends along the penetration direction to the inner wall of the ring structure 101. It can be understood that the semiconductor channel 01 is penetrated to form the through-hole 013, and the through-hole 013 is filled by the bridge structure 102, meaning the inner wall of the through-hole 013 is covered by the bridge structure 102. This increases the coverage area of ​​the gate structure 10 over the semiconductor channel 01, thereby further improving the gate control capability of the formed transistor.

[0117] In this embodiment of the disclosure, reference is made to Figure 20 After the gate structure 10, which includes the ring structure 101 and the bridge structure 102, is formed, the initial dielectric layer can be deposited to form the second part 402 of the dielectric layer 40.

[0118] S103, forming a covering layer and a first sacrificial structure.

[0119] In this embodiment of the disclosure, combined with Figure 20 and Figure 21 First, the initial dielectric layer can be etched back, and the remaining initial dielectric layer becomes the second part 402 of dielectric layer 40. Then, refer to... Figure 21 An initial capping layer 21 can be deposited, which covers the semiconductor channel 01, the first isolation layer 41, and the second part 402 of the dielectric layer 40. The material of the initial capping layer 21 has a higher etching rate than that of ordinary materials.

[0120] In this embodiment, the initial capping layer 21 can be made of boron nitride silicon (SiBxNy), where the ratio of x to y represents the ratio of the number of boron to nitrogen atoms in the boron nitride, and 4 ≥ y > x > 0, yx ≤ 2. In some embodiments, the boron nitride silicon (SiBxNy) can be SiB2N4 or SiB2.6N4. It should be noted that the representation of SiBxNy does not indicate that the number of silicon atoms is 1. Compared to general materials, boron nitride silicon has a higher etching rate, meaning it is easier to etch.

[0121] In this embodiment, boron can be introduced into the cavity during silicon nitride formation to form boron silicon nitride, i.e., the initial capping layer 21. Simultaneously, the ratio of boron to nitrogen atoms in the boron silicon nitride can be adjusted by controlling the flow rate ratio of nitrogen atoms to boron atoms. It should be noted that boron silicon nitride is easier to etch than silicon nitride. Furthermore, doping boron atoms into silicon nitride reduces its stress, meaning lower stress and weaker internal interactions, making it less prone to structural damage and thus improving device performance. When the difference between the number of nitrogen and boron atoms is less than or equal to 2, the nitrogen atom content in the boron silicon nitride can be increased, thereby increasing the etching rate and reducing stress.

[0122] In this embodiment of the disclosure, reference is made to Figure 21 After the initial capping layer 21 is formed, a first sacrificial layer 31 can be deposited on the initial capping layer 21. Then, combined with... Figure 21 and Figure 22 Ion implantation (IMP) can be performed on the first sacrificial layer 31 to form an additional doped region 302 and a bulk region 303 in the first sacrificial layer 31. Figure 22 The diagram illustrates the direction of ion implantation. By controlling the ion implantation with different energies, regions at different depths in the first sacrificial layer 31 can be doped, thereby forming an additional doped region 302 and a bulk region 303. The additional doped region 302 and the bulk region 303 are arranged alternately along the vertical direction Z. The doping concentration of the additional doped region 302 is higher than that of the bulk region 303, and the thickness of the additional doped region 302 along the vertical direction Z is less than that of the bulk region 303 along the vertical direction Z.

[0123] In this embodiment of the disclosure, combined with Figure 21 and Figure 22 The material of the first sacrificial layer 31 can be boron-doped borosilicate glass (BPSG). Boron can be further doped into the boron-doped BPSG through ion implantation to form an additional doped region 302 and a bulk region 303. Of course, in some embodiments, the bulk region 332 can also be undoped BPSG, that is, the material of the first sacrificial layer 31 is undoped BPSG.

[0124] In this embodiment of the disclosure, combined with Figure 22 and Figure 23 After forming additional doped regions 302 and body regions 303 in the first sacrificial layer 31, a patterned first mask 70 can be formed on the first sacrificial layer 31. The first mask 70 includes third vias 701, each corresponding to a semiconductor channel 01. Figure 23 and Figure 24 , Figure 24 This is a top view. Figure 23 For along Figure 24 In the cross-sectional view along line A-A1, the third connecting holes 701 are distributed on the first mask 70, and the position of each third connecting hole 701 corresponds to the position of a semiconductor channel 01, that is, each third connecting hole 701 is located directly above a semiconductor channel 01.

[0125] Then, combined Figure 23 and Figure 24 The top of the semiconductor channel 01 can be exposed by etching according to the third connecting hole 701 on the first mask 70, until the top of the semiconductor channel 01 is exposed, the second connecting hole 301 is formed in the first sacrificial layer 31, and the first connecting hole 201 is formed in the initial cover layer 21, thereby forming the first sacrificial structure 30 and the cover layer 20 respectively.

[0126] like Figure 24 As shown, a capping layer 20 is located in the spacer region between adjacent semiconductor channels 01. The capping layer 20 includes a first connecting hole 201 extending in the vertical direction Z, which exposes the top of the semiconductor channel 01 and a portion of the sidewall near the top. A first sacrificial structure 30 is located above the capping layer 20. The first sacrificial structure 30 includes a second connecting hole 301 extending in the vertical direction Z, which connects to the top of the semiconductor channel 01 through the first connecting hole 201. The first sacrificial structure 30 also includes an additional doped region 302 and a body region 303. The doping concentration in the additional doped region 302 is higher than the doping concentration in the body region 303. The aperture of the second connecting hole 301 in the additional doped region 302 is larger than its aperture in the body region 303.

[0127] Understandably, on the one hand, because the material of the initial capping layer 21 has a higher etching rate than ordinary materials, etching the initial capping layer 21 makes it easier to form the first connecting hole 201 with a larger central aperture, and exposes the top of the semiconductor channel 01 and part of the sidewalls near the top, such as... Figure 24 As shown. Thus, the capacitor formed in the first through hole 201 has a larger surface area of ​​electrode plate and a larger capacitance. At the same time, its contact area with the semiconductor channel 01 is larger and its contact resistance is smaller.

[0128] On the other hand, since the additional doped region 302 is easier to etch than the body region 303, the inner wall of the second connecting hole 301 has an irregular shape, and a capacitor can be formed in the second connecting hole 301. The capacitor plate covers the inner wall of the second connecting hole 301. Therefore, the area of ​​the capacitor plate can be increased and the capacitance can be improved.

[0129] In some embodiments of this disclosure, combined with Figures 13 to 20 The steps for forming the gate structure 10 include S201 to S207, which will be explained in conjunction with each step.

[0130] S201, A groove 61 is formed in the semiconductor channel 01.

[0131] In this embodiment of the disclosure, such as Figure 13 As shown, a mask layer 60 is covered on the semiconductor channel 01. The first part 601 of the mask layer 60 covers the sidewalls and top of the semiconductor channel 01, and the second part 602 of the mask layer 60 fills the middle of the first part 601.

[0132] Combination Figure 13 and Figure 14 The etching can be performed according to a certain selection ratio, removing only the second part 602 and the part of the semiconductor channel 01 it covers, forming a groove 61 in the middle of the semiconductor channel 01. Figure 15 A top view of a single semiconductor channel 01, as shown below. Figure 15 As shown, the groove 61 extends along the second direction Y and passes through the semiconductor channel 01.

[0133] In this embodiment of the disclosure, combined with Figure 14 and Figure 16 After etching to form the groove 61, an epitaxial layer 62 can be formed on the inner wall of the groove 61 to reduce its width. Since smaller mask patterns increase the manufacturing difficulty, the second portion 602 of the wider mask layer is etched first, followed by the formation of the epitaxial layer 62 to reduce the width of the groove 61. This allows a smaller groove to be formed from a larger mask pattern, reducing manufacturing complexity. Simultaneously, the etching process may introduce defects and damage to the inner wall of the groove 61. The epitaxial layer 62 can repair these defects and damage, thereby reducing defects in the semiconductor channel 01 and improving the performance of the formed semiconductor structure.

[0134] S202, A second sacrificial layer 63 is formed in the groove 61.

[0135] In this embodiment of the disclosure, combined with Figure 16 and Figure 17After the groove 61 is formed, a second sacrificial layer 63 can be formed within the groove 61. The material of the second sacrificial layer 63 can be silicon germanium (SiGe), which makes it easy to remove in subsequent processes.

[0136] S203. A filling layer 64 is formed in the groove 61. The filling layer 64 is located on the second sacrificial layer 63 and fills the remaining groove 61.

[0137] In this embodiment of the disclosure, if the gate structure to be formed only includes a bridge structure, the filling layer 64 formed on the second sacrificial layer 63 directly fills the remaining groove 61, such as... Figure 17 As shown. If the gate structure to be formed includes at least two bridge structures, after a fill layer 64 is formed on the second sacrificial layer 63, the second sacrificial layer 63 and the fill layer 64 are formed sequentially within the groove 61, and finally the top of the groove 61 is filled with the fill layer 64. It can be understood that the sequential formation of the second sacrificial layer 63 and the fill layer 64 within the groove 61 provides a basis for the subsequent process to form the bridge structures in the gate structure.

[0138] S204. Remove the second sacrificial layer 63 to form a through hole 013.

[0139] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 A wet etching process can be used to remove the second sacrificial layer 63 filled in the semiconductor channel 01, forming... Figure 19 Through hole 013. Through hole 013 penetrates semiconductor channel 01 along the second direction Y.

[0140] S205. An initial dielectric layer is formed on the sidewall of the central region of semiconductor channel 01 and the inner wall of through hole 013.

[0141] In this embodiment of the disclosure, combined with Figure 19 and Figure 20 After the through-hole 013 is formed, a chemical vapor deposition (CVD) process can be used to form an initial dielectric layer on the sidewall of the central region of the semiconductor channel 01 and the inner wall of the through-hole 013. The portion of the initial dielectric layer located in the central region forms the first portion 401 of the dielectric layer 40, which is located between the gate structure 10 and the semiconductor channel 01. The material of the initial dielectric layer can be silicon oxide.

[0142] S206, a gate layer is formed by surrounding the sidewalls of the initial dielectric layer and filling the through-hole 013. The portion of the gate layer filling the through-hole 013 forms a bridge structure 102.

[0143] In this embodiment of the disclosure, combined with Figure 19and Figure 20 After the initial dielectric layer is formed, a gate layer can be formed around the sidewalls of the initial dielectric layer and filling the through-hole 013, wherein the portion of the gate layer filling the through-hole 013 forms a bridge structure 102. The material of the gate layer can be a conductive material such as titanium nitride.

[0144] S207. Etch the portion of the gate layer surrounding the sidewall of the initial dielectric layer to form a ring structure 101.

[0145] In this embodiment of the disclosure, reference is made to Figure 20 After the gate layer is formed, the portion of the gate layer surrounding the sidewall of the initial dielectric layer can be etched back. After the etch back, the remaining gate layer forms a ring structure 101, thus forming a gate structure 10 including a ring structure 101 and a bridge structure 102.

[0146] Understandably, the gate structure 10 includes a ring structure 101 and a bridge structure 102, which increases the coverage area of ​​the semiconductor channel 01, thereby further enhancing the control capability of the gate of the formed transistor.

[0147] In this embodiment of the disclosure, combined with Figures 20 to 24 The steps for forming the covering layer 20 and the first sacrificial structure 30 include S301 to S304, which will be explained in conjunction with each step.

[0148] S301, initial depositional overburden 21.

[0149] In this embodiment of the disclosure, combined with Figure 20 and Figure 21 After the gate structure 10 is formed, an initial capping layer 21 can be deposited. The initial capping layer 21 covers the semiconductor channel 01, the first isolation layer 41, and the second part 402 of the dielectric layer 40. The material of the initial capping layer 21 has a higher etching rate than general materials.

[0150] In this embodiment, the initial capping layer 21 can be made of boron nitride silicon (SiBxNy), where the ratio of x to y represents the ratio of the number of boron to nitrogen atoms in the boron nitride, and 4 ≥ y > x > 0, yx ≤ 2. In some embodiments, the boron nitride silicon (SiBxNy) can be SiB2N4 or SiB2.6N4. It should be noted that the representation of SiBxNy does not indicate that the number of silicon atoms is 1. Compared to general materials, boron nitride silicon has a higher etching rate, meaning it is easier to etch.

[0151] In this embodiment, boron can be introduced into the cavity during silicon nitride formation to form boron silicon nitride, i.e., the initial capping layer 21. Simultaneously, the ratio of boron to nitrogen atoms in the boron silicon nitride can be adjusted by controlling the flow rate ratio of nitrogen atoms to boron atoms. It should be noted that boron silicon nitride is easier to etch than silicon nitride. Furthermore, doping boron atoms into silicon nitride reduces its stress, meaning lower stress and weaker internal interactions, making it less prone to structural damage and thus improving device performance. When the difference between the number of nitrogen and boron atoms is less than or equal to 2, the nitrogen atom content in the boron silicon nitride can be increased, thereby increasing the etching rate and reducing stress.

[0152] S302. A first sacrificial layer 31 is deposited on the initial capping layer 21.

[0153] In this embodiment of the disclosure, reference is made to Figure 21 After the initial capping layer 21 is formed, a first sacrificial layer 31 can be deposited on the initial capping layer 21.

[0154] S303, A patterned first mask 70 is formed on the first sacrificial layer 31.

[0155] In this embodiment of the disclosure, combined with Figure 22 and Figure 23 A patterned first mask 70 can be formed on the first sacrificial layer 31. The first mask 70 includes a third connecting hole 701, which corresponds to a semiconductor channel 01. Figure 23 and Figure 24 , Figure 24 This is a top view. Figure 23 For along Figure 24 In the cross-sectional view along line A-A1, the third connecting holes 701 are distributed on the first mask 70, and the position of each third connecting hole 701 corresponds to the position of a semiconductor channel 01, that is, each third connecting hole 701 is located directly above a semiconductor channel 01.

[0156] S304. Etch according to the third connecting hole 701 until the top of the semiconductor channel 01, form the second connecting hole 301 in the first sacrificial layer 31, and form the first connecting hole 201 in the initial cover layer 21, thereby forming the first sacrificial structure 30 and the cover layer 20 respectively.

[0157] In this embodiment of the disclosure, combined with Figure 23 and Figure 24The first mask 70 can be etched along the third via 701 until the top of the semiconductor channel 01 is exposed, forming the second via 301 in the first sacrificial layer 31 and the first via 201 in the initial capping layer 21, thereby forming the first sacrificial structure 30 and the capping layer 20, respectively. Since the first sacrificial layer 31 includes an additional doped region 302 and a body region 303, and the doping concentration of the additional doped region 302 is higher than that of the body region 303, meaning that the additional doped region 302 is easier to etch than the body region 303, the aperture of the second via 301 located in the additional doped region 302 is larger than its aperture located in the body region 303.

[0158] Understandably, on the one hand, the material of the initial capping layer 21 has a higher etching rate than ordinary materials, making it easier to form the first connecting hole 201 with a larger central aperture. Therefore, the capacitor formed in the first connecting hole 201 has a larger surface area of ​​its electrode plates, resulting in a larger capacitance. Simultaneously, its contact area with the semiconductor channel 01 is larger, leading to lower contact resistance. On the other hand, since the additional doped region 302 is easier to etch than the body region 303, the inner wall of the second connecting hole 301 has an irregular shape. Since a capacitor can be formed in the second connecting hole 301, and the capacitor plates cover the inner wall of the second connecting hole 301, the area of ​​the capacitor plates can be increased, and the capacitance can be improved.

[0159] In some embodiments of this disclosure, reference is made to Figure 21 and Figure 22 Prior to S304, the semiconductor structure manufacturing method also includes S305, which will be explained in conjunction with each step.

[0160] S305. Ion implantation is performed on the first sacrificial layer to form an additional doped region and a bulk region in the first sacrificial layer.

[0161] In this embodiment of the disclosure, combined with Figure 21 and Figure 22 After the first sacrificial layer 31 is formed, ion implantation (IMP) can be performed on the first sacrificial layer 31 to form an additional doped region 302 and a bulk region 303 in the first sacrificial layer 31. Figure 22 The diagram illustrates the direction of ion implantation. By controlling the ion implantation with different energies, regions at different depths in the first sacrificial layer 31 can be doped, thereby forming an additional doped region 302 and a bulk region 303. The additional doped region 302 and the bulk region 303 are arranged alternately along the vertical direction Z. The doping concentration of the additional doped region 302 is higher than that of the bulk region 303, and the thickness of the additional doped region 302 along the vertical direction Z is less than that of the bulk region 303 along the vertical direction Z.

[0162] In this embodiment of the disclosure, combined with Figure 21 and Figure 22 The material of the first sacrificial layer 31 can be boron-doped borosilicate glass (BPSG). Boron can be further doped into the boron-doped BPSG through ion implantation to form an additional doped region 302 and a bulk region 303. Of course, in some embodiments, the bulk region 332 can also be undoped BPSG, that is, the material of the first sacrificial layer 31 is undoped BPSG.

[0163] It is understandable that by controlling the energy of ion implantation, regions at different depths in the first sacrificial layer 31 can be doped, thereby forming additional doped regions 302 and body regions 303 arranged alternately along the vertical direction Z, and thus forming a second connecting hole 301 with an irregular inner wall shape.

[0164] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0165] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0166] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes discrete semiconductor channels; The semiconductor channel is disposed on the top of the substrate and extends in a vertical direction; A gate structure, disposed in the middle region of the semiconductor channel, includes a ring structure and a bridge structure, wherein the ring structure surrounds the semiconductor channel, and the bridge structure penetrates the semiconductor channel and extends along the penetration direction to the inner wall of the ring structure; A capping layer is located in a spacer region between adjacent semiconductor channels; the capping layer includes a first connecting hole extending along the vertical direction; A first sacrificial structure is located above the cover layer; the first sacrificial structure includes a second connecting hole extending along the vertical direction, the second connecting hole connecting to the top of the semiconductor channel through the first connecting hole; the inner sidewall of the second connecting hole has an irregular shape.

2. The semiconductor structure according to claim 1, characterized in that, The first sacrificial structure further includes: an additional doped region and a bulk region; the doping concentration in the additional doped region is higher than the doping concentration in the bulk region; In the first sacrificial structure, the diameter of the second connecting hole located in the additional doped region is larger than its diameter located in the body region.

3. The semiconductor structure according to claim 2, characterized in that, In the first sacrificial structure, the additional doped region and the body region are arranged alternately along the vertical direction.

4. The semiconductor structure according to claim 2, characterized in that, The thickness of the additional doped region along the vertical direction is less than the thickness of the body region along the vertical direction.

5. The semiconductor structure according to claim 2, characterized in that, The material of the first sacrificial structure is borosilicate glass, wherein the boron content of the additional doped region is higher than the boron content of the bulk region.

6. The semiconductor structure according to claim 1, characterized in that, The top of the first connecting hole is higher than the top of the semiconductor channel, and the top of the semiconductor channel and a portion of its sidewalls near the top are exposed by the first connecting hole; In the cover layer, the diameter of the middle part of the first connecting hole is larger than its top or bottom diameter.

7. The semiconductor structure according to claim 1, characterized in that, The length of the ring structure along the vertical direction is less than the length of the semiconductor channel along the vertical direction; the length of the bridge structure along the vertical direction is less than or equal to the length of the ring structure along the vertical direction.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a dielectric layer; the dielectric layer includes: a first portion and a second portion; The first portion of the dielectric layer is located between the gate structure and the semiconductor channel; The second portion of the dielectric layer is located between the ring structure and the cover layer; The thickness of the second portion of the dielectric layer is greater than the thickness of the first portion of the dielectric layer.

9. The semiconductor structure according to claim 1, characterized in that, The width of the middle region of the semiconductor channel and the top width of the semiconductor channel are both smaller than the bottom width of the semiconductor channel.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first isolation layer is located in the interval region and is covered by the cover layer; the ring structure is located between the first isolation layer and the semiconductor channel.

11. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Bit lines are located inside the substrate and are electrically connected to the bottom of the semiconductor channel.

12. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, on which discrete semiconductor channels are included; The semiconductor channel is disposed on the top of the substrate and extends in a vertical direction; A gate structure is formed in the central region of the semiconductor channel. The gate structure includes a ring structure and a bridge structure, wherein the ring structure surrounds the semiconductor channel, and the bridge structure penetrates the semiconductor channel and extends along the penetration direction to the inner wall of the ring structure. A capping layer is formed; the capping layer is located in the spacer region between adjacent semiconductor channels, and the capping layer includes a first connecting hole extending along the vertical direction; A first sacrificial structure is formed; the first sacrificial structure is located above the cover layer, and the first sacrificial structure includes a second connecting hole extending along the vertical direction, the second connecting hole connecting to the top of the semiconductor channel through the first connecting hole; the inner sidewall of the second connecting hole has an irregular shape.

13. The manufacturing method according to claim 12, characterized in that, The steps of forming the cover layer and the first sacrificial structure include: Deposition of the initial overburden layer; A first sacrificial layer is deposited on the initial capping layer; A patterned first mask is formed on the first sacrificial layer; the first mask includes third connecting holes, each of which corresponds to a semiconductor channel. Etching is performed according to the third connecting hole until the top of the semiconductor channel is reached, forming the second connecting hole in the first sacrificial layer and the first connecting hole in the initial capping layer, thereby forming the first sacrificial structure and the capping layer respectively; wherein, the first sacrificial structure further includes: an additional doped region and a body region; the aperture of the second connecting hole located in the additional doped region is larger than its aperture located in the body region.

14. The manufacturing method according to claim 13, characterized in that, Before etching along the third via until the top of the semiconductor channel, the method further includes: Ion implantation is performed on the first sacrificial layer to form the additional doped region and the body region in the first sacrificial layer; the doping concentration in the additional doped region is higher than the doping concentration in the body region; the additional doped region and the body region are arranged alternately along the vertical direction, and the thickness of the additional doped region along the vertical direction is less than the thickness of the body region along the vertical direction.

15. The manufacturing method according to claim 12, characterized in that, The steps for forming the gate structure include: A groove is formed within the semiconductor channel; A second sacrificial layer is formed within the groove; A filling layer is formed in the groove, the filling layer is located on the second sacrificial layer, and the filling layer fills the remaining groove; The second sacrificial layer is removed to form a through-hole; the through-hole penetrates the semiconductor channel. An initial dielectric layer is formed on the sidewall of the central region of the semiconductor channel and the inner wall of the through hole; the portion of the initial dielectric layer located in the central region forms a first portion of the dielectric layer, and the first portion of the dielectric layer is located between the gate structure and the semiconductor channel; A gate layer is formed by surrounding the sidewalls of the initial dielectric layer and filling the through-hole; wherein the portion of the gate layer filling the through-hole forms the bridge structure; The portion of the gate layer surrounding the sidewall of the initial dielectric layer is etched to form the ring structure.

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