A method and device for determining the power consumption of a composite gate circuit, and an electronic device

Abstract

The specification provides a method for determining the glitch power consumption of a composite gate circuit, the composite gate circuit comprising at least two stages of gates and N input signals, the method comprising: for any input signal of the N input signals of the composite gate circuit, determining the width of a glitch signal carried by the input signal; determining the number of gate stages affected by the glitch signal according to the width of the glitch signal and the delay of the composite gate circuit; determining the power consumption generated by the glitch signal inside the composite gate circuit based on the determined number of gate stages and the total dynamic power consumption of the composite gate circuit; and aggregating the power consumption of the glitch signals corresponding to the N input signals to obtain the power consumption of the glitch signal of the composite gate circuit.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a method, apparatus, and electronic device for determining the power consumption of glitch in a composite gate circuit. Background Technology

[0002] A glitch is a signal that ineffectively flips during transitions in a logic gate. Glitches can occur due to various factors and result in power consumption. Since glitch power consumption can impact chip design, such as the width of power supply lines, external packaging, and board-level design, it's essential to calculate glitch power consumption during the chip design phase and then analyze the chip's performance based on the calculation results.

[0003] Currently, when calculating the power consumption of glitches, the industry typically calculates the power consumption of a glitch signal only when it appears at the output of a logic gate. However, in complex gate circuits with multi-level gate structures, glitches often do not appear at the output of the complex gate circuit but instead appear inside the complex gate circuit and cause a certain amount of power consumption. Existing technologies ignore this part of the power consumption. However, with the rapid increase in complex gate circuits in chips, if the existing method is still used to calculate the power consumption of glitches, most of the power consumption will be ignored, resulting in a large difference between the actual power consumption and the calculated power consumption. Therefore, a new method for determining the power consumption of glitches in complex gate circuits is urgently needed. Summary of the Invention

[0004] To address the aforementioned technical problems, this specification provides a method and apparatus for determining the power consumption of glitches in composite gate circuits, the technical solution of which is as follows.

[0005] According to a first aspect of this specification, a method for determining the glitch power consumption of a composite gate circuit is provided, comprising:

[0006] For any one of the N input signals of the composite gate circuit, determine the width of the glitch signal carried by that input signal;

[0007] Based on the width of the glitch signal and the delay of the composite gate circuit, determine the number of gate stages of the composite gate circuit affected by the glitch signal;

[0008] Based on the determined number of gate levels and the total dynamic power consumption of the composite gate circuit, the power consumption generated by the glitch signal inside the composite gate circuit is determined.

[0009] The power consumption of the glitch signals corresponding to the N input signals is summarized to obtain the power consumption of the glitch signals of the composite gate circuit.

[0010] In one embodiment, determining the number of gate stages of the composite gate circuit affected by the glitch signal based on the width of the glitch signal and the delay of the composite gate circuit includes:

[0011] Determine the number of gate levels in the composite gate circuit;

[0012] The delay corresponding to each gate level is determined based on the number of gate levels and the delay of the composite gate circuit.

[0013] The number of gate stages affected by the glitch in the composite gate circuit is determined based on the width of the glitch signal and the delay corresponding to each gate stage.

[0014] In one embodiment, determining the number of gate stages of the composite gate circuit affected by the glitch signal based on the width of the glitch signal and the delay of the composite gate circuit includes:

[0015] Based on the width of the glitch signal and the delay of the composite gate circuit, determine the gate level ratio of the composite gate circuit affected by the glitch signal;

[0016] Determine the number of gate levels in the composite gate circuit;

[0017] The number of gates in the composite gate circuit affected by the glitch signal is determined by using the gate level ratio and the number of gates in the composite gate circuit.

[0018] In one embodiment, determining the number of gate levels of the composite gate circuit includes:

[0019] Based on the number of input signals N of the composite gate circuit, the gate level L of the composite gate circuit is determined using the following formula:

[0020] In one embodiment, determining the power consumption generated by the glitch signal within the composite gate circuit based on a determined number of gate levels and the total dynamic power consumption of the composite gate circuit includes:

[0021] Determine the number of gates Q in the composite gate circuit;

[0022] Based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit, the power consumption P0 of each gate is determined;

[0023] Based on the power consumption P0 of each gate and the number of gate stages B of the composite gate circuit affected by the glitch signal, the power consumption P generated by the glitch signal inside the composite gate circuit is calculated using the following formula. X :

[0024]

[0025] According to a second aspect of the embodiments of this application, an apparatus for determining the glitch power consumption of a composite gate circuit is provided, the composite gate circuit including at least two levels of gates and N input signals, the apparatus comprising:

[0026] A width determination module is used to determine the width of any glitch signal carried by any of the N input signals of the composite gate circuit.

[0027] The level determination module is used to determine the number of gate levels of the composite gate circuit affected by the glitch signal based on the width of the glitch signal and the delay of the composite gate circuit.

[0028] A power consumption determination module is used to determine the power consumption generated by the glitch signal inside the composite gate circuit based on a determined number of gate levels and the total dynamic power consumption of the composite gate circuit.

[0029] The summarization module is used to summarize the power consumption of the glitch signals corresponding to the N input signals to obtain the power consumption of the glitch signals of the composite gate circuit.

[0030] In one embodiment, the level determination module is specifically used to determine the number of gate levels of the composite gate circuit; determine the delay corresponding to each gate level based on the number of gate levels of the composite gate circuit and the delay of the composite gate circuit; and determine the number of gate levels of the composite gate circuit affected by the glitch based on the width of the glitch signal and the delay corresponding to each gate level.

[0031] In one embodiment, the level determination module is specifically configured to determine the gate level ratio of the glitch signal affecting the composite gate circuit based on the width of the glitch signal and the delay of the composite gate circuit; determine the gate level of the composite gate circuit; and determine the gate level of the composite gate circuit affected by the glitch signal using the gate level ratio and the gate level of the composite gate circuit.

[0032] In one embodiment, the level determination module is specifically used to determine the gate level L of the composite gate circuit based on the number N of input signals N using the following formula:

[0033] In one embodiment, the power consumption determination module is specifically used to determine the number of gates Q in the composite gate circuit;

[0034] Based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit, the power consumption P0 of each gate is determined;

[0035] Based on the power consumption P0 of each gate and the number of gate stages B of the composite gate circuit affected by the glitch signal, the power consumption P generated by the glitch signal inside the composite gate circuit is calculated using the following formula. X :

[0036]

[0037] According to a third aspect of the embodiments of this application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described method for determining the power consumption of a composite gate circuit glitches.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. The accompanying drawings described herein are used to provide a further understanding of this application and constitute a part of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0040] Figure 1 This is a schematic diagram illustrating the generation of a glitch signal according to an embodiment of this specification;

[0041] Figure 2 This is a schematic diagram of a composite gate circuit according to an embodiment of this specification;

[0042] Figure 3 This is a schematic diagram of an input signal state according to an embodiment of this specification;

[0043] Figure 4 This is a schematic flowchart illustrating a method for determining the power consumption of a composite gate circuit according to an embodiment of this specification.

[0044] Figure 5 This is a schematic diagram of another composite gate circuit according to an embodiment of this specification;

[0045] Figure 6 This is a schematic diagram illustrating the correspondence between input and output signal states in an embodiment of this specification.

[0046] Figure 7 This is a schematic diagram illustrating another input / output signal state correspondence in an embodiment of this specification;

[0047] Figure 8 This is a schematic diagram of a device for determining the power consumption of a composite gate circuit according to an embodiment of this specification.

[0048] Figure 9This is a schematic diagram of the structure of a device used to configure the apparatus of the embodiments of this specification. Detailed Implementation

[0049] To make the technical solutions and advantages in the embodiments of this application clearer, the technical solutions and advantages in the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art should be within the scope of protection.

[0050] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of protection of the application. In this application, unless the context clearly indicates otherwise, the singular forms “a,” “the,” and “the” used also include the plural forms. It should also be understood that the term “and / or” as used herein includes any or all possible combinations of the listed associated items.

[0051] It should be understood that although the terms "first," "second," etc., may be used in this specification to describe various information, such information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if," "for example," as used herein, may be interpreted as "when," "in response to determination," or "in the event of a determination." It should also be understood that the terms "comprising" and / or "including" as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof. It should also be mentioned that in some alternative implementations, the mentioned functions / actions may occur in a different order than that shown in the figures. For example, depending on the functions / actions involved, two figures shown successively may actually be performed substantially simultaneously or sometimes in reverse order.

[0052] A glitch is a signal that invalidally flips within a logic gate. Glitches can occur due to various factors, such as inconsistent timing of signals arriving at the logic gate inputs. Figure 1As shown, the logic gate G0 is an OR gate. The OR logic is: if any one of the conditions is met, a certain event will occur. Therefore, in an OR gate circuit, when any input signal is high level 1, the output signal is high level 1. Only when all input signals are low level 0 will the output signal be low level 0. Therefore, as shown in the figure, during the time interval t0-t1, input signal A0 is low and input signal A1 is high. During this time interval, the output signal is also high. At time t1, input signal A1 changes, while input signal A0 does not. A0 changes at time t2. The two input signals, which should change simultaneously, do not change simultaneously but have a time delay, which is time t2-t1. During this time interval, both input signals are low, so the output signal is also low. After input signal A0 changes at time t2, since one signal is high and the other low, the output signal stabilizes at a high level from time t2 onwards. The phenomenon of invalid signal flips occurring before the output signal stabilizes, i.e., during the time interval t2-t1, is called a glitch signal. The power consumption of one invalid flip is the power consumption of one flip of the logic gate G0. Furthermore, logic gates have an inertial delay. Only when the delay difference of the input signal, i.e., the width of the glitch signal, is greater than the inertial delay of the logic gate can the generated glitch signal be output by the logic gate, thus producing a glitch signal. If the delay difference is less than the inertial delay, the glitch signal cannot be output by the logic gate, i.e., no glitch signal is generated. It is understood that the above explanation only uses an OR gate as an example to illustrate the generation of glitch signals. The principle of generating glitch signals in other logic gates is similar, and will not be elaborated here; please refer to relevant technologies. In addition to the glitch signal generation caused by the delay difference between input signals, glitch signals in circuits can also be caused by factors such as temperature, voltage, and noise.

[0053] It is understandable that the output signal will also serve as the input signal for other gates, and the circuit itself carries glitches, for example... Figure 1 The OUT signal carries a glitch signal, which may be used as the input signal for other gates. The width of the glitch signal must be greater than the inertial delay of the other gate in order to be output by that gate.

[0054] As the above analysis shows, a glitch signal can cause significant power consumption. A glitch signal can lead to invalid circuit switching, and the power consumption of a single invalid switching is typically equivalent to that of a normal gate switching. In actual circuit operation, the power consumption caused by a glitch signal can reach 20%-30% of the total power consumption of the chip circuit, or even 50%. Therefore, when analyzing chip performance, it is often necessary to consider the power consumption of glitch signals. However, currently, the power consumption of a glitch signal is usually detected and determined only when a glitch signal appears at the output of a logic gate. But in complex gate circuits with multi-level gate structures, glitch signals often do not appear at the output of the complex gate circuit, but rather appear inside the complex gate circuit and cause a certain amount of power consumption, such as... Figure 2 The diagram shows a schematic of a composite gate circuit. This circuit has two stages: the first stage consists of gates G0 and G1, and the second stage is gate G2. The composite gate circuit includes four input signals, also called input terminals, namely A0, A1, A2, and A3. A0 and A1 are the inputs to gate G0, and A2 and A3 are the inputs to gate G1. The outputs of G0 and G1 are the inputs to G2. In existing methods, only when a glitch signal appears at the output of G2, i.e., a glitch signal waveform is detected at the output, will the power consumption of that glitch signal be determined. However, since composite gate circuits also have inertial delay, according to the above... Figure 1 Analysis shows that each gate has an inertial delay, which can be understood as the sum of the inertial delays of each gate in a composite gate circuit. For example... Figure 2 As shown, the input signal A0 passes through two gates, G0 and G2, from its arrival at the composite gate circuit to its output, meaning it goes through two stages of gates. Therefore, the inertial delay of this composite gate circuit is approximately equal to the sum of the delays of each stage of gates. Consequently, the inertial delay of the composite gate circuit is greater than the inertial delay of any single gate. Furthermore, as mentioned above, the width of a glitch signal must be greater than the inertial delay of the composite gate circuit for it to be output. Therefore, some narrow glitches may not be output by the composite gate circuit. However, if the width of these glitches is greater than the inertial delay of some gates in the composite gate circuit, these glitches will affect certain gates within the composite gate circuit, resulting in power consumption.

[0055] For example, such as Figure 3 As shown, Figure 2The input signal A0 carries a glitch signal with a width of T0. If the glitch signal can be output by the compound gate circuit, then the width T0 of the glitch signal must be greater than the inertial delay of the compound gate circuit. If it is not greater than the inertial delay of the compound gate circuit, it cannot be output by the compound gate circuit. If the width T0 of the glitch signal is greater than the inertial delay of the gate G0, it may still be output at the GO output terminal, causing a certain amount of power consumption.

[0056] Currently, the industry directly ignores the power consumption generated by glitches inside composite gate circuits. However, since the power consumption is not small, and with the rapid increase in composite gate circuits in chips, if the existing method is still used to calculate the power consumption of glitches, most of the power consumption will be ignored, resulting in a large difference between the actual power consumption and the calculated power consumption. Therefore, a new method for determining the power consumption of glitches in composite gate circuits is urgently needed.

[0057] like Figure 4 The diagram shown is a flowchart illustrating a method for determining the glitch power consumption of a composite gate circuit as proposed in this specification. The composite gate circuit includes at least two gate stages and N input signals, for example, such as... Figure 5 As shown, the composite gate logic circuit includes three levels of gates and eight input signals.

[0058] The method includes:

[0059] S401, for any one of the N input signals of the composite gate circuit, determine the width of the glitch signal carried by the input signal;

[0060] The glitches carried by any input signal can be obtained through a pre-stored process library file. Specifically, the state of each input signal of the chip in a specific scenario can be simulated in advance through simulation, thereby obtaining the state of each input signal of the composite gate circuit. This allows us to determine whether each input signal carries a glitch signal and the width of the glitch signal, and store the results in the process library file. In addition to the state of each input signal in the process library file, the structure of each composite gate circuit can also be stored in the process library file, such as the number of gate levels and gates in the composite gate circuit, as well as the delay and power consumption of the composite gate circuit.

[0061] In this step, when determining the width of the glitch signal carried by the input signal, it can be directly obtained from the technology library file. For example, for input signal A0, we can check from the technology library file whether input signal A0 carries a glitch signal. If it does, we obtain the width of the glitch signal. It can be understood that each input signal may carry more than one glitch signal. In this step, we can obtain the widths of multiple glitch signals carried by the input signal and execute S402-S403 for each glitch signal to determine the power consumption of all glitch signals carried by an input signal. For example, input signal A0 carries one glitch signal, and the width of the glitch signal is T0.

[0062] S402, based on the width of the glitch signal and the delay of the composite gate circuit, determine the number of gate stages of the composite gate circuit affected by the glitch signal;

[0063] As described above, the width of the glitch signal determines whether it can be output by the composite gate circuit, and also determines which gates inside the composite gate can output the glitch signal. Therefore, in this step, we can determine which gates the glitch signal can affect based on the width of the glitch signal.

[0064] In one embodiment, this step may specifically be:

[0065] Determine the number of gate stages of the composite gate circuit; determine the delay corresponding to each gate stage based on the number of gate stages and the delay of the composite gate circuit; determine the number of gate stages affected by the glitch based on the width of the glitch signal and the delay corresponding to each gate stage.

[0066] The number of gate levels of the composite gate circuit can be obtained directly from the pre-stored process library file. In addition, in actual work, the internal gate structure of the composite gate circuit may not be known. For example, if the manufacturer of the composite gate circuit does not provide the internal structure of the composite gate circuit, the number of gate levels of the composite gate circuit can be determined by the number of input signals.

[0067] Specifically, the number of gate stages of a composite gate circuit can be estimated by the number N of its input signals; for example... Figure 5 As shown, this composite gate circuit includes 8 input signals and 3 gate levels. In practical scenarios, each gate in the composite gate circuit has a two-input structure. Therefore, the number of gate levels in the composite gate circuit can be determined using the following formula: L: in This is a mathematical symbol representing rounding up. For example... Figure 5 As shown, with 8 input signals, what is the gate stage?

[0068] After determining the number of gate stages L, the delay T of the composite gate circuit can be determined by consulting the technology library file. Since each stage of the signal passes through a gate consisting of one gate, the delay of each stage is similar. Therefore, the delay U of each stage can be determined as T / L, i.e., U = T / L. After determining the delay U of each stage, the number of gate stages affected by the glitch can be determined using the width T0 of the glitch signal and U, i.e., the number of gate stages affected by the glitch B = T0 / U.

[0069] In another embodiment, this step may specifically be:

[0070] Based on the width of the glitch signal and the delay of the composite gate circuit, determine the gate level ratio of the glitch signal affecting the composite gate circuit; determine the number of gate levels of the composite gate circuit; and use the gate level ratio and the number of gate levels of the composite gate circuit to determine the number of gate levels of the composite gate circuit affected by the glitch signal.

[0071] The ratio V = T0 / T, where V is the ratio of the glitch signal width T0 to the delay T of the composite gate circuit, represents the gate-level weight of the glitch signal affecting the composite gate circuit. The method for determining the number of gate stages L of the composite gate circuit can be referred to the previous embodiment and will not be repeated here. After obtaining the gate-level weight V and the number of gate stages L, the product B = V*L can be determined, which is the number of gate stages affected by the glitch in the composite gate circuit.

[0072] It is understood that B obtained in these two embodiments may be an integer or a non-integer. For example, if B = 2, it means that the glitch signal affects two levels of gates. If B = 1.5, it means that the glitch signal only affects the first level gate and not the second level gate.

[0073] S403, based on the determined number of gate levels and the total dynamic power consumption of the composite gate circuit, determine the power consumption generated by the glitch signal inside the composite gate circuit;

[0074] After determining the number of gates in the composite gate circuit affected by the glitch signal in S402, the number of gates Q in the composite gate circuit can be estimated based on the number of input signals N of the composite gate circuit; of course, if the number of gates Q is pre-stored in the process library file, it can be obtained directly from the process library file.

[0075] Assuming that each gate in the composite gate circuit has two inputs, the number of gates in the composite gate circuit can be estimated as Q = N / 2. 1 +N / 2 2 +…N / 2 n , of which 2 n ≤N. For example... Figure 5 As shown, Q = 8 / 2 + 8 / 4 + 8 / 8 = 7.

[0076] Based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit, the power consumption P0 of each gate is determined;

[0077] The total dynamic power consumption P of the composite gate circuit can be determined by searching the process library file. This total dynamic power consumption can be understood as the power consumption generated when all the gates inside the composite gate flip. Therefore, the power consumption of each gate flip can be regarded as P0 = P / Q.

[0078] After determining the power consumption P0 of each gate, the power consumption P generated by the glitch signal within the composite gate circuit can be determined based on P0 and the gate level B of the composite gate circuit affected by the glitch signal. X Determine P based on P0 and B. X The method is described below and will not be elaborated here.

[0079] S404, summarize the power consumption of the glitch signals corresponding to the N input signals to obtain the power consumption of the glitch signals inside the composite gate circuit.

[0080] By using the methods described in S401-S403, the power consumption of the glitch signal carried by each input signal can be determined. After determining the power consumption of the glitch signals carried by all input signals, the total glitch power consumption of the composite gate circuit can be obtained.

[0081] For example, still using Figure 5 For example, if A0 carries a glitch signal, the power consumption is P. X0 A1 does not carry a glitch signal; the glitch signal carried by A2 has no effect on the composite gate circuit (B<1), i.e., no power consumption; A3, A4, A5, and A6 each carry one glitch signal, with power consumption of P respectively. X3 P X4 P X5 P X6 A7 carries two glitch signals and has a power consumption of P. X7a P X7b Then the glitch power consumption corresponding to the composite gate circuit is P. X0 +P X3 +P X4 +P X5 +P X6 +P X7a +P X7b .

[0082] By adopting the above method, the power consumption generated by the glitch signal in the composite gate circuit can be calculated relatively accurately based on known information such as the width of the glitch signal carried by the input signals, the number of input signals, the delay of the composite gate circuit, and the total dynamic power consumption of the composite gate circuit. Compared with the existing methods, the actual power consumption of the glitch signal can be calculated more accurately (when the glitch is not output by the composite gate circuit, the power consumption of the glitch signal inside the composite gate can also be calculated), thereby enabling more accurate evaluation of chip performance.

[0083] The following describes the method for calculating the power consumption P based on the power consumption P0 of each gate and the number of gate stages B affected by the glitch signal in the composite gate circuit in the above step S403 X .

[0084] In one embodiment, based on the power consumption P0 of each gate and the number of gate stages B of the composite gate circuit affected by the glitch signal, the following formula can be used to calculate the power consumption P generated by the glitch signal inside the composite gate circuit X :

[0085]

[0086] With reference to Figure 5 the composite gate circuit shown, the overall calculation method can be shown in Table 1,

[0087] Compare B Level 1 gate Secondary gate Level 3 Gate Power consumption B<1 Not selected Not selected Not selected 0 1<B<2 Selected Not selected Not selected P0 / Q*0.5 2<B<3 Selected Selected Not selected P0 / Q*0.5+P0 / Q*0.25 B>3 Selected Selected Selected P0 / Q*0.5+P0 / Q*0.25+P0 / Q*0.125

[0088] Table 1

[0089] As shown in Figure 5 , if the width of the glitch signal carried by the A0 input signal is greater than the inertial delay of G0 and less than the inertial delay of G0+G5, that is, 1<B<2, then P X =P0 / Q*0.5. As shown in Figure 5 , G0 is an OR gate. As shown in Figure 6 , if A0 carries a glitch signal, when A1 is 1, the output signal of G0 does not include the glitch signal. As shown in Figure 7 , when A1 is 0, the output signal of G0 includes the glitch signal. Therefore, whether G0 outputs the glitch signal carried by A0 also needs to refer to the state of input signal A1. Input signal A1 can be either high level 1 or low level 0, that is, the probability that input signal A1 is 0 is 50%. Therefore, the probability of outputting a glitch signal at the output of G0 is also 0.5, and thus the power consumption caused by outputting the glitch signal at the output of G0 is P X=P0 / Q*0.5; if the glitch signal width carried by the A0 input signal is greater than the inertial delay of G0+G5, that is, 2<B<3, then the value is P0 / Q*0.5+P0 / Q*0.25. That is, the probability that G0 outputs a glitch is 0.5, and the probability that G1 outputs 0 is also 0.5. Therefore, the probability of outputting a glitch at the G5 output terminal is the product of 0.5 corresponding to G0 and 0.5 corresponding to G1, which is 0.25. Therefore, the probability of outputting a glitch signal at the G5 output terminal is 0.25, and further the power consumption caused by the output glitch signal at the G5 output terminal is P0 / Q*0.25. Since the premise of G5 outputting a glitch is that G0 also outputs a glitch, when 2<B<3, the power consumption of the output glitch includes the power consumption caused at the G0 output terminal and the power consumption caused at the G5 output terminal, that is, P0 / Q*0.5+P0 / Q*0.25. Similarly, when B>3, the value is P0 / Q*0.5+P0 / Q*0.25+P0 / Q*0.125.

[0090] In the above method, actually it is not known whether each input signal is at a high level or a low level, that is, the waveform data of each input signal is not obtained from the process file library, so it is not known whether each input signal is at a high level or a low level at each moment. Therefore, by default, the probability that the state of each signal is high level and low level is 1 / 2 respectively.

[0091] However, in actual work, the waveform data of each input signal can also be obtained from the process file library, and then the power consumption of each glitch signal can be calculated more accurately according to the waveform data of each input signal.

[0092] Therefore, in another embodiment, the waveform data of each input signal pre-stored in the process library file can also be read, the waveform data is analyzed, and it is determined whether the glitch signal will be output. If it will be output, P X =P0 / Q; if it will not be output, P X =0.

[0093] as Figure 5 shown, if the glitch signal width carried by the A0 input signal is greater than the inertial delay of G0 and less than the inertial delay of G0+G5, that is, 1<B<2, then P X =P0 / Q or P X =0. Since the waveform data of each input signal is obtained, analyzing the waveform data can determine whether the time period of the glitch signal carried by G1 corresponding to G0 is high level 1 or low level 0. If it is high level 1, the glitch will not be output by G0, and thus no power consumption will be generated; if it is low level 0, the glitch will be output by G0, so it will definitely cause power consumption, and thus the power consumption is P X=P0 / Q. Similarly, when B>3 or 3>B>2, it can be determined whether the glitch will be output, and thus the power consumption of the glitch. For example, if 3>B>2, and it is determined that G0 will output a waveform, then the output of G1 can be determined as high or low based on the waveforms of A2 and A3, and thus whether the glitch signal output by G0 can be output by G5. If it can be output by G5, then the power consumption of the glitch is P. X = 2*P0 / Q, if it is not output by G5, then the glitch power consumption is P. X =P0 / Q. And so on.

[0094] In the two embodiments described above, the first embodiment does not require acquiring the waveform data of the input signal and directly assumes that the high and low levels of the input signal are 50% respectively. In the second embodiment, it is necessary to acquire and parse the waveform and analyze the waveform to determine whether the glitch signal will be output by the gate. Therefore, the second embodiment is more accurate, but the efficiency of determining the glitch power consumption is lower. Those skilled in the art can choose the appropriate implementation method according to actual needs.

[0095] In another embodiment, the Monte Carlo method, also known as the statistical simulation method, can be used. This method analyzes and predicts the state of an input signal based on the circuit structure preceding each input signal of the composite gate circuit. Figure 5 In this context, the circuit structure before A1 can be used to predict whether A1 is high or low. Based on this prediction, it can be determined whether a glitch signal will be output by the gate, and the power consumption of the glitch signal can be calculated. For example, if the glitch signal carried by A0 corresponds to B>1 and B<2, and A1 is an AND gate output, the Monte Carlo method predicts that the probability of A1 being low (0) is 3 / 4, and the probability of it being high (1) is 1 / 4. Therefore, the power consumption at the output of G0 due to the glitch signal can be determined as P. X =P0 / Q*3 / 4, because when A1 is low (0), the glitches will be output by G0. Using this embodiment, it is not necessary to read and analyze waveform files with large amounts of data to calculate power consumption relatively accurately. For using the Monte Carlo method to predict the signal state, please refer to relevant techniques, which will not be detailed here.

[0096] like Figure 8 As shown, corresponding to the above-described method for determining the glitch power consumption of a composite gate circuit, this specification also proposes an apparatus for determining the glitch power consumption of a composite gate circuit, the apparatus comprising:

[0097] The width determination module 810 is used to determine the width of any glitch signal carried by any of the N input signals of the composite gate circuit.

[0098] The level determination module 820 is used to determine the number of gate levels of the composite gate circuit affected by the glitch signal based on the width of the glitch signal and the delay of the composite gate circuit.

[0099] The power consumption determination module 830 is used to determine the power consumption generated by the glitch signal inside the composite gate circuit based on the determined number of gate levels and the total dynamic power consumption of the composite gate circuit.

[0100] The summarization module 840 is used to summarize the power consumption of the glitch signals corresponding to the N input signals to obtain the power consumption of the glitch signals of the composite gate circuit.

[0101] In one embodiment, the level determination module 820 is specifically used to determine the number of gate levels of the composite gate circuit; determine the delay corresponding to each gate level based on the number of gate levels of the composite gate circuit and the delay of the composite gate circuit; and determine the number of gate levels of the composite gate circuit affected by the glitch based on the width of the glitch signal and the delay corresponding to each gate level.

[0102] In one embodiment, the level determination module 820 is specifically configured to determine the gate level ratio of the glitch signal affecting the composite gate circuit based on the width of the glitch signal and the delay of the composite gate circuit; determine the gate level of the composite gate circuit; and determine the gate level of the composite gate circuit affected by the glitch signal using the gate level ratio and the gate level of the composite gate circuit.

[0103] In one embodiment, the level determination module 820 is specifically used to determine the gate level L of the composite gate circuit based on the number N of input signals N of the composite gate circuit using the following formula:

[0104] In one embodiment, the power consumption determination module 830 is specifically used to determine the number of gates Q in the composite gate circuit; determine the power consumption P0 of each gate based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit; and calculate the power consumption P generated by the glitch signal inside the composite gate circuit using the following formula based on the power consumption P0 of each gate and the number of gate stages B affected by the glitch signal. X :

[0105]

[0106] The specific implementation process of the functions and roles of each component in the above-mentioned equipment can be found in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0107] For the apparatus embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The apparatus embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0108] This specification also provides a computer device, which includes at least a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the aforementioned method. The method includes at least... Figure 4 As shown in the diagram.

[0109] Figure 9 This diagram illustrates a more specific hardware structure of an electronic device provided in an embodiment of this specification. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0110] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0111] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0112] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0113] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0114] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0115] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0116] This specification also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the aforementioned method. The method includes at least... Figure 4 The method shown

[0117] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0118] While preferred embodiments of this application have been described above, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Changes and modifications made by those skilled in the art without departing from the spirit and scope of this application should also be considered within the protection scope of the embodiments in this specification.

Claims

1. A method for determining the glitch power consumption of a composite gate circuit, the composite gate circuit comprising at least two gate stages and N input signals, the method comprising: For any one of the N input signals of the composite gate circuit, determine the width of the glitch signal carried by that input signal; Determine the number of gate levels in the composite gate circuit; The delay corresponding to each gate level is determined based on the number of gate levels and the delay of the composite gate circuit. The number of gate stages affected by the glitch in the composite gate circuit is determined based on the width of the glitch signal and the delay corresponding to each gate stage. Determine the number of gates Q in the composite gate circuit; Based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit, the power consumption P0 of each gate is determined; Based on the power consumption P0 of each gate and the number of gate stages B of the composite gate circuit affected by the glitch signal, the power consumption P generated by the glitch signal inside the composite gate circuit is calculated using the following formula. X : ； The power consumption of the glitch signals corresponding to the N input signals is summarized to obtain the power consumption of the glitch signals of the composite gate circuit.

2. The method according to claim 1, wherein determining the number of gate stages of the composite gate circuit comprises: Based on the number of input signals N of the composite gate circuit, the gate level L of the composite gate circuit is determined using the following formula: .

3. An apparatus for determining the glitch power consumption of a composite gate circuit, the composite gate circuit comprising at least two gate stages and N input signals, the apparatus comprising: A width determination module is used to determine the width of any glitch signal carried by any of the N input signals of the composite gate circuit. A level determination module is used to determine the number of gate levels of the composite gate circuit; determine the delay corresponding to each gate level based on the number of gate levels and the delay of the composite gate circuit; and determine the number of gate levels affected by the glitch based on the width of the glitch signal and the delay corresponding to each gate level. A power consumption determination module is used to determine the number of gates Q in the composite gate circuit; based on the number of gates Q and the total dynamic power consumption P of the composite gate circuit, determine the power consumption P0 of each gate; based on the power consumption P0 of each gate and the number of gate stages B affected by the glitch signal in the composite gate circuit, calculate the power consumption P generated by the glitch signal inside the composite gate circuit using the following formula. X : ； The summarization module is used to summarize the power consumption of the glitch signals corresponding to the N input signals to obtain the power consumption of the glitch signals of the composite gate circuit.

4. The apparatus according to claim 3, The level determination module is specifically used to determine the gate level L of the composite gate circuit based on the number N of input signals N using the following formula: .

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein, When the processor executes the program, it implements the method as described in any one of claims 1 to 2.

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