A high PWM duty cycle priority based implementation method for LED hybrid dimming

Abstract

The present application belongs to the technical field of LED driving, and particularly relates to a high-PWM duty cycle priority-based implementation method for LED hybrid dimming. The present application is a high-PWM duty cycle priority-based implementation mode of a hybrid dimming algorithm, and the high-PWM duty cycle priority-based mode combines a PWM dimming algorithm and a DC dimming algorithm. The hybrid dimming algorithm has no code loss at low brightness, and less code loss meets the visual experience of human eyes, and has good display effect. The implementation mode is simple, and the cost is low. With very few hardware resources, the hybrid dimming algorithm realizes no code loss at low brightness, and the refresh frequency of PWM can be greatly improved, with a multiplication of 2 N , which improves the visual experience of human eyes. Moreover, the hybrid dimming algorithm has fast response speed and small system delay.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of LED driving, and particularly relates to an implementation method based on high PWM duty cycle priority for LED hybrid dimming. BACKGROUND

[0002] Whether it is a direct LED system or a backlight LED system, LED dimming technology plays an important role. Generally speaking, increasing the current will make the LED brighter, and reducing the current will reduce the brightness of the LED. DC dimming and PWM dimming are two common dimming methods. DC dimming is to adjust the brightness of the LED by changing the current flowing through the LED. When the current is small, the LED is dim, and when the current is large, the LED is brighter. The disadvantage of DC dimming is that it is difficult to achieve accurate current adjustment at low brightness. The human eye is very sensitive to brightness information, especially low brightness information. At low brightness, large quantization errors can be easily perceived by the human eye, affecting the display effect.

[0003] PWM dimming uses PWM (Pulse Width Modulation) technology to change the switching frequency and duty cycle of the LED to control the brightness of the LED. In a cycle, the brightness of the LED is adjusted by adjusting the ratio of the on time and the off time of the LED. Shorter on time can make the LED dimmer, and longer on time can make the LED brighter. The disadvantage of PWM dimming is the noise problem at low PWM frequency.

[0004] As shown in Figure 1 , hybrid dimming is a dimming algorithm that combines DC dimming and PWM dimming. Good hybrid dimming can reduce the disadvantages of the two dimming algorithms. Hybrid dimming requires the support of two sets of hardware for DC dimming and PWM dimming, and also requires additional software or hardware to decompose the brightness into DC and PWM parts, which increases the complexity of the algorithm and requires more software and hardware resources to implement.

[0005] Therefore, how to implement the LED hybrid dimming algorithm in a simple structure, with less external resources, low cost, and good display effect, is one of the difficulties in the industry.

[0006] The hybrid dimming is a dimming algorithm combining DC dimming and PWM dimming. Different from the single current or pulse width value reflecting the brightness information, the hybrid dimming algorithm reflects the brightness by the product of the current value and the pulse width value, and the product of the unit current and the unit pulse width represents a unit brightness. In the hybrid dimming, some brightness values have multiple implementation manners of the current value and the pulse width value, and the display effects are different in different implementation manners; and some brightness values cannot be decomposed into the product of the current value and the pulse width value, but can only be decomposed into approximate brightness values. Taking the 8192-level (13-bit) dimming range as an example, it is usually the addition of 10-bit PWM dimming and 3-bit DC dimming. The 3-bit DC dimming supports a maximum of 8 brightness units. The 10-bit PWM dimming supports a maximum of 1024 pulse width values. The brightness coding of 2047 cannot be decomposed into the product of the integer current value and the integer pulse width value. Usually, the decomposition values of the adjacent brightness values 2046 or 2048 are adopted. The implementation manner 1 of the brightness coding of 2048: the DC dimming is 2 unit current values, and the PWM dimming value is 1024 (that is, 100%); the implementation manner 2 of the brightness coding of 2048: the DC dimming is 4 unit current values, and the PWM dimming value is 512 (that is, 50%); the implementation manner 3 of the brightness coding of 2048: the DC dimming is 8 unit current values, and the PWM dimming value is 256 (that is, 25%).

[0007] In order to achieve good display effect, the lookup table is usually used to solve the above problems. The lookup table lists all the current values and pulse width values corresponding to the brightness values. The method of using the lookup table can convert the brightness value into the current value and the pulse width value corresponding thereto. The disadvantages are that the implementation manner of the lookup table is complex and high in cost. Usually, additional hardware resources such as FPGA or MCU are needed to realize, or additional software resources are needed to realize. The reaction speed is slow, which leads to large system delay. SUMMARY

[0008] In view of the above problems, the application provides an implementation method for LED hybrid dimming based on high PWM duty cycle priority.

[0009] The technical scheme of the application is as follows:

[0010] An implementation method for LED hybrid dimming based on high PWM duty cycle priority, the dimming method is that the dimming brightness coding level is represented as 2 X M+N, that is, 2 X =2 (N+M) , wherein N is the precision bit number of the PWM dimming, corresponding to 2 N unit pulse width, and M is the precision bit number of the DC dimming, corresponding to 2 MA unit current; the target dimming brightness coding level Y is compared with 2 0 *2 N , 2 1 *2 N , … 2 M-1 *2 N , if less than or equal to 2 0 *2 N , the corresponding pulse width value is adopted according to the value of Y to dim, and the pulse width value is output at 1 times unit current; otherwise, the range interval where the target dimming brightness coding level is located is obtained, defined as 2 A *2 N and 2 B *2 N , and B=A+1, that is, 2 A *2 N ≤Y≤2 B *2 N , the pulse width value of Y>>B is adopted to dim, the symbol >> represents that Y represented by binary bits is right shifted by B bits, and the pulse width value is output at 2 B times unit current, so that the hybrid dimming of high PWM duty cycle priority is realized.

[0011] The present application has the advantages that the present application is a high PWM duty cycle priority implementation method of a hybrid dimming algorithm, and PWM dimming algorithm and DC dimming algorithm are combined based on the high PWM duty cycle priority mode. The hybrid dimming algorithm has no code loss at low brightness, and the code loss meets the visual experience of the human eye, and the display effect is good. The implementation method is simple, and the cost is low. The hardware resources are used to realize no code loss at low brightness, and the refresh frequency of PWM can be greatly improved, the improvement multiple is 2 N , and the visual experience of the human eye is improved. Moreover, the reaction speed is fast, and the system delay is small. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 It is a traditional hybrid dimming algorithm waveform diagram;

[0013] Figure 2 It is a hybrid dimming algorithm high PWM duty cycle priority implementation method schematic diagram proposed by the present application;

[0014] Figure 3 It is a Code<2 N hybrid dimming algorithm high PWM duty cycle priority implementation method schematic diagram proposed by the present application;

[0015] Figure 4 It is a Code>2 N hybrid dimming algorithm high PWM duty cycle priority implementation method schematic diagram proposed by the present application;

[0016] Figure 5 A schematic diagram illustrating the implementation of the hybrid dimming algorithm proposed in this invention with a high PWM duty cycle priority when Code < 1024;

[0017] Figure 6 A schematic diagram of the implementation method of the hybrid dimming algorithm proposed in this invention, which prioritizes high PWM duty cycle, when 2048>Code>1023;

[0018] Figure 7 A schematic diagram of the implementation method of the hybrid dimming algorithm proposed in this invention prioritizing high PWM duty cycle when 4096>Code>2047;

[0019] Figure 8 A schematic diagram of the implementation method of the hybrid dimming algorithm proposed in this invention, which prioritizes high PWM duty cycle, when 8192>Code>4095. Detailed Implementation

[0020] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] like Figure 2 As shown, for X-bit brightness adjustment, this invention decomposes it into brightness modulation with (M+N) precision bits, where M is the precision bit depth of DC dimming and N is the precision bit depth of PWM dimming. The brightness data needs to be compared with N brightness values ​​(the brightness values ​​to be compared are: 2...). 0 *2 N ,2 1 *2 N ,2 2 *2 N ...2 M-2 *2 N ,2 M-1 *2 N The comparison results from the comparator and the brightness value are processed by the data processing module to obtain the DC dimming value and the PWM dimming value.

[0022] like Figure 3 , Figure 4 As shown, the specific implementation principle is as follows: when the brightness data (i.e., Code) is less than 2... 0 *2 N Initially, the DC dimming value is set to 1 unit current. As the brightness data increases, the PWM dimming pulse width value is increased by Code step by step to achieve the dimming effect. As the brightness increases to just above 2... N At level 2, this algorithm will double the DC dimming value and decrease the PWM pulse width value to Code>>1 (>> is a binary right shift operation; Code>>1 means the binary data Code is shifted right by one bit, reducing it to half its original value). Afterwards, each time the brightness reaches level 2...k *2 N Where k=0 / 1 / 2..., M-1, all will be achieved in this way, DC dimming brightness doubled, PWM pulse width value reduced.

[0023] Luminance data only need to compare with N luminance values (the luminance values need to be compared: 2 0 *2 N , 2 1 *2 N , 2 2 *2 N ... 2 M-2 *2 N , 2 M-1 *2 N ), the circuit is very easy to implement, and the resources used are very small.

[0024] When the luminance data is greater than 2 N-1 , the PWM duty cycle is always maintained above 50%, achieving high PWM duty cycle. DC dimming position uses binary coding to achieve, simple, the circuit is very easy to implement, and the resources used are very small.

[0025] Take 13-bit binary luminance adjustment as an example, which is decomposed into 10-bit PWM dimming and 3-bit DC dimming. The input luminance value is represented by Code.

[0026] When the luminance value Code is less than 1024 (Code < 1024), the DC current is 1 unit current. This algorithm is similar to the PWM dimming algorithm, as the luminance increases, the PWM pulse width value equals Code and constantly increases, the PWM duty cycle gradually increases from 0% to 100%. As shown in Figure 5 , the shaded part represents the state of light emission. There is no loss of code phenomenon.

[0027] When the luminance value Code is less than 2048, greater than 1023 (2048 > Code > 1023), as shown in Figure 6 , this algorithm increases the DC current value by one time on the basis of the previous DC brightness, becoming 2 unit current. The corresponding PWM pulse width value is reduced to Code >> 1 (>> is a binary right shift operation, Code >> 1 represents the binary data Code right shift one bit, reduced to half of the original value of Code), the PWM duty cycle is reduced to 50%, and as the luminance increases, the PWM duty cycle gradually increases to 100%.

[0028] When the luminance is less than 4096, greater than 2047 (4096 > Code > 2047), as shown in Figure 7As shown, the algorithm increases the DC current value by one time on the basis of the previous DC brightness, and becomes 4 unit currents. The corresponding PWM pulse value is reduced to Code>>2 (>> is a binary right shift operation, Code>>2 indicates that the binary data Code is right shifted by two bits, and is reduced to one fourth of the original Code), and the PWM duty cycle is reduced to 50%, and gradually increases to 100% with the increase of brightness.

[0029] When the brightness is less than 8192 and greater than 4095 (8192>Code>4095), as shown, Figure 8 As shown, the algorithm increases the DC current value by one time on the basis of the previous DC brightness, and becomes 4 unit currents. The corresponding PWM pulse value is reduced to Code>>2 (>> is a binary right shift operation, Code>>2 indicates that the binary data Code is right shifted by two bits, and is reduced to one fourth of the original Code), and the PWM duty cycle is reduced to 50%, and gradually increases to 100% with the increase of brightness.

[0030] When the brightness data is greater than 512 (Code>512), the PWM duty cycle is always maintained to be more than 50%, and high PWM duty cycle is realized.

[0031] The DC dimming position adopts binary coding to realize, which is simple, and the circuit is very easy to realize, and the resources used are very few.

[0032] The brightness data only needs to be compared with 1024 / 2048 / 4096 three brightness values, and the circuit is very easy to realize, and the resources used are very few.

[0033] The application proposes a mixed dimming algorithm high PWM duty cycle priority implementation mode. A very simple circuit structure is adopted, and a very small amount of hardware resources is used, so that the mixed dimming effect of no loss code at low brightness and few loss codes in line with human eye visual experience is realized.

Claims

1. A high-PWM duty cycle priority based implementation method for LED hybrid dimming, characterized in that, The dimming method is: representing dimming brightness coding level as 2 X , adopting PWM dimming and DC dimming mixed mode for dimming, and the specific method is: splitting X into M+N, i.e. 2 X =2 (N+M) , wherein N is the precision bit number of PWM dimming, corresponding to 2 N unit pulse width, and M is the precision bit number of DC dimming, corresponding to 2 M unit current; The target dimming brightness coding level Y is compared with 2 0 *2 N , 2 1 *2 N , …, 2 M-1 *2 N , if less than or equal to 2 0 *2 N , the corresponding pulse width value is used for dimming according to the value of Y, and the pulse width value is output at 1 times the unit current; otherwise, the range interval in which the target dimming brightness coding level is located is obtained, defined as 2 A *2 N and 2 B *2 N , and B=A+1, that is, 2 A *2 N ≤Y≤2 B *2 N , the pulse width value of Y>>B is used for dimming, the symbol >> represents that Y represented by binary bits is right shifted by B bits, and the pulse width value is output at 2 B times the unit current, thereby realizing hybrid dimming with high PWM duty cycle priority.

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