Chip packaging structure and packaging method

Abstract

A chip packaging structure and packaging method provided in an embodiment of the present application relate to the field of chip packaging technology. The chip packaging structure includes a substrate, an electrostatic protection unit and a redistribution layer; the electrostatic protection unit is located on one side of the substrate, and the electrostatic protection unit can be unidirectionally conductive; the redistribution layer is located on the side of the electrostatic protection unit away from the substrate, and the redistribution layer includes a chip connection line and a fixed voltage line, and the chip connection line and the fixed voltage line are electrically connected through the electrostatic protection unit. The present application will not increase the size of the chip packaging structure, and thus can meet the market demand for miniaturization of chip packaging structures.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a packaging method. Background Art

[0002] With the development of chip technology, in order to meet the needs of users, multiple chips are integrated together in a chip packaging structure. The connection positions of the pins of different chips in the same chip packaging structure are prone to generate static electricity. In order to prevent static electricity from damaging the chip, it is necessary to set an electrostatic protection unit in the chip packaging structure.

[0003] However, as the density of chip pins increases, the electrostatic protection unit in the prior art will increase the size of the chip packaging structure, which is not conducive to the demand of the miniaturization market. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a chip packaging structure, wherein the chip packaging structure includes:

[0005] substrate;

[0006] An electrostatic protection unit located at one side of the substrate, wherein the electrostatic protection unit can be unidirectionally conductive;

[0007] A redistribution layer is located on a side of the electrostatic protection unit away from the substrate, the redistribution layer includes a chip connection wiring and a fixed voltage wiring, and the chip connection wiring and the fixed voltage wiring are electrically connected through the electrostatic protection unit.

[0008] In some possible implementations, the fixed voltage routing includes a first voltage routing and a second voltage routing, and the electrostatic protection unit includes a first protection unit and a second protection unit;

[0009] The chip connection wiring and the first voltage wiring are electrically connected through the first protection unit, and the chip connection wiring and the second voltage wiring are electrically connected through the second protection unit;

[0010] The first protection unit allows current to flow from the chip connection line to the first voltage line, and the second protection unit allows current to flow from the second voltage line to the chip connection line.

[0011] In some possible implementations, the first protection unit includes a first metal trace located on one side of the substrate and a first switch located on a side of the first metal trace away from the substrate; the second protection unit includes a second metal trace located on one side of the substrate and a second switch located on a side of the second metal trace away from the substrate;

[0012] The chip connection line is electrically connected to the first metal line, the first metal line is electrically connected to one end of the first switch, and the first voltage line is electrically connected to the other end of the first switch; the second voltage line is electrically connected to the second metal line, the second metal line is electrically connected to one end of the second switch, and the chip connection line is electrically connected to the other end of the second switch.

[0013] In some possible implementations, the first switch includes a first p-type semiconductor layer located on a side of the first metal trace away from the substrate and a first n-type semiconductor layer located on a side of the first p-type semiconductor layer away from the substrate; the second switch includes a second p-type semiconductor layer located on a side of the second metal trace away from the substrate and a second n-type semiconductor layer located on a side of the second p-type semiconductor layer away from the substrate;

[0014] The first metal wiring is electrically connected to the first p-type semiconductor layer, and the first voltage wiring is electrically connected to the first n-type semiconductor layer; the second metal wiring is electrically connected to the second p-type semiconductor layer, and the chip connection wiring is electrically connected to the second n-type semiconductor layer;

[0015] Preferably, the chip packaging structure further comprises an insulating layer located on one side of the substrate, wherein the insulating layer covers at least a portion of the first metal trace, at least a portion of the second metal trace, at least a portion of the first p-type semiconductor layer, at least a portion of the second p-type semiconductor layer, at least a portion of the first n-type semiconductor layer, and at least a portion of the second n-type semiconductor layer;

[0016] Preferably, a plurality of vias are provided on the insulating layer along a direction perpendicular to the substrate, the chip connection wiring is electrically connected to the first metal wiring through the vias, and the first voltage wiring is electrically connected to the first n-type semiconductor layer through the vias; the chip connection wiring is electrically connected to the second n-type semiconductor layer through the vias, and the second voltage wiring is electrically connected to the second metal wiring through the vias.

[0017] In some possible implementations, the chip packaging structure further includes a seed metal layer located on a side of the insulating layer away from the substrate, and the seed metal layer includes a first seed routing line, a second seed routing line, and a third seed routing line;

[0018] The first voltage routing is electrically connected to the first n-type semiconductor layer through the first seed routing; the chip connection routing is electrically connected to the first metal routing and the second n-type semiconductor layer respectively through the second seed routing, and the second voltage routing is electrically connected to the second metal routing through the third seed routing.

[0019] In some possible implementations, the chip packaging structure further includes at least two chips located on a side of the redistribution layer away from the substrate, and the at least two chips are electrically connected through the chip connection wiring;

[0020] Preferably, the chip packaging structure further comprises a packaging layer located on a side of the redistribution layer away from the substrate, and the packaging layer covers the at least two chips.

[0021] In some possible implementations, the voltage of the first voltage routing line is less than the voltage of the second voltage routing line;

[0022] Preferably, the first voltage routing includes a common ground voltage routing, and / or the second voltage routing includes a power supply voltage routing.

[0023] In some possible implementations, the present application further provides a chip packaging method, the method comprising:

[0024] providing a substrate;

[0025] An electrostatic protection unit is formed on one side of the substrate; the electrostatic protection unit can be unidirectionally conductive;

[0026] A redistribution layer is formed on a side of the electrostatic protection unit away from the substrate; the redistribution layer includes chip connection wiring and fixed voltage wiring, and the chip connection wiring and the fixed voltage wiring are electrically connected through the electrostatic protection unit.

[0027] In some possible implementations, the step of forming an electrostatic protection unit on one side of the substrate includes:

[0028] forming a first protection unit and a second protection unit on one side of the substrate;

[0029] The step of forming a redistribution layer on a side of the electrostatic protection unit away from the substrate comprises:

[0030] A first voltage routing, a chip connection routing, and a second voltage routing that are isolated from each other are formed on a side of the electrostatic protection unit away from the substrate; the chip connection routing and the first voltage routing are electrically connected through the first protection unit, and the chip connection routing and the second voltage routing are electrically connected through the second protection unit; the first protection unit allows current to flow from the chip connection routing to the first voltage routing, and the second protection unit allows current to flow from the second voltage routing to the chip connection routing.

[0031] Preferably, the step of forming a mutually isolated first voltage wiring, a chip connection wiring and a second voltage wiring on a side of the electrostatic protection unit away from the substrate comprises:

[0032] An insulating layer is formed on one side of the substrate, and a via hole is formed on the insulating layer; the insulating layer covers at least a portion of the first protection unit and at least a portion of the second protection unit;

[0033] forming a seed metal layer on a side of the insulating layer away from the substrate;

[0034] forming a patterned photoresist on a side of the seed metal layer away from the substrate;

[0035] forming a wiring metal layer on a side of the insulating layer away from the substrate;

[0036] The patterned photoresist and the seed metal layer exposed by the patterned photoresist are removed to form a first voltage trace, a chip connection trace and a second voltage trace.

[0037] In some possible implementations, the step of forming a first protection unit and a second protection unit on one side of the substrate includes:

[0038] forming a first metal trace and a second metal trace on one side of the substrate;

[0039] A first p-type semiconductor layer is formed on a side of the first metal routing away from the substrate, a second p-type semiconductor layer is formed on a side of the second metal routing away from the substrate, and a first n-type semiconductor layer is formed on a side of the first p-type semiconductor layer away from the substrate, and a second n-type semiconductor layer is formed on a side of the second p-type semiconductor layer away from the substrate; the first metal routing is electrically connected to the first p-type semiconductor layer, and the first voltage routing is electrically connected to the first n-type semiconductor layer; the second metal routing is electrically connected to the second p-type semiconductor layer, and the chip connection routing is electrically connected to the second n-type semiconductor layer.

[0040] Compared with the prior art, this application has the following beneficial effects:

[0041] The present application provides a chip packaging structure and packaging method. By setting the electrostatic protection unit between the redistribution layer and the substrate, the electrostatic protection unit can be designed vertically with a larger design space, which will not increase the size of the chip packaging structure, thereby meeting the market demand for miniaturization of chip packaging structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0044] Figure 2 Provided for the embodiments of this application Figure 1 One of the specific structural diagrams of the dotted box;

[0045] Figure 3 Provided for the embodiments of this application Figure 1 The second schematic diagram of the specific structure of the dotted line box;

[0046] Figure 4 Provided for the embodiments of this application Figure 1 The third schematic diagram of the specific structure in the middle dotted box;

[0047] Figure 5 Provided for the embodiments of this application Figure 1 The fourth schematic diagram of the specific structure of the dotted line box;

[0048] Figure 6 Provided for the embodiments of this application Figure 5 A circuit diagram of the working principle of the corresponding electrostatic protection unit;

[0049] Figure 7 Provided for the embodiments of this application Figure 1 The fifth schematic diagram of the specific structure in the middle dotted box;

[0050] Figure 8 Provided for the embodiments of this application Figure 1 The sixth schematic diagram of the specific structure in the middle dotted box;

[0051] Fig. 9 The chip packaging structure provided in the embodiment of the present application includes a schematic diagram of a cross-sectional structure of a packaging layer;

[0052] Fig.10 A schematic diagram of a chip packaging method provided in an embodiment of the present application;

[0053] Fig.11 A schematic diagram of a structure of an electrostatic protection unit formed on one side of a substrate provided in an embodiment of the present application;

[0054] Fig.12A schematic diagram of a structure in which a redistribution layer is formed on a side of an electrostatic protection unit away from a substrate provided in an embodiment of the present application;

[0055] Fig.13 A flowchart of a specific execution method of step S11 provided in an embodiment of the present application;

[0056] Fig.14 A schematic diagram of a structure in which a first metal trace and a second metal trace are formed on one side of a substrate according to an embodiment of the present application;

[0057] Fig.15 A schematic diagram of a structure in which a first diode and a second diode are formed on a side of a first metal wiring away from a substrate provided in an embodiment of the present application;

[0058] Fig.16 A flowchart of a specific execution method of step S12 provided in an embodiment of the present application;

[0059] Fig.17 A schematic diagram of a structure in which an insulating layer is formed on one side of a substrate according to an embodiment of the present application;

[0060] Fig.18 A schematic diagram of a structure in which a seed metal layer is formed on a side of an insulating layer away from a substrate provided in an embodiment of the present application;

[0061] Fig.19 A schematic diagram of a structure in which a patterned photoresist is formed on a side of a seed metal layer away from a substrate provided in an embodiment of the present application;

[0062] Fig. 20 A schematic diagram of a structure in which a wiring metal layer is formed on a side of an insulating layer away from a substrate provided in an embodiment of the present application.

[0063] Figure numerals: 2, substrate; 3, redistribution layer; 4, chip; 5, electrostatic protection unit; 51, first protection unit; 511, first metal routing; 512, first switch; 5121, first p-type semiconductor layer; 5122, first n-type semiconductor layer; 52, second protection unit; 521, second metal routing; 522, second switch; 5221, second p-type semiconductor layer; 5222, second n-type semiconductor layer; 6, fixed voltage routing; 61, first voltage routing; 62, second voltage routing; 7, chip connection routing; 8, insulating layer; 81, via; 9, first seed routing; 10, second seed routing; 11, third seed routing; 12, packaging layer; 13, seed metal layer; 14, patterned photoresist; 15, wiring metal layer. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0066] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0067] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0068] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0069] This embodiment provides a solution that does not increase the size of the chip packaging structure. The solution provided by this embodiment is described in detail below.

[0070] See also Figure 1 This embodiment provides a chip packaging structure, which includes a substrate 2, an electrostatic protection unit 5, a redistribution layer 3 and at least two chips 4.

[0071] The electrostatic protection unit 5 is located on one side of the substrate 2, and the electrostatic protection unit 5 can be unidirectionally conductive. Unidirectional conductivity means that the current mainly flows from one direction to another direction, and cannot flow in the reverse direction, or the current flowing in the reverse direction is very small.

[0072] See also Figure 2The redistribution layer 3 is located on a side of the electrostatic protection unit 5 away from the substrate 2 . The redistribution layer 3 includes a chip connection wiring 7 and a fixed voltage wiring 6 . The chip connection wiring 7 and the fixed voltage wiring 6 are electrically connected through the electrostatic protection unit 5 .

[0073] The thickness of the redistribution layer 3 is generally 5um to 10um, and the material may be copper. The redistribution layer 3 may be one layer or multiple layers. Specifically, if the number of pins of the chip 4 is relatively small, only one layer of the redistribution layer 3 may be designed. If the number of pins of the chip 4 is relatively large, multiple layers of the redistribution layer 3 may be designed. For example, the redistribution layer 3 may be set to have two layers, and some external signal lines are input to the chip 4 through the first layer of the redistribution layer 3, and some are input to the chip 4 through the second layer of the redistribution layer 3.

[0074] At least two chips 4 are located on a side of the redistribution layer 3 away from the substrate 2 , and at least two chips 4 are electrically connected via chip connection traces 7 .

[0075] The chip connection line 7 and the fixed voltage line 6 are arranged on the same layer, the voltage of the fixed voltage line 6 is fixed or the voltage fluctuation is very small, and the fixed voltage line 6 has the function of releasing static electricity. The pins of at least two chips 4 are electrically connected to the chip connection line 7, so the chip 4, the chip connection line 7, the electrostatic protection unit 5 and the fixed voltage line 6 are electrically connected in sequence. When static electricity is generated at the chip connection line 7 where the pins of the two chips 4 are connected, the static electricity will be transmitted to the electrostatic protection unit 5 and the fixed voltage line 6 in sequence, and the static electricity will eventually be released at the fixed voltage line 6, thereby preventing the chip 4 from being damaged by static electricity.

[0076] The electrostatic protection unit 5 is located between the substrate 2 and the redistribution layer 3. The electrostatic protection unit 5 is arranged below the redistribution layer 3, and the design space is relatively large, so the size of the chip packaging structure will not be increased.

[0077] Based on the above design, by setting the electrostatic protection unit 5 between the redistribution layer 3 and the substrate 2, the electrostatic protection unit 5 can be designed vertically with a larger design space, thereby not increasing the size of the chip packaging structure, and thus meeting the market demand for miniaturization of chip packaging structures.

[0078] For some possible implementations, see Figure 3 The fixed voltage routing 6 includes a first voltage routing 61 and a second voltage routing 62, and the electrostatic protection unit 5 includes a first protection unit 51 and a second protection unit 52; the chip connection routing 7 and the first voltage routing 61 are electrically connected through the first protection unit 51, and the chip connection routing 7 and the second voltage routing 62 are electrically connected through the second protection unit 52; the first protection unit 51 allows current to flow from the chip connection routing 7 to the first voltage routing 61, and the second protection unit 52 allows current to flow from the second voltage routing 62 to the chip connection routing 7.

[0079] The first protection unit 51 and the second protection unit 52 are arranged in the same layer and on the side of the redistribution layer 3 close to the substrate 2. In this way, the first protection unit 51 and the second protection unit 52 have a larger setting space, thereby not increasing the size of the chip protection structure.

[0080] When positive static electricity is generated at the chip connection wiring 7 where the pins of the two chips 4 are connected, the positive static electricity reaches the first voltage wiring 61 through the first protection unit 51, and the positive static electricity is released through the first voltage wiring 61. When negative static electricity is generated at the chip connection wiring 7 where the pins of the two chips 4 are connected, the negative static electricity reaches the second voltage wiring 62 through the second protection unit 52, and the negative static electricity is released through the second voltage wiring 62. In this way, by designing the first protection unit 51 and the second protection unit 52, different types of static electricity can be processed separately, so that the static electricity generated by the chip 4 can be released more easily, thereby improving the protection effect of the chip.

[0081] For some possible implementations, see Figure 4 The first protection unit 51 includes a first metal routing 511 located on one side of the substrate 2 and a first switch 512 located on the side of the first metal routing 511 away from the substrate 2; the second protection unit 52 includes a second metal routing 521 located on one side of the substrate 2 and a second switch 522 located on the side of the second metal routing 521 away from the substrate 2; the chip connection routing 7 is electrically connected to the first metal routing 511, the first metal routing 511 is electrically connected to one end of the first switch 512, and the first voltage routing 61 is electrically connected to the other end of the first switch 512; the second voltage routing 62 is electrically connected to the second metal routing 521, the second metal routing 521 is electrically connected to one end of the second switch 522, and the chip connection routing 7 is electrically connected to the other end of the second switch 522.

[0082] The first switch 512 allows positive current to flow from the chip connection wire 7 to the first voltage wire 61, and the second switch 522 allows negative current to flow from the chip connection wire 7 to the second voltage wire 62. In this way, the first switch 512 can make it easier for positive static current to be released to the first voltage wire 61, and the second switch 522 can make it easier for negative static current to be released to the second voltage wire 62.

[0083] For some possible implementations, see Figure 5The first switch 512 includes a first p-type semiconductor layer 5121 located on a side of the first metal wiring 511 away from the substrate 2 and a first n-type semiconductor layer 5122 located on a side of the first p-type semiconductor layer 5121 away from the substrate 2; the second switch 522 includes a second p-type semiconductor layer 5221 located on a side of the second metal wiring 521 away from the substrate 2 and a second n-type semiconductor layer 5222 located on a side of the second p-type semiconductor layer 5221 away from the substrate 2; the first metal wiring 511 is electrically connected to the first p-type semiconductor layer 5121, and the first voltage wiring 61 is electrically connected to the first n-type semiconductor layer 5122; the second metal wiring 521 is electrically connected to the second p-type semiconductor layer 5221, and the chip connection wiring 7 is electrically connected to the second n-type semiconductor layer 5222.

[0084] See also Figure 6 The first p-type semiconductor layer 5121 and the first n-type semiconductor layer 5122 form a first diode P1, and the second p-type semiconductor layer 5221 and the second n-type semiconductor layer 5222 form a second diode P2. Both the first diode P1 and the second diode P2 have the characteristic of unidirectional conductivity.

[0085] Since the resistance of the first diode P1 and the second diode P2 is relatively large, and the first voltage line 61 and the second voltage line 62 are both constant voltages, the voltage difference between the first voltage line 61 and the second voltage line 62 is relatively small, and no instantaneous high voltage difference will be generated, so the first voltage line 61 and the second voltage line 62 will not be turned on.

[0086] When a high instantaneous positive static electricity is generated at the chip pins connected by the pins of the two chips 4, the positive static electricity reaches the first diode P1 through the chip connection wiring 7 and the first metal wiring 511, the first diode P1 is turned on, and the positive static electricity reaches the first voltage wiring 61 after passing through the first diode P1 to release the positive static electricity. When a high instantaneous negative static electricity is generated at the chip pins connected by the pins of the two chips 4, the negative static electricity reaches the second diode P2 through the chip connection wiring 7 and the second metal wiring 521, the second diode P2 is turned on, and the negative static electricity reaches the second voltage wiring 62 after passing through the second diode P2 to release the negative static electricity. In this way, by designing the first diode P1, it is easier to conduct the positive static electricity to the first voltage wiring 61, and by designing the second diode P2, it is easier to conduct the negative static electricity to the second voltage wiring 62, so that the static electricity generated by the chip can be more easily released.

[0087] Preferably, see Figure 7The chip packaging structure also includes an insulating layer 8 located on one side of the substrate 2, and the insulating layer 8 covers at least a portion of the first metal wiring 511, at least a portion of the second metal wiring 521, at least a portion of the first p-type semiconductor layer 5121, at least a portion of the second p-type semiconductor layer 5221, at least a portion of the first n-type semiconductor layer 5122, and at least a portion of the second n-type semiconductor layer 5222.

[0088] The insulating layer 8 can prevent short circuit between the first metal routing 511 and the second metal routing 521, and can also support the first voltage routing 61, the chip connection routing 7, the second voltage routing 62, etc., thereby making it easier to set up the first voltage routing 61, the chip connection routing 7, the second voltage routing 62, etc.

[0089] Preferably, see again Figure 7 , a plurality of vias are provided on the insulating layer 8 along a direction perpendicular to the substrate 2, the chip connection trace 7 is electrically connected to the first metal trace 511 through the via, and the first voltage trace 61 is electrically connected to the first n-type semiconductor layer 5122 through the via; the chip connection trace 7 is electrically connected to the second n-type semiconductor layer 5222 through the via, and the second voltage trace 62 is electrically connected to the second metal trace 521 through the via.

[0090] Vias can be opened at positions of the insulating layer 8 where different layers of metal or semiconductor layers need to be connected by etching. Through the vias, it is more convenient to electrically connect the chip connection wiring 7 of different layers with the first metal wiring 511, and to electrically connect the first voltage wiring 61 of different layers with the first n-type semiconductor layer 5122; to electrically connect the chip connection wiring 7 of different layers with the second n-type semiconductor layer 5222, and to electrically connect the second voltage wiring 62 of different layers with the second metal wiring 521.

[0091] For some possible implementations, see Figure 8 The chip packaging structure also includes a seed metal layer 13 located on the side of the insulating layer 8 away from the substrate 2, and the seed metal layer 13 includes a first seed routing 9, a second seed routing 10 and a third seed routing 11; the first voltage routing 61 is electrically connected to the first n-type semiconductor layer 5122 through the first seed routing 9; the chip connection routing 7 is electrically connected to the first metal routing 511 and the second n-type semiconductor layer 5222 through the second seed routing 10, and the second voltage routing 62 is electrically connected to the second metal routing 521 through the third seed routing 11.

[0092] The first voltage routing 61, the chip connection routing 7, and the second voltage routing 62 are not easy to be directly arranged on the insulating layer 8, and the first voltage routing 61, the chip connection routing 7, and the second voltage routing 62 are easy to fall off. Therefore, the first seed routing 9, the second seed routing 10, and the third seed routing 11 of the same layer are first arranged on the side of the insulating layer 8 away from the substrate 2, and then the first voltage routing 61 is arranged on the side of the first seed routing 9 away from the substrate 2, the chip connection routing 7 is arranged on the side of the second seed routing 10 away from the substrate 2, and the second voltage routing 62 is arranged on the side of the third seed routing 11 away from the substrate 2. In this way, the first voltage routing 61 can be more firmly arranged on the first seed routing 9, the chip connection routing 7 can be more firmly arranged on the second seed routing 10, and the second voltage routing 62 can be more firmly arranged on the third seed routing 11.

[0093] For some possible implementations, see Fig. 9 The chip packaging structure further includes a packaging layer 12 located on the side of the redistribution layer 3 away from the substrate 2, and the packaging layer 12 covers at least two chips 4. The material of the packaging layer 12 can be an epoxy resin molding material, and the packaging layer 12 can encapsulate at least two chips 4 and various metal wirings, so that the chips 4 and various metal wirings are not easily corroded by external water and oxygen, thereby improving the service life of the chip.

[0094] For some possible implementations, see again Figure 6 , the voltage of the first voltage line 61 is less than the voltage of the second voltage line 62. The first voltage line 61 can be a common ground voltage line (VSS), and the second voltage line 62 can be a power supply voltage line (VDD). Since the voltage of the first voltage line 61 is less than the voltage of the second voltage line 62, when positive static electricity is generated at the pin connected to the chip 4, the positive static electricity reaches Figure 6 The N2 point in the circuit then passes through the first diode P1 to Figure 6 When the positive static electricity is generated at the pin connected to the chip, the negative static electricity reaches the N3 point in the circuit, and then reaches the first voltage line 61 to release the positive static electricity. Figure 6 The N2 point in the circuit then passes through the second diode P2 to Figure 6 The negative voltage reaches point N1 in the circuit, and then reaches the second voltage wiring 62 to release the negative voltage static electricity.

[0095] For some possible implementations, see Fig.10 The present application also provides a chip packaging method, the method comprising:

[0096] S10: providing a substrate 2.

[0097] The substrate 2 in this embodiment may include a carrier plate, a temporary bonding layer and a buffer layer, wherein the material of the carrier plate may be glass, metal, organic material, etc.; the material of the temporary bonding layer may be polyimide, a thermal release layer, a laser induced release layer, etc.; the material of the buffer layer may be one of inorganic insulating films such as silicon oxide and silicon nitride, or a composite film of any combination.

[0098] S11: forming an electrostatic protection unit 5 on one side of the substrate 2; the electrostatic protection unit 5 can be unidirectionally conductive.

[0099] See also Fig.11 Unidirectional conduction means that the current mainly flows from one direction to another and cannot flow in the reverse direction, or the current flowing in the reverse direction is very small.

[0100] S12: forming a redistribution layer 3 on a side of the electrostatic protection unit 5 away from the substrate 2; the redistribution layer 3 includes a chip connection wiring 7 and a fixed voltage wiring 6, and the chip connection wiring 7 and the fixed voltage wiring 6 are electrically connected through the electrostatic protection unit 5.

[0101] See also Fig.12 , a rewiring layer 3 is formed on the side of the electrostatic protection unit 5 away from the substrate 2. The chip connection wiring 7 and the fixed voltage wiring 6 are arranged on the same layer. The voltage of the fixed voltage wiring 6 is fixed or the voltage fluctuation is very small. The fixed voltage wiring 6 has the function of releasing static electricity. The thickness of the rewiring layer 3 is generally 5um~10um, and the material can be copper. The rewiring layer 3 can be one layer or multiple layers. Specifically, if the number of pins of the chip 4 is relatively small, only one layer of the rewiring layer 3 can be designed. If the number of pins of the chip 4 is relatively large, multiple layers of the rewiring layer 3 need to be designed. For example, the rewiring layer 3 can be set to two layers, and some external signal lines are input to the chip 4 through the first layer of the rewiring layer 3, and some are input to the chip 4 through the second layer of the rewiring layer 3.

[0102] In some embodiments, at least two chips 4 are mounted on a side of the redistribution layer 3 away from the substrate 2 ; and the at least two chips 4 are electrically connected via chip connection traces 7 .

[0103] The pins of at least two chips 4 are electrically connected to the chip connection traces 7, so that at least two chips 4 are installed on the side of the redistribution layer 3 away from the substrate 2, forming a Figure 1 The chip 4, the chip connection line 7, the electrostatic protection unit 5 and the fixed voltage line 6 are electrically connected in sequence. When static electricity is generated at the chip connection line 7 where the pins of the two chips 4 are connected, the static electricity will be transmitted to the chip connection line 7, the electrostatic protection unit 5 and the fixed voltage line 6 in sequence, and the static electricity will eventually be released at the fixed voltage line 6, thereby preventing the chip from being damaged by static electricity.

[0104] In this embodiment, the electrostatic protection unit 5 is arranged between the redistribution layer 3 and the substrate 2 by the above method, so that the electrostatic protection unit 5 can be designed vertically, with a larger design space, thereby not increasing the size of the chip packaging structure, and thus meeting the market demand for miniaturization of chip packaging structures. In addition, through panel-level fan-out packaging, the electrostatic protection unit 5 is more easily integrated using the thin-film device preparation technology in the panel process.

[0105] In some possible implementations, the step of forming the electrostatic protection unit 5 on one side of the substrate 2 includes: forming a first protection unit 51 and a second protection unit 52 on one side of the substrate 2;

[0106] The step of forming a redistribution layer 3 on the side of the electrostatic protection unit 5 away from the substrate 2 includes: forming a mutually isolated first voltage trace 61, a chip connection trace 7 and a second voltage trace 62 on the side of the electrostatic protection unit 5 away from the substrate 2; the chip connection trace 7 and the first voltage trace 61 are electrically connected through the first protection unit 51, and the chip connection trace 7 and the second voltage trace 62 are electrically connected through the second protection unit 52; the first protection unit 51 allows current to flow from the chip connection trace 7 to the first voltage trace 61, and the second protection unit 52 allows current to flow from the second voltage trace 62 to the chip connection trace 7.

[0107] The first protection unit 51 and the second protection unit 52 are arranged in the same layer and on the side of the redistribution layer 3 close to the substrate 2. In this way, the first protection unit 51 and the second protection unit 52 have a larger setting space, thereby not increasing the size of the chip protection structure.

[0108] When positive static electricity is generated at the chip connection trace 7 where the pins of the two chips 4 are connected, the positive static electricity reaches the first voltage trace 61 through the first protection unit 51, and the positive static electricity is released through the first voltage trace 61. When negative static electricity is generated at the chip connection trace 7 where the pins of the two chips 4 are connected, the negative static electricity reaches the second voltage trace 62 through the second protection unit 52, and the negative static electricity is released through the second voltage trace 62. In this way, by designing the first protection unit 51 and the second protection unit 52, different types of static electricity can be processed separately, so that the static electricity generated by the chip can be more easily released, thereby improving the protection effect of the chip.

[0109] For some possible implementations, see Fig.13 The step of forming a first protection unit 51 and a second protection unit 52 on one side of the substrate 2 includes:

[0110] S111 : forming a first metal wiring 511 and a second metal wiring 521 on one side of the substrate 2 .

[0111] See also Fig.14, the entire surface of the metal layer is connected by physical vapor deposition, and then the required first metal wiring 511 and second metal wiring 521 are formed by photoresist coating, exposure, development, etching and stripping processes. The material of the first metal wiring 511 and the second metal wiring 521 can be a composite layer of one or more metals such as titanium, molybdenum and aluminum, and the etching process preferably adopts dry etching.

[0112] S112: A first p-type semiconductor layer 5121 is formed on a side of the first metal routing 511 away from the substrate 2, a second p-type semiconductor layer 5221 is formed on a side of the second metal routing 521 away from the substrate 2, and a first n-type semiconductor layer 5122 is formed on a side of the first p-type semiconductor layer 5121 away from the substrate 2, and a second n-type semiconductor layer 5222 is formed on a side of the second p-type semiconductor layer 5221 away from the substrate 2; the first metal routing 511 is electrically connected to the first p-type semiconductor layer 5121, and the first voltage routing 61 is electrically connected to the first n-type semiconductor layer 5122; the second metal routing 521 is electrically connected to the second p-type semiconductor layer 5221, and the chip connection routing 7 is electrically connected to the second n-type semiconductor layer 5222.

[0113] A p-type semiconductor layer and an n-type semiconductor layer are continuously deposited by plasma chemical vapor deposition. The specific implementation method is to first prepare a p-type semiconductor layer, and the gases for the deposition reaction are SiH4, H2 and B2H6, and then continuously deposit an n-type semiconductor layer, and the gases for the deposition reaction are SiH4, H2 and PH3. After the continuous deposition is completed, a whole thin film is formed, and then a process of photoresist coating, exposure, development, etching and degumming is used to form a film such as Fig.15 The required first p-type semiconductor layer 5121, second p-type semiconductor layer 5221, first n-type semiconductor layer 5122 and second n-type semiconductor layer 5222 are shown. The etching here is dry etching, because there is an etching ratio between the semiconductor layer and the first metal wiring 511 and the first metal wiring 511, so it can be ensured that the first metal wiring 511 and the first metal wiring 511 are retained where the semiconductor layer is etched.

[0114] The first n-type semiconductor layer 5122 and the first p-type semiconductor layer 5121 formed by the above method can form a first diode P1, and the second n-type semiconductor layer 5222 and the second p-type semiconductor layer 5221 can form a second diode P2. The resistance of the first diode P1 and the second diode P2 is relatively large, and the first voltage trace 61 and the second voltage trace 62 are both constant voltages. The voltage difference between the first voltage trace 61 and the second voltage trace 62 is small, and no instantaneous high voltage difference will be generated, so the first voltage trace 61 and the second voltage trace 62 will not be turned on. In addition, the first p-type semiconductor layer 5121, the second p-type semiconductor layer 5221, the first n-type semiconductor layer 5122 and the second n-type semiconductor layer 5222 are prepared by a chemical vapor deposition continuous deposition process, and the process is relatively simple.

[0115] When a high instantaneous positive static electricity is generated at the chip pins connected by the pins of the two chips 4, the positive static electricity reaches the first diode P1 through the chip connection wiring 7 and the first metal wiring 511, the first diode P1 is turned on, and the positive static electricity reaches the first voltage wiring 61 after passing through the first diode P1 to release the positive static electricity. When a high instantaneous negative static electricity is generated at the chip pins connected by the pins of the two chips 4, the negative static electricity reaches the second diode P2 through the chip connection wiring 7 and the second metal wiring 521, the second diode P2 is turned on, and the negative static electricity reaches the second voltage wiring 62 after passing through the second diode P2 to release the negative static electricity. In this way, by designing the first diode P1, it is easier to conduct the positive static electricity to the first voltage wiring 61, and by designing the second diode P2, it is easier to conduct the negative static electricity to the second voltage wiring 62, so that the static electricity generated by the chip can be more easily released.

[0116] For some possible implementations, see Fig.16 The step of forming a redistribution layer 3 on a side of the electrostatic protection unit 5 away from the substrate 2 includes:

[0117] S121: An insulating layer 8 is formed on one side of the substrate 2, and a via 81 is formed on the insulating layer 8; the insulating layer 8 covers at least a portion of the first metal wiring 511, at least a portion of the second metal wiring 521, at least a portion of the first p-type semiconductor layer 5121, at least a portion of the second p-type semiconductor layer 5221, at least a portion of the first n-type semiconductor layer 5122, and at least a portion of the second n-type semiconductor layer 5222.

[0118] See also Fig.17 The insulating layer 8 can be formed by chemical vapor deposition or coating process. The material of the insulating layer 8 can be inorganic materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and organic materials such as polyimide, and then the required via 81 is formed by photolithography process.

[0119] S122 : forming a seed metal layer 13 on a side of the insulating layer 8 away from the substrate 2 .

[0120] See also Fig.18 A seed metal layer 13 is formed on the side of the insulating layer 8 away from the substrate 2 by a physical vapor deposition process. The seed metal layer 13 is the basis for the subsequent preparation process of the redistribution layer 3. The seed metal layer 13 is generally made of titanium, molybdenum, copper, etc.

[0121] S123 : forming a patterned photoresist 14 on a side of the seed metal layer 13 away from the substrate 2 .

[0122] See also Fig.19 First, a layer of photoresist is formed on the side of the seed metal layer 13 away from the substrate 2, and then a patterned photoresist 14 is formed by exposure, development, etc. The thickness of the patterned photoresist 14 is generally 10um to 15um.

[0123] S124 : forming a wiring metal layer 15 on the side of the insulating layer 8 away from the substrate 2 .

[0124] See also Fig. 20 A wiring metal layer 15 is electroplated and deposited in the window area of ​​the patterned photoresist 14 on the side of the insulating layer 8 away from the substrate 2. The wiring metal layer 15 can be made of copper metal, and the thickness of the wiring metal layer 15 is generally 5um to 8um.

[0125] S125 : removing the patterned photoresist 14 and the seed metal layer 13 exposed by the patterned photoresist 14 to form a first voltage wiring 61 , a chip connecting wiring 7 and a second voltage wiring 62 .

[0126] After removing the patterned photoresist 14, the exposed seed metal layer 13 is removed by wet etching. After removing the patterned photoresist 14 and the seed metal layer 13 exposed by the patterned photoresist 14, the remaining seed metal layer 13 includes the first voltage wiring 61, the chip connection wiring 7 and the second voltage wiring 62, and finally forms the following: Figure 8 The structure shown.

[0127] By the above method, the electrostatic protection unit 5 can be formed together with the redistribution layer 3, so that the process can be simplified and it can be more convenient to prepare the first voltage trace 61, the chip connection trace 7 and the second voltage trace 62. By arranging the electrostatic protection unit 5 between the redistribution layer 3 and the substrate 2, the electrostatic protection unit 5 can be designed vertically, with a larger design space, so that the size of the chip packaging structure will not be increased, and the market demand for miniaturization of chip packaging structures can be met.

[0128] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: substrate; An electrostatic protection unit located at one side of the substrate, wherein the electrostatic protection unit can be unidirectionally conductive; A redistribution layer located on a side of the electrostatic protection unit away from the substrate, the redistribution layer comprising a chip connection wiring and a fixed voltage wiring, the chip connection wiring and the fixed voltage wiring being electrically connected through the electrostatic protection unit; At least two chips are located on a side of the redistribution layer away from the substrate, and the at least two chips are electrically connected through the chip connection wiring.

2. The chip packaging structure according to claim 1, characterized in that: The fixed voltage wiring includes a first voltage wiring and a second voltage wiring, and the electrostatic protection unit includes a first protection unit and a second protection unit; The chip connection wiring and the first voltage wiring are electrically connected through the first protection unit, and the chip connection wiring and the second voltage wiring are electrically connected through the second protection unit; The first protection unit allows current to flow from the chip connection line to the first voltage line, and the second protection unit allows current to flow from the second voltage line to the chip connection line.

3. The chip packaging structure according to claim 2, characterized in that: The first protection unit includes a first metal routing located on one side of the substrate and a first switch located on a side of the first metal routing away from the substrate; the second protection unit includes a second metal routing located on one side of the substrate and a second switch located on a side of the second metal routing away from the substrate; the chip connection routing is electrically connected to the first metal routing, the first metal routing is electrically connected to one end of the first switch, and the first voltage routing is electrically connected to the other end of the first switch; the second voltage routing is electrically connected to the second metal routing, the second metal routing is electrically connected to one end of the second switch, and the chip connection routing is electrically connected to the other end of the second switch.

4. The chip packaging structure according to claim 3, characterized in that: The first switch comprises a first p-type semiconductor layer located on a side of the first metal trace away from the substrate and a first n-type semiconductor layer located on a side of the first p-type semiconductor layer away from the substrate; the second switch comprises a second p-type semiconductor layer located on a side of the second metal trace away from the substrate and a second n-type semiconductor layer located on a side of the second p-type semiconductor layer away from the substrate; The first metal wiring is electrically connected to the first p-type semiconductor layer, and the first voltage wiring is electrically connected to the first n-type semiconductor layer; the second metal wiring is electrically connected to the second p-type semiconductor layer, and the chip connection wiring is electrically connected to the second n-type semiconductor layer.

5. The chip packaging structure according to claim 4, characterized in that: The chip packaging structure also includes an insulating layer located on one side of the substrate, and the insulating layer covers at least a portion of the first metal trace, at least a portion of the second metal trace, at least a portion of the first p-type semiconductor layer, at least a portion of the second p-type semiconductor layer, at least a portion of the first n-type semiconductor layer, and at least a portion of the second n-type semiconductor layer.

6. The chip packaging structure according to claim 5, characterized in that: A plurality of vias are provided on the insulating layer along a direction perpendicular to the substrate, the chip connection wiring is electrically connected to the first metal wiring through the vias, and the first voltage wiring is electrically connected to the first n-type semiconductor layer through the vias; the chip connection wiring is electrically connected to the second n-type semiconductor layer through the vias, and the second voltage wiring is electrically connected to the second metal wiring through the vias.

7. The chip packaging structure according to claim 5, characterized in that: The chip packaging structure further includes a seed metal layer located on a side of the insulating layer away from the substrate, the seed metal layer including a first seed routing line, a second seed routing line and a third seed routing line; The first voltage routing is electrically connected to the first n-type semiconductor layer through the first seed routing; the chip connection routing is electrically connected to the first metal routing and the second n-type semiconductor layer respectively through the second seed routing, and the second voltage routing is electrically connected to the second metal routing through the third seed routing.

8. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a packaging layer located on a side of the redistribution layer away from the substrate, and the packaging layer covers the at least two chips.

9. The chip packaging structure according to any one of claims 2 to 7, characterized in that: The voltage of the first voltage trace is lower than the voltage of the second voltage trace.

10. The chip packaging structure according to any one of claims 2 to 7, characterized in that: The first voltage routing includes a common ground voltage routing, and / or the second voltage routing includes a power supply voltage routing.

11. A chip packaging method, characterized in that: The method comprises: providing a substrate; An electrostatic protection unit is formed on one side of the substrate; the electrostatic protection unit can be unidirectionally conductive; A redistribution layer is formed on a side of the electrostatic protection unit away from the substrate; the redistribution layer includes a chip connection wiring and a fixed voltage wiring, and the chip connection wiring and the fixed voltage wiring are electrically connected through the electrostatic protection unit; At least two chips are formed on a side of the redistribution layer away from the substrate, and the at least two chips are electrically connected through the chip connection wiring.

12. The method according to claim 11, characterized in that The step of forming an electrostatic protection unit on one side of the substrate comprises: forming a first protection unit and a second protection unit on one side of the substrate; The step of forming a redistribution layer on a side of the electrostatic protection unit away from the substrate comprises: A first voltage routing, a chip connection routing, and a second voltage routing that are isolated from each other are formed on a side of the electrostatic protection unit away from the substrate; the chip connection routing and the first voltage routing are electrically connected through the first protection unit, and the chip connection routing and the second voltage routing are electrically connected through the second protection unit; the first protection unit allows current to flow from the chip connection routing to the first voltage routing, and the second protection unit allows current to flow from the second voltage routing to the chip connection routing.

13. The method according to claim 12, characterized in that The step of forming a mutually isolated first voltage routing line, a chip connection routing line, and a second voltage routing line on a side of the electrostatic protection unit away from the substrate comprises: An insulating layer is formed on one side of the substrate, and a via hole is formed on the insulating layer; the insulating layer covers at least a portion of the first protection unit and at least a portion of the second protection unit; forming a seed metal layer on a side of the insulating layer away from the substrate; forming a patterned photoresist on a side of the seed metal layer away from the substrate; forming a wiring metal layer on a side of the insulating layer away from the substrate; The patterned photoresist and the seed metal layer exposed by the patterned photoresist are removed to form a first voltage trace, a chip connection trace and a second voltage trace.

14. The method according to claim 12, characterized in that The step of forming a first protection unit and a second protection unit on one side of the substrate includes: forming a first metal trace and a second metal trace on one side of the substrate; A first p-type semiconductor layer is formed on a side of the first metal trace away from the substrate, a second p-type semiconductor layer is formed on a side of the second metal trace away from the substrate, and a first n-type semiconductor layer is formed on a side of the first p-type semiconductor layer away from the substrate, and a second n-type semiconductor layer is formed on a side of the second p-type semiconductor layer away from the substrate; the first metal trace is electrically connected to the first p-type semiconductor layer, and the first voltage trace is electrically connected to the first n The second metal wiring is electrically connected to the second p-type semiconductor layer; the second metal wiring is electrically connected to the second p-type semiconductor layer, The chip connection wiring is electrically connected to the second n-type semiconductor layer.

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