Test case generation method, chip verification method, chip verification system and medium

Abstract

The application relates to a test case generation method, a chip verification system, a computer readable storage medium and a computer program product. The test case generation method comprises the following steps: reading configuration parameters and configuration parameter values in a target configuration file during simulation; updating parameter values of internal registers of a chip verification system according to the configuration parameters and the configuration parameter values; obtaining a compiled basic test case; and generating a target test case based on the parameter values of the internal registers and the compiled basic test case. The method can reduce the compilation time and the number of test cases, and improve the chip verification efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, in particular to a test case generation method, a chip verification method, a chip verification system and a storage medium. BACKGROUND

[0002] With the rapid development of integrated circuits, the verification work of ASIC (Application Specific Integrated Circuit) and SOC (System on a Chip) chips becomes particularly important. The verification methodology based on System Verilog (UVM, Universal Verification Methodology) inherits the advantages of VMM (Verification Methodology Manual) and OVM (Open Verification Methodology), overcomes their respective shortcomings, represents the development direction of the verification methodology, and also gradually becomes the main way for verification engineers to verify chips.

[0003] The UVM based on System Verilog provides a series of mechanisms and base classes for verification engineers, such as sequence mechanism, factory mechanism, callback mechanism, phase mechanism, and register model, etc. Verification engineers can develop a suitable verification platform according to project requirements. The transaction modeling of UVM also facilitates engineers to model transactions, and the internal components are relatively independent, without the need to reserve data ports outside the verification platform. Each component can complete its own behavior in the corresponding phase stage; the TLM (Transaction-Level Modeling) communication in it also facilitates the data exchange between components. All the above makes the verification process formatted and standardized, and each UVM-based verification platform has similar structure, which makes the verification platform have strong reusability.

[0004] But at present, the verification platform based on UVM needs to add different test cases to simulate different application scenarios for each simulation verification of the chip. The higher the integration of the chip, the more scenes need to be tested, and the number of test cases needed is multiplied. After adding new test cases, the simulation needs to be recompiled, which increases the time needed for compilation and thus increases the chip verification time. In addition, a large number of test cases also cause a burden on the compilation tool, increasing the time needed for tool compilation. The simulation file generated after compilation is also very large, which reduces the simulation rate of the simulation tool and further increases the simulation time. Finally, a large number of redundant test cases are very difficult to manage and inherit for subsequent chip iterations. The UVM-based verification platform has problems such as a large number of test cases and long compilation time, which leads to low chip verification efficiency. SUMMARY

[0005] Therefore, it is necessary to provide a test case generation method, a chip verification method, a chip verification system, a computer readable storage medium and a computer program product, which can reduce the compilation time and the number of test cases and improve the chip verification efficiency.

[0006] In a first aspect, the present application provides a test case generation method, which comprises:

[0007] reading configuration parameters and configuration parameter values in a target configuration file during simulation;

[0008] updating the parameter values of the internal registers of the chip verification system according to the configuration parameters and the configuration parameter values;

[0009] obtaining a compiled basic test case;

[0010] generating a target test case based on the parameter values of the internal registers and the compiled basic test case.

[0011] In one embodiment, the method comprises:

[0012] obtaining configuration parameters and configuration parameter values by parsing a test case parameter table through a script;

[0013] storing the configuration parameters and the configuration parameter values into a target configuration file.

[0014] In one embodiment, before obtaining the configuration parameters and the configuration parameter values by parsing the test case parameter table through the script, the method further comprises:

[0015] parsing a basic test case and extracting configuration parameters of a chip under test in the basic test case;

[0016] generating a test case parameter table based on the configuration parameters;

[0017] configuring configuration parameter values of the configuration parameters in the test case parameter table.

[0018] In one embodiment, before the configuration parameters and the configuration parameter values are parsed from the test case parameter table by the script, the method further comprises:

[0019] adjusting the configuration parameters and / or the configuration parameter values in the test case parameter table.

[0020] In a second aspect, the application further provides a chip verification method, which comprises:

[0021] obtaining a target test case generated based on the test case generation method in any one of the above embodiments;

[0022] generating a test stimulus based on the target test case and inputting the test stimulus into a chip under test to obtain a chip response;

[0023] collecting behavior parameters and behavior parameter values of an input interface of the chip under test and inputting the behavior parameters and the behavior parameter values into a reference model to obtain a model response;

[0024] comparing the chip response and the model response to obtain a verification result.

[0025] In a third aspect, the application further provides a chip verification system, which comprises:

[0026] a reference model;

[0027] a test case generation module for generating a target test case based on the chip verification system test case generation method described above;

[0028] an input module for generating a test stimulus based on the target test case and inputting the test stimulus into a chip under test, and collecting behavior parameters and behavior parameter values of an input interface of the chip under test and inputting the behavior parameters and the behavior parameter values into the reference model;

[0029] an output module for collecting a chip response of the chip under test under the test stimulus;

[0030] a comparison module for collecting a model response of the reference model and comparing the chip response and the model response to obtain a verification result.

[0031] In one embodiment, the test case generation module comprises:

[0032] The script analysis unit is configured to obtain configuration parameters and configuration parameter values by analyzing the test case parameter table through a script, and store the configuration parameters and configuration parameter values into a target configuration file.

[0033] The register updating unit is configured to read the configuration parameters and configuration parameter values in the target configuration file during simulation, update parameter values of internal registers of the chip verification system according to the configuration parameters and configuration parameter values, obtain the compiled basic test case, and generate the target test case based on the parameter values of the internal registers and the compiled basic test case.

[0034] In one embodiment, the system further comprises:

[0035] The test case parameter table adjustment module is configured to adjust the configuration parameters and / or configuration parameter values in the test case parameter table.

[0036] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed to implement the steps of the method in any one of the above embodiments.

[0037] In a fifth aspect, the present application further provides a computer program product, which comprises a computer program, and the computer program is executed to implement the steps of the method in any one of the above embodiments.

[0038] The test case generation method, the chip verification method, the chip verification system, the storage medium and the computer program product described above, during simulation, the configuration parameters and configuration parameter values in the target configuration file are read, the parameter values of the internal registers of the chip verification system are updated according to the configuration parameters and configuration parameter values, the compiled basic test case is obtained, and the target test case is generated based on the parameter values of the internal registers and the compiled basic test case. Thus, it is not necessary to write a corresponding test case in the verification system for each parameter configuration to compile, the amount of test cases in the chip verification system is reduced, the configuration file is an "external" file relative to the verification system, and takes effect only in the simulation stage. Adding or reducing does not need to compile again to make the modification effective, time waste caused by the number of compilations is reduced, and chip verification efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 FIG. 1 is a system structure diagram of a chip verification system in one embodiment;

[0040] Figure 2 FIG. 2 is a flowchart of a chip verification method in one embodiment;

[0041] Figure 3 FIG. 3 is a flowchart of a test case generation method in one embodiment. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0043] In combination with Figure 1 As shown in the drawings, the present application provides a chip verification system, which comprises a test case generation module, an input module, a reference model, an output module and a comparison module; wherein the output end of the test case generation module is connected with the input end of the input module, the first output end of the input module is connected with the input end of the chip under test, the detection end is connected with the input end of the chip under test, the second output end is connected with the input end of the reference model, the output end of the reference model is connected with the first input end of the comparison module, the output end of the chip under test is connected with the input end of the output module, the output end of the output module is connected with the second input end of the comparison module, and the comparison module is used to output a verification result.

[0044] The chip verification system encapsulates the chip under test and the entire verification environment together, and encapsulates each component in the verification environment. The reference model is used to simulate various real test scenarios of the chip under test. The test case generation module is used to generate a target test case. The input module is used to generate a test stimulus based on the target test case, input the test stimulus into the chip under test, collect behavior parameters and behavior parameter values of the input interface of the chip under test, and input the behavior parameters and the behavior parameter values into the reference model. The output module is used to collect a chip response of the chip under test under the test stimulus. The comparison module is used to collect a model response of the reference model, and compare the chip response and the model response to obtain a verification result.

[0045] The test case generation module comprises a script analysis unit and a register updating unit. The script analysis unit is used to obtain configuration parameters and configuration parameter values by analyzing a test case parameter table through a script, and store the configuration parameters and the configuration parameter values into a target configuration file. The register updating unit is used to read the configuration parameters and the configuration parameter values in the target configuration file during simulation, update parameter values of internal registers of the chip verification system according to the configuration parameters and the configuration parameter values, obtain a compiled basic test case, and generate a target test case based on the parameter values of the internal registers and the compiled basic test case.

[0046] The test case parameter table is a file in which configuration parameters of the chip under test are extracted and arranged in a certain order according to a certain rule, wherein each set of configuration parameter values in the test case parameter table corresponds to a test case, and each set of configuration parameters corresponds to a test case. The script analysis unit stores a script, which is used to analyze the test case parameter table to obtain the configuration parameters and the configuration parameter values, and store the configuration parameters and the configuration parameter values in a target configuration file in a designated directory according to the corresponding relationship.

[0047] The register updating unit reads the configuration parameters and the configuration parameter values from the target configuration file in the designated directory at the beginning of simulation, and updates the parameter values of the internal registers, thereby generating a new target test case. Therefore, it is not necessary to write a corresponding test case in the verification system for each parameter configuration to compile, which reduces the amount of test cases in the chip verification system. The configuration file is an "external" file relative to the verification system, and takes effect only in the simulation stage. Adding or reducing does not require recompilation to make the modification effective, thereby reducing the time waste caused by the number of compilations and improving the chip verification efficiency. Moreover, the method is more convenient and flexible for the increase or decrease of test cases and the modification of parameters in some test cases, and only the parameters in the test case list need to be changed. In addition, the modified content in the test case parameter table can take effect without repeated compilation, which reduces the time spent on compilation, and further solves the low efficiency of the chip verification system in the verification process, and realizes efficient chip verification work.

[0048] In combination with Figure 1 As shown in FIG. 6, the register updating unit updates the parameter values of the registers in the input module, and the driving unit in the input module obtains the test stimulus according to the test stimulus parameter configuration in the updated parameter values of the registers, and applies the test stimulus to the chip under test. The test stimulus can include normal stimulus and abnormal stimulus. The monitoring unit in the input module monitors the test stimulus transmitted to the chip under test, and transmits the test stimulus to the reference model.

[0049] For convenience of understanding, a chip test process is given, in combination with Figure 2 As shown in FIG. 7, before simulation, a target test case is generated. Specifically, the script analysis unit analyzes the test case parameter table to obtain the configuration parameters and the configuration parameter values, and stores the configuration parameters and the configuration parameter values in the target configuration file. During simulation, the register updating unit opens the target configuration file to obtain the configuration parameters and the configuration parameter values in the target configuration file, and updates the parameter values of the internal registers based on the configuration parameters and the configuration parameter values.

[0050] The register updating unit transmits the parameter updated register parameter value to the driving unit, the driving unit generates corresponding test excitation to the measured chip, and inputs the test excitation into the measured chip to obtain the chip response, and the monitoring unit collects the behavior parameter on the interface of the measured chip and sends it to the reference model, the reference model simulates the behavior of the measured chip to generate the model response according to the parameter sent by the monitoring unit through the processing of the software, and inputs the model response into the comparison module, and the monitoring unit of the output module collects the chip response of the measured chip after the test excitation is input, and sends the chip response to the comparison module, the comparison module compares the chip response and the model response to obtain the verification result, and outputs the verification result for the verification personnel to judge.

[0051] In one of the optional embodiments, if it is needed to increase the test case or modify the related configuration parameter after one simulation, the test case parameter table is adjusted, and the above process is executed again. Optionally, the chip verification system further comprises a test case parameter table adjusting module for adjusting the configuration parameter and / or the configuration parameter value in the test case parameter table. The new test case is generated after the adjustment for testing. Because of the existence of the test case parameter table and the target configuration file, the modification of the parameter only needs to modify the corresponding value in the test case parameter table, and the increase of the test case only needs to add the parameter and the parameter value in the test case parameter table, and the test case parameter table and the target configuration file are the "external" files of the chip verification system, and any modification of the parameter does not need to be compiled again, so that the modification of the test case is more flexible and convenient.

[0052] In one embodiment, as shown in Figure 3 , a test case generation method is provided, which is applied to the chip verification system in Figure 1 for example, and includes the following steps:

[0053] S302: reading the configuration parameter and the configuration parameter value in the target configuration file during simulation.

[0054] The register parameter updating unit in the chip verification system reads the configuration parameter and the configuration parameter value in the target configuration file during simulation, wherein the configuration parameter and the configuration value are read from the configuration parameter and the configuration value in the test case parameter table through the script in advance, and are stored in the target configuration file. The configuration parameter and the configuration value are the configuration parameter of the measured chip and the corresponding configuration parameter value, which can include the parameter related to the excitation of the measured chip.

[0055] S304: updating the parameter value of the internal register of the chip verification system according to the configuration parameter and the configuration parameter value.

[0056] The register parameter updating unit in the chip verification system updates the parameter values of the internal registers of the chip verification system according to the read configuration parameters and configuration parameter values, so that the configuration parameter values can be transmitted to the driving unit subsequently, so that the driving unit generates the test excitation for the chip under test. The register updating unit can be obtained based on the sequence mechanism of the UVM platform. When the simulation starts, the sequence opens the target configuration file, parses the configuration parameters and their configuration parameter values in the target configuration file, and updates the corresponding configuration parameter values in the internal registers with the configuration parameter values, completes the update of the sequence, and the sequencer on the input module side transmits the sequence after the update of the parameters to the driving unit to generate the test excitation.

[0057] S306: Obtain the compiled basic test case.

[0058] The basic test case is a common part of a type of test case, and the test cases of this type only differ in part of the register parameter values, and the part of the register parameter values is configured through a test case parameter table. The test case parameter table is an external file of the chip verification system and does not need to be compiled, so when compiling, only the basic test case of this type needs to be compiled, and when simulating, the target test case is obtained by reading the register parameter values.

[0059] S308: Generate a target test case based on the parameter values of the internal registers and the compiled basic test case.

[0060] Specifically, the driving unit generates a target test case based on the parameter values of the internal registers and the compiled basic test case, and generates a test excitation based on the target test case, and inputs the test excitation into the interface of the chip under test to verify the chip under test. The monitoring unit of the input module also monitors the behavior parameters of the interface of the chip under test, so as to generate the input of the reference model to make the reference model simulate the chip under test to obtain a model response, and finally the comparison module obtains a verification result based on the chip response of the chip under test and the simulation response.

[0061] The chip verification system test case generation method reads configuration parameters and configuration parameter values in a target configuration file during simulation, updates parameter values of internal registers of the chip verification system according to the configuration parameters and the configuration parameter values, obtains compiled basic test cases, and generates target test cases based on the parameter values of the internal registers and the compiled basic test cases. In this way, each set of parameter values in the test case parameter table corresponds to a test case, a large number of test cases can be obtained through only one target configuration file, and it is not necessary to write a corresponding test case in the verification system for each type of parameter configuration to compile, thereby reducing the number of test cases in the chip verification system. In the compilation stage, the number of files that need to be compiled by the compilation tool is reduced, the compilation time of the tool is shortened, the target configuration file is an "external" file relative to the verification system and takes effect only in the simulation stage, and adding or reducing does not need to recompile to make the modification effective, thereby reducing the time waste caused by the number of compilations and improving the chip verification efficiency.

[0062] In one embodiment, the target configuration file is generated by: parsing the test case parameter table by a script to obtain the configuration parameters and the configuration parameter values; and storing the configuration parameters and the configuration parameter values in the target configuration file.

[0063] Specifically, the test case parameter table is pre-generated, and a script parsing unit is configured to parse the test case parameter table to obtain the configuration parameters and the configuration parameter values. The test case parameter table is stored by columns, and one column of parameter values corresponds to one test case. Each set of configuration parameter values in the test case parameter table corresponds to one test case, and each set of configuration parameters corresponds to one test case. The script parsing unit stores a script, which is configured to parse the test case parameter table to obtain the configuration parameters and the configuration parameter values, and store the configuration parameters and the configuration parameter values in the target configuration file in a specified directory according to the correspondence.

[0064] Optionally, the script parsing unit can automatically detect whether the test case parameter table changes based on a trigger. When the test case parameter table changes, the script parsing unit automatically parses the test case parameter table to obtain the configuration parameters and the configuration parameter values, and stores the configuration parameters and the configuration parameter values in the target configuration file.

[0065] In one optional embodiment, before the configuration parameters and the configuration parameter values are obtained by parsing the test case parameter table by the script, the method further includes: parsing a basic test case, and extracting configuration parameters of a chip under test in the basic test case; generating a test case parameter table based on the configuration parameters; and configuring configuration parameter values of the configuration parameters in the test case parameter table.

[0066] In particular, the base test case is a common part of a type of test cases, which only differ in some register parameter values. The register parameter values are configured by a test case parameter table. Before use, the base test case is parsed to obtain the parameters of different register parameter values, and a test case parameter table is generated based on the parameters. The values of the parameters in the test case parameter table are configured to obtain a completed test case parameter table. The test case generation module can generate a target test case based on the completed test case parameter table.

[0067] In one optional embodiment, before the configuration parameters and the configuration parameter values are obtained by parsing the test case parameter table by the script, the test case parameter table is adjusted.

[0068] After one simulation is completed, if it is necessary to add test cases or modify related configuration parameters, the test case parameter table is adjusted, and the above process is executed again. Optionally, the chip verification system further includes a test case parameter table adjustment module, which is configured to adjust the configuration parameters and / or the configuration parameter values in the test case parameter table. After adjustment, new test cases are generated for testing. Because of the test case parameter table and the target configuration file, modification of parameters only needs to modify the corresponding values in the test case parameter table, and addition of test cases only needs to add parameters and parameter values in the test case parameter table. The test case parameter table and the target configuration file are external files of the chip verification system. Modification of any parameter in the test case parameter table or the target configuration file does not need to be recompiled, so that modification of test cases is more flexible and convenient.

[0069] It should be understood that although each step in the flowchart involved in each embodiment described above is shown in sequence according to the arrow, the steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of the steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0070] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed to implement the following steps: reading configuration parameters and configuration parameter values in a target configuration file during simulation; updating parameter values of internal registers of a chip verification system according to the configuration parameters and the configuration parameter values; obtaining a compiled basic test case; and generating a target test case based on the parameter values of the internal registers and the compiled basic test case.

[0071] In one embodiment, the computer program is further executed to implement the following steps: obtaining the configuration parameters and the configuration parameter values by parsing a test case parameter table through a script; and storing the configuration parameters and the configuration parameter values into the target configuration file.

[0072] In one embodiment, before the computer program is executed to implement the following steps: obtaining the configuration parameters and the configuration parameter values by parsing a test case parameter table through a script, the computer program is further executed to implement the following steps: parsing a basic test case, and extracting configuration parameters of a chip under test in the basic test case; generating a test case parameter table based on the configuration parameters; and configuring configuration parameter values of the configuration parameters in the test case parameter table.

[0073] In one embodiment, before the computer program is executed to implement the following steps: obtaining the configuration parameters and the configuration parameter values by parsing a test case parameter table through a script, the computer program is further executed to implement the following steps: adjusting the configuration parameters and / or the configuration parameter values in the test case parameter table.

[0074] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed to implement the following steps: obtaining a target test case generated based on the test case generation method in any one of the above embodiments; generating a test stimulus based on the target test case, and inputting the test stimulus into a chip under test to obtain a chip response; collecting behavior parameters and behavior parameter values of an input interface of the chip under test, and inputting the behavior parameters and the behavior parameter values into a reference model to obtain a model response; and comparing the chip response and the model response to obtain a verification result.

[0075] In one embodiment, a computer program product is provided, and the computer program product includes a computer program, and the computer program is executed by a processor to implement the following steps: reading configuration parameters and configuration parameter values in a target configuration file during simulation; updating parameter values of internal registers of a chip verification system according to the configuration parameters and the configuration parameter values; obtaining a compiled basic test case; and generating a target test case based on the parameter values of the internal registers and the compiled basic test case.

[0076] In one embodiment, the computer program, when executed, further implements the following steps: parsing the test case parameter table by script to obtain configuration parameters and configuration parameter values; and storing the configuration parameters and configuration parameter values into a target configuration file.

[0077] In one embodiment, before the computer program, when executed, implements the parsing of the test case parameter table by script to obtain configuration parameters and configuration parameter values, it further includes: parsing a basic test case and extracting configuration parameters of a chip under test in the basic test case; generating a test case parameter table based on the configuration parameters; and configuring configuration parameter values of the configuration parameters in the test case parameter table.

[0078] In one embodiment, before the computer program, when executed, implements the parsing of the test case parameter table by script to obtain configuration parameters and configuration parameter values, it further includes: adjusting the configuration parameters and / or configuration parameter values in the test case parameter table.

[0079] In one embodiment, a computer program product is provided, including a computer program which, when executed by a processor, implements the following steps: obtaining a target test case generated based on the test case generation method in any one of the above embodiments; generating a test stimulus based on the target test case and inputting the test stimulus into a chip under test to obtain a chip response; collecting behavior parameters and behavior parameter values of an input interface of the chip under test and inputting the behavior parameters and the behavior parameter values into a reference model to obtain a model response; and comparing the chip response and the model response to obtain a verification result.

[0080] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0081] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0082] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A test case generation method characterized by, The method comprises: After the base test case compilation is completed, before the simulation starts, detecting whether the test case parameter table has a change; when the test case parameter table has a change, obtaining configuration parameters and configuration parameter values by script parsing the test case parameter table, and storing the configuration parameters and the configuration parameter values in a target configuration file in a specified directory according to a corresponding relationship; the test case parameter table is a file in which configuration parameters of a chip under test are extracted and arranged in a certain rule order, wherein each set of configuration parameter values in the test case parameter table corresponds to a test case, and each set of configuration parameters corresponds to a test case; At the start of the simulation, the configuration parameters and the configuration parameter values in the target configuration file are read through sequence; According to the configuration parameters and the configuration parameter values, the parameter values of internal registers of a chip verification system are updated; The compiled base test case is obtained; Based on the parameter values of the internal registers and the compiled base test case, a target test case is generated.

2. The method of claim 1, wherein, Before the configuration parameters and the configuration parameter values are obtained by script parsing the test case parameter table, the method further comprises: The base test case is parsed, and the configuration parameters of the chip under test in the base test case are extracted; Based on the configuration parameters, a test case parameter table is generated; The configuration parameter values of the configuration parameters in the test case parameter table are configured.

3. The method of claim 1, wherein, Before the configuration parameters and the configuration parameter values are obtained by script parsing the test case parameter table, the method further comprises: The configuration parameters and / or the configuration parameter values in the test case parameter table are adjusted.

4. A chip verification method characterized by, The chip verification method comprises: A target test case generated based on the test case generation method according to any one of claims 1 to 3 is obtained; Based on the target test case, a test stimulus is generated, and the test stimulus is input to a chip under test to obtain a chip response; The behavior parameters and the behavior parameter values of an input interface of the chip under test are collected, and the behavior parameters and the behavior parameter values are input to a reference model to obtain a model response; The chip response and the model response are compared to obtain a verification result.

5. A chip verification system characterized by comprising: The verification system comprises: A reference model; A test case generation module for generating a target test case based on the test case generation method according to any one of claims 1 to 3; An input module for generating a test stimulus based on the target test case, inputting the test stimulus to a chip under test, collecting behavior parameters and behavior parameter values of an input interface of the chip under test, and inputting the behavior parameters and the behavior parameter values to the reference model; An output module for collecting a chip response of the chip under test under the test stimulus; A comparison module for collecting a model response of the reference model, and comparing the chip response and the model response to obtain a verification result.

6. The system of claim 5, wherein, The test case generation module comprises: A script parsing unit for obtaining configuration parameters and configuration parameter values by script parsing a test case parameter table, and storing the configuration parameters and the configuration parameter values in a target configuration file; The register updating unit is configured to read configuration parameters and configuration parameter values in the target configuration file during simulation, update parameter values of internal registers of the chip verification system according to the configuration parameters and the configuration parameter values, obtain the compiled basic test case, and generate the target test case based on the parameter values of the internal registers and the compiled basic test case.

7. The system of claim 5, wherein, The system further comprises: The test case parameter table adjusting module is configured to adjust the configuration parameters and / or the configuration parameter values in the test case parameter table.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed, implements the following steps: After the basic test case is compiled, before the simulation starts, it is detected whether the test case parameter table has changed; when the test case parameter table has changed, the configuration parameters and the configuration parameter values are obtained by parsing the test case parameter table through a script, and the configuration parameters and the configuration parameter values are stored in the target configuration file in a specified directory according to a corresponding relationship; the test case parameter table is a file in which configuration parameters of a chip under test are extracted and arranged in a certain rule order, wherein each set of configuration parameter values in the test case parameter table corresponds to a test case, and each set of configuration parameters corresponds to a test case; The configuration parameters and the configuration parameter values in the target configuration file are read through sequence when the simulation starts; The parameter values of internal registers of the chip verification system are updated according to the configuration parameters and the configuration parameter values; The compiled basic test case is obtained; The target test case is generated based on the parameter values of the internal registers and the compiled basic test case.

9. The computer-readable storage medium of claim 8, wherein, Before the configuration parameters and the configuration parameter values are obtained by parsing the test case parameter table through a script, the computer program, when executed, further comprises: The basic test case is parsed, and the configuration parameters of the chip under test in the basic test case are extracted; The test case parameter table is generated based on the configuration parameters; The configuration parameter values of the configuration parameters in the test case parameter table are configured.

10. The computer-readable storage medium of claim 8, wherein, Before the configuration parameters and the configuration parameter values are obtained by parsing the test case parameter table through a script, the computer program, when executed, further comprises: The configuration parameters and / or the configuration parameter values in the test case parameter table are adjusted.

11. A computer program product comprising a computer program, characterized in that, The computer program, when executed, implements the steps of the method of any one of claims 1 to 3 or 4.

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