Display driving circuit and display device

Abstract

The application discloses a display driving circuit and a display device. The display driving circuit comprises: a plurality of first signal generating circuits, the plurality of first signal generating circuits are connected in series with each other, each first signal generating circuit generates a first signal based on a clock signal, so that the plurality of first signal generating circuits output the first signal in sequence; a second signal generating circuit, the second signal generating circuit outputs a second signal under the condition that a preset condition is met; and a plurality of third signal generating circuits, a first input end of each third signal generating circuit is connected with an output end of a corresponding first signal generating circuit, second input ends of all the third signal generating circuits are connected with an output end of the second signal generating circuit, and the third signal generating circuit outputs a third signal based on the first signal and the second signal. Based on the above mode, the complexity of the structure of the display driving circuit can be reduced, and the cost of the display device is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving circuit and a display device. BACKGROUND

[0002] In the prior art, when refreshing the pixels corresponding to each row or each column of the pixel array in the display device, a high-level signal corresponding to each row or each column of the pixel circuit in the pixel array is usually sent one by one to realize the row-by-row or column-by-column refresh of the picture corresponding to the display device.

[0003] The defect of the prior art is that when the high-level signal corresponding to each row or each column of the pixel circuit in the pixel array is sent one by one, a decoder is usually needed to cooperate with the operation, and the address code corresponding to each row or each column of the pixel circuit is input to the decoder one by one, so that the decoder outputs the corresponding high-level signal to each row or each column of the pixel circuit one by one to complete the row-by-row or column-by-column refresh of the picture. The address code corresponding to each row or each column of the pixel circuit is usually input to the decoder one by one, which usually needs to configure a corresponding decoder, a corresponding storage space and a corresponding input circuit, and the implementation is relatively complex and inconvenient, thereby increasing the cost of the display device. SUMMARY

[0004] The technical problem solved by the present application is how to reduce the complexity of the structure of the display driving circuit and thereby reduce the cost of the display device.

[0005] To solve the above technical problem, the first technical solution adopted by the present application is: a display driving circuit, comprising: a plurality of first signal generating circuits, the first input end of each first signal generating circuit receiving a clock signal, and the plurality of first signal generating circuits being connected in series with each other, each first signal generating circuit generating a first signal based on the clock signal, so that the plurality of first signal generating circuits output the first signal in turn; a second signal generating circuit, the second signal generating circuit outputting a second signal under the condition that a preset condition is met; a plurality of third signal generating circuits, the first input end of each third signal generating circuit being connected with the output end of the corresponding first signal generating circuit, the second input end of all third signal generating circuits being connected with the output end of the second signal generating circuit, and the third signal generating circuit outputting a third signal based on the first signal and the second signal.

[0006] The display driving circuit further comprises a pixel array module, the pixel array module comprises a plurality of pixel unit groups, each pixel unit group comprises a plurality of pixel units, and the input end of each pixel unit group is connected with the output end of the corresponding third signal generation circuit; the pixel unit group is configured to control the corresponding plurality of pixel units to respectively acquire pixel display data when the third signal is received, and the plurality of pixel units respectively perform display based on the pixel display data when the third signal is received.

[0007] The display driving circuit further comprises a data storage module, and the data storage module is connected with the plurality of pixel unit groups respectively; the pixel unit group is specifically configured to control the corresponding plurality of pixel units to respectively acquire pixel display data from the data storage module when the third signal is received.

[0008] The first signal generation circuit comprises a plurality of D flip-flops; the D flip-flop comprises a first input end, a second input end and an output end, the first input ends of the plurality of D flip-flops receive the same clock signal, the first input end of each third signal generation circuit is connected with the output end of the corresponding D flip-flop, the output end of an Nth D flip-flop is connected with the second input end of an N+1th D flip-flop, wherein the Nth D flip-flop is any one of the plurality of D flip-flops except the last D flip-flop, and the second input end of the first D flip-flop in the plurality of D flip-flops receives a trigger signal sent by an external control circuit.

[0009] The third signal generation circuit comprises a first AND gate circuit, the first input end of the third signal generation circuit corresponds to the first input end of the first AND gate circuit, the second input end of the third signal generation circuit corresponds to the second input end of the first AND gate circuit, and the output end of the third signal generation circuit corresponds to the output end of the first AND gate circuit.

[0010] The first AND gate circuit comprises a first NAND gate and a first NOT gate; the first input end of the first NAND gate corresponds to the first input end of the first AND gate circuit, the second input end of the first NAND gate corresponds to the second input end of the first AND gate circuit, the output end of the first NAND gate is connected with the input end of the first NOT gate, and the output end of the first NOT gate corresponds to the output end of the first AND gate circuit.

[0011] The second signal generation circuit comprises a first circuit and a second circuit; the first circuit is configured to output an enable signal when it is detected that the pixel display data of the display driving circuit is loaded; and the second circuit is configured to output the second signal when the enable signal is received.

[0012] The second circuit comprises a delay circuit and a second AND gate circuit, and the delay circuit comprises a second NOT gate, a third NOT gate, a signal delay circuit and a fourth NOT gate; the input end of the second NOT gate is connected with the output end of the first circuit, the output end of the second NOT gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the input end of the signal delay circuit, the signal delay circuit is used for delaying the output of the received signal, the output end of the signal delay circuit is connected with the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected with the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected with the output end of the first circuit, and the output end of the second AND gate circuit is connected with the second input end of the third signal generating circuit.

[0013] The second AND gate circuit comprises a second NAND gate and a fifth NOT gate; the first input end of the second NAND gate corresponds to the first input end of the second AND gate circuit, the second input end of the second NAND gate corresponds to the second input end of the second AND gate circuit, the output end of the second NAND gate is connected with the input end of the fifth NOT gate, and the output end of the fifth NOT gate corresponds to the output end of the second AND gate circuit.

[0014] To solve the above technical problems, a second technical solution adopted by the present application is a display device comprising the display driving circuit.

[0015] The display driving circuit in the technical solution of the present application comprises a plurality of first signal generating circuits capable of sequentially outputting first signals, a second signal generating circuit capable of outputting second signals under the condition of meeting preset conditions, and a third signal generating circuit capable of outputting third signals based on the received first signals and second signals, and the display driving circuit can sequentially output the third signals, thereby avoiding the use of a decoder, reducing the complexity of the structure and use method of the display driving circuit, and reducing the cost of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a structural schematic diagram of a first embodiment of the display driving circuit of the present application;

[0018] Figure 2 is a structural schematic diagram of a second embodiment of the display driving circuit of the present application;

[0019] Figure 3 is a structural schematic diagram of a third embodiment of the display driving circuit of the present application;

[0020] Figure 4 is a structural schematic diagram of a fourth embodiment of the display driving circuit of the present application;

[0021] Figure 5 is a structural schematic diagram of a fifth embodiment of the display driving circuit of the present application;

[0022] Figure 6 is a structural schematic diagram of a sixth embodiment of the display driving circuit of the present application;

[0023] Figure 7 is a structural schematic diagram of an embodiment of the display device of the present application;

[0024] Figure 8 is a schematic diagram of an embodiment of the signal timing of the present application. DETAILED DESCRIPTION

[0025] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It is particularly pointed out that the following embodiments are only for illustrating the present application, but not for limiting the scope of the present application. Similarly, the following embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application. All other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of the present application.

[0026] In this document, reference to“an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. Those skilled in the art will appreciate that embodiments described herein can be combined with other embodiments in various ways.

[0027] In the description of the present application, it is to be noted that, unless otherwise explicitly specified and limited, the terms“mounting”,“setting”,“connecting”,“connecting” should be understood in a broad sense, for example, it can be fixedly connected, it can be detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or connected through an intermediate medium. For those skilled in the art, the above-mentioned specific meanings can be connected according to the specific circumstances.

[0028] The present application first proposes a display driving circuit, as shown in Figure 1 , Figure 1 is a structural schematic diagram of a first embodiment of the display driving circuit of the present application, as shown in Figure 1As shown, the display driving circuit includes a plurality of first signal generating circuits 11, a second signal generating circuit 12 and a plurality of third signal generating circuits 13.

[0029] In the plurality of first signal generating circuits 11, the first input end of each first signal generating circuit 11 is connected to the same clock signal source to receive a clock signal (CLK), and the first signal generating circuits 11 are connected in series with each other, which can be achieved by connecting the output end of a previous first signal generating circuit 11 to the second input end of a subsequent first signal generating circuit 11. Based on the above circuit structure, the first signal generating circuits 11 except the first one can output according to the output state of the previous first signal generating circuit 11, so that the plurality of first signal generating circuits 11 can generate first signals in turn.

[0030] The second signal generating circuit 12 is configured to output a second signal when a preset condition is met.

[0031] In the plurality of third signal generating circuits 13, the first input end of each third signal generating circuit 13 is connected to the output end of a first signal generating circuit 11, and the second input end of all third signal generating circuits 13 is connected to the output end of the second signal generating circuit 12. The third signal generating circuit 13 is configured to receive the first signal output by the first signal generating circuit 11 and the second signal output by the second signal generating circuit 12, and to generate and output a corresponding third signal (such as one of WL1, WL2, …, WLx in the figure) based on the first signal and the second signal when the first signal and the second signal are received simultaneously.

[0032] When the plurality of first signal generating circuits 11 generate first signals in turn, the plurality of third signal generating circuits 13 can receive the first signals in turn, and generate and output corresponding third signals based on the received second signal and the first signals received in turn.

[0033] In practice, the plurality of outputs of the plurality of third signal generating circuits 13 correspond to the plurality of outputs of the decoder in the prior art, and can output corresponding third signals in turn, so that each row / column pixel unit displays when receiving the corresponding third signal, that is, the technical effect of refreshing and displaying the row / column pixel units in turn is achieved, avoiding the use of the decoder and reducing the structural complexity of the display driving circuit. At the same time, since the use of the decoder is avoided, the step of inputting the address code corresponding to each row / column pixel unit to the decoder in turn is also avoided, reducing the use complexity of the display driving circuit.

[0034] In summary, based on the above method, the complexity of the display driving circuit can be reduced, and the cost of the display driving circuit can be reduced.

[0035] Differing from the prior art, the display driving circuit in the technical scheme of the application comprises a plurality of first signal generation circuits capable of sequentially outputting first signals, a second signal generation circuit capable of outputting a second signal in a case where a preset condition is met, and a third signal generation circuit capable of outputting a third signal based on the received first signal and second signal. The technical effect of sequentially triggering each column / row of pixel units of the display device to display can be achieved based on the structure of the display driving circuit, the use of a decoder is avoided, the complexity of the structure and use method of the display driving circuit is reduced, and the cost of the display device is reduced.

[0036] In an embodiment, referring to Figure 2 , Figure 2 is a structural schematic diagram of a second embodiment of the display driving circuit of the application, as Figure 2 indicated, the display driving circuit further comprises a pixel array module 14, the pixel array module 14 comprises a plurality of pixel unit groups 141, each pixel unit group 141 comprises a plurality of pixel units, and the input end of each pixel unit group 141 is connected with the output end of the corresponding third signal generation circuit 13 to receive the corresponding third signal.

[0037] Each pixel unit group 141 is configured to control the plurality of pixel units contained therein to respectively acquire pixel display data when the third signal is received, and each pixel unit is configured to display based on the acquired pixel display data when the third signal is received.

[0038] Specifically, the pixel array module 14 can comprise a pixel array composed of a plurality of pixel units, and each pixel unit group 141 can be a plurality of pixel units in a row or a column of the pixel array. After the plurality of pixel units in a certain row or a certain column receive the corresponding third signal, the plurality of pixel units in the row or the column can respectively acquire the pixel display data required to be displayed at the corresponding positions from the designated data storage module, so that each pixel unit can refresh and display the pixel points based on the acquired pixel display data, and then the rows or columns of pixel units are sequentially refreshed and displayed, and finally the overall refresh and display of the display picture corresponding to a pixel array is completed.

[0039] Optionally, as Figure 2 indicated, the display driving circuit further comprises a data storage module 15, the data storage module 15 is connected with the plurality of pixel unit groups 141 respectively, and the pixel unit group 141 is specifically configured to control the plurality of pixel units contained therein to respectively acquire the pixel display data from the data storage module 15 when the third signal is received.

[0040] Specifically, there may be one or more data storage modules 15, and each pixel unit group 141 is connected to the data storage module 15 that stores the pixel display data required for the corresponding pixel unit group.

[0041] In one embodiment, see Figure 3 , Figure 3 This is a schematic diagram of the structure of the third embodiment of the display driving circuit of this application, as shown below. Figure 3 As shown, the first signal generation circuit 11 includes a D flip-flop 111, which includes a first input terminal B, a second input terminal A, and an output terminal C.

[0042] The first input terminals of multiple D flip-flops 111 are connected to the same clock signal source to receive the same clock signal, and the output terminal of each D flip-flop 1111 is connected to the first input terminal of a corresponding third signal generation circuit 13.

[0043] In a circuit where multiple D flip-flops 111 are connected in series, the output of the Nth D flip-flop 111 is connected to the second input of the (N+1)th D flip-flop 111. The Nth D flip-flop 111 is any one of the multiple D flip-flops 111 except the last one, that is, the (N+1)th D flip-flop 111 is any one of the multiple D flip-flops 111 except the first one.

[0044] The second input terminal of the first D flip-flop 111 among the multiple D flip-flops 111 receives the trigger signal InputD sent by the external control circuit. That is, the first D flip-flop 111 uses the trigger signal InputD as the input signal of the D flip-flop and makes a corresponding output based on the received input signal. Any other D flip-flop 111 among the multiple D flip-flops 111 except the first D flip-flop 111 uses the output of the previous D flip-flop 111 as the input signal of the D flip-flop and makes a corresponding output based on the received input signal.

[0045] Based on the above method, a circuit composed of relatively simple D flip-flops can be used to achieve the technical effect of having multiple D flip-flops 111 output the first signal in sequence, that is, to output high-level signals in sequence, thus avoiding the need for a decoder and reducing the complexity and cost of the display driver circuit.

[0046] In one embodiment, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the display driving circuit of this application, as shown below. Figure 4As shown, the third signal generation circuit 13 includes a first AND gate circuit 131. The first input terminal of the third signal generation circuit 13 corresponds to the first input terminal of the first AND gate circuit 131, the second input terminal of the third signal generation circuit 13 corresponds to the second input terminal of the first AND gate circuit 131, and the output terminal of the third signal generation circuit 13 corresponds to the output terminal of the first AND gate circuit 131.

[0047] Specifically, the third signal can be a high-level signal, and the first AND gate circuit 131 is used to output a high-level signal when the first input terminal and the second input terminal receive high-level signals at the same time.

[0048] In the first type of circuit, the first AND gate circuit 131 may include an AND gate device, the first input terminal of which corresponds to the first input terminal of the first AND gate circuit 131, the second input terminal of which corresponds to the second input terminal of the first AND gate circuit 131, and the output terminal of which corresponds to the output terminal of the first AND gate circuit 131.

[0049] In the second circuit, the first AND gate circuit 131 may include a first NAND gate and a first NOT gate. The first input terminal of the first NAND gate corresponds to the first input terminal of the first AND gate circuit 131, the second input terminal of the first NAND gate corresponds to the second input terminal of the first AND gate circuit 131, the output terminal of the first NAND gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate corresponds to the output terminal of the first AND gate circuit 131. Compared to a single AND gate, the AND gate circuit composed of a NAND gate and a NOT gate has a larger capacitance-to-resistance ratio, thereby reducing signal transmission delay and improving the operating efficiency of the display driver circuit.

[0050] In one embodiment, see Figure 5 , Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the display driving circuit of this application, as shown below. Figure 5 As shown, the second signal generation circuit 12 includes a first circuit (not shown) and a second circuit 121.

[0051] The first circuit is used to output an enable signal Enable when it detects that the pixel display data of the display driver circuit has been loaded. The second circuit 121 is used to output a second signal when it receives the enable signal Enable.

[0052] Optionally, such as Figure 5 As shown, the second circuit 121 includes a delay circuit and a second AND gate circuit. The delay circuit includes a second NOT gate 1211, a third NOT gate 1212, a signal delay circuit 1213, and a fourth NOT gate 1214.

[0053] The input of the second NOT gate 1211 is connected to the output of the first circuit to receive the enable signal Enable. The output of the second NOT gate 1211 is connected to the input of the third NOT gate 1212. The output of the third NOT gate 1212 is connected to the input of the signal delay circuit 1213. The signal delay circuit 1213 is used to delay the output of the received signal. The output of the signal delay circuit 1213 is connected to the input of the fourth NOT gate 1214. The output of the fourth NOT gate 1214 is connected to the first input of the second AND gate circuit to receive the enable signal Enable. The second input of the second AND gate circuit is connected to the output of the first circuit. The output of the second AND gate circuit is connected to the second input of each of the third signal generation circuits 13.

[0054] Specifically, such as Figure 5 As shown, the second AND gate circuit includes a second NAND gate 1215 and a fifth NOT gate 1216. The first input terminal of the second NAND gate 1215 corresponds to the first input terminal of the second AND gate circuit, the second input terminal of the second NAND gate 1215 corresponds to the second input terminal of the second AND gate circuit, the output terminal of the second NAND gate 1215 is connected to the input terminal of the fifth NOT gate 1216, and the output terminal of the fifth NOT gate 1216 corresponds to the output terminal of the second AND gate circuit.

[0055] In one application scenario, see Figure 6 , Figure 6 This is a schematic diagram of the sixth embodiment of the display driving circuit of this application.

[0056] like Figure 6 As shown, the first signal generation circuit includes a D flip-flop 111, which includes a first input terminal B, a second input terminal A, and an output terminal C. The first input terminals B of multiple D flip-flops 111 are connected to the same clock signal source to receive the same clock signal. The output terminal C of each D flip-flop 111 is connected to the first input terminal of a corresponding third signal generation circuit 13. In the circuit where multiple D flip-flops 111 are connected in series, the output terminal C of the Nth D flip-flop 111 is connected to the second input terminal A of the (N+1)th D flip-flop 111. The Nth D flip-flop 111 is any D flip-flop 111 except the last one, that is, the (N+1)th D flip-flop 111 is any D flip-flop 111 except the first one. The second input terminal of the first D flip-flop 111 receives the trigger signal InputD sent by the external control circuit.

[0057] The third signal generation circuit 13 includes a first AND gate circuit 131. The first input terminal of the third signal generation circuit 13 corresponds to the first input terminal of the first AND gate circuit 131. The second input terminal of the third signal generation circuit 13 corresponds to the second input terminal of the first AND gate circuit 131. The output terminal of the third signal generation circuit 13 corresponds to the output terminal of the first AND gate circuit 131.

[0058] The second signal generation circuit 12 includes a first circuit (not shown) and a second circuit 121. The first circuit outputs an enable signal Enable when it detects that the pixel display data loading of the display driving circuit is complete, and the second circuit 121 outputs a second signal when it receives the enable signal Enable. The second circuit 121 includes a delay circuit and a second AND gate circuit. The delay circuit includes a second NOT gate 1211, a third NOT gate 1212, a signal delay circuit 1213, and a fourth NOT gate 1214. The input of the second NOT gate 1211 is connected to the output of the first circuit to receive the enable signal Enable. The output of the second NOT gate 1211 is connected to the input of the third NOT gate 1212. The output of the third NOT gate 1212 is connected to the input of the signal delay circuit 1213. The signal delay circuit 1213 is used to delay the output of the received signal. The output of the signal delay circuit 1213 is connected to the input of the fourth NOT gate 1214. The output of the fourth NOT gate 1214 is connected to the first input of the second AND gate circuit to receive the enable signal Enable. The second input of the second AND gate circuit is connected to the output of the first circuit. The output of the second AND gate circuit is connected to the second input of each of the third signal generation circuits 13.

[0059] For example, see Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the signal timing of this application, as shown below. Figure 8 As shown, the input signal InputD received by the first D flip-flop among multiple D flip-flops is high before the first rising edge and the first falling edge of the clock signal CLK, and low after that moment.

[0060] In1 is the input signal received by the second D flip-flop among multiple D flip-flops, which is also the output signal of the first D flip-flop, and so on. Inx is the input signal received by the last D flip-flop among multiple D flip-flops.

[0061] Based on the aforementioned input signal InputD, multiple D flip-flops can sequentially receive a high-level signal as their corresponding input signal, thereby causing the multiple D flip-flops to sequentially output high-level signals, and continuously output low-level signals before and after each high-level signal output.

[0062] Furthermore, the enable signal Enable is high until the falling edge of Inx. Based on the enable signal Enable and the high-level signals output sequentially by multiple D flip-flops, multiple first AND gate circuits can output high-level signals sequentially, thereby ultimately achieving the technical effect of sequentially triggering each column / row pixel unit of the display device to display.

[0063] This application also discloses a display device, see [link to relevant documentation] Figure 7 , Figure 7 This is a schematic diagram of the structure of an embodiment of the display device of this application, as shown below. Figure 7 As shown, the display device 20 includes a display driving circuit 21, which can be the display driving circuit in any of the preceding embodiments, and is not limited here.

[0064] The display device can be any of the following: a television, tablet computer, desktop computer screen, mobile phone, or other type of display device, depending on the specific needs; no limitation is made here. The screen of the display device can be an LCD screen or other types of display screen, depending on the specific needs; no limitation is made here.

[0065] Unlike existing technologies, the display driving circuit in this application includes multiple first signal generating circuits capable of sequentially outputting a first signal, a second signal generating circuit capable of outputting a second signal when preset conditions are met, and a third signal generating circuit capable of outputting a third signal based on the received first and second signals. Based on the above-mentioned display driving circuit structure, the third signal can be output sequentially to achieve the technical effect of sequentially triggering each column / row pixel unit of the display device to display, avoiding the use of a decoder, reducing the complexity of the structure and usage of the display driving circuit, and reducing the cost of the display device.

[0066] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0068] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0069] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0070] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display drive circuit, characterized by comprising: The display driving circuit comprises: a plurality of first signal generation circuits, a first input end of each of the first signal generation circuits receiving a clock signal, and the plurality of first signal generation circuits being connected in series with each other, each of the first signal generation circuits generating a first signal based on the clock signal, so that the plurality of first signal generation circuits sequentially output the first signal; a second signal generation circuit, the second signal generation circuit outputting a second signal in a case where a preset condition is met; a plurality of third signal generation circuits, a first input end of each of the third signal generation circuits being connected with an output end of a corresponding first signal generation circuit, a second input end of all the third signal generation circuits being connected with an output end of the second signal generation circuit, the third signal generation circuits outputting a third signal based on the first signal and the second signal; wherein the second signal generation circuit comprises a first circuit and a second circuit; the first circuit is configured to output an enable signal when it is detected that pixel display data of the display driving circuit is loaded completely; the second circuit is configured to output the second signal when the enable signal is received; the second circuit comprises a delay circuit and a second AND gate circuit.

2. The display driving circuit according to claim 1, wherein The display driving circuit further comprises a pixel array module, the pixel array module comprising a plurality of pixel unit groups, each of the pixel unit groups comprising a plurality of pixel units, an input end of each of the pixel unit groups being connected with an output end of a corresponding third signal generation circuit; the pixel unit groups are configured to control a plurality of corresponding pixel units to respectively acquire pixel display data when the third signal is received, and the plurality of pixel units respectively perform display update based on the pixel display data when the third signal is received.

3. The display driving circuit according to claim 2, wherein The display driving circuit further comprises a data storage module, the data storage module being connected with a plurality of pixel unit groups respectively; the pixel unit groups are specifically configured to control a plurality of corresponding pixel units to respectively acquire the pixel display data from the data storage module when the third signal is received.

4. The display driving circuit according to claim 1 or 2, wherein The first signal generation circuit comprises a D flip-flop; the D flip-flop comprises a first input end, a second input end and an output end, a first input end of each of the D flip-flops receiving a same clock signal, a first input end of each of the third signal generation circuits being connected with an output end of a corresponding D flip-flop; an output end of an Nth D flip-flop is connected with a second input end of an N+1th D flip-flop, wherein the Nth D flip-flop is any one of the D flip-flops except for a last D flip-flop, and a second input end of a first D flip-flop of the D flip-flops receives a trigger signal sent by an external control circuit.

5. The display driving circuit according to claim 1 or 2, wherein The third signal generation circuit comprises a first AND gate circuit, a first input end of the third signal generation circuit corresponding to a first input end of the first AND gate circuit, a second input end of the third signal generation circuit corresponding to a second input end of the first AND gate circuit, and an output end of the third signal generation circuit corresponding to an output end of the first AND gate circuit.

6. The display driving circuit according to claim 5, wherein The first AND gate circuit comprises a first NAND gate and a first NOT gate. The first input end of the first NAND gate corresponds to the first input end of the first AND gate circuit, the second input end of the first NAND gate corresponds to the second input end of the first AND gate circuit, the output end of the first NAND gate is connected with the input end of the first NOT gate, and the output end of the first NOT gate corresponds to the output end of the first AND gate circuit.

7. The display driving circuit according to claim 1, wherein The delay circuit comprises a second NOT gate, a third NOT gate, a signal delay circuit and a fourth NOT gate. The input end of the second NOT gate is connected with the output end of the first circuit, the output end of the second NOT gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the input end of the signal delay circuit, the signal delay circuit is used for delaying the output of the received signal, the output end of the signal delay circuit is connected with the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected with the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected with the output end of the first circuit, and the output end of the second AND gate circuit is connected with the second input end of the third signal generation circuit.

8. The display driving circuit according to claim 7, wherein, The second AND gate circuit comprises a second NAND gate and a fifth NOT gate. The first input end of the second NAND gate corresponds to the first input end of the second AND gate circuit, the second input end of the second NAND gate corresponds to the second input end of the second AND gate circuit, the output end of the second NAND gate is connected with the input end of the fifth NOT gate, and the output end of the fifth NOT gate corresponds to the output end of the second AND gate circuit.

9. A display device, characterized by The display driving circuit comprises the display driving circuit according to any one of claims 1 to 8. The first input end of the second NAND gate corresponds to the first input end of the second AND gate circuit, the second input end of the second NAND gate corresponds to the second input end of the second AND gate circuit, the output end of the second NAND gate is connected with the input end of the fifth NOT gate, and the output end of the fifth NOT gate corresponds to the output end of the second AND gate circuit. The display driving circuit comprises the display driving circuit according to any one of claims 1 to 8.

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