Fault handling method, device, and computer-readable storage medium

Abstract

This application discloses a fault handling method, device, and computer-readable storage medium. The method obtains a chip's alarm type, including whether the chip's fault is self-repairable or non-self-repairable. When the alarm type is determined to be non-self-repairable, the chip's historical alarm flags are detected. If the chip's historical alarm flags have been detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1. If the chip is still in an abnormal state after executing the self-repair process M times, the system's entire reset condition is detected, where M is an integer greater than or equal to 1. If the transceiver system meets the entire reset condition, an entire reset is initiated to repair the chip's fault. Based on this, the application can improve the operational efficiency of transceiver chips.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of communication technology, and in particular to a fault handling method, apparatus, and computer-readable storage medium. Background Art

[0002] Existing fault detection and automatic handling methods for communication equipment are mostly aimed at system equipment such as network management and base stations. They do not provide solutions for fault detection and fault repair of transceiver chips in AAU / RRU. This results in low operation and maintenance efficiency of transceiver chips, long-term impact of their failures, and high maintenance labor costs. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present application provide a fault handling method, device, and computer-readable storage medium, which can improve the operation and maintenance efficiency of transceiver chips, shorten the time taken to affect faults, and save maintenance labor costs.

[0005] In a first aspect, an embodiment of the present application provides a fault handling method, including:

[0006] Obtaining an alarm type of the chip, where the alarm type includes whether the fault of the chip is a self-repairable type or a non-self-repairable type;

[0007] When it is determined that the alarm type is that the fault of the chip is of a non-self-repairable type, detecting a historical alarm flag of the chip, and executing a preset self-repair process when it is determined that the historical alarm flag of the chip is detected N times, where N is an integer greater than or equal to 1;

[0008] After executing the self-repair process M times and determining that the chip is still in an abnormal state, detecting a complete reset condition of the transceiver system, wherein M is an integer greater than or equal to 1;

[0009] When the transceiver system meets the whole-machine reset condition, the whole-machine reset is initiated to repair the chip fault.

[0010] In a second aspect, an embodiment of the present application provides a base station, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the fault handling method as described in the first aspect above is implemented.

[0011] In a third aspect, an embodiment of the present application provides a fault handling device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the fault handling method as described in the first aspect above is implemented.

[0012] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the fault handling method described in the first aspect above.

[0013] The present embodiment includes: obtaining a chip alarm type, including whether the chip fault is self-repairable or non-self-repairable; when the alarm type is determined to be non-self-repairable, detecting the chip's historical alarm flags; executing a preset self-repair process if the chip's historical alarm flags have been detected N times, where N is an integer greater than or equal to 1; after executing the self-repair process M times and determining that the chip is still in an abnormal state, detecting a complete reset condition for the transceiver system, where M is an integer greater than or equal to 1; and initiating a complete reset to repair the chip fault if the transceiver system meets the complete reset condition. Based on this, the present application can intelligently perform fault information detection and recovery while minimizing the impact on normal transceiver system operations, providing engineers with effective information for fault analysis. The present application has the advantages of balancing fault information accuracy with short fault recovery times, thereby improving the timeliness of product fault repair. The present application can facilitate intelligent operation and maintenance of transceiver systems, improving production and maintenance efficiency, reducing the time it takes to impact faults, and saving maintenance labor costs.

[0014] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0016] Figure 1 This is a main flow chart of a fault handling method provided by an embodiment of the present application;

[0017] Figure 2 This is a sub-flowchart of a fault handling method provided by an embodiment of the present application;

[0018] Figure 3 This is another sub-flowchart of a fault handling method provided by an embodiment of the present application;

[0019] Figure 4 This is another sub-flowchart of a fault handling method provided by an embodiment of the present application;

[0020] Figure 5 This is another sub-flowchart of a fault handling method provided by an embodiment of the present application;

[0021] Figure 6 This is another sub-flowchart of a fault handling method provided by an embodiment of the present application;

[0022] Figure 7 This is a fault diagnosis and output flow chart provided by an embodiment of the present application;

[0023] Figure 8 This is a schematic diagram of the base station structure provided by an embodiment of the present application;

[0024] Figure 9 This is a schematic diagram of the structure of a fault handling device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0026] It should be understood that in the description of the embodiments of this application, "multiple" (or multiple) means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, and "above," "below," and "within" are understood to include the number itself. The use of "first," "second," and the like in the description is solely for the purpose of distinguishing technical features and is not to be construed as indicating or implying relative importance, or implicitly indicating the number of the indicated technical features, or implicitly indicating the order of the indicated technical features.

[0027] Existing fault detection and automatic handling methods for communication equipment are mostly aimed at system equipment such as network management and base stations. They do not provide solutions for fault detection and fault repair of transceiver chips in AAU / RRU. This results in low operation and maintenance efficiency of transceiver chips, long-term impact of their failures, and high maintenance labor costs.

[0028] To address the above technical issues, embodiments of the present application provide a fault handling method, apparatus, and computer-readable storage medium. These methods obtain a chip's alarm type, including whether the chip's fault is self-repairable or non-self-repairable. When the alarm type is determined to be non-self-repairable, the chip's historical alarm flags are detected. If the chip's historical alarm flags are detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1. If the chip is still in an abnormal state after executing the self-repair process M times, the system's complete reset condition is detected, where M is an integer greater than or equal to 1. If the transceiver system meets the complete reset condition, a complete reset is initiated to repair the chip's fault. Based on this, the present application intelligently performs fault information detection and recovery while minimizing the impact on normal transceiver system operations, providing engineers with effective information for fault analysis. This application offers the advantages of both accurate fault information and short recovery times, improving the timeliness of product fault repair. This application can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time spent on failure impact, and save maintenance labor costs.

[0029] like Figure 1 As shown, Figure 1 This is a flowchart of a fault handling method provided by an embodiment of the present application. The fault handling method includes but is not limited to the following steps:

[0030] Step S101, obtaining the alarm type of the chip, where the alarm type includes whether the chip fault is a self-repairable type or a non-self-repairable type;

[0031] Step S102: When it is determined that the alarm type is that the chip fault is of a non-self-repairable type, the chip's historical alarm flags are detected, and when it is determined that the chip's historical alarm flags are detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1.

[0032] Step S103, after executing the self-repair process M times and determining that the chip is still in an abnormal state, detecting a reset condition of the entire transceiver system, where M is an integer greater than or equal to 1;

[0033] Step S104 : When the transceiver system reaches a complete reset condition, the complete reset is initiated to repair the chip failure.

[0034] In an exemplary embodiment, the method may be applicable to troubleshooting a transceiver chip in an AAU (Active Antenna Unit) or an RRU (Remote Radio Unit).

[0035] In an exemplary embodiment, a fault pre-analysis can be performed before detecting internal chip faults. Specifically, the functions of the transceiver chip and its modules within the transceiver system, as well as the impact of their failures on various system indicators and functions, are analyzed. Next, a method for obtaining operating status information for each chip module and criteria for determining a fault status are determined. Finally, the priorities of various system indicators and functions are determined, and subsequent fault statuses of each chip module are processed in descending order of priority.

[0036] In an exemplary embodiment, a fault detection module can be integrated within the transceiver chip. The fault detection module obtains the alarm status of each chip module and determines the alarm type based on the priority determined during fault analysis. Chip alarm types are divided into two categories: one is a self-repairable chip alarm, and the other is a non-self-repairable chip alarm.

[0037] In an exemplary embodiment, when it is determined that the alarm type is that the chip failure is of a self-repairable type, the chip failure can be directly self-repaired.

[0038] In an exemplary embodiment, a fault recovery module may be integrated within the transceiver chip to automatically handle self-repairable chip faults. If the fault detection module's alarm is of the self-repairable chip type, the fault recovery module will self-repair the chip fault. For example, if the digital power of the transmit channel exceeds the set value and triggers an alarm, the fault self-repair module will attenuate the transmit power to the abnormal set value 1 to protect the transmitting RF device, and latch the alarm indication flag through the register, but will not indicate the alarm flag to the external system through the hardware IO. When the fault recovery module obtains from the fault detection module that the alarm has disappeared, the fault self-repair module will restore the transmit power to the normal set value 2 to restore the transmit power.

[0039] In an exemplary embodiment, the fault recovery module within the transceiver chip obtains the alarm type from the fault detection module. If the alarm is of a type that the chip cannot self-repair, such as a clock, power, or interface alarm, the chip saves key operating status information to the black box module, including chip software and hardware version numbers, clock and power status, SERDES and JESD204 interface status, calibration algorithm, and initialization calibration status. The alarm flag is then displayed to the system via the hardware I / O interface.

[0040] In an exemplary embodiment, the fault detection module detects alarm flags on all chips in the transceiver system via a hardware IO interface. When a chip's historical alarm flag is detected, the module first reads the chip's black box module information and saves it to the system's ROM. This process prevents critical chip fault information from being overwritten by alarm clearing and abnormal recovery operations, providing engineers with more accurate information for fault analysis. The system then clears the chip's historical alarm flags, and the alarm detection module rechecks for historical alarm flags on each chip module. This process is repeated N times (N is an integer greater than or equal to 1) to confirm whether the chip alarm has returned to normal. If a device's historical alarm flag is detected N times, the device is determined to be in an abnormal state and the abnormal fault recovery process is initiated. It should be noted that the number of times a chip's historical alarm flags are detected is greater than one to mitigate the possibility of false detections due to the system not actually clearing the chip's historical alarm flags. Multiple consecutive checks can eliminate the risk of false detections.

[0041] In one exemplary embodiment, the fault recovery process is executed multiple times. If it is less than M times (M is an integer greater than or equal to 1), the pre-designed system automatic recovery process is executed, and the complete operation and log information are saved to the system ROM. It should be noted that the fault recovery process is executed more than once to address probabilistic chip failures. Designing multiple recovery processes can increase the success rate of chip recovery.

[0042] In an exemplary embodiment, the fault recovery process is designed to prioritize not affecting the operating status of other normal chip modules in the entire system or minimizing the number of affected normal chip modules. Secondly, it prioritizes reducing the time and system resource consumption of the fault recovery process. For example, if a JESD204 interface communication error occurs on a transceiver chip, the JESD204 link establishment process for that chip will be reinitiated. For example, if the phase-locked loop (PLL) lock state of a transceiver chip is abnormal, the reset and initialization process for that chip will be reinitiated to reconfigure the reference clock and PLL module.

[0043] In an exemplary embodiment, if the fault recovery process has been executed M times, it is determined that the faulty module cannot be restored to normal operating conditions through the pre-designed automatic fault recovery process. A determination is then made as to whether the transceiver meets the full-machine reset conditions. The full-machine reset conditions can be set to a low-traffic time period based on statistical data or a transceiver sleep mode issued by the network management system. If the full-machine reset conditions are met, the system enters the full-machine reset state and attempts to restart the entire system to recover from the fault. It should be noted that after the full-machine reset conditions are met, the system fault diagnosis and reporting process can also be entered. If the full-machine reset conditions are not met, the system remains in the faulty state until the full-machine reset conditions are met. Based on this, fault information detection and fault recovery can be intelligently completed while minimizing the impact on normal transceiver system operations.

[0044] In an exemplary embodiment, transceiver system faults can be categorized into multiple branches, such as downlink faults, uplink faults, calibration link faults, power supply faults, and clock faults. Fault information is obtained from each module during the fault detection process to determine whether the current fault belongs to a specific functional branch of the transceiver system. The corresponding fault diagnosis process is then initiated. The fault information obtained from each module during the fault detection process represents independent fault reports from each chip module and cannot directly indicate the cause of the system fault; further comprehensive analysis is required. Furthermore, designing the diagnostic process independently by branch simplifies the complexity of analyzing the cause of complex system faults and allows for more detailed and complete diagnostic processes for each branch without increasing diagnostic time, thereby improving the efficiency and accuracy of the diagnostic module. The fault diagnosis process for each fault branch stores complete operation and log information in the system ROM, providing engineers with comprehensive and accurate fault information for fault analysis. Upon completion of the fault diagnosis process, a fault diagnosis report is generated based on the determined functional branch of the transceiver system. This report includes the fault branch, the faulty chip ID, and a preliminary diagnosis of the fault. The transceiver system fault diagnosis results are then reported to the network management system. Finally, the whole machine enters the reset state and attempts to restart the whole machine to recover from the fault.

[0045] In summary, by obtaining the alarm type of the chip, the alarm type includes whether the chip fault is a self-repairable type and whether the chip fault is a non-self-repairable type; when it is determined that the alarm type is a self-repairable type, the chip fault is self-repaired; when it is determined that the alarm type is a non-self-repairable type, the chip's historical alarm flag is detected; when it is determined that the chip's historical alarm flag is detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1; when the self-repair process is executed M times and it is determined that the chip is still in an abnormal state, the entire system reset condition of the transceiver system is detected, where M is an integer greater than or equal to 1; when the transceiver system reaches the entire system reset condition, the entire system reset is initiated to repair the chip fault. Based on this, the present application can intelligently complete fault information detection and fault recovery while minimizing the impact on the normal business of the transceiver system, providing effective information for engineers to analyze the fault. The present application has the advantages of taking into account the accuracy of fault information and the short time consumption of fault recovery, thereby improving the timeliness of product fault repair. This application can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time spent on failure impact, and save maintenance labor costs.

[0046] like Figure 2 As shown, step S101 may include but is not limited to the following sub-steps:

[0047] Step S201, obtaining the alarm status of the chip;

[0048] Step S202: Determine the chip alarm type according to the alarm status.

[0049] In an exemplary embodiment, the alarm type is determined by obtaining the alarm status of the chip. The chip alarm types are divided into two categories: one is a chip self-repair type alarm, and the other is a chip non-self-repair type alarm.

[0050] like Figure 3 As shown, after sub-step S202, the following sub-steps may also be included but not limited to:

[0051] Step S301: determining an alarm flag according to the alarm type of the chip, wherein the alarm flag includes a first alarm flag and a second alarm flag. The first alarm flag is used to indicate that the chip fault is of a self-repairable type, and the second alarm flag is used to indicate that the chip fault is of a non-self-repairable type.

[0052] Step S302: When the warning flag is determined to be the first warning flag, the chip self-repairs the chip fault;

[0053] Step S303: When it is determined that the alarm flag is the second alarm flag, the working status information of the chip is saved, and the chip sends the second alarm flag to the transceiver system.

[0054] In an exemplary embodiment, the alarm type of the chip can be identified by an alarm sign. For example, the alarm sign may include a first alarm sign and a second alarm sign, the first alarm sign is used to indicate that the chip fault is of a self-repairable type, and the second alarm sign is used to indicate that the chip fault is of a non-self-repairable type. When it is determined that the alarm sign is the first alarm sign, it means that the alarm belongs to a chip self-repairable type, and the fault recovery module integrated in the chip can automatically recover the chip fault. When it is determined that the alarm sign is the second alarm sign, it means that the alarm belongs to a chip non-self-repairable type, such as a clock, power supply, or interface alarm, the chip saves key working status information to the black box module, including the chip software and hardware version number, clock, power supply status, SERDES and JESD204 interface status, calibration algorithm, and initialization calibration status. The alarm sign is indicated to the system through the hardware IO interface.

[0055] like Figure 4 As shown, step S302 may include but is not limited to the following sub-steps:

[0056] Step S401: When it is determined that the transmit power of the chip exceeds a preset threshold, the transmit power is attenuated to a first set value and a first alarm flag is latched;

[0057] Step S402: When it is determined that the first alarm sign disappears, the transmission power is restored to the second set value to restore the transmission power.

[0058] In one exemplary embodiment, using a transmitter chip as an example, if the transmit power abnormally exceeds a set value and triggers an alarm, the fault self-repair module will reduce the transmit power to the abnormal set value 1 to protect the transmitting RF device and latch the alarm indication flag in a register, but will not indicate the alarm flag to the external system through hardware IO. When the fault recovery module receives information from the fault detection module that the alarm has disappeared, the fault self-repair module will restore the transmit power to the normal set value 2, thereby restoring the transmit power.

[0059] like Figure 5 As shown, when the transceiver system reaches the complete reset condition, the following sub-steps may be included but not limited to:

[0060] Step S501, save the black box information of the chip;

[0061] Step S502: Clear the historical alarm flags of the chip and re-check whether the chip has any historical alarm flags.

[0062] In one exemplary embodiment, when a chip detects a historical alarm flag, it first reads the chip's black box module information through an instruction and saves it to the system's ROM. This process prevents critical chip fault information from being overwritten by alarm clearing and abnormal recovery operations, providing engineers with more accurate information for fault analysis. The system then clears the chip's historical alarm flag. The alarm detection module then rechecks each chip module for historical alarm flags, repeating this process N times (N is an integer greater than or equal to 1) to confirm whether the chip alarm has returned to normal. If a device detects historical alarms N times, the device is deemed to be in an abnormal state and the abnormal fault recovery process begins.

[0063] like Figure 6 As shown, after step S105, the following steps may also be included but not limited to:

[0064] Step S601, obtaining fault information of the transceiver system;

[0065] Step S602, determining the fault type according to the fault information;

[0066] Step S603, executing the corresponding fault diagnosis process according to the fault type;

[0067] Step S604, saving a fault diagnosis log during the execution of the fault diagnosis process;

[0068] Step S605: Output a fault diagnosis report according to the fault diagnosis process.

[0069] In an exemplary embodiment, Figure 7 As shown, automatic fault diagnosis of faulty chip modules can categorize transceiver system faults into multiple branches, including downlink, uplink, calibration link, power supply, and clock failures. The fault detection process obtains fault information from each module, determines the specific functional branch of the transceiver system to which the current fault belongs, and then enters the corresponding fault diagnosis process. The fault information obtained from each module during the fault detection process represents independent fault reports from each chip module and cannot directly indicate the cause of the system fault; further comprehensive analysis is required. Furthermore, designing the diagnosis process independently by branch simplifies the complexity of analyzing the cause of complex system faults and allows for more detailed and complete diagnostic processes for each branch without increasing diagnostic time, improving the efficiency and accuracy of the diagnosis module. The fault diagnosis process for each fault branch stores complete operation and log information in the system ROM, providing engineers with comprehensive and accurate fault information for fault analysis. After the fault diagnosis process completes, a fault diagnosis report is generated based on the identified functional branch of the transceiver system, including the fault branch, the faulty chip ID, and the preliminary diagnosis cause. The transceiver system fault diagnosis results are then reported to the network management system. Finally, the whole machine enters the reset state and attempts to restart the whole machine to recover from the fault.

[0070] In summary, the present application can be applied to the automatic detection, processing and diagnosis of transceiver chip and transceiver link faults during the normal startup and operation of the AAU / RRU system. In addition, the present application can intelligently complete fault information detection, fault recovery, fault diagnosis and reporting while minimizing the impact on the normal business of the transceiver system, while ensuring that the key fault information of each chip module is not rewritten or lost, providing effective information for engineers to analyze the fault. Taking into account the advantages of fault information accuracy and short fault recovery time, the timeliness of product fault diagnosis and reporting is improved. It can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time-consuming impact of faults, and save maintenance labor costs.

[0071] like Figure 8 As shown, an embodiment of the present application also provides a base station.

[0072] Specifically, the fault handling device includes: one or more processors and a memory, Figure 8 A processor and memory are used as an example. The processor and memory can be connected via a bus or other means. Figure 8 The bus connection is taken as an example.

[0073] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs, such as the fault handling method in the above-mentioned embodiments of the present application. The processor implements the fault handling method in the above-mentioned embodiments of the present application by running the non-transitory software programs and programs stored in the memory.

[0074] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data required to execute the fault handling method in the above-mentioned embodiment of the present application, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the fault handling device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0075] The non-transient software program and program required to implement the fault handling method in the embodiment of the present application are stored in the memory. When executed by one or more processors, the fault handling method in the embodiment of the present application is executed, for example, the above-described Figure 1 Steps S101 to S104 of the method, Figure 2Steps S201 to S202 of the method, Figure 3 Steps S301 to S303 of the method, Figure 4 Steps S401 to S402 of the method, Figure 5 Steps S501 to S502 of the method, Figure 6 In the method, steps S601 to S605 are performed by obtaining the chip's alarm type, which includes whether the chip's fault is self-repairable or non-self-repairable. When the alarm type is determined to be non-self-repairable, the chip's historical alarm flags are detected. If the chip's historical alarm flags have been detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1. If the chip is still in an abnormal state after executing the self-repair process M times, the system reset condition of the transceiver system is detected, where M is an integer greater than or equal to 1. If the transceiver system meets the system reset condition, a system reset is initiated to repair the chip's fault. Based on this, the present application can intelligently complete fault information detection and fault recovery while minimizing the impact on the normal operation of the transceiver system, providing engineers with effective information for fault analysis. The present application has the advantages of balancing the accuracy of fault information with the time-consuming fault recovery process, thereby improving the timeliness of product fault repair. This application can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time spent on failure impact, and save maintenance labor costs.

[0076] like Figure 9 As shown, the embodiment of the present application also provides a fault handling device.

[0077] Specifically, the fault handling device includes: one or more processors and a memory, Figure 9 A processor and memory are used as an example. The processor and memory can be connected via a bus or other means. Figure 9 The bus connection is taken as an example.

[0078] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs, such as the fault handling method in the above-mentioned embodiments of the present application. The processor implements the fault handling method in the above-mentioned embodiments of the present application by running the non-transitory software programs and programs stored in the memory.

[0079] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data required to execute the fault handling method in the above-mentioned embodiment of the present application, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the fault handling device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0080] The non-transient software program and program required to implement the fault handling method in the embodiment of the present application are stored in the memory. When executed by one or more processors, the fault handling method in the embodiment of the present application is executed, for example, the above-described Figure 1 Steps S101 to S104 of the method, Figure 2 Steps S201 to S202 of the method, Figure 3 Steps S301 to S303 of the method, Figure 4 Steps S401 to S402 of the method, Figure 5 Steps S501 to S502 of the method, Figure 6 In the method, steps S601 to S605 are performed by obtaining the chip's alarm type, which includes whether the chip's fault is self-repairable or non-self-repairable. When the alarm type is determined to be non-self-repairable, the chip's historical alarm flags are detected. If the chip's historical alarm flags have been detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1. If the chip is still in an abnormal state after executing the self-repair process M times, the system reset condition of the transceiver system is detected, where M is an integer greater than or equal to 1. If the transceiver system meets the system reset condition, a system reset is initiated to repair the chip's fault. Based on this, the present application can intelligently complete fault information detection and fault recovery while minimizing the impact on the normal operation of the transceiver system, providing engineers with effective information for fault analysis. The present application has the advantages of balancing the accuracy of fault information with the time-consuming fault recovery process, thereby improving the timeliness of product fault repair. This application can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time spent on failure impact, and save maintenance labor costs.

[0081] In addition, the embodiment of the present application further provides a computer-readable storage medium, which stores a computer-executable program, and the computer-executable program is executed by one or more control processors, for example, Figure 9 The execution of one of the processors in the embodiment of the present application may cause the one or more processors to execute the fault handling method in the embodiment of the present application, for example, executing the above-described Figure 1 Steps S101 to S104 of the method, Figure 2 Steps S201 to S202 of the method, Figure 3 Steps S301 to S303 of the method, Figure 4 Steps S401 to S402 of the method, Figure 5 Steps S501 to S502 of the method, Figure 6 In the method, steps S601 to S605 are performed by obtaining the chip's alarm type, which includes whether the chip's fault is self-repairable or non-self-repairable. When the alarm type is determined to be non-self-repairable, the chip's historical alarm flags are detected. If the chip's historical alarm flags have been detected N times, a preset self-repair process is executed, where N is an integer greater than or equal to 1. If the chip is still in an abnormal state after executing the self-repair process M times, the system reset condition of the transceiver system is detected, where M is an integer greater than or equal to 1. If the transceiver system meets the system reset condition, a system reset is initiated to repair the chip's fault. Based on this, the present application can intelligently complete fault information detection and fault recovery while minimizing the impact on the normal operation of the transceiver system, providing engineers with effective information for fault analysis. The present application has the advantages of balancing the accuracy of fault information with the time-consuming fault recovery process, thereby improving the timeliness of product fault repair. This application can help complete intelligent operation and maintenance during the use of the transceiver system, improve production and maintenance efficiency, shorten the time spent on failure impact, and save maintenance labor costs.

[0082] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as a computer-readable program, a data structure, a program module, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable programs, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0083] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the art can also make various equivalent modifications or substitutions under the shared conditions that do not violate the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A fault handling method, applied to a transceiver system, wherein the transceiver system includes a chip, the method comprising: Obtaining an alarm type of the chip, where the alarm type includes whether the fault of the chip is a self-repairable type or a non-self-repairable type; When it is determined that the alarm type is that the fault of the chip is of a non-self-repairable type, detecting a historical alarm flag of the chip, and executing a preset self-repair process when it is determined that the historical alarm flag of the chip is detected N times, where N is an integer greater than or equal to 1; After executing the self-repair process M times and determining that the chip is still in an abnormal state, detecting a complete reset condition of the transceiver system, wherein M is an integer greater than or equal to 1; When the transceiver system meets the whole-machine reset condition, the whole-machine reset is initiated to repair the chip fault.

2. The method according to claim 1, characterized in that The method further comprises: When it is determined that the alarm type is that the fault of the chip is of a self-repairable type, the fault of the chip is self-repaired.

3. The method according to claim 1, characterized in that The obtaining of the alarm type of the chip includes: Obtaining the alarm status of the chip; The alarm type of the chip is determined according to the alarm status.

4. The method according to claim 3, characterized in that After determining the alarm type of the chip according to the alarm state, the method further includes: Determining the alarm flag according to the alarm type of the chip, the alarm flag includes a first alarm flag and a second alarm flag, the first alarm flag is used to indicate that the fault of the chip is of a self-repairable type, and the second alarm flag is used to indicate that the fault of the chip is of a non-self-repairable type; When it is determined that the warning sign is the first warning sign, the chip self-repairs the fault of the chip; When it is determined that the warning flag is the second warning flag, the working status information of the chip is saved, and the chip sends the second warning flag to the transceiver system.

5. The method according to claim 4, characterized in that The chip self-repairs a fault of the chip, including: When it is determined that the transmit power of the chip exceeds a preset threshold, the transmit power is attenuated to a first set value, and the first alarm flag is latched; When it is determined that the first alarm sign disappears, the transmit power is restored to a second set value to restore the transmit power.

6. The method according to claim 1, characterized in that After detecting the historical warning sign of the chip, the method further includes: Saving the black box information of the chip; The historical alarm flag of the chip is cleared, and the chip is re-detected to determine whether the historical alarm flag exists.

7. The method according to claim 1, characterized in that The situation where the transceiver system reaches the whole-machine reset condition includes: The transceiver system is in a low traffic working state; or The transceiver system receives a sleep operation instruction.

8. The method according to claim 1, characterized in that After the transceiver system reaches the complete reset condition, the method further includes: Obtaining fault information of the transceiver system; determining a fault type according to the fault information; Execute the corresponding fault diagnosis process according to the fault type; Saving a fault diagnosis log during the execution of the fault diagnosis process; Output a fault diagnosis report according to the fault diagnosis process.

9. A base station, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the fault handling method according to any one of claims 1 to 8 when executing the computer program.

10. A fault handling device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the fault handling method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the fault handling method according to any one of claims 1 to 8.

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