Controlled by the synchronous input buffer written to the shifter.

Abstract

This disclosure relates to synchronous input buffer control using a write shifter. A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command among the write commands and to shift the first command via the write shifter. The write shifter is also configured to cause the input buffer to be deactivated after a clock cycle of a first threshold when the first write command has been shifted via the write shifter. The write shifter is further configured to receive a second write command and prevent the input buffer from being reactivated until the second write command has been shifted by a level of a second threshold of the write shifter.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory devices. More specifically, embodiments of this disclosure relate to enabling and disabling input buffers of memory devices. Background Technology

[0002] Generally, a computing system may include electronic devices that transmit information via electrical signals during operation. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device, a ferroelectric random access memory (FeRAM) device, another random access memory (RAM) device, and / or a hybrid device incorporating more than one type of RAM. In this way, the processor can communicate with the memory device to, for example, retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor.

[0003] A host device (e.g., a processor) can send data and commands to a memory device. The memory device uses input buffers to capture input data received from the host device. These input buffers can be selectively disabled and enabled using input buffer enable signals. For example, a Data Queuing (DQS) input buffer is used to buffer DQS received from the host device, which helps capture the data received from the host device. A DQS clock generator can also be used to divide the DQS into four phases. A Data (DQ) input buffer can be used to buffer data from the host device. At the end of a write command, when there is a relatively large interval between write commands (e.g., a minimum interval of 25tCK), the data input buffer can be disabled to save power. During this input buffer disable period, the DQS clock generator will reset to the state for the next incoming write synchronous DQS clock. Under a certain write-to-write timing, this input buffer disable period may be too short to correctly reset the DQS clock generator under all operating conditions, and may result in partial reset conditions. This partial reset of the DQS clock generator may be related to the asynchronous behavior of the input buffer enable circuitry that causes a fault in the memory device (e.g., a sliver fail), where the data input buffer discards the first data bit of a second write command after the truncation input buffer is deactivated.

[0004] The embodiments disclosed herein may address one or more of the problems raised above. Summary of the Invention

[0005] On one hand, this disclosure provides a memory device comprising: a command interface configured to receive write commands from a host device; an input buffer configured to buffer data from the host device; and a write shifter configured to: receive a first write command from the write commands and shift the first command via the write shifter; cause the input buffer to be deactivated after a clock cycle of a first threshold when the first write command has been shifted via the write shifter; receive a second write command; and prevent the input buffer from being reactivated until the second write command has been shifted by a level of a second threshold of the write shifter.

[0006] On the other hand, this disclosure provides a method for operating a memory device, comprising: disabling an input buffer; receiving a write command at the memory device; transmitting the write command via a write shifter of the memory device; suppressing the activation of the input buffer after disabling the input buffer until the write command has reached an on / off tap in the write shifter; and activating the input buffer after the write command has reached the on / off tap in the write shifter.

[0007] On the other hand, this disclosure provides a memory device comprising: a command interface configured to receive a write command from a host device; an input buffer configured to buffer data from the host device; an input buffer control circuitry system comprising: a plurality of flip-flops configured to receive a first write command among the write commands and to shift the first command via the plurality of flip-flops; a logic OR circuitry system configured to receive a value from each of the plurality of flip-flops and to cause the input buffer to be deactivated after the first write command has been shifted via all of the plurality of flip-flops; and a control circuitry system configured to prevent the input buffer from being reactivated after the input buffer has been deactivated until a subsequently received second write command has been shifted via a threshold number of flip-flops among the plurality of flip-flops. Attached Figure Description

[0008] Figure 1 This is a simplified block diagram illustrating certain features of a memory device having an input buffer and an input buffer control circuit system according to embodiments of the present disclosure;

[0009] Figure 2 It is a write shifter according to an embodiment of the present disclosure. Figure 1 A block diagram of an embodiment of the input buffer and input buffer control circuit system;

[0010] Figure 3A and 3B(Collectively referred to as FIG3) is an embodiment according to the present disclosure. Figure 2 Circuit diagram of the write shifter;

[0011] Figure 4 Figure 3 is an operational diagram of the write shifter illustrating the input buffer enable signal according to an embodiment of the present disclosure;

[0012] Figure 5 Figure 3 is an operational diagram of a write shifter that illustrates an input buffer enable signal with a write-to-write gap of less than a threshold amount, according to an embodiment of the present disclosure.

[0013] Figure 6 Figure 3 is an operational diagram of a write shifter according to an embodiment of the present disclosure, showing an input buffer enable signal with a write-to-write spacing equal to a threshold amount.

[0014] Figure 7 Figure 3 is an operational diagram of a write shifter that illustrates an input buffer enable signal with a write-to-write gap greater than a threshold amount, according to an embodiment of the present disclosure.

[0015] Figure 8 This is a circuit diagram of a portion of an input buffer control circuit system for selecting whether an input buffer control circuit system operates in fast mode or slow mode, according to embodiments of the present disclosure; and

[0016] Figure 9 Use according to embodiments of this disclosure Figure 8 Figure 3 shows the operation diagram of the write shifter in fast and slow modes. Detailed Implementation

[0017] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation (as in any engineering or design project), many implementation-specific decisions must be made to achieve specific goals of the developer that may vary with the implementation, such as compliance with system-related and business-related constraints. Furthermore, it should be understood that this development effort may be complex and time-consuming, but will still be a routine design, fabrication, and manufacturing task for those of ordinary skill in the art to which this disclosure pertains.

[0018] As previously discussed, truncated input buffer deactivation cycles can cause memory failures, where a portion of the input bits are discarded due to a partial reset of the quad-phase DQS clock generator. To address this failure, the input buffer control circuitry can implement a synchronous solution for enabling and disabling the data and DQS input buffers to ensure deterministic data input buffer enable behavior and sufficient reset pulse duration for both data and DQS input buffers. Specifically, the input buffer control circuitry can ensure that input buffer deactivation only occurs when the interval between write commands (write-to-write interval) is greater than or equal to a number of tCk (e.g., 31). When the write-to-write interval is equal to or greater than said number, the input buffer control circuitry can also provide a minimum pulse width for the deactivation pulse (e.g., 3tCK). The input buffer control circuitry can further increase the deactivation pulse width by an additional tCk for each additional tCk of write-to-write interval, thereby easing larger write-to-write intervals and / or slower tCk.

[0019] Please refer to the diagram below. Figure 1 This is a simplified block diagram illustrating specific features of the memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating the specific functionality of the memory device 10. According to one embodiment, the memory device 10 may be a Double Data Rate Type 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM) device. Compared to previous generations of DDR SDRAM, various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and greater storage capacity.

[0020] Memory device 10 may include a plurality of memory banks 12. For example, memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) disposed on a dual in-line memory module (DIMM). As will be understood, each DIMM may contain a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may contain one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a plurality of memory banks 12. For DDR5, memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may contain 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 2 memory banks. For example, for 16Gb DDR5 SDRAM, the memory chip may contain 32 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 4 memory banks. Depending on the application and design of the overall system, various other configurations, organization and sizes of the memory bank 12 on the memory device 10 may be utilized.

[0021] The memory bank 12 and / or the memory bank control block 22 include a sense amplifier 13. As previously described, the memory device 10 uses the sense amplifier 13 during a read operation. Specifically, the read circuitry of the memory device 10 utilizes the sense amplifier 13 to receive low-voltage (e.g., low-differential) signals from the memory cells of the memory bank 12 and amplifies small voltage differences to enable the memory device 10 to correctly interpret data.

[0022] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide several signals (e.g., signal 15) from an external (e.g., host) device (not shown) (e.g., a processor or controller). The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0023] As will be understood, command interface 14 may include several circuits (e.g., clock input circuitry 18 and command address input circuitry 20) to ensure proper handling of signal 15. Command interface 14 may receive one or more clock signals from an external device. Generally, Double Data Rate (DDR) memory utilizes a differential pair of system clock signals, namely, a true clock signal Clk_t and a bar clock signal Clk_c. The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling bar clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rise of the bar clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically entered on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0024] Clock input circuit 18 receives a true clock signal Clk_t and a bar clock signal Clk_c and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, an I / O interface 16 and used as a timing signal for determining the output timing of read data. In some embodiments, clock input circuit 18 may include circuitry that divides the clock signal into multiple (e.g., four) phases. Clock input circuit 18 may also include phase detection circuitry to detect which phase receives the first pulse when several sets of pulses occur too frequently, allowing clock input circuit 18 to reset between sets of pulses.

[0025] The internal clock signal / phase CLK can also be provided to various other components within the memory device 10 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 32. The command decoder 32 can receive command signals from the command bus 34 and can decode the command signals to provide various internal commands. For example, the command decoder 32 can provide command signals to the DLL circuit 30 via the bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK can be used, for example, to clock data via the I / O interface 16.

[0026] Furthermore, the command decoder 32 can decode commands (e.g., read commands, write commands, mode register setting commands, activation commands, etc.) and provide access to a specific memory bank 12 corresponding to the command via bus path 40. As will be understood, the memory device 10 may include various other decoders (e.g., row decoders and column decoders) to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a memory bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features (e.g., timing control and data control) to facilitate the execution of commands traveling to and from the memory bank 12.

[0027] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus may be a 14-bit bus that houses the command / address signals (CA<13:0>). Clock signals (Clk_t and Clk_c) are used to clock the command / address signals to command interface 14. The command interface may include command address input circuitry 20, configured to receive and transmit commands, for example via command decoder 32, to provide access to memory bank 12. Additionally, command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands input on the CA<13:0> bus. Access to a specific memory bank 12 within memory device 10 is encoded along with the command on the CA<13:0> bus.

[0028] Additionally, command interface 14 can be configured to receive several other command signals. For example, a command / address (CA_ODT) signal on the die termination can be provided to facilitate proper impedance matching within memory device 10. A reset command (RESET_n) can be used, for example, to reset command interface 14, status registers, state machines, and the like during power-up. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on the command / address bus, depending, for example, on the command / address routing for a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex the signal so that it can be switched to implement certain routes for signals to memory device 10. Various signals can also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to put memory device 10 into test mode for connectivity testing.

[0029] Command interface 14 can also be used to provide alarm signals (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a Cyclic Redundancy Check (CRC) error is detected, an alarm signal (ALERT_n) can be emitted from memory device 10. Other alarm signals may also be generated. Furthermore, the bus and pins used for emitting alarm signals (ALERT_n) from memory device 10 can be used as input pins during certain operations, such as connectivity test modes performed using the TEN signal, as described above.

[0030] By transmitting and receiving data signals 44 through I / O interface 16, data can be sent to and from memory device 10 using the command and clock control signals discussed above. More specifically, data can be sent to or retrieved from memory bank 12 via data path 46, which includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received on one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into high-order bytes and low-order bytes. For example, for x16 memory devices, I / O signals can be divided into high and low I / O signals corresponding to, for example, the high-order and low-order bytes of data signals (e.g., DQ<15:8> and DQ<7:0>).

[0031] To allow higher data rates within memory device 10, some memory devices (e.g., DDR memory devices) may utilize data strobe signals, commonly referred to as DQS signals. The DQS signals are driven by an external processor or controller transmitting data (e.g., for write commands) or by memory device 10 itself (e.g., for read commands). For read commands, the DQS signals are actually additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. Similar to the clock signals (Clk_t and Clk_c), the DQS signals can be provided as differential pairs of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during read and write operations. For some memory devices, such as DDR5 SDRAM memory devices, the DQS signal differential pairs may be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of data, for example, sent to or from memory device 10.

[0032] Using a 4-phase clock generator (4PCG) 47 that outputs continuous pulses of DQS to different clocks to generate different phases, DQS can be divided into multiple (e.g., 4 phases). Furthermore, corresponding input buffers (IB) 48 can be used to buffer the DQ and DQS signals in the memory device 10. An input buffer control circuitry (IBC) 50 can enable and disable the input buffers 48. However, as previously described, some input buffer deactivation cycles shorter than a certain width (e.g., 1 to 4tCk) may cause the 4PCG 47 to partially reset, which could result in the input buffers 48 (e.g., data input buffers) failing to buffer / discard at least some data bits transmitted via the DQ signal. Therefore, as discussed below, the input buffer control circuitry 50 can force a minimum write-to-write condition before deactivating the input buffer and, upon deactivation, force a minimum pulse width for the input buffer deactivation cycle to ensure a complete or proper reset of the 4PCG 47.

[0033] An impedance (ZQ) calibration signal can also be provided to memory device 10 via I / O interface 16. The ZQ calibration signal can be provided to a reference pin and can be used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors across process, voltage, and temperature (PVT) values. Since PVT characteristics affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As will be understood, a precision resistor is typically coupled between the ZQ pin on memory device 10 and GND / VSS external to memory device 10. This resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0034] Additionally, a loopback data signal (LBDQ) and a loopback strobe signal (LBDQS) can be provided to memory device 10 via I / O interface 16. The loopback data signal and the loopback strobe signal can be used during testing or debugging to set memory device 10 into a mode where signals are looped back through the same pins. For example, the loopback signal can be used to set memory device 10 to test the data output (DQ) of memory device 10. The loopback may include both LBDQ and LBDQS, or it may only include the loopback data pin. This is typically intended for monitoring data captured by memory device 10 at I / O interface 16. LBDQ can indicate the target memory device, such as memory device 10, data operations, and therefore can be analyzed to monitor (e.g., debug and / or perform diagnostics on it) the data operations of the target memory device. Similarly, LBDQS can indicate the target memory device, such as memory device 10, strobe operations (e.g., clock control of data operations), and therefore can be analyzed to monitor (e.g., debug and / or perform diagnostics on it) the strobe operations of the target memory device.

[0035] As will be understood, various other components, such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of the memory device 10), may also be incorporated into the memory device 10. Therefore, it should be understood that... Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to aid in the subsequent detailed description. Furthermore, although the memory device 10 is described above as a DDR5 device, the memory device 10 may be any suitable device (e.g., double data rate type 4 DRAM (DDR4), ferroelectric RAM device, or a combination of different types of memory devices).

[0036] Figure 2 This is a schematic diagram illustrating an input buffer control circuitry system 50, which includes / utilizes a write shifter 60 to generate a DSIben signal 62. The DSIben signal 62 controls when a DQ 64 can be buffered in a DQ input buffer (DQBuff) 66 to output a buffered DQ signal (BuffDQ) 68. As previously described, the DSIben signal 62 can be synchronized with and deterministically disable the input buffer when the write interval is less than a number (e.g., 31tCk), and can ensure that the disable pulse is at least a minimum width (e.g., 2 or 3tCk). In some embodiments, the write shifter 60 can be used for other purposes during other operations of the memory device 10, and / or can be dedicated to generating the DSIben signal 62.

[0037] Figure 3A and 3B (Collectively referred to as Figure 3) is a circuit diagram of the input buffer control circuitry system 48 including the write shifter 60. As illustrated, the write circuitry system includes serially connected flip-flops 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 154, 156, 158, and 160, collectively referred to as flip-flops 100 to 160. The write shifter 60 receives a command signal 168 indicating an incoming write signal, a system clock (Ck) 162 for controlling the clock control of flip-flops 100 to 160, a complementary clock (CkF) 164 that is complementary to Ck 162 and is used to control the clock control of flip-flops 100 to 160, and a reset signal 166 for resetting flip-flops 100 to 160 (e.g., due to power-on of memory device 10).

[0038] The write shifter 60 also includes a NOR gate 172 that receives the outputs of flip-flops 102, 104, 106, and 108; a NOR gate 174 that receives the outputs of flip-flops 110, 112, 114, and 116; a NOR gate 176 that receives the outputs of flip-flops 118, 120, 122, and 124; a NOR gate 178 that receives the outputs of flip-flops 126, 128, 130, and 132; a NOR gate 180 that receives the outputs of flip-flops 134, 136, 138, and 140; a NOR gate 182 that receives the outputs of flip-flops 142, 144, 146, and 148; and a NOR gate 184 that receives the outputs of flip-flops 150, 152, 154, and 156. Furthermore, the write shifter 60 includes a NAND gate 186 that receives the outputs of inverter 202 and NOR gates 172, 174, and 176 as its inputs and performs a logic NAND on the inputs. Furthermore, write shifter 60 includes NAND gate 188, which receives the outputs of NOR gates 178, 180, 182, and 184 as its inputs and performs a logical NAND operation on the inputs. NOR gate 190 receives the outputs of NAND gates 186 and 188 as its inputs and performs a NOR operation on the inputs. In other words, the output of NOR gate 190 is a logical OR function for each stage of write shifter 60 to ensure that input buffer 48 is not deactivated in the pipeline by a write command. Additionally, input buffer control circuitry 50 widens the 1tCk-wide pulse on command signal 168 to 2tCk. The 2tCk-wide write command in the shifter allows the OR operation of the write command through the shifter to operate without glitches due to overlap as the write command line passes through the write shifter. This extension also extends the write enable duration by 1tCk. In the illustrated embodiment, write shifter 60 includes 30 stages, providing 30tCk plus an additional 1tCk due to the 1tCk extension of the write command. In other embodiments, the number of stages may differ from the number described without altering the operation of the input buffer control technique discussed herein.

[0039] The output of NOR gate 190 (e.g., the logic OR function of all stages) is transmitted to the data input of flip-flop 158, which is synchronously captured with Ck 162, to ensure that flip-flop 160 does not see clock glitches when a write command enters the write shifter 60 and leaves the write shifter on the same cycle. The latched output of flip-flop 158 is transmitted as the clock input of flip-flop 160. Inverter 192 can be used to provide a complementary clock using the output of flip-flop 158. Flip-flop 160 acts as an SR latch with a power-on (PwrUp) signal 210 for resetting flip-flop 160 when the memory device 10 is powered on. The input to the set pin of flip-flop 160 is based on the tap between the flip-flops of the write shifter 60. The position can be set (e.g., 2, 3, or 4tCk), or, as illustrated, selected using switch 170 (or multiplexer). The turn-on tap determines the enable time of input buffer 48 and sets the minimum disable pulse width. The output of switch 170 (i.e., the tap-on) is transmitted to NOR gate 198, coupled to the low-active set pin of flip-flop 200. Another input to NOR gate 198 can be a low-active test mode enable signal 194 (which can be inverted using inverter 196), which can be used to force the input buffer to be enabled for testing whenever the signal is low. In other words, the low-active test mode enable signal 194 bypasses the normal enable timing of the test mode and enables power savings. Using these inputs, the DSIben signal 62 can be used to disable the input buffer 48 when there are several (e.g., >31) tCk between write commands. Furthermore, if the DSIben signal 62 has a disable pulse, then the write shifter 60 ensures that the duration of the disable pulse is longer than a threshold (e.g., 2, 3, or 4 tCK). In other words, the DSIben signal 62 can only be re-enabled after a threshold duration following the receipt of a subsequent write command and its shift to the threshold. Therefore, even if the DSIBen signal 62 is deactivated on tCk before a new write command is received, the DSIBen signal 62 will not be reactivated until the threshold duration of the deactivation pulse is met, thereby mitigating the risk of partial reset of 4PCG 47.

[0040] The write shifter 60 may also include a NOR gate 204 that performs a NOR operation on the output of the flip-flop 102 and the output of the inverter 202 to generate a feedback signal 206 for stretching, as discussed below.

[0041] Figure 4Figure 220 illustrates an embodiment of the operation of writing to shifter 60. As illustrated, figure 220 includes line 222 representing command signal 168. Figure 220 also includes line 224 representing Ck 162 received at flip-flop 100, and line 226 representing the output of flip-flop 100. Line 228 represents the output of flip-flop 102, line 230 represents the output of flip-flop 104, and line 232 represents the output of flip-flop 106. Figure 220 also includes line 234 representing DSIben signal 62. As illustrated, pulse 236 on command signal 168 is widened to 2tCK of Ck 162, and at the next cycle of Ck 162, it causes a 2-tCk wide pulse 238 at the output of flip-flop 100. This pulse 238 at the output of flip-flop 100 causes pulse 240 at the output of flip-flop 102 at the next cycle of Ck 162. The pulse 240 at the output of flip-flop 102 causes pulse 242 at the output of flip-flop 104 in the next cycle of Ck 162. Similarly, the pulse 242 at the output of flip-flop 104 causes pulse 244 at the output of flip-flop 106 in the next cycle of Ck 162. When the output of flip-flop 106 is used as an on tap via switch 170, pulse 244 causes the DSIben signal 62 to be asserted, as described by rising edge 246, to enable input buffer 48.

[0042] As explained, pulse 248 on command signal 168 is widened to 2tCK, and at the next cycle of Ck 162, it causes a 2-tCk wide pulse 250 at the output of flip-flop 100. This pulse 250 at the output of flip-flop 100 causes pulse 252 at the output of flip-flop 102 at the next cycle of Ck 162. This pulse 252 at the output of flip-flop 102, in turn, causes pulse 254 at the output of flip-flop 104 at the next cycle of Ck 162. Similarly, this pulse 254 at the output of flip-flop 104 causes pulse 256 at the output of flip-flop 106 at the next cycle of Ck 162. Since DSIben signal 62 has been asserted (e.g., not deasserted because the write-to-write spacing does not exceed a number (e.g., 31)), DSIben signal 62 remains asserted.

[0043] As previously mentioned, the pulse width is 2tCk. This extension of the write command in the shifter allows the pulses to overlap to avoid potential glitches in the logical OR path.

[0044] Figure 5 This is a diagram 270 illustrating an embodiment of writing to shifter 60. Diagram 270 includes a line 272 for enabling the output of NOR gate 198 of the DSIben signal 62. Line 272 may be... Figure 4The signals represented by line 222 are complementary signals. Specifically, the assertion shown by line 222 corresponds to a pulse to a logic high value, while the assertion shown by line 272 corresponds to a pulse to a logic low value. Figure 270 also includes line 274, which corresponds to the output of NOR gate 190, indicating the result of the logical OR operation written to all stages of shifter 60. Figure 270 further includes line 276 corresponding to Ck 162. Line 278 corresponds to the synchronization result of the logical OR operation output from flip-flop 158. Line 280 corresponds to the DSIben signal 62 output from flip-flop 160.

[0045] The three pulses 282, 284, and 286 each correspond to a write command entering the write shifter 60. The write-to-write interval 287 between pulses 282 and 284 is less than (e.g., 8) the threshold number of tCk (e.g., 31). Therefore, the output of NOR gate 190 does not go high after pulse 282 and before pulse 284. Similarly, the write-to-write interval 288 between pulses 284 and 286 is also less than (e.g., 30) the threshold number of tCK. Therefore, NOR gate 190 does not go high after pulse 284 and before pulse 286. After pulse 286, no other write commands are received for the threshold number (e.g., 31) of tCK. Therefore, the stage of write shifter 60 is empty, causing the rising edge 292 of the output of NOR gate 190 to go high. Rising edge 292 causes the output of flip-flop 158, represented by line 278, to go high at the next clock cycle of Ck 162 as rising edge 294. In other words, flip-flop 158 synchronizes the output of NOR gate 190 to Ck 162. This rising edge 294 causes flip-flop 160 to output the DSIben signal 62 with falling edge 296 to disable the input buffer.

[0046] Figure 6 This is a diagram 300 illustrating alternating timings that can be used in an embodiment utilizing the write shifter 60. As illustrated, diagram 300 includes lines with different pulses, similar to those in diagram 270. Specifically, diagram 300 shows pulses 310, 312, and 314 indicating three different write commands. The write-to-write interval 316 between pulses 310 and 312 is similar to... Figure 5The write-to-write interval 318 between pulses 312 and 314 is equal to the threshold number of tCK (e.g., 31). Therefore, pulse 322 is output from NOR gate 190, indicating that the write shifter 60 stage is empty. This pulse, in turn, causes flip-flop 158 to output the synchronous result of the OR operation, which in turn causes DSIBen signal 62 to de-assert (e.g., disable input buffer 48), as shown by falling edge 326. Re-enabling input buffer 48 via DSIBen signal 62 is prevented until a minimum duration 328 has elapsed after disabling input buffer 48, allowing 4PCG 47 to fully reset. As previously discussed, this minimum duration 328 can be set by the number of stages that capture the turn-on tap after it (e.g., 2, 3, or 4tCk), and can be selected using switch 170 or a multiplexer. The specified minimum duration 328 is 3tCK, but it can be any other selected duration. After this minimum duration 328, the DSIben signal 62 can be allowed to re-enable the input buffer 48 with the rising edge 330 of the DSIben signal 62.

[0047] Following pulse 314, no further write commands are received for tCK 320 of threshold number (e.g., 31). Therefore, the write stage of shifter 60 is empty, causing the rising edge 332 of the output of NOR gate 190 to go high. Rising edge 332 causes the output of flip-flop 158, represented by line 278, to go high at the next clock cycle of Ck 162 as rising edge 334. In other words, flip-flop 158 synchronizes the output of NOR gate 190 to Ck 162. This rising edge 334 causes flip-flop 160 to output a DSIben signal 62 with a falling edge 336 to disable input buffer 48.

[0048] Figure 7 It is similar to Figure 6 The difference between pattern 340 and pattern 300 is that the write-to-write pitch 342 is 1 tCk larger than the write-to-write pitch 318 of pattern 300. Due to this additional 1 tCk of write-to-write pitch 342 above the write-to-write pitch 318, the duration of the pulse after the falling edge 326 is 1 tCk longer than the minimum duration 328. In other words, as previously described, the input buffer control circuitry 50 adds a stop pulse width of an additional tCk for every additional tCk of write-to-write pitch, thereby widening the larger write-to-write pitch (and / or slower tCk).

[0049] In some embodiments, the timing of initiating the command signal into the write shifter 60 can vary based on the frequency of Ck of the memory device 10. For example, the command signal can be initiated at a number less than the full column address strobe (CAS) write delay (CWL) of the device (e.g., 20tCK) as the first available point across all speed levels of the memory device 10. However, this point may be too slow for some of the faster operating frequencies of the memory device. Therefore, the input buffer control circuitry system 50 can select between two different initiation points (e.g., CWL–20tCks(Q20) and CWL–25tCks(Q25)) based on the speed level of the memory device 10.

[0050] The data rate setting and / or trimming code of memory device 10 can be used to determine the inflection point for switching between a slow mode (Q20) and a fast mode (Q25) with the data input buffer enabled. Although Q25 and Q20 for the corresponding fast and slow modes are referred to below, some embodiments may use other initiation points and / or more than two options for potential initiation points. The input buffer remains disabled in both modes whenever a write interval is greater than or equal to a number (e.g., 31) tCk. The fast mode accelerates the entire enable window by a number (e.g., 5 clock cycles) simply by using Q25 instead of Q20. The trimming code can be input via a mode register and / or set via a setting fuse in memory device 10 to set the speed. For example, if silicon testing is fast silicon during manufacturing, the fuse can be set to always use Q20, regardless of whether the data rate setting might otherwise cause the memory device to use Q25.

[0051] Figure 8 A portion 370 of the input buffer control circuitry 50 is shown, which includes a decoding mode circuitry 360 that determines whether to use Q20 or Q25. The decoding mode circuitry 360 receives input 362 (e.g., data rate setting, trim code, fuse value, and / or the like). The decoding mode circuitry 360 uses this input to determine which mode to use for decoding and outputs a FastDSIBen signal 364, indicating whether Q25 or Q20 is used for input buffer control.

[0052] Section 370 also includes circuitry for outputting Q25 366, which initiates the command on command signal 168 five cycles faster than when using Q20F 368. Q20F 368 can supplement Q20 for logic operations within section 370. Q25 366 and FastDSIBen signal 364 are passed to NAND gate 372, which performs a NAND operation on it and outputs the result to an extended circuitry 374 containing delay 376 and NAND gate 378. The output of NAND gate 372 is passed to NAND gate 378 via delay 376 and directly to NAND gate 378, bypassing delay 376. The stretched output of NAND gate 378 is passed through inverters 380, 382, ​​384, and 386. The output of inverter 386 is received at switch 388. Switch 388 can be used to enable or disable Q25 366 by determining whether to transmit the supply voltage 390 or the output of inverter 386 as a command signal 168.

[0053] Q20F 368 and FastDSIBen signal 364 are fed to NOR gate 392 as inputs to perform a NOR operation and output the result to inverter 394, which then outputs to delay 396 for matching the path of Q25 366. The output of the delay is fed to switch 397 to determine whether to force the use of Q20F 368 or use the result from delay 396. The output from switch 397 is fed to stretching circuitry 398, which includes delay 400 and NAND gate 402, where the output of switch 397 is passed to NAND gate 502 via delay 400 and directly to NAND gate 402 bypassing delay 400. NAND gate 402 also receives the output of switch 388. The circuitry between NAND gate 402 and Q25 366 and Q20F 368 is used to select (e.g., multiplex) one as the selected signal 404. When Q20F 368 is selected, the output of NAND gate 402 is also stretched. The selected and stretched signal 404 is inverted in inverter 406. The inverted selected signal 406 is transmitted to NAND gate 408 along with feedback signal 206. The output of NAND gate 408 is transmitted to flip-flop 100 as command signal 168. Although due to potential availability in some embodiments of memory device 10... Figure 8 The specific circuit system is described, but in some embodiments any suitable configuration can be used to stretch and multiplex the signals.

[0054] Figure 9A graph 450 illustrates the timing comparison using Q20 and Q25. Graph 450 includes line 452 corresponding to the command signal 168 using Q25 from section 370. Line 454 corresponds to Ck 162, and line 456 corresponds to the DSIben signal 62. Similarly, graph 450 includes line 458 corresponding to the command signal 168 using Q20 from section 370. Line 460 corresponds to Ck 162, and line 462 corresponds to the DSIben signal 62. Although lines 454 and 460 are shown to have the same frequency, in some embodiments, line 454 may correspond to a higher frequency that may require the use of Q25 instead of Q20.

[0055] Three write commands are received, as indicated by pulses 464, 466, and 468, which are represented by corresponding pulses 464A, 466A, and 468A for use with Q25 and corresponding pulses 464B, 466B, and 468B for use with Q22. As explained, the write shifter 60 entering pulses 464A, 466A, and 468A when using Q25 occurs 5 cycles earlier than the write shifter 60 entering the corresponding pulses 464B, 466B, and 468B when using Q20. Similarly, the rising edges 470A and 474A and the falling edges 472A and 476A occur 5 cycles earlier when using Q25 than the corresponding rising edges 470B and 474B and the falling edges 472B and 476B occur when using Q20. In other words, using Q25 causes the command to enter the write shifter 60 5 cycles earlier, and also causes the input buffer 48 to be deactivated and reactivated 5 cycles earlier than when using Q20.

[0056] While this disclosure is readily presented in various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0057] The techniques proposed and advocated in this paper are cited and applied to practical objects and concrete examples, which significantly improve the field of technology and are therefore not abstract, intangible or purely theoretical.

Claims

1. A memory device comprising: A command interface configured to receive write commands from the host device; An input buffer, configured to buffer data from the host device; Write to the shifter, which is configured to: Receive the first write command from the write commands, and shift the first write command through the write shifter; When the first write command has been shifted by the write shifter, the input buffer is deactivated after a clock cycle of the first threshold. Receive the second write command; as well as The input buffer is prevented from being re-enabled until the second write command has been shifted through the second threshold level of the write shifter.

2. The memory device of claim 1, wherein the write shifter comprises a plurality of serially connected flip-flops, through which the first and second write commands are shifted.

3. The memory device of claim 2, wherein each stage of the write shifter includes a corresponding one of the serially connected flip-flops.

4. The memory device of claim 3, wherein the write shifter includes an on / off tap sampled from both of the serially connected flip-flops.

5. The memory device of claim 4, wherein the number of serially connected triggers prior to the turn-on tap is equal to the number of stages corresponding to the second threshold.

6. The memory device of claim 4, wherein the write shifter includes a switch to select different positions for the on / off tap of the plurality of serially connected triggers.

7. The memory device of claim 3, wherein the total number of flip-flops in the write shifter is equal to the number of clock cycles of the first threshold.

8. The memory device of claim 1, wherein the write shifter includes a logic OR circuitry configured to perform logic OR at all levels to determine when the first write command has been shifted by the write shifter.

9. The memory device of claim 8, wherein shifting via the write shifter includes shifting the write command through all stages of the write shifter.

10. The memory device of claim 1, further comprising a mode selection circuitry configured to select between a fast mode for initiating a write command to the write shifter and a slow mode for initiating a write instruction to the write shifter.

11. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on the speed level of the memory device.

12. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on a fuse-breaking value from the fuse in the memory device.

13. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on a mode register value set by the host device.

14. The memory device of claim 10, wherein the fast mode corresponds to the write command being initiated into the write shifter one or more clock cycles earlier than the slow mode.

15. A method for operating a memory device, comprising: Disable the input buffer; Receive a write command at the memory device; The write command is transmitted via the write shifter of the memory device; After the input buffer is disabled, its activation is suppressed until the write command has reached the on tap in the write shifter; as well as The input buffer is enabled after the write command has reached the on tap in the write shifter.

16. The method of claim 15, further comprising selecting, between two possible positions, the position for the on / off tap using a switch coupled to two possible positions in the write shifter.

17. The method of claim 15, further comprising performing OR at different levels of the write shifter to determine that a previous write command has exited the write shifter to deactivate the input buffer.

18. The method of claim 15, wherein disabling the input buffer includes driving an input buffer enable signal to a first logic value, and enabling the input buffer includes driving the input buffer enable signal to a second logic value.

19. The method of claim 18, wherein the first logic value includes a logic high value and the second logic value includes a logic low value.

20. A memory device comprising: A command interface configured to receive write commands from the host device; An input buffer, configured to buffer data from the host device; The input buffer control circuit system includes: Multiple triggers configured to receive a first write command in the write commands, and to shift the first write command via the multiple triggers; A logic OR circuit system configured to receive a value from each of the plurality of flip-flops, and causing the input buffer to be deactivated after the first write command has been shifted through all of the plurality of flip-flops; and A control circuit system configured to prevent the input buffer from being re-enabled after it has been deactivated, until a subsequently received second write command has been shifted by a threshold number of the plurality of triggers.

21. The memory device of claim 20, wherein the control circuitry includes a flip-flop configured to synchronize an OR operation from the logic OR circuitry with the clock of the memory device.

22. The memory device of claim 20, wherein the input buffer control circuitry includes a switch configured to select among a plurality of potential on / off tap positions, wherein a threshold number of triggers corresponds to the selected on / off tap position.

23. The memory device of claim 20, wherein the input buffer control circuitry includes a mode decoder configured to select between a fast mode and a slow mode of the memory device.

24. The memory device of claim 23, wherein the mode decoder is configured to make the selection based at least in part on the speed class of the memory device or the fuse value in the fuse of the memory device.

25. The memory device of claim 23, wherein the fast mode initiates the write command to the plurality of flip-flops after fewer clock cycles compared to the slow mode, which initiates the write command to the plurality of flip-flops.

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